1/*- |
2 * Copyright (C) 2013 Emulex |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * --- 21 unchanged lines hidden (view full) --- 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 39 |
40/* $FreeBSD: head/sys/dev/oce/oce_if.h 252869 2013-07-06 08:30:45Z delphij $ */ |
41 42#include <sys/param.h> 43#include <sys/endian.h> 44#include <sys/module.h> 45#include <sys/kernel.h> 46#include <sys/bus.h> 47#include <sys/mbuf.h> 48#include <sys/rman.h> --- 43 unchanged lines hidden (view full) --- 92 93/* OCE devices supported by this driver */ 94#define PCI_VENDOR_EMULEX 0x10df /* Emulex */ 95#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */ 96#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */ 97#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */ 98#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */ 99#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */ |
100#define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */ |
101 102#define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \ 103 (sc->flags & OCE_FLAGS_BE2))? 1:0) |
104#define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3) 105#define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2) |
106#define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0) 107#define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0) |
108#define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0) |
109 |
110#define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \ 111 (sc->function_mode & FNM_UMC_MODE) || \ 112 (sc->function_mode & FNM_VNIC_MODE)) 113#define OCE_FUNCTION_CAPS_SUPER_NIC 0x40 114#define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC) |
115 |
116 |
117/* proportion Service Level Interface queues */ 118#define OCE_MAX_UNITS 2 119#define OCE_MAX_PPORT OCE_MAX_UNITS 120#define OCE_MAX_VPORT OCE_MAX_UNITS 121 122extern int mp_ncpus; /* system's total active cpu cores */ 123#define OCE_NCPUS mp_ncpus 124 125/* This should be powers of 2. Like 2,4,8 & 16 */ |
126#define OCE_MAX_RSS 8 |
127#define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/ |
128#define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc)) |
129 130#define OCE_MIN_RQ 1 131#define OCE_MIN_WQ 1 132 133#define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */ 134#define OCE_MAX_WQ 8 135 136#define OCE_MAX_EQ 32 --- 18 unchanged lines hidden (view full) --- 155#define OCE_DEFAULT_PROMISCUOUS 0 156 157 158#define RSS_ENABLE_IPV4 0x1 159#define RSS_ENABLE_TCP_IPV4 0x2 160#define RSS_ENABLE_IPV6 0x4 161#define RSS_ENABLE_TCP_IPV6 0x8 162 |
163#define INDIRECTION_TABLE_ENTRIES 128 |
164 165/* flow control definitions */ 166#define OCE_FC_NONE 0x00000000 167#define OCE_FC_TX 0x00000001 168#define OCE_FC_RX 0x00000002 169#define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 170 171 --- 29 unchanged lines hidden (view full) --- 201 BSWAP_16((x) >> 16)) 202#define BSWAP_64(x) ((BSWAP_32(x) << 32) | \ 203 BSWAP_32((x) >> 32)) 204 205#define for_all_wq_queues(sc, wq, i) \ 206 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i]) 207#define for_all_rq_queues(sc, rq, i) \ 208 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i]) |
209#define for_all_rss_queues(sc, rq, i) \ 210 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \ 211 i++, rq = sc->rq[i + 1]) |
212#define for_all_evnt_queues(sc, eq, i) \ 213 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i]) 214#define for_all_cq_queues(sc, cq, i) \ 215 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) 216 217 218/* Flash specific */ 219#define IOCTL_COOKIE "SERVERENGINES CORP" --- 461 unchanged lines hidden (view full) --- 681 682struct oce_wq { 683 OCE_LOCK tx_lock; 684 void *parent; 685 oce_ring_buffer_t *ring; 686 struct oce_cq *cq; 687 bus_dma_tag_t tag; 688 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE]; |
689 uint32_t pkt_desc_tail; 690 uint32_t pkt_desc_head; |
691 uint32_t wqm_used; 692 boolean_t resched; 693 uint32_t wq_free; 694 uint32_t tx_deferd; 695 uint32_t pkt_drops; 696 qstate_t qstate; 697 uint16_t wq_id; 698 struct wq_config cfg; 699 int queue_index; 700 struct oce_tx_queue_stats tx_stats; 701 struct buf_ring *br; 702 struct task txtask; |
703 uint32_t db_offset; |
704}; 705 706struct rq_config { 707 uint32_t q_len; 708 uint32_t frag_size; 709 uint32_t mtu; 710 uint32_t if_id; 711 uint32_t is_rss_queue; --- 64 unchanged lines hidden (view full) --- 776#define OCE_FLAGS_USING_MSI 0x00000010 777#define OCE_FLAGS_USING_MSIX 0x00000020 778#define OCE_FLAGS_FUNCRESET_RQD 0x00000040 779#define OCE_FLAGS_VIRTUAL_PORT 0x00000080 780#define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100 781#define OCE_FLAGS_BE3 0x00000200 782#define OCE_FLAGS_XE201 0x00000400 783#define OCE_FLAGS_BE2 0x00000800 |
784#define OCE_FLAGS_SH 0x00001000 |
785 786#define OCE_DEV_BE2_CFG_BAR 1 787#define OCE_DEV_CFG_BAR 0 788#define OCE_PCI_CSR_BAR 2 789#define OCE_PCI_DB_BAR 4 790 791typedef struct oce_softc { 792 device_t dev; --- 52 unchanged lines hidden (view full) --- 845 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */ 846 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */ 847 struct oce_mq *mq; /* Mailbox queue */ 848 849 uint32_t neqs; 850 uint32_t ncqs; 851 uint32_t nrqs; 852 uint32_t nwqs; |
853 uint32_t nrssqs; |
854 855 uint32_t tx_ring_size; 856 uint32_t rx_ring_size; 857 uint32_t rq_frag_size; |
858 859 uint32_t if_id; /* interface ID */ 860 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */ 861 uint32_t pmac_id; /* PMAC id */ 862 863 uint32_t if_cap_flags; 864 865 uint32_t flow_control; --- 19 unchanged lines hidden (view full) --- 885 886 887 888/************************************************** 889 * BUS memory read/write macros 890 * BE3: accesses three BAR spaces (CFG, CSR, DB) 891 * Lancer: accesses one BAR space (CFG) 892 **************************************************/ |
893#define OCE_READ_CSR_MPU(sc, space, o) \ |
894 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \ |
895 (sc)->space##_bhandle,o)) \ 896 : (bus_space_read_4((sc)->devcfg_btag, \ 897 (sc)->devcfg_bhandle,o))) 898#define OCE_READ_REG32(sc, space, o) \ 899 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 900 (sc)->space##_bhandle,o)) \ 901 : (bus_space_read_4((sc)->devcfg_btag, \ 902 (sc)->devcfg_bhandle,o))) |
903#define OCE_READ_REG16(sc, space, o) \ |
904 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \ 905 (sc)->space##_bhandle,o)) \ 906 : (bus_space_read_2((sc)->devcfg_btag, \ 907 (sc)->devcfg_bhandle,o))) |
908#define OCE_READ_REG8(sc, space, o) \ |
909 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \ 910 (sc)->space##_bhandle,o)) \ 911 : (bus_space_read_1((sc)->devcfg_btag, \ 912 (sc)->devcfg_bhandle,o))) |
913 |
914#define OCE_WRITE_CSR_MPU(sc, space, o, v) \ |
915 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 916 (sc)->space##_bhandle,o,v)) \ |
917 : (bus_space_write_4((sc)->devcfg_btag, \ 918 (sc)->devcfg_bhandle,o,v))) 919#define OCE_WRITE_REG32(sc, space, o, v) \ 920 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 921 (sc)->space##_bhandle,o,v)) \ 922 : (bus_space_write_4((sc)->devcfg_btag, \ 923 (sc)->devcfg_bhandle,o,v))) |
924#define OCE_WRITE_REG16(sc, space, o, v) \ |
925 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \ |
926 (sc)->space##_bhandle,o,v)) \ |
927 : (bus_space_write_2((sc)->devcfg_btag, \ 928 (sc)->devcfg_bhandle,o,v))) |
929#define OCE_WRITE_REG8(sc, space, o, v) \ |
930 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \ |
931 (sc)->space##_bhandle,o,v)) \ |
932 : (bus_space_write_1((sc)->devcfg_btag, \ 933 (sc)->devcfg_bhandle,o,v))) |
934 935 936/*********************************************************** 937 * DMA memory functions 938 ***********************************************************/ 939#define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f) 940int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags); 941void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma); --- 104 unchanged lines hidden (view full) --- 1046int oce_mbox_create_rq(struct oce_rq *rq); 1047int oce_mbox_create_wq(struct oce_wq *wq); 1048int oce_mbox_create_eq(struct oce_eq *eq); 1049int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, 1050 uint32_t is_eventable); 1051int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num); 1052void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1053 int num); |
1054int oce_get_profile_config(POCE_SOFTC sc); 1055int oce_get_func_config(POCE_SOFTC sc); |
1056void mbx_common_req_hdr_init(struct mbx_hdr *hdr, 1057 uint8_t dom, 1058 uint8_t port, 1059 uint8_t subsys, 1060 uint8_t opcode, 1061 uint32_t timeout, uint32_t pyld_len, 1062 uint8_t version); 1063 --- 32 unchanged lines hidden (view full) --- 1096#define OCE_NO_LOOPBACK 0xff 1097 1098#define atomic_inc_32(x) atomic_add_32(x, 1) 1099#define atomic_dec_32(x) atomic_subtract_32(x, 1) 1100 1101#define LE_64(x) htole64(x) 1102#define LE_32(x) htole32(x) 1103#define LE_16(x) htole16(x) |
1104#define HOST_64(x) le64toh(x) 1105#define HOST_32(x) le32toh(x) 1106#define HOST_16(x) le16toh(x) |
1107#define DW_SWAP(x, l) 1108#define IS_ALIGNED(x,a) ((x % a) == 0) 1109#define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32)) 1110#define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff)); 1111 1112#define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0) 1113#define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) 1114#define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0) --- 16 unchanged lines hidden (view full) --- 1131 } 1132 1133 if (c == 1) 1134 return b; 1135 1136 return 0; 1137} 1138 |
1139static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc) 1140{ 1141 if (IS_BE(sc)) 1142 return MPU_EP_SEMAPHORE_BE3; 1143 else if (IS_SH(sc)) 1144 return MPU_EP_SEMAPHORE_SH; 1145 else 1146 return MPU_EP_SEMAPHORE_XE201; 1147} 1148 |
1149#define TRANSCEIVER_DATA_NUM_ELE 64 1150#define TRANSCEIVER_DATA_SIZE 256 1151#define TRANSCEIVER_A0_SIZE 128 1152#define TRANSCEIVER_A2_SIZE 128 1153#define PAGE_NUM_A0 0xa0 1154#define PAGE_NUM_A2 0xa2 1155#define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\ 1156 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE))) 1157 |