2c2
< * Copyright (C) 2012 Emulex
---
> * Copyright (C) 2013 Emulex
40c40
< /* $FreeBSD: head/sys/dev/oce/oce_if.h 247880 2013-03-06 09:53:38Z delphij $ */
---
> /* $FreeBSD: head/sys/dev/oce/oce_if.h 252869 2013-07-06 08:30:45Z delphij $ */
99a100
> #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */
102a104,105
> #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3)
> #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2)
104a108
> #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
105a110,114
> #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \
> (sc->function_mode & FNM_UMC_MODE) || \
> (sc->function_mode & FNM_VNIC_MODE))
> #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40
> #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
106a116
>
116c126
< #define OCE_MAX_RSS 4 /* TODO: 8*/
---
> #define OCE_MAX_RSS 8
117a128
> #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
151a163
> #define INDIRECTION_TABLE_ENTRIES 128
196a209,211
> #define for_all_rss_queues(sc, rq, i) \
> for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
> i++, rq = sc->rq[i + 1])
674,675c689,690
< uint32_t packets_in;
< uint32_t packets_out;
---
> uint32_t pkt_desc_tail;
> uint32_t pkt_desc_head;
687a703
> uint32_t db_offset;
767a784
> #define OCE_FLAGS_SH 0x00001000
835a853
> uint32_t nrssqs;
840d857
< uint32_t rss_enable;
876c893
< #define OCE_READ_REG32(sc, space, o) \
---
> #define OCE_READ_CSR_MPU(sc, space, o) \
878,880c895,902
< (sc)->space##_bhandle,o)) \
< : (bus_space_read_4((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o)))
---
> (sc)->space##_bhandle,o)) \
> : (bus_space_read_4((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o)))
> #define OCE_READ_REG32(sc, space, o) \
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
> (sc)->space##_bhandle,o)) \
> : (bus_space_read_4((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o)))
882,885c904,907
< ((IS_BE(sc)) ? (bus_space_read_2((sc)->space##_btag, \
< (sc)->space##_bhandle,o)) \
< : (bus_space_read_2((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o)))
---
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
> (sc)->space##_bhandle,o)) \
> : (bus_space_read_2((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o)))
887,890c909,912
< ((IS_BE(sc)) ? (bus_space_read_1((sc)->space##_btag, \
< (sc)->space##_bhandle,o)) \
< : (bus_space_read_1((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o)))
---
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
> (sc)->space##_bhandle,o)) \
> : (bus_space_read_1((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o)))
892c914
< #define OCE_WRITE_REG32(sc, space, o, v) \
---
> #define OCE_WRITE_CSR_MPU(sc, space, o, v) \
895,896c917,923
< : (bus_space_write_4((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o,v)))
---
> : (bus_space_write_4((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o,v)))
> #define OCE_WRITE_REG32(sc, space, o, v) \
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
> (sc)->space##_bhandle,o,v)) \
> : (bus_space_write_4((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o,v)))
898c925
< ((IS_BE(sc)) ? (bus_space_write_2((sc)->space##_btag, \
---
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
900,901c927,928
< : (bus_space_write_2((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o,v)))
---
> : (bus_space_write_2((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o,v)))
903c930
< ((IS_BE(sc)) ? (bus_space_write_1((sc)->space##_btag, \
---
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
905,906c932,933
< : (bus_space_write_1((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o,v)))
---
> : (bus_space_write_1((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o,v)))
1026a1054,1055
> int oce_get_profile_config(POCE_SOFTC sc);
> int oce_get_func_config(POCE_SOFTC sc);
1074a1104,1106
> #define HOST_64(x) le64toh(x)
> #define HOST_32(x) le32toh(x)
> #define HOST_16(x) le16toh(x)
1106a1139,1148
> static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
> {
> if (IS_BE(sc))
> return MPU_EP_SEMAPHORE_BE3;
> else if (IS_SH(sc))
> return MPU_EP_SEMAPHORE_SH;
> else
> return MPU_EP_SEMAPHORE_XE201;
> }
>
< * Copyright (C) 2012 Emulex
---
> * Copyright (C) 2013 Emulex
40c40
< /* $FreeBSD: head/sys/dev/oce/oce_if.h 247880 2013-03-06 09:53:38Z delphij $ */
---
> /* $FreeBSD: head/sys/dev/oce/oce_if.h 252869 2013-07-06 08:30:45Z delphij $ */
99a100
> #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */
102a104,105
> #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3)
> #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2)
104a108
> #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
105a110,114
> #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \
> (sc->function_mode & FNM_UMC_MODE) || \
> (sc->function_mode & FNM_VNIC_MODE))
> #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40
> #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
106a116
>
116c126
< #define OCE_MAX_RSS 4 /* TODO: 8*/
---
> #define OCE_MAX_RSS 8
117a128
> #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
151a163
> #define INDIRECTION_TABLE_ENTRIES 128
196a209,211
> #define for_all_rss_queues(sc, rq, i) \
> for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
> i++, rq = sc->rq[i + 1])
674,675c689,690
< uint32_t packets_in;
< uint32_t packets_out;
---
> uint32_t pkt_desc_tail;
> uint32_t pkt_desc_head;
687a703
> uint32_t db_offset;
767a784
> #define OCE_FLAGS_SH 0x00001000
835a853
> uint32_t nrssqs;
840d857
< uint32_t rss_enable;
876c893
< #define OCE_READ_REG32(sc, space, o) \
---
> #define OCE_READ_CSR_MPU(sc, space, o) \
878,880c895,902
< (sc)->space##_bhandle,o)) \
< : (bus_space_read_4((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o)))
---
> (sc)->space##_bhandle,o)) \
> : (bus_space_read_4((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o)))
> #define OCE_READ_REG32(sc, space, o) \
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
> (sc)->space##_bhandle,o)) \
> : (bus_space_read_4((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o)))
882,885c904,907
< ((IS_BE(sc)) ? (bus_space_read_2((sc)->space##_btag, \
< (sc)->space##_bhandle,o)) \
< : (bus_space_read_2((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o)))
---
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
> (sc)->space##_bhandle,o)) \
> : (bus_space_read_2((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o)))
887,890c909,912
< ((IS_BE(sc)) ? (bus_space_read_1((sc)->space##_btag, \
< (sc)->space##_bhandle,o)) \
< : (bus_space_read_1((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o)))
---
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
> (sc)->space##_bhandle,o)) \
> : (bus_space_read_1((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o)))
892c914
< #define OCE_WRITE_REG32(sc, space, o, v) \
---
> #define OCE_WRITE_CSR_MPU(sc, space, o, v) \
895,896c917,923
< : (bus_space_write_4((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o,v)))
---
> : (bus_space_write_4((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o,v)))
> #define OCE_WRITE_REG32(sc, space, o, v) \
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
> (sc)->space##_bhandle,o,v)) \
> : (bus_space_write_4((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o,v)))
898c925
< ((IS_BE(sc)) ? (bus_space_write_2((sc)->space##_btag, \
---
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
900,901c927,928
< : (bus_space_write_2((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o,v)))
---
> : (bus_space_write_2((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o,v)))
903c930
< ((IS_BE(sc)) ? (bus_space_write_1((sc)->space##_btag, \
---
> ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
905,906c932,933
< : (bus_space_write_1((sc)->devcfg_btag, \
< (sc)->devcfg_bhandle,o,v)))
---
> : (bus_space_write_1((sc)->devcfg_btag, \
> (sc)->devcfg_bhandle,o,v)))
1026a1054,1055
> int oce_get_profile_config(POCE_SOFTC sc);
> int oce_get_func_config(POCE_SOFTC sc);
1074a1104,1106
> #define HOST_64(x) le64toh(x)
> #define HOST_32(x) le32toh(x)
> #define HOST_16(x) le16toh(x)
1106a1139,1148
> static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
> {
> if (IS_BE(sc))
> return MPU_EP_SEMAPHORE_BE3;
> else if (IS_SH(sc))
> return MPU_EP_SEMAPHORE_SH;
> else
> return MPU_EP_SEMAPHORE_XE201;
> }
>