39d38
< /* $FreeBSD: head/sys/dev/oce/oce_if.h 246799 2013-02-14 17:34:17Z jpaetzel $ */
40a40,41
> /* $FreeBSD: head/sys/dev/oce/oce_if.h 247880 2013-03-06 09:53:38Z delphij $ */
>
90,91c91
< /* OCE device driver module component revision informaiton */
< #define COMPONENT_REVISION "4.2.127.0"
---
> #define COMPONENT_REVISION "4.6.95.0"
93d92
<
135c134
< #define OCE_MAX_JUMBO_FRAME_SIZE 16360
---
> #define OCE_MAX_JUMBO_FRAME_SIZE 9018
483a483,484
> #define INTR_RATE_HWM 15000
> #define INTR_RATE_LWM 10000
484a486,487
> #define OCE_MAX_EQD 128u
> #define OCE_MIN_EQD 50u
485a489,504
> struct oce_set_eqd {
> uint32_t eq_id;
> uint32_t phase;
> uint32_t delay_multiplier;
> };
>
> struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
> boolean_t enable;
> uint32_t min_eqd; /* in usecs */
> uint32_t max_eqd; /* in usecs */
> uint32_t cur_eqd; /* in usecs */
> uint32_t et_eqd; /* configured value when aic is off */
> uint64_t ticks;
> uint64_t intr_prev;
> };
>
567a587
> uint64_t intr;
829a850,852
>
> struct oce_aic_obj aic_obj[OCE_MAX_EQ];
>
840c863,865
< uint32_t pvid;
---
> uint16_t qnq_debug_event;
> uint16_t qnqid;
> uint16_t pvid;
998a1024,1026
> int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
> void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
> int num);
1078a1107,1115
> #define TRANSCEIVER_DATA_NUM_ELE 64
> #define TRANSCEIVER_DATA_SIZE 256
> #define TRANSCEIVER_A0_SIZE 128
> #define TRANSCEIVER_A2_SIZE 128
> #define PAGE_NUM_A0 0xa0
> #define PAGE_NUM_A2 0xa2
> #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
> || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
>
< /* $FreeBSD: head/sys/dev/oce/oce_if.h 246799 2013-02-14 17:34:17Z jpaetzel $ */
40a40,41
> /* $FreeBSD: head/sys/dev/oce/oce_if.h 247880 2013-03-06 09:53:38Z delphij $ */
>
90,91c91
< /* OCE device driver module component revision informaiton */
< #define COMPONENT_REVISION "4.2.127.0"
---
> #define COMPONENT_REVISION "4.6.95.0"
93d92
<
135c134
< #define OCE_MAX_JUMBO_FRAME_SIZE 16360
---
> #define OCE_MAX_JUMBO_FRAME_SIZE 9018
483a483,484
> #define INTR_RATE_HWM 15000
> #define INTR_RATE_LWM 10000
484a486,487
> #define OCE_MAX_EQD 128u
> #define OCE_MIN_EQD 50u
485a489,504
> struct oce_set_eqd {
> uint32_t eq_id;
> uint32_t phase;
> uint32_t delay_multiplier;
> };
>
> struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
> boolean_t enable;
> uint32_t min_eqd; /* in usecs */
> uint32_t max_eqd; /* in usecs */
> uint32_t cur_eqd; /* in usecs */
> uint32_t et_eqd; /* configured value when aic is off */
> uint64_t ticks;
> uint64_t intr_prev;
> };
>
567a587
> uint64_t intr;
829a850,852
>
> struct oce_aic_obj aic_obj[OCE_MAX_EQ];
>
840c863,865
< uint32_t pvid;
---
> uint16_t qnq_debug_event;
> uint16_t qnqid;
> uint16_t pvid;
998a1024,1026
> int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
> void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
> int num);
1078a1107,1115
> #define TRANSCEIVER_DATA_NUM_ELE 64
> #define TRANSCEIVER_DATA_SIZE 256
> #define TRANSCEIVER_A0_SIZE 128
> #define TRANSCEIVER_A2_SIZE 128
> #define PAGE_NUM_A0 0xa0
> #define PAGE_NUM_A2 0xa2
> #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
> || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
>