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oce_hw.h (231879) oce_hw.h (247880)
1/*-
2 * Copyright (C) 2012 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

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31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
1/*-
2 * Copyright (C) 2012 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

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31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39/* $FreeBSD: head/sys/dev/oce/oce_hw.h 231879 2012-02-17 13:55:17Z luigi $ */
39/* $FreeBSD: head/sys/dev/oce/oce_hw.h 247880 2013-03-06 09:53:38Z delphij $ */
40
40
41/* $FreeBSD: head/sys/dev/oce/oce_hw.h 247880 2013-03-06 09:53:38Z delphij $ */
42
41#include <sys/types.h>
42
43#undef _BIG_ENDIAN /* TODO */
44#pragma pack(1)
45
46#define OC_CNA_GEN2 0x2
47#define OC_CNA_GEN3 0x3
48#define DEVID_TIGERSHARK 0x700

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150#define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
151
152#define MBX_DB_READY_BIT 0x1
153#define MBX_DB_HI_BIT 0x2
154#define ASYNC_EVENT_CODE_LINK_STATE 0x1
155#define ASYNC_EVENT_LINK_UP 0x1
156#define ASYNC_EVENT_LINK_DOWN 0x0
157#define ASYNC_EVENT_GRP5 0x5
43#include <sys/types.h>
44
45#undef _BIG_ENDIAN /* TODO */
46#pragma pack(1)
47
48#define OC_CNA_GEN2 0x2
49#define OC_CNA_GEN3 0x3
50#define DEVID_TIGERSHARK 0x700

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152#define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
153
154#define MBX_DB_READY_BIT 0x1
155#define MBX_DB_HI_BIT 0x2
156#define ASYNC_EVENT_CODE_LINK_STATE 0x1
157#define ASYNC_EVENT_LINK_UP 0x1
158#define ASYNC_EVENT_LINK_DOWN 0x0
159#define ASYNC_EVENT_GRP5 0x5
160#define ASYNC_EVENT_CODE_DEBUG 0x6
158#define ASYNC_EVENT_PVID_STATE 0x3
161#define ASYNC_EVENT_PVID_STATE 0x3
162#define ASYNC_EVENT_DEBUG_QNQ 0x1
163#define ASYNC_EVENT_CODE_SLIPORT 0x11
159#define VLAN_VID_MASK 0x0FFF
160
161/* port link_status */
162#define ASYNC_EVENT_LOGICAL 0x02
163
164/* Logical Link Status */
165#define NTWK_LOGICAL_LINK_DOWN 0
166#define NTWK_LOGICAL_LINK_UP 1

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702 uint8_t enabled;
703 uint8_t rsvd0;
704 uint16_t tag;
705 uint32_t event_tag;
706 uint32_t rsvd1;
707 uint32_t code;
708};
709
164#define VLAN_VID_MASK 0x0FFF
165
166/* port link_status */
167#define ASYNC_EVENT_LOGICAL 0x02
168
169/* Logical Link Status */
170#define NTWK_LOGICAL_LINK_DOWN 0
171#define NTWK_LOGICAL_LINK_UP 1

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707 uint8_t enabled;
708 uint8_t rsvd0;
709 uint16_t tag;
710 uint32_t event_tag;
711 uint32_t rsvd1;
712 uint32_t code;
713};
714
715/* async event indicating outer VLAN tag in QnQ */
716struct oce_async_event_qnq {
717 uint8_t valid; /* Indicates if outer VLAN is valid */
718 uint8_t rsvd0;
719 uint16_t vlan_tag;
720 uint32_t event_tag;
721 uint8_t rsvd1[4];
722 uint32_t code;
723} ;
724
725
710typedef union oce_mq_ext_ctx_u {
711 uint32_t dw[6];
712 struct {
713 #ifdef _BIG_ENDIAN
714 /* dw0 */
715 uint32_t dw4rsvd1:16;
716 uint32_t num_pages:16;
717 /* dw1 */

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745 /* dw4 */
746 uint32_t async_cq_valid:1;
747 uint32_t async_cq_id:10;
748 uint32_t dw7rsvd1:21;
749 #endif
750 /* dw5 */
751 uint32_t dw8rsvd1;
752 } v0;
726typedef union oce_mq_ext_ctx_u {
727 uint32_t dw[6];
728 struct {
729 #ifdef _BIG_ENDIAN
730 /* dw0 */
731 uint32_t dw4rsvd1:16;
732 uint32_t num_pages:16;
733 /* dw1 */

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761 /* dw4 */
762 uint32_t async_cq_valid:1;
763 uint32_t async_cq_id:10;
764 uint32_t dw7rsvd1:21;
765 #endif
766 /* dw5 */
767 uint32_t dw8rsvd1;
768 } v0;
769 struct {
770 #ifdef _BIG_ENDIAN
771 /* dw0 */
772 uint32_t cq_id:16;
773 uint32_t num_pages:16;
774 /* dw1 */
775 uint32_t async_evt_bitmap;
776 /* dw2 */
777 uint32_t dw5rsvd2:12;
778 uint32_t ring_size:4;
779 uint32_t async_cq_id:16;
780 /* dw3 */
781 uint32_t valid:1;
782 uint32_t dw6rsvd1:31;
783 /* dw4 */
784 uint32_t dw7rsvd1:31;
785 uint32_t async_cq_valid:1;
786 #else
787 /* dw0 */
788 uint32_t num_pages:16;
789 uint32_t cq_id:16;
790 /* dw1 */
791 uint32_t async_evt_bitmap;
792 /* dw2 */
793 uint32_t async_cq_id:16;
794 uint32_t ring_size:4;
795 uint32_t dw5rsvd2:12;
796 /* dw3 */
797 uint32_t dw6rsvd1:31;
798 uint32_t valid:1;
799 /* dw4 */
800 uint32_t async_cq_valid:1;
801 uint32_t dw7rsvd1:31;
802 #endif
803 /* dw5 */
804 uint32_t dw8rsvd1;
805 } v1;
806
753} oce_mq_ext_ctx_t;
754
755
756/* MQ mailbox structure */
757struct oce_bmbx {
758 struct oce_mbx mbx;
759 struct oce_mq_cqe cqe;
760};

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821 OPCODE_COMMON_DEL_IFACE_MAC = 60,
822 OPCODE_COMMON_FUNCTION_RESET = 61,
823 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
824 OPCODE_COMMON_GET_BOOT_CONFIG = 66,
825 OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
826 OPCODE_COMMON_SET_BEACON_CONFIG = 69,
827 OPCODE_COMMON_GET_BEACON_CONFIG = 70,
828 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
807} oce_mq_ext_ctx_t;
808
809
810/* MQ mailbox structure */
811struct oce_bmbx {
812 struct oce_mbx mbx;
813 struct oce_mq_cqe cqe;
814};

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875 OPCODE_COMMON_DEL_IFACE_MAC = 60,
876 OPCODE_COMMON_FUNCTION_RESET = 61,
877 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
878 OPCODE_COMMON_GET_BOOT_CONFIG = 66,
879 OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
880 OPCODE_COMMON_SET_BEACON_CONFIG = 69,
881 OPCODE_COMMON_GET_BEACON_CONFIG = 70,
882 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
883 OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73,
829 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
830 OPCODE_COMMON_GET_PORT_NAME = 77,
831 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
832 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
833 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
834 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
835 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
836 OPCODE_COMMON_GET_RESET_NEEDED = 84,

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1719struct mbx_set_common_iface_rx_filter {
1720 struct mbx_hdr hdr;
1721 union {
1722 iface_rx_filter_ctx_t req;
1723 iface_rx_filter_ctx_t rsp;
1724 } params;
1725};
1726
884 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
885 OPCODE_COMMON_GET_PORT_NAME = 77,
886 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
887 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
888 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
889 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
890 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
891 OPCODE_COMMON_GET_RESET_NEEDED = 84,

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1774struct mbx_set_common_iface_rx_filter {
1775 struct mbx_hdr hdr;
1776 union {
1777 iface_rx_filter_ctx_t req;
1778 iface_rx_filter_ctx_t rsp;
1779 } params;
1780};
1781
1782struct be_set_eqd {
1783 uint32_t eq_id;
1784 uint32_t phase;
1785 uint32_t dm;
1786};
1787
1727/* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
1728struct mbx_modify_common_eq_delay {
1729 struct mbx_hdr hdr;
1730 union {
1731 struct {
1732 uint32_t num_eq;
1733 struct {
1734 uint32_t eq_id;
1735 uint32_t phase;
1736 uint32_t dm;
1737 } delay[8];
1738 } req;
1739
1740 struct {
1741 uint32_t rsvd0;
1742 } rsp;
1743 } params;
1744};
1745
1788/* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
1789struct mbx_modify_common_eq_delay {
1790 struct mbx_hdr hdr;
1791 union {
1792 struct {
1793 uint32_t num_eq;
1794 struct {
1795 uint32_t eq_id;
1796 uint32_t phase;
1797 uint32_t dm;
1798 } delay[8];
1799 } req;
1800
1801 struct {
1802 uint32_t rsvd0;
1803 } rsp;
1804 } params;
1805};
1806
1807/* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */
1808
1809struct mgmt_hba_attr {
1810 int8_t flashrom_ver_str[32];
1811 int8_t manufac_name[32];
1812 uint32_t supp_modes;
1813 int8_t seeprom_ver_lo;
1814 int8_t seeprom_ver_hi;
1815 int8_t rsvd0[2];
1816 uint32_t ioctl_data_struct_ver;
1817 uint32_t ep_fw_data_struct_ver;
1818 uint8_t ncsi_ver_str[12];
1819 uint32_t def_ext_to;
1820 int8_t cntl_mod_num[32];
1821 int8_t cntl_desc[64];
1822 int8_t cntl_ser_num[32];
1823 int8_t ip_ver_str[32];
1824 int8_t fw_ver_str[32];
1825 int8_t bios_ver_str[32];
1826 int8_t redboot_ver_str[32];
1827 int8_t drv_ver_str[32];
1828 int8_t fw_on_flash_ver_str[32];
1829 uint32_t funcs_supp;
1830 uint16_t max_cdblen;
1831 uint8_t asic_rev;
1832 uint8_t gen_guid[16];
1833 uint8_t hba_port_count;
1834 uint16_t default_link_down_timeout;
1835 uint8_t iscsi_ver_min_max;
1836 uint8_t multifunc_dev;
1837 uint8_t cache_valid;
1838 uint8_t hba_status;
1839 uint8_t max_domains_supp;
1840 uint8_t phy_port;
1841 uint32_t fw_post_status;
1842 uint32_t hba_mtu[8];
1843 uint8_t iSCSI_feat;
1844 uint8_t asic_gen;
1845 uint8_t future_u8[2];
1846 uint32_t future_u32[3];
1847};
1848
1849struct mgmt_cntl_attr {
1850 struct mgmt_hba_attr hba_attr;
1851 uint16_t pci_vendor_id;
1852 uint16_t pci_device_id;
1853 uint16_t pci_sub_vendor_id;
1854 uint16_t pci_sub_system_id;
1855 uint8_t pci_bus_num;
1856 uint8_t pci_dev_num;
1857 uint8_t pci_func_num;
1858 uint8_t interface_type;
1859 uint64_t unique_id;
1860 uint8_t netfilters;
1861 uint8_t rsvd0[3];
1862 uint32_t future_u32[4];
1863};
1864
1865struct mbx_common_get_cntl_attr {
1866 struct mbx_hdr hdr;
1867 union {
1868 struct {
1869 uint32_t rsvd0;
1870 } req;
1871 struct {
1872 struct mgmt_cntl_attr cntl_attr_info;
1873 } rsp;
1874 } params;
1875};
1876
1746/* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1747struct mbx_add_common_iface_mac {
1748 struct mbx_hdr hdr;
1749 union {
1750 struct {
1751 uint32_t if_id;
1752 uint8_t mac_address[6];
1753 uint8_t rsvd0[2];

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1780 } rsp;
1781};
1782
1783/* [61] OPCODE_COMMON_FUNCTION_RESET */
1784struct ioctl_common_function_reset {
1785 struct mbx_hdr hdr;
1786};
1787
1877/* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1878struct mbx_add_common_iface_mac {
1879 struct mbx_hdr hdr;
1880 union {
1881 struct {
1882 uint32_t if_id;
1883 uint8_t mac_address[6];
1884 uint8_t rsvd0[2];

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1911 } rsp;
1912};
1913
1914/* [61] OPCODE_COMMON_FUNCTION_RESET */
1915struct ioctl_common_function_reset {
1916 struct mbx_hdr hdr;
1917};
1918
1919/* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */
1920struct mbx_read_common_transrecv_data {
1921 struct mbx_hdr hdr;
1922 union {
1923 struct {
1924 uint32_t page_num;
1925 uint32_t port;
1926 } req;
1927 struct {
1928 uint32_t page_num;
1929 uint32_t port;
1930 uint32_t page_data[32];
1931 } rsp;
1932 } params;
1933
1934};
1935
1788/* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1789struct mbx_common_func_link_cfg {
1790 struct mbx_hdr hdr;
1791 union {
1792 struct {
1793 uint32_t enable;
1794 } req;
1795 struct {

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2105};
2106
2107/* Hash option flags for RSS enable */
2108enum RSS_ENABLE_FLAGS {
2109 RSS_ENABLE_NONE = 0x0, /* (No RSS) */
2110 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */
2111 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */
2112 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */
1936/* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1937struct mbx_common_func_link_cfg {
1938 struct mbx_hdr hdr;
1939 union {
1940 struct {
1941 uint32_t enable;
1942 } req;
1943 struct {

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2253};
2254
2255/* Hash option flags for RSS enable */
2256enum RSS_ENABLE_FLAGS {
2257 RSS_ENABLE_NONE = 0x0, /* (No RSS) */
2258 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */
2259 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */
2260 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */
2113 RSS_ENABLE_TCP_IPV6 = 0x8 /* (TCP IPV6 HASH */
2261 RSS_ENABLE_TCP_IPV6 = 0x8, /* (TCP IPV6 HASH */
2262 RSS_ENABLE_UDP_IPV4 = 0x10, /* UDP IPV4 HASH */
2263 RSS_ENABLE_UDP_IPV6 = 0x20 /* UDP IPV6 HASH */
2114};
2115#define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
2116#define RSS_DISABLE RSS_ENABLE_NONE
2117
2118/* NIC header WQE */
2119struct oce_nic_hdr_wqe {
2120 union {
2121 struct {

--- 1343 unchanged lines hidden --- 		2264};
2265#define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
2266#define RSS_DISABLE RSS_ENABLE_NONE
2267
2268/* NIC header WQE */
2269struct oce_nic_hdr_wqe {
2270 union {
2271 struct {

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