1/*-
2 * Copyright (C) 2012 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
| 1/*-
2 * Copyright (C) 2012 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
|
39/* $FreeBSD: head/sys/dev/oce/oce_hw.h 231879 2012-02-17 13:55:17Z luigi $ */
| 39/* $FreeBSD: head/sys/dev/oce/oce_hw.h 247880 2013-03-06 09:53:38Z delphij $ */
|
40
| 40
|
| 41/* $FreeBSD: head/sys/dev/oce/oce_hw.h 247880 2013-03-06 09:53:38Z delphij $ */
42
|
41#include <sys/types.h>
42
43#undef _BIG_ENDIAN /* TODO */
44#pragma pack(1)
45
46#define OC_CNA_GEN2 0x2
47#define OC_CNA_GEN3 0x3
48#define DEVID_TIGERSHARK 0x700
49#define DEVID_TOMCAT 0x710
50
51/* PCI CSR offsets */
52#define PCICFG_F1_CSR 0x0 /* F1 for NIC */
53#define PCICFG_SEMAPHORE 0xbc
54#define PCICFG_SOFT_RESET 0x5c
55#define PCICFG_UE_STATUS_HI_MASK 0xac
56#define PCICFG_UE_STATUS_LO_MASK 0xa8
57#define PCICFG_ONLINE0 0xb0
58#define PCICFG_ONLINE1 0xb4
59#define INTR_EN 0x20000000
60#define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */
61
62/* CSR register offsets */
63#define MPU_EP_CONTROL 0
64#define MPU_EP_SEMAPHORE_BE3 0xac
65#define MPU_EP_SEMAPHORE_XE201 0x400
66#define MPU_EP_SEMAPHORE(sc) \
67 ((IS_BE(sc)) ? MPU_EP_SEMAPHORE_BE3 : MPU_EP_SEMAPHORE_XE201)
68#define PCICFG_INTR_CTRL 0xfc
69#define HOSTINTR_MASK (1 << 29)
70#define HOSTINTR_PFUNC_SHIFT 26
71#define HOSTINTR_PFUNC_MASK 7
72
73/* POST status reg struct */
74#define POST_STAGE_POWER_ON_RESET 0x00
75#define POST_STAGE_AWAITING_HOST_RDY 0x01
76#define POST_STAGE_HOST_RDY 0x02
77#define POST_STAGE_CHIP_RESET 0x03
78#define POST_STAGE_ARMFW_READY 0xc000
79#define POST_STAGE_ARMFW_UE 0xf000
80
81/* DOORBELL registers */
82#define PD_RXULP_DB 0x0100
83#define PD_TXULP_DB 0x0060
84#define DB_RQ_ID_MASK 0x3FF
85
86#define PD_CQ_DB 0x0120
87#define PD_EQ_DB PD_CQ_DB
88#define PD_MPU_MBOX_DB 0x0160
89#define PD_MQ_DB 0x0140
90
91/* EQE completion types */
92#define EQ_MINOR_CODE_COMPLETION 0x00
93#define EQ_MINOR_CODE_OTHER 0x01
94#define EQ_MAJOR_CODE_COMPLETION 0x00
95
96/* Link Status field values */
97#define PHY_LINK_FAULT_NONE 0x0
98#define PHY_LINK_FAULT_LOCAL 0x01
99#define PHY_LINK_FAULT_REMOTE 0x02
100
101#define PHY_LINK_SPEED_ZERO 0x0 /* No link */
102#define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
103#define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
104#define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
105#define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
106
107#define PHY_LINK_DUPLEX_NONE 0x0
108#define PHY_LINK_DUPLEX_HALF 0x1
109#define PHY_LINK_DUPLEX_FULL 0x2
110
111#define NTWK_PORT_A 0x0 /* (Port A) */
112#define NTWK_PORT_B 0x1 /* (Port B) */
113
114#define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */
115#define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
116#define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
117#define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
118#define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
119
120/* Hardware Address types */
121#define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */
122#define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */
123#define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */
124#define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */
125#define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */
126
127/* CREATE_IFACE capability and cap_en flags */
128#define MBX_RX_IFACE_FLAGS_RSS 0x4
129#define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8
130#define MBX_RX_IFACE_FLAGS_BROADCAST 0x10
131#define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20
132#define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80
133#define MBX_RX_IFACE_FLAGS_VLAN 0x100
134#define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200
135#define MBX_RX_IFACE_FLAGS_PASS_L2_ERR 0x400
136#define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR 0x800
137#define MBX_RX_IFACE_FLAGS_MULTICAST 0x1000
138#define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000
139#define MBX_RX_IFACE_FLAGS_HDS 0x4000
140#define MBX_RX_IFACE_FLAGS_DIRECTED 0x8000
141#define MBX_RX_IFACE_FLAGS_VMQ 0x10000
142#define MBX_RX_IFACE_FLAGS_NETQ 0x20000
143#define MBX_RX_IFACE_FLAGS_QGROUPS 0x40000
144#define MBX_RX_IFACE_FLAGS_LSO 0x80000
145#define MBX_RX_IFACE_FLAGS_LRO 0x100000
146
147#define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */
148#define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */
149#define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */
150#define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
151
152#define MBX_DB_READY_BIT 0x1
153#define MBX_DB_HI_BIT 0x2
154#define ASYNC_EVENT_CODE_LINK_STATE 0x1
155#define ASYNC_EVENT_LINK_UP 0x1
156#define ASYNC_EVENT_LINK_DOWN 0x0
157#define ASYNC_EVENT_GRP5 0x5
| 43#include <sys/types.h>
44
45#undef _BIG_ENDIAN /* TODO */
46#pragma pack(1)
47
48#define OC_CNA_GEN2 0x2
49#define OC_CNA_GEN3 0x3
50#define DEVID_TIGERSHARK 0x700
51#define DEVID_TOMCAT 0x710
52
53/* PCI CSR offsets */
54#define PCICFG_F1_CSR 0x0 /* F1 for NIC */
55#define PCICFG_SEMAPHORE 0xbc
56#define PCICFG_SOFT_RESET 0x5c
57#define PCICFG_UE_STATUS_HI_MASK 0xac
58#define PCICFG_UE_STATUS_LO_MASK 0xa8
59#define PCICFG_ONLINE0 0xb0
60#define PCICFG_ONLINE1 0xb4
61#define INTR_EN 0x20000000
62#define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */
63
64/* CSR register offsets */
65#define MPU_EP_CONTROL 0
66#define MPU_EP_SEMAPHORE_BE3 0xac
67#define MPU_EP_SEMAPHORE_XE201 0x400
68#define MPU_EP_SEMAPHORE(sc) \
69 ((IS_BE(sc)) ? MPU_EP_SEMAPHORE_BE3 : MPU_EP_SEMAPHORE_XE201)
70#define PCICFG_INTR_CTRL 0xfc
71#define HOSTINTR_MASK (1 << 29)
72#define HOSTINTR_PFUNC_SHIFT 26
73#define HOSTINTR_PFUNC_MASK 7
74
75/* POST status reg struct */
76#define POST_STAGE_POWER_ON_RESET 0x00
77#define POST_STAGE_AWAITING_HOST_RDY 0x01
78#define POST_STAGE_HOST_RDY 0x02
79#define POST_STAGE_CHIP_RESET 0x03
80#define POST_STAGE_ARMFW_READY 0xc000
81#define POST_STAGE_ARMFW_UE 0xf000
82
83/* DOORBELL registers */
84#define PD_RXULP_DB 0x0100
85#define PD_TXULP_DB 0x0060
86#define DB_RQ_ID_MASK 0x3FF
87
88#define PD_CQ_DB 0x0120
89#define PD_EQ_DB PD_CQ_DB
90#define PD_MPU_MBOX_DB 0x0160
91#define PD_MQ_DB 0x0140
92
93/* EQE completion types */
94#define EQ_MINOR_CODE_COMPLETION 0x00
95#define EQ_MINOR_CODE_OTHER 0x01
96#define EQ_MAJOR_CODE_COMPLETION 0x00
97
98/* Link Status field values */
99#define PHY_LINK_FAULT_NONE 0x0
100#define PHY_LINK_FAULT_LOCAL 0x01
101#define PHY_LINK_FAULT_REMOTE 0x02
102
103#define PHY_LINK_SPEED_ZERO 0x0 /* No link */
104#define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
105#define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
106#define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
107#define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
108
109#define PHY_LINK_DUPLEX_NONE 0x0
110#define PHY_LINK_DUPLEX_HALF 0x1
111#define PHY_LINK_DUPLEX_FULL 0x2
112
113#define NTWK_PORT_A 0x0 /* (Port A) */
114#define NTWK_PORT_B 0x1 /* (Port B) */
115
116#define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */
117#define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
118#define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
119#define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
120#define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
121
122/* Hardware Address types */
123#define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */
124#define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */
125#define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */
126#define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */
127#define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */
128
129/* CREATE_IFACE capability and cap_en flags */
130#define MBX_RX_IFACE_FLAGS_RSS 0x4
131#define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8
132#define MBX_RX_IFACE_FLAGS_BROADCAST 0x10
133#define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20
134#define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80
135#define MBX_RX_IFACE_FLAGS_VLAN 0x100
136#define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200
137#define MBX_RX_IFACE_FLAGS_PASS_L2_ERR 0x400
138#define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR 0x800
139#define MBX_RX_IFACE_FLAGS_MULTICAST 0x1000
140#define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000
141#define MBX_RX_IFACE_FLAGS_HDS 0x4000
142#define MBX_RX_IFACE_FLAGS_DIRECTED 0x8000
143#define MBX_RX_IFACE_FLAGS_VMQ 0x10000
144#define MBX_RX_IFACE_FLAGS_NETQ 0x20000
145#define MBX_RX_IFACE_FLAGS_QGROUPS 0x40000
146#define MBX_RX_IFACE_FLAGS_LSO 0x80000
147#define MBX_RX_IFACE_FLAGS_LRO 0x100000
148
149#define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */
150#define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */
151#define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */
152#define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
153
154#define MBX_DB_READY_BIT 0x1
155#define MBX_DB_HI_BIT 0x2
156#define ASYNC_EVENT_CODE_LINK_STATE 0x1
157#define ASYNC_EVENT_LINK_UP 0x1
158#define ASYNC_EVENT_LINK_DOWN 0x0
159#define ASYNC_EVENT_GRP5 0x5
|
| 160#define ASYNC_EVENT_CODE_DEBUG 0x6
|
158#define ASYNC_EVENT_PVID_STATE 0x3
| 161#define ASYNC_EVENT_PVID_STATE 0x3
|
| 162#define ASYNC_EVENT_DEBUG_QNQ 0x1
163#define ASYNC_EVENT_CODE_SLIPORT 0x11
|
159#define VLAN_VID_MASK 0x0FFF
160
161/* port link_status */
162#define ASYNC_EVENT_LOGICAL 0x02
163
164/* Logical Link Status */
165#define NTWK_LOGICAL_LINK_DOWN 0
166#define NTWK_LOGICAL_LINK_UP 1
167
168/* Rx filter bits */
169#define NTWK_RX_FILTER_IP_CKSUM 0x1
170#define NTWK_RX_FILTER_TCP_CKSUM 0x2
171#define NTWK_RX_FILTER_UDP_CKSUM 0x4
172#define NTWK_RX_FILTER_STRIP_CRC 0x8
173
174/* max SGE per mbx */
175#define MAX_MBX_SGE 19
176
177/* Max multicast filter size*/
178#define OCE_MAX_MC_FILTER_SIZE 64
179
180/* PCI SLI (Service Level Interface) capabilities register */
181#define OCE_INTF_REG_OFFSET 0x58
182#define OCE_INTF_VALID_SIG 6 /* register's signature */
183#define OCE_INTF_FUNC_RESET_REQD 1
184#define OCE_INTF_HINT1_NOHINT 0
185#define OCE_INTF_HINT1_SEMAINIT 1
186#define OCE_INTF_HINT1_STATCTRL 2
187#define OCE_INTF_IF_TYPE_0 0
188#define OCE_INTF_IF_TYPE_1 1
189#define OCE_INTF_IF_TYPE_2 2
190#define OCE_INTF_IF_TYPE_3 3
191#define OCE_INTF_SLI_REV3 3 /* not supported by driver */
192#define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */
193#define OCE_INTF_PHYS_FUNC 0
194#define OCE_INTF_VIRT_FUNC 1
195#define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */
196#define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */
197#define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */
198#define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */
199
200#define NIC_WQE_SIZE 16
201#define NIC_UNICAST 0x00
202#define NIC_MULTICAST 0x01
203#define NIC_BROADCAST 0x02
204
205#define NIC_HDS_NO_SPLIT 0x00
206#define NIC_HDS_SPLIT_L3PL 0x01
207#define NIC_HDS_SPLIT_L4PL 0x02
208
209#define NIC_WQ_TYPE_FORWARDING 0x01
210#define NIC_WQ_TYPE_STANDARD 0x02
211#define NIC_WQ_TYPE_LOW_LATENCY 0x04
212
213#define OCE_RESET_STATS 1
214#define OCE_RETAIN_STATS 0
215#define OCE_TXP_SW_SZ 48
216
217typedef union pci_sli_intf_u {
218 uint32_t dw0;
219 struct {
220#ifdef _BIG_ENDIAN
221 uint32_t sli_valid:3;
222 uint32_t sli_hint2:5;
223 uint32_t sli_hint1:8;
224 uint32_t sli_if_type:4;
225 uint32_t sli_family:4;
226 uint32_t sli_rev:4;
227 uint32_t rsv0:3;
228 uint32_t sli_func_type:1;
229#else
230 uint32_t sli_func_type:1;
231 uint32_t rsv0:3;
232 uint32_t sli_rev:4;
233 uint32_t sli_family:4;
234 uint32_t sli_if_type:4;
235 uint32_t sli_hint1:8;
236 uint32_t sli_hint2:5;
237 uint32_t sli_valid:3;
238#endif
239 } bits;
240} pci_sli_intf_t;
241
242
243
244/* physical address structure to be used in MBX */
245struct phys_addr {
246 /* dw0 */
247 uint32_t lo;
248 /* dw1 */
249 uint32_t hi;
250};
251
252
253
254typedef union pcicfg_intr_ctl_u {
255 uint32_t dw0;
256 struct {
257#ifdef _BIG_ENDIAN
258 uint32_t winselect:2;
259 uint32_t hostintr:1;
260 uint32_t pfnum:3;
261 uint32_t vf_cev_int_line_en:1;
262 uint32_t winaddr:23;
263 uint32_t membarwinen:1;
264#else
265 uint32_t membarwinen:1;
266 uint32_t winaddr:23;
267 uint32_t vf_cev_int_line_en:1;
268 uint32_t pfnum:3;
269 uint32_t hostintr:1;
270 uint32_t winselect:2;
271#endif
272 } bits;
273} pcicfg_intr_ctl_t;
274
275
276
277
278typedef union pcicfg_semaphore_u {
279 uint32_t dw0;
280 struct {
281#ifdef _BIG_ENDIAN
282 uint32_t rsvd:31;
283 uint32_t lock:1;
284#else
285 uint32_t lock:1;
286 uint32_t rsvd:31;
287#endif
288 } bits;
289} pcicfg_semaphore_t;
290
291
292
293
294typedef union pcicfg_soft_reset_u {
295 uint32_t dw0;
296 struct {
297#ifdef _BIG_ENDIAN
298 uint32_t nec_ll_rcvdetect:8;
299 uint32_t dbg_all_reqs_62_49:14;
300 uint32_t scratchpad0:1;
301 uint32_t exception_oe:1;
302 uint32_t soft_reset:1;
303 uint32_t rsvd0:7;
304#else
305 uint32_t rsvd0:7;
306 uint32_t soft_reset:1;
307 uint32_t exception_oe:1;
308 uint32_t scratchpad0:1;
309 uint32_t dbg_all_reqs_62_49:14;
310 uint32_t nec_ll_rcvdetect:8;
311#endif
312 } bits;
313} pcicfg_soft_reset_t;
314
315
316
317
318typedef union pcicfg_online1_u {
319 uint32_t dw0;
320 struct {
321#ifdef _BIG_ENDIAN
322 uint32_t host8_online:1;
323 uint32_t host7_online:1;
324 uint32_t host6_online:1;
325 uint32_t host5_online:1;
326 uint32_t host4_online:1;
327 uint32_t host3_online:1;
328 uint32_t host2_online:1;
329 uint32_t ipc_online:1;
330 uint32_t arm_online:1;
331 uint32_t txp_online:1;
332 uint32_t xaui_online:1;
333 uint32_t rxpp_online:1;
334 uint32_t txpb_online:1;
335 uint32_t rr_online:1;
336 uint32_t pmem_online:1;
337 uint32_t pctl1_online:1;
338 uint32_t pctl0_online:1;
339 uint32_t pcs1online_online:1;
340 uint32_t mpu_iram_online:1;
341 uint32_t pcs0online_online:1;
342 uint32_t mgmt_mac_online:1;
343 uint32_t lpcmemhost_online:1;
344#else
345 uint32_t lpcmemhost_online:1;
346 uint32_t mgmt_mac_online:1;
347 uint32_t pcs0online_online:1;
348 uint32_t mpu_iram_online:1;
349 uint32_t pcs1online_online:1;
350 uint32_t pctl0_online:1;
351 uint32_t pctl1_online:1;
352 uint32_t pmem_online:1;
353 uint32_t rr_online:1;
354 uint32_t txpb_online:1;
355 uint32_t rxpp_online:1;
356 uint32_t xaui_online:1;
357 uint32_t txp_online:1;
358 uint32_t arm_online:1;
359 uint32_t ipc_online:1;
360 uint32_t host2_online:1;
361 uint32_t host3_online:1;
362 uint32_t host4_online:1;
363 uint32_t host5_online:1;
364 uint32_t host6_online:1;
365 uint32_t host7_online:1;
366 uint32_t host8_online:1;
367#endif
368 } bits;
369} pcicfg_online1_t;
370
371
372
373typedef union mpu_ep_semaphore_u {
374 uint32_t dw0;
375 struct {
376#ifdef _BIG_ENDIAN
377 uint32_t error:1;
378 uint32_t backup_fw:1;
379 uint32_t iscsi_no_ip:1;
380 uint32_t iscsi_ip_conflict:1;
381 uint32_t option_rom_installed:1;
382 uint32_t iscsi_drv_loaded:1;
383 uint32_t rsvd0:10;
384 uint32_t stage:16;
385#else
386 uint32_t stage:16;
387 uint32_t rsvd0:10;
388 uint32_t iscsi_drv_loaded:1;
389 uint32_t option_rom_installed:1;
390 uint32_t iscsi_ip_conflict:1;
391 uint32_t iscsi_no_ip:1;
392 uint32_t backup_fw:1;
393 uint32_t error:1;
394#endif
395 } bits;
396} mpu_ep_semaphore_t;
397
398
399
400
401typedef union mpu_ep_control_u {
402 uint32_t dw0;
403 struct {
404#ifdef _BIG_ENDIAN
405 uint32_t cpu_reset:1;
406 uint32_t rsvd1:15;
407 uint32_t ep_ram_init_status:1;
408 uint32_t rsvd0:12;
409 uint32_t m2_rxpbuf:1;
410 uint32_t m1_rxpbuf:1;
411 uint32_t m0_rxpbuf:1;
412#else
413 uint32_t m0_rxpbuf:1;
414 uint32_t m1_rxpbuf:1;
415 uint32_t m2_rxpbuf:1;
416 uint32_t rsvd0:12;
417 uint32_t ep_ram_init_status:1;
418 uint32_t rsvd1:15;
419 uint32_t cpu_reset:1;
420#endif
421 } bits;
422} mpu_ep_control_t;
423
424
425
426
427/* RX doorbell */
428typedef union pd_rxulp_db_u {
429 uint32_t dw0;
430 struct {
431#ifdef _BIG_ENDIAN
432 uint32_t num_posted:8;
433 uint32_t invalidate:1;
434 uint32_t rsvd1:13;
435 uint32_t qid:10;
436#else
437 uint32_t qid:10;
438 uint32_t rsvd1:13;
439 uint32_t invalidate:1;
440 uint32_t num_posted:8;
441#endif
442 } bits;
443} pd_rxulp_db_t;
444
445
446/* TX doorbell */
447typedef union pd_txulp_db_u {
448 uint32_t dw0;
449 struct {
450#ifdef _BIG_ENDIAN
451 uint32_t rsvd1:2;
452 uint32_t num_posted:14;
453 uint32_t rsvd0:6;
454 uint32_t qid:10;
455#else
456 uint32_t qid:10;
457 uint32_t rsvd0:6;
458 uint32_t num_posted:14;
459 uint32_t rsvd1:2;
460#endif
461 } bits;
462} pd_txulp_db_t;
463
464/* CQ doorbell */
465typedef union cq_db_u {
466 uint32_t dw0;
467 struct {
468#ifdef _BIG_ENDIAN
469 uint32_t rsvd1:2;
470 uint32_t rearm:1;
471 uint32_t num_popped:13;
472 uint32_t rsvd0:5;
473 uint32_t event:1;
474 uint32_t qid:10;
475#else
476 uint32_t qid:10;
477 uint32_t event:1;
478 uint32_t rsvd0:5;
479 uint32_t num_popped:13;
480 uint32_t rearm:1;
481 uint32_t rsvd1:2;
482#endif
483 } bits;
484} cq_db_t;
485
486/* EQ doorbell */
487typedef union eq_db_u {
488 uint32_t dw0;
489 struct {
490#ifdef _BIG_ENDIAN
491 uint32_t rsvd1:2;
492 uint32_t rearm:1;
493 uint32_t num_popped:13;
494 uint32_t rsvd0:5;
495 uint32_t event:1;
496 uint32_t clrint:1;
497 uint32_t qid:9;
498#else
499 uint32_t qid:9;
500 uint32_t clrint:1;
501 uint32_t event:1;
502 uint32_t rsvd0:5;
503 uint32_t num_popped:13;
504 uint32_t rearm:1;
505 uint32_t rsvd1:2;
506#endif
507 } bits;
508} eq_db_t;
509
510/* bootstrap mbox doorbell */
511typedef union pd_mpu_mbox_db_u {
512 uint32_t dw0;
513 struct {
514#ifdef _BIG_ENDIAN
515 uint32_t address:30;
516 uint32_t hi:1;
517 uint32_t ready:1;
518#else
519 uint32_t ready:1;
520 uint32_t hi:1;
521 uint32_t address:30;
522#endif
523 } bits;
524} pd_mpu_mbox_db_t;
525
526/* MQ ring doorbell */
527typedef union pd_mq_db_u {
528 uint32_t dw0;
529 struct {
530#ifdef _BIG_ENDIAN
531 uint32_t rsvd1:2;
532 uint32_t num_posted:14;
533 uint32_t rsvd0:5;
534 uint32_t mq_id:11;
535#else
536 uint32_t mq_id:11;
537 uint32_t rsvd0:5;
538 uint32_t num_posted:14;
539 uint32_t rsvd1:2;
540#endif
541 } bits;
542} pd_mq_db_t;
543
544/*
545 * Event Queue Entry
546 */
547struct oce_eqe {
548 uint32_t evnt;
549};
550
551/* MQ scatter gather entry. Array of these make an SGL */
552struct oce_mq_sge {
553 uint32_t pa_lo;
554 uint32_t pa_hi;
555 uint32_t length;
556};
557
558/*
559 * payload can contain an SGL or an embedded array of upto 59 dwords
560 */
561struct oce_mbx_payload {
562 union {
563 union {
564 struct oce_mq_sge sgl[MAX_MBX_SGE];
565 uint32_t embedded[59];
566 } u1;
567 uint32_t dw[59];
568 } u0;
569};
570
571/*
572 * MQ MBX structure
573 */
574struct oce_mbx {
575 union {
576 struct {
577#ifdef _BIG_ENDIAN
578 uint32_t special:8;
579 uint32_t rsvd1:16;
580 uint32_t sge_count:5;
581 uint32_t rsvd0:2;
582 uint32_t embedded:1;
583#else
584 uint32_t embedded:1;
585 uint32_t rsvd0:2;
586 uint32_t sge_count:5;
587 uint32_t rsvd1:16;
588 uint32_t special:8;
589#endif
590 } s;
591 uint32_t dw0;
592 } u0;
593
594 uint32_t payload_length;
595 uint32_t tag[2];
596 uint32_t rsvd2[1];
597 struct oce_mbx_payload payload;
598};
599
600/* completion queue entry for MQ */
601struct oce_mq_cqe {
602 union {
603 struct {
604#ifdef _BIG_ENDIAN
605 /* dw0 */
606 uint32_t extended_status:16;
607 uint32_t completion_status:16;
608 /* dw1 dw2 */
609 uint32_t mq_tag[2];
610 /* dw3 */
611 uint32_t valid:1;
612 uint32_t async_event:1;
613 uint32_t hpi_buffer_cmpl:1;
614 uint32_t completed:1;
615 uint32_t consumed:1;
616 uint32_t rsvd0:3;
617 uint32_t async_type:8;
618 uint32_t event_type:8;
619 uint32_t rsvd1:8;
620#else
621 /* dw0 */
622 uint32_t completion_status:16;
623 uint32_t extended_status:16;
624 /* dw1 dw2 */
625 uint32_t mq_tag[2];
626 /* dw3 */
627 uint32_t rsvd1:8;
628 uint32_t event_type:8;
629 uint32_t async_type:8;
630 uint32_t rsvd0:3;
631 uint32_t consumed:1;
632 uint32_t completed:1;
633 uint32_t hpi_buffer_cmpl:1;
634 uint32_t async_event:1;
635 uint32_t valid:1;
636#endif
637 } s;
638 uint32_t dw[4];
639 } u0;
640};
641
642/* Mailbox Completion Status Codes */
643enum MBX_COMPLETION_STATUS {
644 MBX_CQE_STATUS_SUCCESS = 0x00,
645 MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01,
646 MBX_CQE_STATUS_INVALID_PARAMETER = 0x02,
647 MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03,
648 MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04,
649 MBX_CQE_STATUS_DMA_FAILED = 0x05
650};
651
652struct oce_async_cqe_link_state {
653 union {
654 struct {
655#ifdef _BIG_ENDIAN
656 /* dw0 */
657 uint8_t speed;
658 uint8_t duplex;
659 uint8_t link_status;
660 uint8_t phy_port;
661 /* dw1 */
662 uint16_t qos_link_speed;
663 uint8_t rsvd0;
664 uint8_t fault;
665 /* dw2 */
666 uint32_t event_tag;
667 /* dw3 */
668 uint32_t valid:1;
669 uint32_t async_event:1;
670 uint32_t rsvd2:6;
671 uint32_t event_type:8;
672 uint32_t event_code:8;
673 uint32_t rsvd1:8;
674#else
675 /* dw0 */
676 uint8_t phy_port;
677 uint8_t link_status;
678 uint8_t duplex;
679 uint8_t speed;
680 /* dw1 */
681 uint8_t fault;
682 uint8_t rsvd0;
683 uint16_t qos_link_speed;
684 /* dw2 */
685 uint32_t event_tag;
686 /* dw3 */
687 uint32_t rsvd1:8;
688 uint32_t event_code:8;
689 uint32_t event_type:8;
690 uint32_t rsvd2:6;
691 uint32_t async_event:1;
692 uint32_t valid:1;
693#endif
694 } s;
695 uint32_t dw[4];
696 } u0;
697};
698
699
700/* PVID aync event */
701struct oce_async_event_grp5_pvid_state {
702 uint8_t enabled;
703 uint8_t rsvd0;
704 uint16_t tag;
705 uint32_t event_tag;
706 uint32_t rsvd1;
707 uint32_t code;
708};
709
| 164#define VLAN_VID_MASK 0x0FFF
165
166/* port link_status */
167#define ASYNC_EVENT_LOGICAL 0x02
168
169/* Logical Link Status */
170#define NTWK_LOGICAL_LINK_DOWN 0
171#define NTWK_LOGICAL_LINK_UP 1
172
173/* Rx filter bits */
174#define NTWK_RX_FILTER_IP_CKSUM 0x1
175#define NTWK_RX_FILTER_TCP_CKSUM 0x2
176#define NTWK_RX_FILTER_UDP_CKSUM 0x4
177#define NTWK_RX_FILTER_STRIP_CRC 0x8
178
179/* max SGE per mbx */
180#define MAX_MBX_SGE 19
181
182/* Max multicast filter size*/
183#define OCE_MAX_MC_FILTER_SIZE 64
184
185/* PCI SLI (Service Level Interface) capabilities register */
186#define OCE_INTF_REG_OFFSET 0x58
187#define OCE_INTF_VALID_SIG 6 /* register's signature */
188#define OCE_INTF_FUNC_RESET_REQD 1
189#define OCE_INTF_HINT1_NOHINT 0
190#define OCE_INTF_HINT1_SEMAINIT 1
191#define OCE_INTF_HINT1_STATCTRL 2
192#define OCE_INTF_IF_TYPE_0 0
193#define OCE_INTF_IF_TYPE_1 1
194#define OCE_INTF_IF_TYPE_2 2
195#define OCE_INTF_IF_TYPE_3 3
196#define OCE_INTF_SLI_REV3 3 /* not supported by driver */
197#define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */
198#define OCE_INTF_PHYS_FUNC 0
199#define OCE_INTF_VIRT_FUNC 1
200#define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */
201#define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */
202#define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */
203#define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */
204
205#define NIC_WQE_SIZE 16
206#define NIC_UNICAST 0x00
207#define NIC_MULTICAST 0x01
208#define NIC_BROADCAST 0x02
209
210#define NIC_HDS_NO_SPLIT 0x00
211#define NIC_HDS_SPLIT_L3PL 0x01
212#define NIC_HDS_SPLIT_L4PL 0x02
213
214#define NIC_WQ_TYPE_FORWARDING 0x01
215#define NIC_WQ_TYPE_STANDARD 0x02
216#define NIC_WQ_TYPE_LOW_LATENCY 0x04
217
218#define OCE_RESET_STATS 1
219#define OCE_RETAIN_STATS 0
220#define OCE_TXP_SW_SZ 48
221
222typedef union pci_sli_intf_u {
223 uint32_t dw0;
224 struct {
225#ifdef _BIG_ENDIAN
226 uint32_t sli_valid:3;
227 uint32_t sli_hint2:5;
228 uint32_t sli_hint1:8;
229 uint32_t sli_if_type:4;
230 uint32_t sli_family:4;
231 uint32_t sli_rev:4;
232 uint32_t rsv0:3;
233 uint32_t sli_func_type:1;
234#else
235 uint32_t sli_func_type:1;
236 uint32_t rsv0:3;
237 uint32_t sli_rev:4;
238 uint32_t sli_family:4;
239 uint32_t sli_if_type:4;
240 uint32_t sli_hint1:8;
241 uint32_t sli_hint2:5;
242 uint32_t sli_valid:3;
243#endif
244 } bits;
245} pci_sli_intf_t;
246
247
248
249/* physical address structure to be used in MBX */
250struct phys_addr {
251 /* dw0 */
252 uint32_t lo;
253 /* dw1 */
254 uint32_t hi;
255};
256
257
258
259typedef union pcicfg_intr_ctl_u {
260 uint32_t dw0;
261 struct {
262#ifdef _BIG_ENDIAN
263 uint32_t winselect:2;
264 uint32_t hostintr:1;
265 uint32_t pfnum:3;
266 uint32_t vf_cev_int_line_en:1;
267 uint32_t winaddr:23;
268 uint32_t membarwinen:1;
269#else
270 uint32_t membarwinen:1;
271 uint32_t winaddr:23;
272 uint32_t vf_cev_int_line_en:1;
273 uint32_t pfnum:3;
274 uint32_t hostintr:1;
275 uint32_t winselect:2;
276#endif
277 } bits;
278} pcicfg_intr_ctl_t;
279
280
281
282
283typedef union pcicfg_semaphore_u {
284 uint32_t dw0;
285 struct {
286#ifdef _BIG_ENDIAN
287 uint32_t rsvd:31;
288 uint32_t lock:1;
289#else
290 uint32_t lock:1;
291 uint32_t rsvd:31;
292#endif
293 } bits;
294} pcicfg_semaphore_t;
295
296
297
298
299typedef union pcicfg_soft_reset_u {
300 uint32_t dw0;
301 struct {
302#ifdef _BIG_ENDIAN
303 uint32_t nec_ll_rcvdetect:8;
304 uint32_t dbg_all_reqs_62_49:14;
305 uint32_t scratchpad0:1;
306 uint32_t exception_oe:1;
307 uint32_t soft_reset:1;
308 uint32_t rsvd0:7;
309#else
310 uint32_t rsvd0:7;
311 uint32_t soft_reset:1;
312 uint32_t exception_oe:1;
313 uint32_t scratchpad0:1;
314 uint32_t dbg_all_reqs_62_49:14;
315 uint32_t nec_ll_rcvdetect:8;
316#endif
317 } bits;
318} pcicfg_soft_reset_t;
319
320
321
322
323typedef union pcicfg_online1_u {
324 uint32_t dw0;
325 struct {
326#ifdef _BIG_ENDIAN
327 uint32_t host8_online:1;
328 uint32_t host7_online:1;
329 uint32_t host6_online:1;
330 uint32_t host5_online:1;
331 uint32_t host4_online:1;
332 uint32_t host3_online:1;
333 uint32_t host2_online:1;
334 uint32_t ipc_online:1;
335 uint32_t arm_online:1;
336 uint32_t txp_online:1;
337 uint32_t xaui_online:1;
338 uint32_t rxpp_online:1;
339 uint32_t txpb_online:1;
340 uint32_t rr_online:1;
341 uint32_t pmem_online:1;
342 uint32_t pctl1_online:1;
343 uint32_t pctl0_online:1;
344 uint32_t pcs1online_online:1;
345 uint32_t mpu_iram_online:1;
346 uint32_t pcs0online_online:1;
347 uint32_t mgmt_mac_online:1;
348 uint32_t lpcmemhost_online:1;
349#else
350 uint32_t lpcmemhost_online:1;
351 uint32_t mgmt_mac_online:1;
352 uint32_t pcs0online_online:1;
353 uint32_t mpu_iram_online:1;
354 uint32_t pcs1online_online:1;
355 uint32_t pctl0_online:1;
356 uint32_t pctl1_online:1;
357 uint32_t pmem_online:1;
358 uint32_t rr_online:1;
359 uint32_t txpb_online:1;
360 uint32_t rxpp_online:1;
361 uint32_t xaui_online:1;
362 uint32_t txp_online:1;
363 uint32_t arm_online:1;
364 uint32_t ipc_online:1;
365 uint32_t host2_online:1;
366 uint32_t host3_online:1;
367 uint32_t host4_online:1;
368 uint32_t host5_online:1;
369 uint32_t host6_online:1;
370 uint32_t host7_online:1;
371 uint32_t host8_online:1;
372#endif
373 } bits;
374} pcicfg_online1_t;
375
376
377
378typedef union mpu_ep_semaphore_u {
379 uint32_t dw0;
380 struct {
381#ifdef _BIG_ENDIAN
382 uint32_t error:1;
383 uint32_t backup_fw:1;
384 uint32_t iscsi_no_ip:1;
385 uint32_t iscsi_ip_conflict:1;
386 uint32_t option_rom_installed:1;
387 uint32_t iscsi_drv_loaded:1;
388 uint32_t rsvd0:10;
389 uint32_t stage:16;
390#else
391 uint32_t stage:16;
392 uint32_t rsvd0:10;
393 uint32_t iscsi_drv_loaded:1;
394 uint32_t option_rom_installed:1;
395 uint32_t iscsi_ip_conflict:1;
396 uint32_t iscsi_no_ip:1;
397 uint32_t backup_fw:1;
398 uint32_t error:1;
399#endif
400 } bits;
401} mpu_ep_semaphore_t;
402
403
404
405
406typedef union mpu_ep_control_u {
407 uint32_t dw0;
408 struct {
409#ifdef _BIG_ENDIAN
410 uint32_t cpu_reset:1;
411 uint32_t rsvd1:15;
412 uint32_t ep_ram_init_status:1;
413 uint32_t rsvd0:12;
414 uint32_t m2_rxpbuf:1;
415 uint32_t m1_rxpbuf:1;
416 uint32_t m0_rxpbuf:1;
417#else
418 uint32_t m0_rxpbuf:1;
419 uint32_t m1_rxpbuf:1;
420 uint32_t m2_rxpbuf:1;
421 uint32_t rsvd0:12;
422 uint32_t ep_ram_init_status:1;
423 uint32_t rsvd1:15;
424 uint32_t cpu_reset:1;
425#endif
426 } bits;
427} mpu_ep_control_t;
428
429
430
431
432/* RX doorbell */
433typedef union pd_rxulp_db_u {
434 uint32_t dw0;
435 struct {
436#ifdef _BIG_ENDIAN
437 uint32_t num_posted:8;
438 uint32_t invalidate:1;
439 uint32_t rsvd1:13;
440 uint32_t qid:10;
441#else
442 uint32_t qid:10;
443 uint32_t rsvd1:13;
444 uint32_t invalidate:1;
445 uint32_t num_posted:8;
446#endif
447 } bits;
448} pd_rxulp_db_t;
449
450
451/* TX doorbell */
452typedef union pd_txulp_db_u {
453 uint32_t dw0;
454 struct {
455#ifdef _BIG_ENDIAN
456 uint32_t rsvd1:2;
457 uint32_t num_posted:14;
458 uint32_t rsvd0:6;
459 uint32_t qid:10;
460#else
461 uint32_t qid:10;
462 uint32_t rsvd0:6;
463 uint32_t num_posted:14;
464 uint32_t rsvd1:2;
465#endif
466 } bits;
467} pd_txulp_db_t;
468
469/* CQ doorbell */
470typedef union cq_db_u {
471 uint32_t dw0;
472 struct {
473#ifdef _BIG_ENDIAN
474 uint32_t rsvd1:2;
475 uint32_t rearm:1;
476 uint32_t num_popped:13;
477 uint32_t rsvd0:5;
478 uint32_t event:1;
479 uint32_t qid:10;
480#else
481 uint32_t qid:10;
482 uint32_t event:1;
483 uint32_t rsvd0:5;
484 uint32_t num_popped:13;
485 uint32_t rearm:1;
486 uint32_t rsvd1:2;
487#endif
488 } bits;
489} cq_db_t;
490
491/* EQ doorbell */
492typedef union eq_db_u {
493 uint32_t dw0;
494 struct {
495#ifdef _BIG_ENDIAN
496 uint32_t rsvd1:2;
497 uint32_t rearm:1;
498 uint32_t num_popped:13;
499 uint32_t rsvd0:5;
500 uint32_t event:1;
501 uint32_t clrint:1;
502 uint32_t qid:9;
503#else
504 uint32_t qid:9;
505 uint32_t clrint:1;
506 uint32_t event:1;
507 uint32_t rsvd0:5;
508 uint32_t num_popped:13;
509 uint32_t rearm:1;
510 uint32_t rsvd1:2;
511#endif
512 } bits;
513} eq_db_t;
514
515/* bootstrap mbox doorbell */
516typedef union pd_mpu_mbox_db_u {
517 uint32_t dw0;
518 struct {
519#ifdef _BIG_ENDIAN
520 uint32_t address:30;
521 uint32_t hi:1;
522 uint32_t ready:1;
523#else
524 uint32_t ready:1;
525 uint32_t hi:1;
526 uint32_t address:30;
527#endif
528 } bits;
529} pd_mpu_mbox_db_t;
530
531/* MQ ring doorbell */
532typedef union pd_mq_db_u {
533 uint32_t dw0;
534 struct {
535#ifdef _BIG_ENDIAN
536 uint32_t rsvd1:2;
537 uint32_t num_posted:14;
538 uint32_t rsvd0:5;
539 uint32_t mq_id:11;
540#else
541 uint32_t mq_id:11;
542 uint32_t rsvd0:5;
543 uint32_t num_posted:14;
544 uint32_t rsvd1:2;
545#endif
546 } bits;
547} pd_mq_db_t;
548
549/*
550 * Event Queue Entry
551 */
552struct oce_eqe {
553 uint32_t evnt;
554};
555
556/* MQ scatter gather entry. Array of these make an SGL */
557struct oce_mq_sge {
558 uint32_t pa_lo;
559 uint32_t pa_hi;
560 uint32_t length;
561};
562
563/*
564 * payload can contain an SGL or an embedded array of upto 59 dwords
565 */
566struct oce_mbx_payload {
567 union {
568 union {
569 struct oce_mq_sge sgl[MAX_MBX_SGE];
570 uint32_t embedded[59];
571 } u1;
572 uint32_t dw[59];
573 } u0;
574};
575
576/*
577 * MQ MBX structure
578 */
579struct oce_mbx {
580 union {
581 struct {
582#ifdef _BIG_ENDIAN
583 uint32_t special:8;
584 uint32_t rsvd1:16;
585 uint32_t sge_count:5;
586 uint32_t rsvd0:2;
587 uint32_t embedded:1;
588#else
589 uint32_t embedded:1;
590 uint32_t rsvd0:2;
591 uint32_t sge_count:5;
592 uint32_t rsvd1:16;
593 uint32_t special:8;
594#endif
595 } s;
596 uint32_t dw0;
597 } u0;
598
599 uint32_t payload_length;
600 uint32_t tag[2];
601 uint32_t rsvd2[1];
602 struct oce_mbx_payload payload;
603};
604
605/* completion queue entry for MQ */
606struct oce_mq_cqe {
607 union {
608 struct {
609#ifdef _BIG_ENDIAN
610 /* dw0 */
611 uint32_t extended_status:16;
612 uint32_t completion_status:16;
613 /* dw1 dw2 */
614 uint32_t mq_tag[2];
615 /* dw3 */
616 uint32_t valid:1;
617 uint32_t async_event:1;
618 uint32_t hpi_buffer_cmpl:1;
619 uint32_t completed:1;
620 uint32_t consumed:1;
621 uint32_t rsvd0:3;
622 uint32_t async_type:8;
623 uint32_t event_type:8;
624 uint32_t rsvd1:8;
625#else
626 /* dw0 */
627 uint32_t completion_status:16;
628 uint32_t extended_status:16;
629 /* dw1 dw2 */
630 uint32_t mq_tag[2];
631 /* dw3 */
632 uint32_t rsvd1:8;
633 uint32_t event_type:8;
634 uint32_t async_type:8;
635 uint32_t rsvd0:3;
636 uint32_t consumed:1;
637 uint32_t completed:1;
638 uint32_t hpi_buffer_cmpl:1;
639 uint32_t async_event:1;
640 uint32_t valid:1;
641#endif
642 } s;
643 uint32_t dw[4];
644 } u0;
645};
646
647/* Mailbox Completion Status Codes */
648enum MBX_COMPLETION_STATUS {
649 MBX_CQE_STATUS_SUCCESS = 0x00,
650 MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01,
651 MBX_CQE_STATUS_INVALID_PARAMETER = 0x02,
652 MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03,
653 MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04,
654 MBX_CQE_STATUS_DMA_FAILED = 0x05
655};
656
657struct oce_async_cqe_link_state {
658 union {
659 struct {
660#ifdef _BIG_ENDIAN
661 /* dw0 */
662 uint8_t speed;
663 uint8_t duplex;
664 uint8_t link_status;
665 uint8_t phy_port;
666 /* dw1 */
667 uint16_t qos_link_speed;
668 uint8_t rsvd0;
669 uint8_t fault;
670 /* dw2 */
671 uint32_t event_tag;
672 /* dw3 */
673 uint32_t valid:1;
674 uint32_t async_event:1;
675 uint32_t rsvd2:6;
676 uint32_t event_type:8;
677 uint32_t event_code:8;
678 uint32_t rsvd1:8;
679#else
680 /* dw0 */
681 uint8_t phy_port;
682 uint8_t link_status;
683 uint8_t duplex;
684 uint8_t speed;
685 /* dw1 */
686 uint8_t fault;
687 uint8_t rsvd0;
688 uint16_t qos_link_speed;
689 /* dw2 */
690 uint32_t event_tag;
691 /* dw3 */
692 uint32_t rsvd1:8;
693 uint32_t event_code:8;
694 uint32_t event_type:8;
695 uint32_t rsvd2:6;
696 uint32_t async_event:1;
697 uint32_t valid:1;
698#endif
699 } s;
700 uint32_t dw[4];
701 } u0;
702};
703
704
705/* PVID aync event */
706struct oce_async_event_grp5_pvid_state {
707 uint8_t enabled;
708 uint8_t rsvd0;
709 uint16_t tag;
710 uint32_t event_tag;
711 uint32_t rsvd1;
712 uint32_t code;
713};
714
|
| 715/* async event indicating outer VLAN tag in QnQ */
716struct oce_async_event_qnq {
717 uint8_t valid; /* Indicates if outer VLAN is valid */
718 uint8_t rsvd0;
719 uint16_t vlan_tag;
720 uint32_t event_tag;
721 uint8_t rsvd1[4];
722 uint32_t code;
723} ;
724
725
|
710typedef union oce_mq_ext_ctx_u {
711 uint32_t dw[6];
712 struct {
713 #ifdef _BIG_ENDIAN
714 /* dw0 */
715 uint32_t dw4rsvd1:16;
716 uint32_t num_pages:16;
717 /* dw1 */
718 uint32_t async_evt_bitmap;
719 /* dw2 */
720 uint32_t cq_id:10;
721 uint32_t dw5rsvd2:2;
722 uint32_t ring_size:4;
723 uint32_t dw5rsvd1:16;
724 /* dw3 */
725 uint32_t valid:1;
726 uint32_t dw6rsvd1:31;
727 /* dw4 */
728 uint32_t dw7rsvd1:21;
729 uint32_t async_cq_id:10;
730 uint32_t async_cq_valid:1;
731 #else
732 /* dw0 */
733 uint32_t num_pages:16;
734 uint32_t dw4rsvd1:16;
735 /* dw1 */
736 uint32_t async_evt_bitmap;
737 /* dw2 */
738 uint32_t dw5rsvd1:16;
739 uint32_t ring_size:4;
740 uint32_t dw5rsvd2:2;
741 uint32_t cq_id:10;
742 /* dw3 */
743 uint32_t dw6rsvd1:31;
744 uint32_t valid:1;
745 /* dw4 */
746 uint32_t async_cq_valid:1;
747 uint32_t async_cq_id:10;
748 uint32_t dw7rsvd1:21;
749 #endif
750 /* dw5 */
751 uint32_t dw8rsvd1;
752 } v0;
| 726typedef union oce_mq_ext_ctx_u {
727 uint32_t dw[6];
728 struct {
729 #ifdef _BIG_ENDIAN
730 /* dw0 */
731 uint32_t dw4rsvd1:16;
732 uint32_t num_pages:16;
733 /* dw1 */
734 uint32_t async_evt_bitmap;
735 /* dw2 */
736 uint32_t cq_id:10;
737 uint32_t dw5rsvd2:2;
738 uint32_t ring_size:4;
739 uint32_t dw5rsvd1:16;
740 /* dw3 */
741 uint32_t valid:1;
742 uint32_t dw6rsvd1:31;
743 /* dw4 */
744 uint32_t dw7rsvd1:21;
745 uint32_t async_cq_id:10;
746 uint32_t async_cq_valid:1;
747 #else
748 /* dw0 */
749 uint32_t num_pages:16;
750 uint32_t dw4rsvd1:16;
751 /* dw1 */
752 uint32_t async_evt_bitmap;
753 /* dw2 */
754 uint32_t dw5rsvd1:16;
755 uint32_t ring_size:4;
756 uint32_t dw5rsvd2:2;
757 uint32_t cq_id:10;
758 /* dw3 */
759 uint32_t dw6rsvd1:31;
760 uint32_t valid:1;
761 /* dw4 */
762 uint32_t async_cq_valid:1;
763 uint32_t async_cq_id:10;
764 uint32_t dw7rsvd1:21;
765 #endif
766 /* dw5 */
767 uint32_t dw8rsvd1;
768 } v0;
|
| 769 struct {
770 #ifdef _BIG_ENDIAN
771 /* dw0 */
772 uint32_t cq_id:16;
773 uint32_t num_pages:16;
774 /* dw1 */
775 uint32_t async_evt_bitmap;
776 /* dw2 */
777 uint32_t dw5rsvd2:12;
778 uint32_t ring_size:4;
779 uint32_t async_cq_id:16;
780 /* dw3 */
781 uint32_t valid:1;
782 uint32_t dw6rsvd1:31;
783 /* dw4 */
784 uint32_t dw7rsvd1:31;
785 uint32_t async_cq_valid:1;
786 #else
787 /* dw0 */
788 uint32_t num_pages:16;
789 uint32_t cq_id:16;
790 /* dw1 */
791 uint32_t async_evt_bitmap;
792 /* dw2 */
793 uint32_t async_cq_id:16;
794 uint32_t ring_size:4;
795 uint32_t dw5rsvd2:12;
796 /* dw3 */
797 uint32_t dw6rsvd1:31;
798 uint32_t valid:1;
799 /* dw4 */
800 uint32_t async_cq_valid:1;
801 uint32_t dw7rsvd1:31;
802 #endif
803 /* dw5 */
804 uint32_t dw8rsvd1;
805 } v1;
806
|
753} oce_mq_ext_ctx_t;
754
755
756/* MQ mailbox structure */
757struct oce_bmbx {
758 struct oce_mbx mbx;
759 struct oce_mq_cqe cqe;
760};
761
762/* ---[ MBXs start here ]---------------------------------------------- */
763/* MBXs sub system codes */
764enum MBX_SUBSYSTEM_CODES {
765 MBX_SUBSYSTEM_RSVD = 0,
766 MBX_SUBSYSTEM_COMMON = 1,
767 MBX_SUBSYSTEM_COMMON_ISCSI = 2,
768 MBX_SUBSYSTEM_NIC = 3,
769 MBX_SUBSYSTEM_TOE = 4,
770 MBX_SUBSYSTEM_PXE_UNDI = 5,
771 MBX_SUBSYSTEM_ISCSI_INI = 6,
772 MBX_SUBSYSTEM_ISCSI_TGT = 7,
773 MBX_SUBSYSTEM_MILI_PTL = 8,
774 MBX_SUBSYSTEM_MILI_TMD = 9,
775 MBX_SUBSYSTEM_RDMA = 10,
776 MBX_SUBSYSTEM_LOWLEVEL = 11,
777 MBX_SUBSYSTEM_LRO = 13,
778 IOCBMBX_SUBSYSTEM_DCBX = 15,
779 IOCBMBX_SUBSYSTEM_DIAG = 16,
780 IOCBMBX_SUBSYSTEM_VENDOR = 17
781};
782
783/* common ioctl opcodes */
784enum COMMON_SUBSYSTEM_OPCODES {
785/* These opcodes are common to both networking and storage PCI functions
786 * They are used to reserve resources and configure CNA. These opcodes
787 * all use the MBX_SUBSYSTEM_COMMON subsystem code.
788 */
789 OPCODE_COMMON_QUERY_IFACE_MAC = 1,
790 OPCODE_COMMON_SET_IFACE_MAC = 2,
791 OPCODE_COMMON_SET_IFACE_MULTICAST = 3,
792 OPCODE_COMMON_CONFIG_IFACE_VLAN = 4,
793 OPCODE_COMMON_QUERY_LINK_CONFIG = 5,
794 OPCODE_COMMON_READ_FLASHROM = 6,
795 OPCODE_COMMON_WRITE_FLASHROM = 7,
796 OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8,
797 OPCODE_COMMON_CREATE_CQ = 12,
798 OPCODE_COMMON_CREATE_EQ = 13,
799 OPCODE_COMMON_CREATE_MQ = 21,
800 OPCODE_COMMON_GET_QOS = 27,
801 OPCODE_COMMON_SET_QOS = 28,
802 OPCODE_COMMON_READ_EPROM = 30,
803 OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32,
804 OPCODE_COMMON_NOP = 33,
805 OPCODE_COMMON_SET_IFACE_RX_FILTER = 34,
806 OPCODE_COMMON_GET_FW_VERSION = 35,
807 OPCODE_COMMON_SET_FLOW_CONTROL = 36,
808 OPCODE_COMMON_GET_FLOW_CONTROL = 37,
809 OPCODE_COMMON_SET_FRAME_SIZE = 39,
810 OPCODE_COMMON_MODIFY_EQ_DELAY = 41,
811 OPCODE_COMMON_CREATE_IFACE = 50,
812 OPCODE_COMMON_DESTROY_IFACE = 51,
813 OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52,
814 OPCODE_COMMON_DESTROY_MQ = 53,
815 OPCODE_COMMON_DESTROY_CQ = 54,
816 OPCODE_COMMON_DESTROY_EQ = 55,
817 OPCODE_COMMON_UPLOAD_TCP = 56,
818 OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57,
819 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58,
820 OPCODE_COMMON_ADD_IFACE_MAC = 59,
821 OPCODE_COMMON_DEL_IFACE_MAC = 60,
822 OPCODE_COMMON_FUNCTION_RESET = 61,
823 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
824 OPCODE_COMMON_GET_BOOT_CONFIG = 66,
825 OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
826 OPCODE_COMMON_SET_BEACON_CONFIG = 69,
827 OPCODE_COMMON_GET_BEACON_CONFIG = 70,
828 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
| 807} oce_mq_ext_ctx_t;
808
809
810/* MQ mailbox structure */
811struct oce_bmbx {
812 struct oce_mbx mbx;
813 struct oce_mq_cqe cqe;
814};
815
816/* ---[ MBXs start here ]---------------------------------------------- */
817/* MBXs sub system codes */
818enum MBX_SUBSYSTEM_CODES {
819 MBX_SUBSYSTEM_RSVD = 0,
820 MBX_SUBSYSTEM_COMMON = 1,
821 MBX_SUBSYSTEM_COMMON_ISCSI = 2,
822 MBX_SUBSYSTEM_NIC = 3,
823 MBX_SUBSYSTEM_TOE = 4,
824 MBX_SUBSYSTEM_PXE_UNDI = 5,
825 MBX_SUBSYSTEM_ISCSI_INI = 6,
826 MBX_SUBSYSTEM_ISCSI_TGT = 7,
827 MBX_SUBSYSTEM_MILI_PTL = 8,
828 MBX_SUBSYSTEM_MILI_TMD = 9,
829 MBX_SUBSYSTEM_RDMA = 10,
830 MBX_SUBSYSTEM_LOWLEVEL = 11,
831 MBX_SUBSYSTEM_LRO = 13,
832 IOCBMBX_SUBSYSTEM_DCBX = 15,
833 IOCBMBX_SUBSYSTEM_DIAG = 16,
834 IOCBMBX_SUBSYSTEM_VENDOR = 17
835};
836
837/* common ioctl opcodes */
838enum COMMON_SUBSYSTEM_OPCODES {
839/* These opcodes are common to both networking and storage PCI functions
840 * They are used to reserve resources and configure CNA. These opcodes
841 * all use the MBX_SUBSYSTEM_COMMON subsystem code.
842 */
843 OPCODE_COMMON_QUERY_IFACE_MAC = 1,
844 OPCODE_COMMON_SET_IFACE_MAC = 2,
845 OPCODE_COMMON_SET_IFACE_MULTICAST = 3,
846 OPCODE_COMMON_CONFIG_IFACE_VLAN = 4,
847 OPCODE_COMMON_QUERY_LINK_CONFIG = 5,
848 OPCODE_COMMON_READ_FLASHROM = 6,
849 OPCODE_COMMON_WRITE_FLASHROM = 7,
850 OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8,
851 OPCODE_COMMON_CREATE_CQ = 12,
852 OPCODE_COMMON_CREATE_EQ = 13,
853 OPCODE_COMMON_CREATE_MQ = 21,
854 OPCODE_COMMON_GET_QOS = 27,
855 OPCODE_COMMON_SET_QOS = 28,
856 OPCODE_COMMON_READ_EPROM = 30,
857 OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32,
858 OPCODE_COMMON_NOP = 33,
859 OPCODE_COMMON_SET_IFACE_RX_FILTER = 34,
860 OPCODE_COMMON_GET_FW_VERSION = 35,
861 OPCODE_COMMON_SET_FLOW_CONTROL = 36,
862 OPCODE_COMMON_GET_FLOW_CONTROL = 37,
863 OPCODE_COMMON_SET_FRAME_SIZE = 39,
864 OPCODE_COMMON_MODIFY_EQ_DELAY = 41,
865 OPCODE_COMMON_CREATE_IFACE = 50,
866 OPCODE_COMMON_DESTROY_IFACE = 51,
867 OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52,
868 OPCODE_COMMON_DESTROY_MQ = 53,
869 OPCODE_COMMON_DESTROY_CQ = 54,
870 OPCODE_COMMON_DESTROY_EQ = 55,
871 OPCODE_COMMON_UPLOAD_TCP = 56,
872 OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57,
873 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58,
874 OPCODE_COMMON_ADD_IFACE_MAC = 59,
875 OPCODE_COMMON_DEL_IFACE_MAC = 60,
876 OPCODE_COMMON_FUNCTION_RESET = 61,
877 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
878 OPCODE_COMMON_GET_BOOT_CONFIG = 66,
879 OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
880 OPCODE_COMMON_SET_BEACON_CONFIG = 69,
881 OPCODE_COMMON_GET_BEACON_CONFIG = 70,
882 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
|
| 883 OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73,
|
829 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
830 OPCODE_COMMON_GET_PORT_NAME = 77,
831 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
832 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
833 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
834 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
835 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
836 OPCODE_COMMON_GET_RESET_NEEDED = 84,
837 OPCODE_COMMON_GET_SERIAL_NUMBER = 85,
838 OPCODE_COMMON_GET_NCSI_CONFIG = 86,
839 OPCODE_COMMON_SET_NCSI_CONFIG = 87,
840 OPCODE_COMMON_CREATE_MQ_EXT = 90,
841 OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100,
842 OPCODE_COMMON_SET_VF_PORT_TYPE = 101,
843 OPCODE_COMMON_GET_PHY_CONFIG = 102,
844 OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103,
845 OPCODE_COMMON_GET_ADAPTER_ID = 110,
846 OPCODE_COMMON_GET_UPGRADE_FEATURES = 111,
847 OPCODE_COMMON_GET_INSTALLED_FEATURES = 112,
848 OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113,
849 OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114,
850 OPCODE_COMMON_SEND_ACTIVATION = 115,
851 OPCODE_COMMON_RESET_LICENSES = 116,
852 OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121,
853 OPCODE_COMMON_QUERY_TCB = 144,
854 OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145,
855 OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146,
856 OPCODE_COMMON_GET_IFACE_MAC_LIST = 147,
857 OPCODE_COMMON_SET_IFACE_MAC_LIST = 148,
858 OPCODE_COMMON_MODIFY_CQ = 149,
859 OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150,
860 OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151,
861 OPCODE_COMMON_GET_HSW_CONFIG = 152,
862 OPCODE_COMMON_SET_HSW_CONFIG = 153,
863 OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154,
864 OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155,
865 OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156,
866 OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157,
867 OPCODE_COMMON_SET_DIAG_REGISTERS = 158,
868 OPCODE_COMMON_GET_FUNCTION_CONFIG = 160,
869 OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161,
870 OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162,
871 OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163,
872 OPCODE_COMMON_GET_PROFILE_CONFIG = 164,
873 OPCODE_COMMON_SET_PROFILE_CONFIG = 165,
874 OPCODE_COMMON_GET_PROFILE_LIST = 166,
875 OPCODE_COMMON_GET_ACTIVE_PROFILE = 167,
876 OPCODE_COMMON_SET_ACTIVE_PROFILE = 168,
877 OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170,
878 OPCODE_COMMON_READ_OBJECT = 171,
879 OPCODE_COMMON_WRITE_OBJECT = 172
880};
881
882/* common ioctl header */
883#define OCE_MBX_VER_V2 0x0002 /* Version V2 mailbox command */
884#define OCE_MBX_VER_V1 0x0001 /* Version V1 mailbox command */
885#define OCE_MBX_VER_V0 0x0000 /* Version V0 mailbox command */
886struct mbx_hdr {
887 union {
888 uint32_t dw[4];
889 struct {
890 #ifdef _BIG_ENDIAN
891 /* dw 0 */
892 uint32_t domain:8;
893 uint32_t port_number:8;
894 uint32_t subsystem:8;
895 uint32_t opcode:8;
896 /* dw 1 */
897 uint32_t timeout;
898 /* dw 2 */
899 uint32_t request_length;
900 /* dw 3 */
901 uint32_t rsvd0:24;
902 uint32_t version:8;
903 #else
904 /* dw 0 */
905 uint32_t opcode:8;
906 uint32_t subsystem:8;
907 uint32_t port_number:8;
908 uint32_t domain:8;
909 /* dw 1 */
910 uint32_t timeout;
911 /* dw 2 */
912 uint32_t request_length;
913 /* dw 3 */
914 uint32_t version:8;
915 uint32_t rsvd0:24;
916 #endif
917 } req;
918 struct {
919 #ifdef _BIG_ENDIAN
920 /* dw 0 */
921 uint32_t domain:8;
922 uint32_t rsvd0:8;
923 uint32_t subsystem:8;
924 uint32_t opcode:8;
925 /* dw 1 */
926 uint32_t rsvd1:16;
927 uint32_t additional_status:8;
928 uint32_t status:8;
929 #else
930 /* dw 0 */
931 uint32_t opcode:8;
932 uint32_t subsystem:8;
933 uint32_t rsvd0:8;
934 uint32_t domain:8;
935 /* dw 1 */
936 uint32_t status:8;
937 uint32_t additional_status:8;
938 uint32_t rsvd1:16;
939 #endif
940 uint32_t rsp_length;
941 uint32_t actual_rsp_length;
942 } rsp;
943 } u0;
944};
945#define OCE_BMBX_RHDR_SZ 20
946#define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
947#define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
948#define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
949
950/* [05] OPCODE_COMMON_QUERY_LINK_CONFIG */
951struct mbx_query_common_link_config {
952 struct mbx_hdr hdr;
953 union {
954 struct {
955 uint32_t rsvd0;
956 } req;
957
958 struct {
959 /* dw 0 */
960 uint8_t physical_port;
961 uint8_t mac_duplex;
962 uint8_t mac_speed;
963 uint8_t mac_fault;
964 /* dw 1 */
965 uint8_t mgmt_mac_duplex;
966 uint8_t mgmt_mac_speed;
967 uint16_t qos_link_speed;
968 uint32_t logical_link_status;
969 } rsp;
970 } params;
971};
972
973/* [57] OPCODE_COMMON_SET_LINK_SPEED */
974struct mbx_set_common_link_speed {
975 struct mbx_hdr hdr;
976 union {
977 struct {
978#ifdef _BIG_ENDIAN
979 uint8_t rsvd0;
980 uint8_t mac_speed;
981 uint8_t virtual_port;
982 uint8_t physical_port;
983#else
984 uint8_t physical_port;
985 uint8_t virtual_port;
986 uint8_t mac_speed;
987 uint8_t rsvd0;
988#endif
989 } req;
990
991 struct {
992 uint32_t rsvd0;
993 } rsp;
994
995 uint32_t dw;
996 } params;
997};
998
999struct mac_address_format {
1000 uint16_t size_of_struct;
1001 uint8_t mac_addr[6];
1002};
1003
1004/* [01] OPCODE_COMMON_QUERY_IFACE_MAC */
1005struct mbx_query_common_iface_mac {
1006 struct mbx_hdr hdr;
1007 union {
1008 struct {
1009#ifdef _BIG_ENDIAN
1010 uint16_t if_id;
1011 uint8_t permanent;
1012 uint8_t type;
1013#else
1014 uint8_t type;
1015 uint8_t permanent;
1016 uint16_t if_id;
1017#endif
1018
1019 } req;
1020
1021 struct {
1022 struct mac_address_format mac;
1023 } rsp;
1024 } params;
1025};
1026
1027/* [02] OPCODE_COMMON_SET_IFACE_MAC */
1028struct mbx_set_common_iface_mac {
1029 struct mbx_hdr hdr;
1030 union {
1031 struct {
1032#ifdef _BIG_ENDIAN
1033 /* dw 0 */
1034 uint16_t if_id;
1035 uint8_t invalidate;
1036 uint8_t type;
1037#else
1038 /* dw 0 */
1039 uint8_t type;
1040 uint8_t invalidate;
1041 uint16_t if_id;
1042#endif
1043 /* dw 1 */
1044 struct mac_address_format mac;
1045 } req;
1046
1047 struct {
1048 uint32_t rsvd0;
1049 } rsp;
1050
1051 uint32_t dw[2];
1052 } params;
1053};
1054
1055/* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */
1056struct mbx_set_common_iface_multicast {
1057 struct mbx_hdr hdr;
1058 union {
1059 struct {
1060 /* dw 0 */
1061 uint16_t num_mac;
1062 uint8_t promiscuous;
1063 uint8_t if_id;
1064 /* dw 1-48 */
1065 struct {
1066 uint8_t byte[6];
1067 } mac[32];
1068
1069 } req;
1070
1071 struct {
1072 uint32_t rsvd0;
1073 } rsp;
1074
1075 uint32_t dw[49];
1076 } params;
1077};
1078
1079struct qinq_vlan {
1080#ifdef _BIG_ENDIAN
1081 uint16_t inner;
1082 uint16_t outer;
1083#else
1084 uint16_t outer;
1085 uint16_t inner;
1086#endif
1087};
1088
1089struct normal_vlan {
1090 uint16_t vtag;
1091};
1092
1093struct ntwk_if_vlan_tag {
1094 union {
1095 struct normal_vlan normal;
1096 struct qinq_vlan qinq;
1097 } u0;
1098};
1099
1100/* [50] OPCODE_COMMON_CREATE_IFACE */
1101struct mbx_create_common_iface {
1102 struct mbx_hdr hdr;
1103 union {
1104 struct {
1105 uint32_t version;
1106 uint32_t cap_flags;
1107 uint32_t enable_flags;
1108 uint8_t mac_addr[6];
1109 uint8_t rsvd0;
1110 uint8_t mac_invalid;
1111 struct ntwk_if_vlan_tag vlan_tag;
1112 } req;
1113
1114 struct {
1115 uint32_t if_id;
1116 uint32_t pmac_id;
1117 } rsp;
1118 uint32_t dw[4];
1119 } params;
1120};
1121
1122/* [51] OPCODE_COMMON_DESTROY_IFACE */
1123struct mbx_destroy_common_iface {
1124 struct mbx_hdr hdr;
1125 union {
1126 struct {
1127 uint32_t if_id;
1128 } req;
1129
1130 struct {
1131 uint32_t rsvd0;
1132 } rsp;
1133
1134 uint32_t dw;
1135 } params;
1136};
1137
1138/* event queue context structure */
1139struct oce_eq_ctx {
1140#ifdef _BIG_ENDIAN
1141 uint32_t dw4rsvd1:16;
1142 uint32_t num_pages:16;
1143
1144 uint32_t size:1;
1145 uint32_t dw5rsvd2:1;
1146 uint32_t valid:1;
1147 uint32_t dw5rsvd1:29;
1148
1149 uint32_t armed:1;
1150 uint32_t dw6rsvd2:2;
1151 uint32_t count:3;
1152 uint32_t dw6rsvd1:26;
1153
1154 uint32_t dw7rsvd2:9;
1155 uint32_t delay_mult:10;
1156 uint32_t dw7rsvd1:13;
1157
1158 uint32_t dw8rsvd1;
1159#else
1160 uint32_t num_pages:16;
1161 uint32_t dw4rsvd1:16;
1162
1163 uint32_t dw5rsvd1:29;
1164 uint32_t valid:1;
1165 uint32_t dw5rsvd2:1;
1166 uint32_t size:1;
1167
1168 uint32_t dw6rsvd1:26;
1169 uint32_t count:3;
1170 uint32_t dw6rsvd2:2;
1171 uint32_t armed:1;
1172
1173 uint32_t dw7rsvd1:13;
1174 uint32_t delay_mult:10;
1175 uint32_t dw7rsvd2:9;
1176
1177 uint32_t dw8rsvd1;
1178#endif
1179};
1180
1181/* [13] OPCODE_COMMON_CREATE_EQ */
1182struct mbx_create_common_eq {
1183 struct mbx_hdr hdr;
1184 union {
1185 struct {
1186 struct oce_eq_ctx ctx;
1187 struct phys_addr pages[8];
1188 } req;
1189
1190 struct {
1191 uint16_t eq_id;
1192 uint16_t rsvd0;
1193 } rsp;
1194 } params;
1195};
1196
1197/* [55] OPCODE_COMMON_DESTROY_EQ */
1198struct mbx_destroy_common_eq {
1199 struct mbx_hdr hdr;
1200 union {
1201 struct {
1202#ifdef _BIG_ENDIAN
1203 uint16_t rsvd0;
1204 uint16_t id;
1205#else
1206 uint16_t id;
1207 uint16_t rsvd0;
1208#endif
1209 } req;
1210
1211 struct {
1212 uint32_t rsvd0;
1213 } rsp;
1214 } params;
1215};
1216
1217/* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */
1218typedef union oce_cq_ctx_u {
1219 uint32_t dw[5];
1220 struct {
1221 #ifdef _BIG_ENDIAN
1222 /* dw4 */
1223 uint32_t dw4rsvd1:16;
1224 uint32_t num_pages:16;
1225 /* dw5 */
1226 uint32_t eventable:1;
1227 uint32_t dw5rsvd3:1;
1228 uint32_t valid:1;
1229 uint32_t count:2;
1230 uint32_t dw5rsvd2:12;
1231 uint32_t nodelay:1;
1232 uint32_t coalesce_wm:2;
1233 uint32_t dw5rsvd1:12;
1234 /* dw6 */
1235 uint32_t armed:1;
1236 uint32_t dw6rsvd2:1;
1237 uint32_t eq_id:8;
1238 uint32_t dw6rsvd1:22;
1239 #else
1240 /* dw4 */
1241 uint32_t num_pages:16;
1242 uint32_t dw4rsvd1:16;
1243 /* dw5 */
1244 uint32_t dw5rsvd1:12;
1245 uint32_t coalesce_wm:2;
1246 uint32_t nodelay:1;
1247 uint32_t dw5rsvd2:12;
1248 uint32_t count:2;
1249 uint32_t valid:1;
1250 uint32_t dw5rsvd3:1;
1251 uint32_t eventable:1;
1252 /* dw6 */
1253 uint32_t dw6rsvd1:22;
1254 uint32_t eq_id:8;
1255 uint32_t dw6rsvd2:1;
1256 uint32_t armed:1;
1257 #endif
1258 /* dw7 */
1259 uint32_t dw7rsvd1;
1260 /* dw8 */
1261 uint32_t dw8rsvd1;
1262 } v0;
1263 struct {
1264 #ifdef _BIG_ENDIAN
1265 /* dw4 */
1266 uint32_t dw4rsvd1:8;
1267 uint32_t page_size:8;
1268 uint32_t num_pages:16;
1269 /* dw5 */
1270 uint32_t eventable:1;
1271 uint32_t dw5rsvd3:1;
1272 uint32_t valid:1;
1273 uint32_t count:2;
1274 uint32_t dw5rsvd2:11;
1275 uint32_t autovalid:1;
1276 uint32_t nodelay:1;
1277 uint32_t coalesce_wm:2;
1278 uint32_t dw5rsvd1:12;
1279 /* dw6 */
1280 uint32_t armed:1;
1281 uint32_t dw6rsvd1:15;
1282 uint32_t eq_id:16;
1283 /* dw7 */
1284 uint32_t dw7rsvd1:16;
1285 uint32_t cqe_count:16;
1286 #else
1287 /* dw4 */
1288 uint32_t num_pages:16;
1289 uint32_t page_size:8;
1290 uint32_t dw4rsvd1:8;
1291 /* dw5 */
1292 uint32_t dw5rsvd1:12;
1293 uint32_t coalesce_wm:2;
1294 uint32_t nodelay:1;
1295 uint32_t autovalid:1;
1296 uint32_t dw5rsvd2:11;
1297 uint32_t count:2;
1298 uint32_t valid:1;
1299 uint32_t dw5rsvd3:1;
1300 uint32_t eventable:1;
1301 /* dw6 */
1302 uint32_t eq_id:8;
1303 uint32_t dw6rsvd1:15;
1304 uint32_t armed:1;
1305 /* dw7 */
1306 uint32_t cqe_count:16;
1307 uint32_t dw7rsvd1:16;
1308 #endif
1309 /* dw8 */
1310 uint32_t dw8rsvd1;
1311 } v2;
1312} oce_cq_ctx_t;
1313
1314/* [12] OPCODE_COMMON_CREATE_CQ */
1315struct mbx_create_common_cq {
1316 struct mbx_hdr hdr;
1317 union {
1318 struct {
1319 oce_cq_ctx_t cq_ctx;
1320 struct phys_addr pages[4];
1321 } req;
1322
1323 struct {
1324 uint16_t cq_id;
1325 uint16_t rsvd0;
1326 } rsp;
1327 } params;
1328};
1329
1330/* [54] OPCODE_COMMON_DESTROY_CQ */
1331struct mbx_destroy_common_cq {
1332 struct mbx_hdr hdr;
1333 union {
1334 struct {
1335#ifdef _BIG_ENDIAN
1336 uint16_t rsvd0;
1337 uint16_t id;
1338#else
1339 uint16_t id;
1340 uint16_t rsvd0;
1341#endif
1342 } req;
1343
1344 struct {
1345 uint32_t rsvd0;
1346 } rsp;
1347 } params;
1348};
1349
1350typedef union oce_mq_ctx_u {
1351 uint32_t dw[5];
1352 struct {
1353 #ifdef _BIG_ENDIAN
1354 /* dw4 */
1355 uint32_t dw4rsvd1:16;
1356 uint32_t num_pages:16;
1357 /* dw5 */
1358 uint32_t cq_id:10;
1359 uint32_t dw5rsvd2:2;
1360 uint32_t ring_size:4;
1361 uint32_t dw5rsvd1:16;
1362 /* dw6 */
1363 uint32_t valid:1;
1364 uint32_t dw6rsvd1:31;
1365 /* dw7 */
1366 uint32_t dw7rsvd1:21;
1367 uint32_t async_cq_id:10;
1368 uint32_t async_cq_valid:1;
1369 #else
1370 /* dw4 */
1371 uint32_t num_pages:16;
1372 uint32_t dw4rsvd1:16;
1373 /* dw5 */
1374 uint32_t dw5rsvd1:16;
1375 uint32_t ring_size:4;
1376 uint32_t dw5rsvd2:2;
1377 uint32_t cq_id:10;
1378 /* dw6 */
1379 uint32_t dw6rsvd1:31;
1380 uint32_t valid:1;
1381 /* dw7 */
1382 uint32_t async_cq_valid:1;
1383 uint32_t async_cq_id:10;
1384 uint32_t dw7rsvd1:21;
1385 #endif
1386 /* dw8 */
1387 uint32_t dw8rsvd1;
1388 } v0;
1389} oce_mq_ctx_t;
1390
1391/**
1392 * @brief [21] OPCODE_COMMON_CREATE_MQ
1393 * A MQ must be at least 16 entries deep (corresponding to 1 page) and
1394 * at most 128 entries deep (corresponding to 8 pages).
1395 */
1396struct mbx_create_common_mq {
1397 struct mbx_hdr hdr;
1398 union {
1399 struct {
1400 oce_mq_ctx_t context;
1401 struct phys_addr pages[8];
1402 } req;
1403
1404 struct {
1405 uint32_t mq_id:16;
1406 uint32_t rsvd0:16;
1407 } rsp;
1408 } params;
1409};
1410
1411struct mbx_create_common_mq_ex {
1412 struct mbx_hdr hdr;
1413 union {
1414 struct {
1415 oce_mq_ext_ctx_t context;
1416 struct phys_addr pages[8];
1417 } req;
1418
1419 struct {
1420 uint32_t mq_id:16;
1421 uint32_t rsvd0:16;
1422 } rsp;
1423 } params;
1424};
1425
1426
1427
1428/* [53] OPCODE_COMMON_DESTROY_MQ */
1429struct mbx_destroy_common_mq {
1430 struct mbx_hdr hdr;
1431 union {
1432 struct {
1433#ifdef _BIG_ENDIAN
1434 uint16_t rsvd0;
1435 uint16_t id;
1436#else
1437 uint16_t id;
1438 uint16_t rsvd0;
1439#endif
1440 } req;
1441
1442 struct {
1443 uint32_t rsvd0;
1444 } rsp;
1445 } params;
1446};
1447
1448/* [35] OPCODE_COMMON_GET_ FW_VERSION */
1449struct mbx_get_common_fw_version {
1450 struct mbx_hdr hdr;
1451 union {
1452 struct {
1453 uint32_t rsvd0;
1454 } req;
1455
1456 struct {
1457 uint8_t fw_ver_str[32];
1458 uint8_t fw_on_flash_ver_str[32];
1459 } rsp;
1460 } params;
1461};
1462
1463/* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
1464struct mbx_common_cev_modify_msi_messages {
1465 struct mbx_hdr hdr;
1466 union {
1467 struct {
1468 uint32_t num_msi_msgs;
1469 } req;
1470
1471 struct {
1472 uint32_t rsvd0;
1473 } rsp;
1474 } params;
1475};
1476
1477/* [36] OPCODE_COMMON_SET_FLOW_CONTROL */
1478/* [37] OPCODE_COMMON_GET_FLOW_CONTROL */
1479struct mbx_common_get_set_flow_control {
1480 struct mbx_hdr hdr;
1481#ifdef _BIG_ENDIAN
1482 uint16_t tx_flow_control;
1483 uint16_t rx_flow_control;
1484#else
1485 uint16_t rx_flow_control;
1486 uint16_t tx_flow_control;
1487#endif
1488};
1489
1490enum e_flash_opcode {
1491 MGMT_FLASHROM_OPCODE_FLASH = 1,
1492 MGMT_FLASHROM_OPCODE_SAVE = 2
1493};
1494
1495/* [06] OPCODE_READ_COMMON_FLASHROM */
1496/* [07] OPCODE_WRITE_COMMON_FLASHROM */
1497
1498struct mbx_common_read_write_flashrom {
1499 struct mbx_hdr hdr;
1500 uint32_t flash_op_code;
1501 uint32_t flash_op_type;
1502 uint32_t data_buffer_size;
1503 uint32_t data_offset;
1504 uint8_t data_buffer[4]; /* + IMAGE_TRANSFER_SIZE */
1505};
1506
1507struct oce_phy_info {
1508 uint16_t phy_type;
1509 uint16_t interface_type;
1510 uint32_t misc_params;
1511 uint16_t ext_phy_details;
1512 uint16_t rsvd;
1513 uint16_t auto_speeds_supported;
1514 uint16_t fixed_speeds_supported;
1515 uint32_t future_use[2];
1516};
1517
1518struct mbx_common_phy_info {
1519 struct mbx_hdr hdr;
1520 union {
1521 struct {
1522 uint32_t rsvd0[4];
1523 } req;
1524 struct {
1525 struct oce_phy_info phy_info;
1526 } rsp;
1527 } params;
1528};
1529
1530/*Lancer firmware*/
1531
1532struct mbx_lancer_common_write_object {
1533 union {
1534 struct {
1535 struct mbx_hdr hdr;
1536 uint32_t write_length: 24;
1537 uint32_t rsvd: 7;
1538 uint32_t eof: 1;
1539 uint32_t write_offset;
1540 uint8_t object_name[104];
1541 uint32_t descriptor_count;
1542 uint32_t buffer_length;
1543 uint32_t address_lower;
1544 uint32_t address_upper;
1545 } req;
1546 struct {
1547 uint8_t opcode;
1548 uint8_t subsystem;
1549 uint8_t rsvd1[2];
1550 uint8_t status;
1551 uint8_t additional_status;
1552 uint8_t rsvd2[2];
1553 uint32_t response_length;
1554 uint32_t actual_response_length;
1555 uint32_t actual_write_length;
1556 } rsp;
1557 } params;
1558};
1559
1560/**
1561 * @brief MBX Common Quiery Firmaware Config
1562 * This command retrieves firmware configuration parameters and adapter
1563 * resources available to the driver originating the request. The firmware
1564 * configuration defines supported protocols by the installed adapter firmware.
1565 * This includes which ULP processors support the specified protocols and
1566 * the number of TCP connections allowed for that protocol.
1567 */
1568struct mbx_common_query_fw_config {
1569 struct mbx_hdr hdr;
1570 union {
1571 struct {
1572 uint32_t rsvd0[30];
1573 } req;
1574
1575 struct {
1576 uint32_t config_number;
1577 uint32_t asic_revision;
1578 uint32_t port_id; /* used for stats retrieval */
1579 uint32_t function_mode;
1580 struct {
1581
1582 uint32_t ulp_mode;
1583 uint32_t nic_wqid_base;
1584 uint32_t nic_wq_tot;
1585 uint32_t toe_wqid_base;
1586 uint32_t toe_wq_tot;
1587 uint32_t toe_rqid_base;
1588 uint32_t toe_rqid_tot;
1589 uint32_t toe_defrqid_base;
1590 uint32_t toe_defrqid_count;
1591 uint32_t lro_rqid_base;
1592 uint32_t lro_rqid_tot;
1593 uint32_t iscsi_icd_base;
1594 uint32_t iscsi_icd_count;
1595 } ulp[2];
1596 uint32_t function_caps;
1597 uint32_t cqid_base;
1598 uint32_t cqid_tot;
1599 uint32_t eqid_base;
1600 uint32_t eqid_tot;
1601 } rsp;
1602 } params;
1603};
1604
1605enum CQFW_CONFIG_NUMBER {
1606 FCN_NIC_ISCSI_Initiator = 0x0,
1607 FCN_ISCSI_Target = 0x3,
1608 FCN_FCoE = 0x7,
1609 FCN_ISCSI_Initiator_Target = 0x9,
1610 FCN_NIC_RDMA_TOE = 0xA,
1611 FCN_NIC_RDMA_FCoE = 0xB,
1612 FCN_NIC_RDMA_iSCSI = 0xC,
1613 FCN_NIC_iSCSI_FCoE = 0xD
1614};
1615
1616/**
1617 * @brief Function Capabilites
1618 * This field contains the flags indicating the capabilities of
1619 * the SLI Host���s PCI function.
1620 */
1621enum CQFW_FUNCTION_CAPABILITIES {
1622 FNC_UNCLASSIFIED_STATS = 0x1,
1623 FNC_RSS = 0x2,
1624 FNC_PROMISCUOUS = 0x4,
1625 FNC_LEGACY_MODE = 0x8,
1626 FNC_HDS = 0x4000,
1627 FNC_VMQ = 0x10000,
1628 FNC_NETQ = 0x20000,
1629 FNC_QGROUPS = 0x40000,
1630 FNC_LRO = 0x100000,
1631 FNC_VLAN_OFFLOAD = 0x800000
1632};
1633
1634enum CQFW_ULP_MODES_SUPPORTED {
1635 ULP_TOE_MODE = 0x1,
1636 ULP_NIC_MODE = 0x2,
1637 ULP_RDMA_MODE = 0x4,
1638 ULP_ISCSI_INI_MODE = 0x10,
1639 ULP_ISCSI_TGT_MODE = 0x20,
1640 ULP_FCOE_INI_MODE = 0x40,
1641 ULP_FCOE_TGT_MODE = 0x80,
1642 ULP_DAL_MODE = 0x100,
1643 ULP_LRO_MODE = 0x200
1644};
1645
1646/**
1647 * @brief Function Modes Supported
1648 * Valid function modes (or protocol-types) supported on the SLI-Host���s
1649 * PCIe function. This field is a logical OR of the following values:
1650 */
1651enum CQFW_FUNCTION_MODES_SUPPORTED {
1652 FNM_TOE_MODE = 0x1, /* TCP offload supported */
1653 FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */
1654 FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */
1655 FNM_VM_MODE = 0x8, /* Virtual Machines supported */
1656 FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */
1657 FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */
1658 FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */
1659 FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */
1660 FNM_DAL_MODE = 0x100, /* DAL supported */
1661 FNM_LRO_MODE = 0x200, /* LRO supported */
1662 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */
1663 FNM_NCSI_MODE = 0x800, /* NCSI supported */
1664 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */
1665 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/
1666 FNM_INVALID_MODE = 0x8000, /* Invalid */
1667 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */
1668 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */
1669 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */
1670 FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */
1671 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */
1672 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */
1673 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */
1674 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */
1675};
1676
1677
1678struct mbx_common_config_vlan {
1679 struct mbx_hdr hdr;
1680 union {
1681 struct {
1682#ifdef _BIG_ENDIAN
1683 uint8_t num_vlans;
1684 uint8_t untagged;
1685 uint8_t promisc;
1686 uint8_t if_id;
1687#else
1688 uint8_t if_id;
1689 uint8_t promisc;
1690 uint8_t untagged;
1691 uint8_t num_vlans;
1692#endif
1693 union {
1694 struct normal_vlan normal_vlans[64];
1695 struct qinq_vlan qinq_vlans[32];
1696 } tags;
1697 } req;
1698
1699 struct {
1700 uint32_t rsvd;
1701 } rsp;
1702 } params;
1703};
1704
1705typedef struct iface_rx_filter_ctx {
1706 uint32_t global_flags_mask;
1707 uint32_t global_flags;
1708 uint32_t iface_flags_mask;
1709 uint32_t iface_flags;
1710 uint32_t if_id;
1711 #define IFACE_RX_NUM_MCAST_MAX 64
1712 uint32_t num_mcast;
1713 struct mbx_mcast_addr {
1714 uint8_t byte[6];
1715 } mac[IFACE_RX_NUM_MCAST_MAX];
1716} iface_rx_filter_ctx_t;
1717
1718/* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */
1719struct mbx_set_common_iface_rx_filter {
1720 struct mbx_hdr hdr;
1721 union {
1722 iface_rx_filter_ctx_t req;
1723 iface_rx_filter_ctx_t rsp;
1724 } params;
1725};
1726
| 884 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
885 OPCODE_COMMON_GET_PORT_NAME = 77,
886 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
887 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
888 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
889 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
890 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
891 OPCODE_COMMON_GET_RESET_NEEDED = 84,
892 OPCODE_COMMON_GET_SERIAL_NUMBER = 85,
893 OPCODE_COMMON_GET_NCSI_CONFIG = 86,
894 OPCODE_COMMON_SET_NCSI_CONFIG = 87,
895 OPCODE_COMMON_CREATE_MQ_EXT = 90,
896 OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100,
897 OPCODE_COMMON_SET_VF_PORT_TYPE = 101,
898 OPCODE_COMMON_GET_PHY_CONFIG = 102,
899 OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103,
900 OPCODE_COMMON_GET_ADAPTER_ID = 110,
901 OPCODE_COMMON_GET_UPGRADE_FEATURES = 111,
902 OPCODE_COMMON_GET_INSTALLED_FEATURES = 112,
903 OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113,
904 OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114,
905 OPCODE_COMMON_SEND_ACTIVATION = 115,
906 OPCODE_COMMON_RESET_LICENSES = 116,
907 OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121,
908 OPCODE_COMMON_QUERY_TCB = 144,
909 OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145,
910 OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146,
911 OPCODE_COMMON_GET_IFACE_MAC_LIST = 147,
912 OPCODE_COMMON_SET_IFACE_MAC_LIST = 148,
913 OPCODE_COMMON_MODIFY_CQ = 149,
914 OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150,
915 OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151,
916 OPCODE_COMMON_GET_HSW_CONFIG = 152,
917 OPCODE_COMMON_SET_HSW_CONFIG = 153,
918 OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154,
919 OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155,
920 OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156,
921 OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157,
922 OPCODE_COMMON_SET_DIAG_REGISTERS = 158,
923 OPCODE_COMMON_GET_FUNCTION_CONFIG = 160,
924 OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161,
925 OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162,
926 OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163,
927 OPCODE_COMMON_GET_PROFILE_CONFIG = 164,
928 OPCODE_COMMON_SET_PROFILE_CONFIG = 165,
929 OPCODE_COMMON_GET_PROFILE_LIST = 166,
930 OPCODE_COMMON_GET_ACTIVE_PROFILE = 167,
931 OPCODE_COMMON_SET_ACTIVE_PROFILE = 168,
932 OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170,
933 OPCODE_COMMON_READ_OBJECT = 171,
934 OPCODE_COMMON_WRITE_OBJECT = 172
935};
936
937/* common ioctl header */
938#define OCE_MBX_VER_V2 0x0002 /* Version V2 mailbox command */
939#define OCE_MBX_VER_V1 0x0001 /* Version V1 mailbox command */
940#define OCE_MBX_VER_V0 0x0000 /* Version V0 mailbox command */
941struct mbx_hdr {
942 union {
943 uint32_t dw[4];
944 struct {
945 #ifdef _BIG_ENDIAN
946 /* dw 0 */
947 uint32_t domain:8;
948 uint32_t port_number:8;
949 uint32_t subsystem:8;
950 uint32_t opcode:8;
951 /* dw 1 */
952 uint32_t timeout;
953 /* dw 2 */
954 uint32_t request_length;
955 /* dw 3 */
956 uint32_t rsvd0:24;
957 uint32_t version:8;
958 #else
959 /* dw 0 */
960 uint32_t opcode:8;
961 uint32_t subsystem:8;
962 uint32_t port_number:8;
963 uint32_t domain:8;
964 /* dw 1 */
965 uint32_t timeout;
966 /* dw 2 */
967 uint32_t request_length;
968 /* dw 3 */
969 uint32_t version:8;
970 uint32_t rsvd0:24;
971 #endif
972 } req;
973 struct {
974 #ifdef _BIG_ENDIAN
975 /* dw 0 */
976 uint32_t domain:8;
977 uint32_t rsvd0:8;
978 uint32_t subsystem:8;
979 uint32_t opcode:8;
980 /* dw 1 */
981 uint32_t rsvd1:16;
982 uint32_t additional_status:8;
983 uint32_t status:8;
984 #else
985 /* dw 0 */
986 uint32_t opcode:8;
987 uint32_t subsystem:8;
988 uint32_t rsvd0:8;
989 uint32_t domain:8;
990 /* dw 1 */
991 uint32_t status:8;
992 uint32_t additional_status:8;
993 uint32_t rsvd1:16;
994 #endif
995 uint32_t rsp_length;
996 uint32_t actual_rsp_length;
997 } rsp;
998 } u0;
999};
1000#define OCE_BMBX_RHDR_SZ 20
1001#define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
1002#define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
1003#define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
1004
1005/* [05] OPCODE_COMMON_QUERY_LINK_CONFIG */
1006struct mbx_query_common_link_config {
1007 struct mbx_hdr hdr;
1008 union {
1009 struct {
1010 uint32_t rsvd0;
1011 } req;
1012
1013 struct {
1014 /* dw 0 */
1015 uint8_t physical_port;
1016 uint8_t mac_duplex;
1017 uint8_t mac_speed;
1018 uint8_t mac_fault;
1019 /* dw 1 */
1020 uint8_t mgmt_mac_duplex;
1021 uint8_t mgmt_mac_speed;
1022 uint16_t qos_link_speed;
1023 uint32_t logical_link_status;
1024 } rsp;
1025 } params;
1026};
1027
1028/* [57] OPCODE_COMMON_SET_LINK_SPEED */
1029struct mbx_set_common_link_speed {
1030 struct mbx_hdr hdr;
1031 union {
1032 struct {
1033#ifdef _BIG_ENDIAN
1034 uint8_t rsvd0;
1035 uint8_t mac_speed;
1036 uint8_t virtual_port;
1037 uint8_t physical_port;
1038#else
1039 uint8_t physical_port;
1040 uint8_t virtual_port;
1041 uint8_t mac_speed;
1042 uint8_t rsvd0;
1043#endif
1044 } req;
1045
1046 struct {
1047 uint32_t rsvd0;
1048 } rsp;
1049
1050 uint32_t dw;
1051 } params;
1052};
1053
1054struct mac_address_format {
1055 uint16_t size_of_struct;
1056 uint8_t mac_addr[6];
1057};
1058
1059/* [01] OPCODE_COMMON_QUERY_IFACE_MAC */
1060struct mbx_query_common_iface_mac {
1061 struct mbx_hdr hdr;
1062 union {
1063 struct {
1064#ifdef _BIG_ENDIAN
1065 uint16_t if_id;
1066 uint8_t permanent;
1067 uint8_t type;
1068#else
1069 uint8_t type;
1070 uint8_t permanent;
1071 uint16_t if_id;
1072#endif
1073
1074 } req;
1075
1076 struct {
1077 struct mac_address_format mac;
1078 } rsp;
1079 } params;
1080};
1081
1082/* [02] OPCODE_COMMON_SET_IFACE_MAC */
1083struct mbx_set_common_iface_mac {
1084 struct mbx_hdr hdr;
1085 union {
1086 struct {
1087#ifdef _BIG_ENDIAN
1088 /* dw 0 */
1089 uint16_t if_id;
1090 uint8_t invalidate;
1091 uint8_t type;
1092#else
1093 /* dw 0 */
1094 uint8_t type;
1095 uint8_t invalidate;
1096 uint16_t if_id;
1097#endif
1098 /* dw 1 */
1099 struct mac_address_format mac;
1100 } req;
1101
1102 struct {
1103 uint32_t rsvd0;
1104 } rsp;
1105
1106 uint32_t dw[2];
1107 } params;
1108};
1109
1110/* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */
1111struct mbx_set_common_iface_multicast {
1112 struct mbx_hdr hdr;
1113 union {
1114 struct {
1115 /* dw 0 */
1116 uint16_t num_mac;
1117 uint8_t promiscuous;
1118 uint8_t if_id;
1119 /* dw 1-48 */
1120 struct {
1121 uint8_t byte[6];
1122 } mac[32];
1123
1124 } req;
1125
1126 struct {
1127 uint32_t rsvd0;
1128 } rsp;
1129
1130 uint32_t dw[49];
1131 } params;
1132};
1133
1134struct qinq_vlan {
1135#ifdef _BIG_ENDIAN
1136 uint16_t inner;
1137 uint16_t outer;
1138#else
1139 uint16_t outer;
1140 uint16_t inner;
1141#endif
1142};
1143
1144struct normal_vlan {
1145 uint16_t vtag;
1146};
1147
1148struct ntwk_if_vlan_tag {
1149 union {
1150 struct normal_vlan normal;
1151 struct qinq_vlan qinq;
1152 } u0;
1153};
1154
1155/* [50] OPCODE_COMMON_CREATE_IFACE */
1156struct mbx_create_common_iface {
1157 struct mbx_hdr hdr;
1158 union {
1159 struct {
1160 uint32_t version;
1161 uint32_t cap_flags;
1162 uint32_t enable_flags;
1163 uint8_t mac_addr[6];
1164 uint8_t rsvd0;
1165 uint8_t mac_invalid;
1166 struct ntwk_if_vlan_tag vlan_tag;
1167 } req;
1168
1169 struct {
1170 uint32_t if_id;
1171 uint32_t pmac_id;
1172 } rsp;
1173 uint32_t dw[4];
1174 } params;
1175};
1176
1177/* [51] OPCODE_COMMON_DESTROY_IFACE */
1178struct mbx_destroy_common_iface {
1179 struct mbx_hdr hdr;
1180 union {
1181 struct {
1182 uint32_t if_id;
1183 } req;
1184
1185 struct {
1186 uint32_t rsvd0;
1187 } rsp;
1188
1189 uint32_t dw;
1190 } params;
1191};
1192
1193/* event queue context structure */
1194struct oce_eq_ctx {
1195#ifdef _BIG_ENDIAN
1196 uint32_t dw4rsvd1:16;
1197 uint32_t num_pages:16;
1198
1199 uint32_t size:1;
1200 uint32_t dw5rsvd2:1;
1201 uint32_t valid:1;
1202 uint32_t dw5rsvd1:29;
1203
1204 uint32_t armed:1;
1205 uint32_t dw6rsvd2:2;
1206 uint32_t count:3;
1207 uint32_t dw6rsvd1:26;
1208
1209 uint32_t dw7rsvd2:9;
1210 uint32_t delay_mult:10;
1211 uint32_t dw7rsvd1:13;
1212
1213 uint32_t dw8rsvd1;
1214#else
1215 uint32_t num_pages:16;
1216 uint32_t dw4rsvd1:16;
1217
1218 uint32_t dw5rsvd1:29;
1219 uint32_t valid:1;
1220 uint32_t dw5rsvd2:1;
1221 uint32_t size:1;
1222
1223 uint32_t dw6rsvd1:26;
1224 uint32_t count:3;
1225 uint32_t dw6rsvd2:2;
1226 uint32_t armed:1;
1227
1228 uint32_t dw7rsvd1:13;
1229 uint32_t delay_mult:10;
1230 uint32_t dw7rsvd2:9;
1231
1232 uint32_t dw8rsvd1;
1233#endif
1234};
1235
1236/* [13] OPCODE_COMMON_CREATE_EQ */
1237struct mbx_create_common_eq {
1238 struct mbx_hdr hdr;
1239 union {
1240 struct {
1241 struct oce_eq_ctx ctx;
1242 struct phys_addr pages[8];
1243 } req;
1244
1245 struct {
1246 uint16_t eq_id;
1247 uint16_t rsvd0;
1248 } rsp;
1249 } params;
1250};
1251
1252/* [55] OPCODE_COMMON_DESTROY_EQ */
1253struct mbx_destroy_common_eq {
1254 struct mbx_hdr hdr;
1255 union {
1256 struct {
1257#ifdef _BIG_ENDIAN
1258 uint16_t rsvd0;
1259 uint16_t id;
1260#else
1261 uint16_t id;
1262 uint16_t rsvd0;
1263#endif
1264 } req;
1265
1266 struct {
1267 uint32_t rsvd0;
1268 } rsp;
1269 } params;
1270};
1271
1272/* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */
1273typedef union oce_cq_ctx_u {
1274 uint32_t dw[5];
1275 struct {
1276 #ifdef _BIG_ENDIAN
1277 /* dw4 */
1278 uint32_t dw4rsvd1:16;
1279 uint32_t num_pages:16;
1280 /* dw5 */
1281 uint32_t eventable:1;
1282 uint32_t dw5rsvd3:1;
1283 uint32_t valid:1;
1284 uint32_t count:2;
1285 uint32_t dw5rsvd2:12;
1286 uint32_t nodelay:1;
1287 uint32_t coalesce_wm:2;
1288 uint32_t dw5rsvd1:12;
1289 /* dw6 */
1290 uint32_t armed:1;
1291 uint32_t dw6rsvd2:1;
1292 uint32_t eq_id:8;
1293 uint32_t dw6rsvd1:22;
1294 #else
1295 /* dw4 */
1296 uint32_t num_pages:16;
1297 uint32_t dw4rsvd1:16;
1298 /* dw5 */
1299 uint32_t dw5rsvd1:12;
1300 uint32_t coalesce_wm:2;
1301 uint32_t nodelay:1;
1302 uint32_t dw5rsvd2:12;
1303 uint32_t count:2;
1304 uint32_t valid:1;
1305 uint32_t dw5rsvd3:1;
1306 uint32_t eventable:1;
1307 /* dw6 */
1308 uint32_t dw6rsvd1:22;
1309 uint32_t eq_id:8;
1310 uint32_t dw6rsvd2:1;
1311 uint32_t armed:1;
1312 #endif
1313 /* dw7 */
1314 uint32_t dw7rsvd1;
1315 /* dw8 */
1316 uint32_t dw8rsvd1;
1317 } v0;
1318 struct {
1319 #ifdef _BIG_ENDIAN
1320 /* dw4 */
1321 uint32_t dw4rsvd1:8;
1322 uint32_t page_size:8;
1323 uint32_t num_pages:16;
1324 /* dw5 */
1325 uint32_t eventable:1;
1326 uint32_t dw5rsvd3:1;
1327 uint32_t valid:1;
1328 uint32_t count:2;
1329 uint32_t dw5rsvd2:11;
1330 uint32_t autovalid:1;
1331 uint32_t nodelay:1;
1332 uint32_t coalesce_wm:2;
1333 uint32_t dw5rsvd1:12;
1334 /* dw6 */
1335 uint32_t armed:1;
1336 uint32_t dw6rsvd1:15;
1337 uint32_t eq_id:16;
1338 /* dw7 */
1339 uint32_t dw7rsvd1:16;
1340 uint32_t cqe_count:16;
1341 #else
1342 /* dw4 */
1343 uint32_t num_pages:16;
1344 uint32_t page_size:8;
1345 uint32_t dw4rsvd1:8;
1346 /* dw5 */
1347 uint32_t dw5rsvd1:12;
1348 uint32_t coalesce_wm:2;
1349 uint32_t nodelay:1;
1350 uint32_t autovalid:1;
1351 uint32_t dw5rsvd2:11;
1352 uint32_t count:2;
1353 uint32_t valid:1;
1354 uint32_t dw5rsvd3:1;
1355 uint32_t eventable:1;
1356 /* dw6 */
1357 uint32_t eq_id:8;
1358 uint32_t dw6rsvd1:15;
1359 uint32_t armed:1;
1360 /* dw7 */
1361 uint32_t cqe_count:16;
1362 uint32_t dw7rsvd1:16;
1363 #endif
1364 /* dw8 */
1365 uint32_t dw8rsvd1;
1366 } v2;
1367} oce_cq_ctx_t;
1368
1369/* [12] OPCODE_COMMON_CREATE_CQ */
1370struct mbx_create_common_cq {
1371 struct mbx_hdr hdr;
1372 union {
1373 struct {
1374 oce_cq_ctx_t cq_ctx;
1375 struct phys_addr pages[4];
1376 } req;
1377
1378 struct {
1379 uint16_t cq_id;
1380 uint16_t rsvd0;
1381 } rsp;
1382 } params;
1383};
1384
1385/* [54] OPCODE_COMMON_DESTROY_CQ */
1386struct mbx_destroy_common_cq {
1387 struct mbx_hdr hdr;
1388 union {
1389 struct {
1390#ifdef _BIG_ENDIAN
1391 uint16_t rsvd0;
1392 uint16_t id;
1393#else
1394 uint16_t id;
1395 uint16_t rsvd0;
1396#endif
1397 } req;
1398
1399 struct {
1400 uint32_t rsvd0;
1401 } rsp;
1402 } params;
1403};
1404
1405typedef union oce_mq_ctx_u {
1406 uint32_t dw[5];
1407 struct {
1408 #ifdef _BIG_ENDIAN
1409 /* dw4 */
1410 uint32_t dw4rsvd1:16;
1411 uint32_t num_pages:16;
1412 /* dw5 */
1413 uint32_t cq_id:10;
1414 uint32_t dw5rsvd2:2;
1415 uint32_t ring_size:4;
1416 uint32_t dw5rsvd1:16;
1417 /* dw6 */
1418 uint32_t valid:1;
1419 uint32_t dw6rsvd1:31;
1420 /* dw7 */
1421 uint32_t dw7rsvd1:21;
1422 uint32_t async_cq_id:10;
1423 uint32_t async_cq_valid:1;
1424 #else
1425 /* dw4 */
1426 uint32_t num_pages:16;
1427 uint32_t dw4rsvd1:16;
1428 /* dw5 */
1429 uint32_t dw5rsvd1:16;
1430 uint32_t ring_size:4;
1431 uint32_t dw5rsvd2:2;
1432 uint32_t cq_id:10;
1433 /* dw6 */
1434 uint32_t dw6rsvd1:31;
1435 uint32_t valid:1;
1436 /* dw7 */
1437 uint32_t async_cq_valid:1;
1438 uint32_t async_cq_id:10;
1439 uint32_t dw7rsvd1:21;
1440 #endif
1441 /* dw8 */
1442 uint32_t dw8rsvd1;
1443 } v0;
1444} oce_mq_ctx_t;
1445
1446/**
1447 * @brief [21] OPCODE_COMMON_CREATE_MQ
1448 * A MQ must be at least 16 entries deep (corresponding to 1 page) and
1449 * at most 128 entries deep (corresponding to 8 pages).
1450 */
1451struct mbx_create_common_mq {
1452 struct mbx_hdr hdr;
1453 union {
1454 struct {
1455 oce_mq_ctx_t context;
1456 struct phys_addr pages[8];
1457 } req;
1458
1459 struct {
1460 uint32_t mq_id:16;
1461 uint32_t rsvd0:16;
1462 } rsp;
1463 } params;
1464};
1465
1466struct mbx_create_common_mq_ex {
1467 struct mbx_hdr hdr;
1468 union {
1469 struct {
1470 oce_mq_ext_ctx_t context;
1471 struct phys_addr pages[8];
1472 } req;
1473
1474 struct {
1475 uint32_t mq_id:16;
1476 uint32_t rsvd0:16;
1477 } rsp;
1478 } params;
1479};
1480
1481
1482
1483/* [53] OPCODE_COMMON_DESTROY_MQ */
1484struct mbx_destroy_common_mq {
1485 struct mbx_hdr hdr;
1486 union {
1487 struct {
1488#ifdef _BIG_ENDIAN
1489 uint16_t rsvd0;
1490 uint16_t id;
1491#else
1492 uint16_t id;
1493 uint16_t rsvd0;
1494#endif
1495 } req;
1496
1497 struct {
1498 uint32_t rsvd0;
1499 } rsp;
1500 } params;
1501};
1502
1503/* [35] OPCODE_COMMON_GET_ FW_VERSION */
1504struct mbx_get_common_fw_version {
1505 struct mbx_hdr hdr;
1506 union {
1507 struct {
1508 uint32_t rsvd0;
1509 } req;
1510
1511 struct {
1512 uint8_t fw_ver_str[32];
1513 uint8_t fw_on_flash_ver_str[32];
1514 } rsp;
1515 } params;
1516};
1517
1518/* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
1519struct mbx_common_cev_modify_msi_messages {
1520 struct mbx_hdr hdr;
1521 union {
1522 struct {
1523 uint32_t num_msi_msgs;
1524 } req;
1525
1526 struct {
1527 uint32_t rsvd0;
1528 } rsp;
1529 } params;
1530};
1531
1532/* [36] OPCODE_COMMON_SET_FLOW_CONTROL */
1533/* [37] OPCODE_COMMON_GET_FLOW_CONTROL */
1534struct mbx_common_get_set_flow_control {
1535 struct mbx_hdr hdr;
1536#ifdef _BIG_ENDIAN
1537 uint16_t tx_flow_control;
1538 uint16_t rx_flow_control;
1539#else
1540 uint16_t rx_flow_control;
1541 uint16_t tx_flow_control;
1542#endif
1543};
1544
1545enum e_flash_opcode {
1546 MGMT_FLASHROM_OPCODE_FLASH = 1,
1547 MGMT_FLASHROM_OPCODE_SAVE = 2
1548};
1549
1550/* [06] OPCODE_READ_COMMON_FLASHROM */
1551/* [07] OPCODE_WRITE_COMMON_FLASHROM */
1552
1553struct mbx_common_read_write_flashrom {
1554 struct mbx_hdr hdr;
1555 uint32_t flash_op_code;
1556 uint32_t flash_op_type;
1557 uint32_t data_buffer_size;
1558 uint32_t data_offset;
1559 uint8_t data_buffer[4]; /* + IMAGE_TRANSFER_SIZE */
1560};
1561
1562struct oce_phy_info {
1563 uint16_t phy_type;
1564 uint16_t interface_type;
1565 uint32_t misc_params;
1566 uint16_t ext_phy_details;
1567 uint16_t rsvd;
1568 uint16_t auto_speeds_supported;
1569 uint16_t fixed_speeds_supported;
1570 uint32_t future_use[2];
1571};
1572
1573struct mbx_common_phy_info {
1574 struct mbx_hdr hdr;
1575 union {
1576 struct {
1577 uint32_t rsvd0[4];
1578 } req;
1579 struct {
1580 struct oce_phy_info phy_info;
1581 } rsp;
1582 } params;
1583};
1584
1585/*Lancer firmware*/
1586
1587struct mbx_lancer_common_write_object {
1588 union {
1589 struct {
1590 struct mbx_hdr hdr;
1591 uint32_t write_length: 24;
1592 uint32_t rsvd: 7;
1593 uint32_t eof: 1;
1594 uint32_t write_offset;
1595 uint8_t object_name[104];
1596 uint32_t descriptor_count;
1597 uint32_t buffer_length;
1598 uint32_t address_lower;
1599 uint32_t address_upper;
1600 } req;
1601 struct {
1602 uint8_t opcode;
1603 uint8_t subsystem;
1604 uint8_t rsvd1[2];
1605 uint8_t status;
1606 uint8_t additional_status;
1607 uint8_t rsvd2[2];
1608 uint32_t response_length;
1609 uint32_t actual_response_length;
1610 uint32_t actual_write_length;
1611 } rsp;
1612 } params;
1613};
1614
1615/**
1616 * @brief MBX Common Quiery Firmaware Config
1617 * This command retrieves firmware configuration parameters and adapter
1618 * resources available to the driver originating the request. The firmware
1619 * configuration defines supported protocols by the installed adapter firmware.
1620 * This includes which ULP processors support the specified protocols and
1621 * the number of TCP connections allowed for that protocol.
1622 */
1623struct mbx_common_query_fw_config {
1624 struct mbx_hdr hdr;
1625 union {
1626 struct {
1627 uint32_t rsvd0[30];
1628 } req;
1629
1630 struct {
1631 uint32_t config_number;
1632 uint32_t asic_revision;
1633 uint32_t port_id; /* used for stats retrieval */
1634 uint32_t function_mode;
1635 struct {
1636
1637 uint32_t ulp_mode;
1638 uint32_t nic_wqid_base;
1639 uint32_t nic_wq_tot;
1640 uint32_t toe_wqid_base;
1641 uint32_t toe_wq_tot;
1642 uint32_t toe_rqid_base;
1643 uint32_t toe_rqid_tot;
1644 uint32_t toe_defrqid_base;
1645 uint32_t toe_defrqid_count;
1646 uint32_t lro_rqid_base;
1647 uint32_t lro_rqid_tot;
1648 uint32_t iscsi_icd_base;
1649 uint32_t iscsi_icd_count;
1650 } ulp[2];
1651 uint32_t function_caps;
1652 uint32_t cqid_base;
1653 uint32_t cqid_tot;
1654 uint32_t eqid_base;
1655 uint32_t eqid_tot;
1656 } rsp;
1657 } params;
1658};
1659
1660enum CQFW_CONFIG_NUMBER {
1661 FCN_NIC_ISCSI_Initiator = 0x0,
1662 FCN_ISCSI_Target = 0x3,
1663 FCN_FCoE = 0x7,
1664 FCN_ISCSI_Initiator_Target = 0x9,
1665 FCN_NIC_RDMA_TOE = 0xA,
1666 FCN_NIC_RDMA_FCoE = 0xB,
1667 FCN_NIC_RDMA_iSCSI = 0xC,
1668 FCN_NIC_iSCSI_FCoE = 0xD
1669};
1670
1671/**
1672 * @brief Function Capabilites
1673 * This field contains the flags indicating the capabilities of
1674 * the SLI Host���s PCI function.
1675 */
1676enum CQFW_FUNCTION_CAPABILITIES {
1677 FNC_UNCLASSIFIED_STATS = 0x1,
1678 FNC_RSS = 0x2,
1679 FNC_PROMISCUOUS = 0x4,
1680 FNC_LEGACY_MODE = 0x8,
1681 FNC_HDS = 0x4000,
1682 FNC_VMQ = 0x10000,
1683 FNC_NETQ = 0x20000,
1684 FNC_QGROUPS = 0x40000,
1685 FNC_LRO = 0x100000,
1686 FNC_VLAN_OFFLOAD = 0x800000
1687};
1688
1689enum CQFW_ULP_MODES_SUPPORTED {
1690 ULP_TOE_MODE = 0x1,
1691 ULP_NIC_MODE = 0x2,
1692 ULP_RDMA_MODE = 0x4,
1693 ULP_ISCSI_INI_MODE = 0x10,
1694 ULP_ISCSI_TGT_MODE = 0x20,
1695 ULP_FCOE_INI_MODE = 0x40,
1696 ULP_FCOE_TGT_MODE = 0x80,
1697 ULP_DAL_MODE = 0x100,
1698 ULP_LRO_MODE = 0x200
1699};
1700
1701/**
1702 * @brief Function Modes Supported
1703 * Valid function modes (or protocol-types) supported on the SLI-Host���s
1704 * PCIe function. This field is a logical OR of the following values:
1705 */
1706enum CQFW_FUNCTION_MODES_SUPPORTED {
1707 FNM_TOE_MODE = 0x1, /* TCP offload supported */
1708 FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */
1709 FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */
1710 FNM_VM_MODE = 0x8, /* Virtual Machines supported */
1711 FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */
1712 FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */
1713 FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */
1714 FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */
1715 FNM_DAL_MODE = 0x100, /* DAL supported */
1716 FNM_LRO_MODE = 0x200, /* LRO supported */
1717 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */
1718 FNM_NCSI_MODE = 0x800, /* NCSI supported */
1719 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */
1720 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/
1721 FNM_INVALID_MODE = 0x8000, /* Invalid */
1722 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */
1723 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */
1724 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */
1725 FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */
1726 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */
1727 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */
1728 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */
1729 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */
1730};
1731
1732
1733struct mbx_common_config_vlan {
1734 struct mbx_hdr hdr;
1735 union {
1736 struct {
1737#ifdef _BIG_ENDIAN
1738 uint8_t num_vlans;
1739 uint8_t untagged;
1740 uint8_t promisc;
1741 uint8_t if_id;
1742#else
1743 uint8_t if_id;
1744 uint8_t promisc;
1745 uint8_t untagged;
1746 uint8_t num_vlans;
1747#endif
1748 union {
1749 struct normal_vlan normal_vlans[64];
1750 struct qinq_vlan qinq_vlans[32];
1751 } tags;
1752 } req;
1753
1754 struct {
1755 uint32_t rsvd;
1756 } rsp;
1757 } params;
1758};
1759
1760typedef struct iface_rx_filter_ctx {
1761 uint32_t global_flags_mask;
1762 uint32_t global_flags;
1763 uint32_t iface_flags_mask;
1764 uint32_t iface_flags;
1765 uint32_t if_id;
1766 #define IFACE_RX_NUM_MCAST_MAX 64
1767 uint32_t num_mcast;
1768 struct mbx_mcast_addr {
1769 uint8_t byte[6];
1770 } mac[IFACE_RX_NUM_MCAST_MAX];
1771} iface_rx_filter_ctx_t;
1772
1773/* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */
1774struct mbx_set_common_iface_rx_filter {
1775 struct mbx_hdr hdr;
1776 union {
1777 iface_rx_filter_ctx_t req;
1778 iface_rx_filter_ctx_t rsp;
1779 } params;
1780};
1781
|
| 1782struct be_set_eqd {
1783 uint32_t eq_id;
1784 uint32_t phase;
1785 uint32_t dm;
1786};
1787
|
1727/* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
1728struct mbx_modify_common_eq_delay {
1729 struct mbx_hdr hdr;
1730 union {
1731 struct {
1732 uint32_t num_eq;
1733 struct {
1734 uint32_t eq_id;
1735 uint32_t phase;
1736 uint32_t dm;
1737 } delay[8];
1738 } req;
1739
1740 struct {
1741 uint32_t rsvd0;
1742 } rsp;
1743 } params;
1744};
1745
| 1788/* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
1789struct mbx_modify_common_eq_delay {
1790 struct mbx_hdr hdr;
1791 union {
1792 struct {
1793 uint32_t num_eq;
1794 struct {
1795 uint32_t eq_id;
1796 uint32_t phase;
1797 uint32_t dm;
1798 } delay[8];
1799 } req;
1800
1801 struct {
1802 uint32_t rsvd0;
1803 } rsp;
1804 } params;
1805};
1806
|
| 1807/* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */
1808
1809struct mgmt_hba_attr {
1810 int8_t flashrom_ver_str[32];
1811 int8_t manufac_name[32];
1812 uint32_t supp_modes;
1813 int8_t seeprom_ver_lo;
1814 int8_t seeprom_ver_hi;
1815 int8_t rsvd0[2];
1816 uint32_t ioctl_data_struct_ver;
1817 uint32_t ep_fw_data_struct_ver;
1818 uint8_t ncsi_ver_str[12];
1819 uint32_t def_ext_to;
1820 int8_t cntl_mod_num[32];
1821 int8_t cntl_desc[64];
1822 int8_t cntl_ser_num[32];
1823 int8_t ip_ver_str[32];
1824 int8_t fw_ver_str[32];
1825 int8_t bios_ver_str[32];
1826 int8_t redboot_ver_str[32];
1827 int8_t drv_ver_str[32];
1828 int8_t fw_on_flash_ver_str[32];
1829 uint32_t funcs_supp;
1830 uint16_t max_cdblen;
1831 uint8_t asic_rev;
1832 uint8_t gen_guid[16];
1833 uint8_t hba_port_count;
1834 uint16_t default_link_down_timeout;
1835 uint8_t iscsi_ver_min_max;
1836 uint8_t multifunc_dev;
1837 uint8_t cache_valid;
1838 uint8_t hba_status;
1839 uint8_t max_domains_supp;
1840 uint8_t phy_port;
1841 uint32_t fw_post_status;
1842 uint32_t hba_mtu[8];
1843 uint8_t iSCSI_feat;
1844 uint8_t asic_gen;
1845 uint8_t future_u8[2];
1846 uint32_t future_u32[3];
1847};
1848
1849struct mgmt_cntl_attr {
1850 struct mgmt_hba_attr hba_attr;
1851 uint16_t pci_vendor_id;
1852 uint16_t pci_device_id;
1853 uint16_t pci_sub_vendor_id;
1854 uint16_t pci_sub_system_id;
1855 uint8_t pci_bus_num;
1856 uint8_t pci_dev_num;
1857 uint8_t pci_func_num;
1858 uint8_t interface_type;
1859 uint64_t unique_id;
1860 uint8_t netfilters;
1861 uint8_t rsvd0[3];
1862 uint32_t future_u32[4];
1863};
1864
1865struct mbx_common_get_cntl_attr {
1866 struct mbx_hdr hdr;
1867 union {
1868 struct {
1869 uint32_t rsvd0;
1870 } req;
1871 struct {
1872 struct mgmt_cntl_attr cntl_attr_info;
1873 } rsp;
1874 } params;
1875};
1876
|
1746/* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1747struct mbx_add_common_iface_mac {
1748 struct mbx_hdr hdr;
1749 union {
1750 struct {
1751 uint32_t if_id;
1752 uint8_t mac_address[6];
1753 uint8_t rsvd0[2];
1754 } req;
1755 struct {
1756 uint32_t pmac_id;
1757 } rsp;
1758 } params;
1759};
1760
1761/* [60] OPCODE_DEL_COMMON_IFACE_MAC */
1762struct mbx_del_common_iface_mac {
1763 struct mbx_hdr hdr;
1764 union {
1765 struct {
1766 uint32_t if_id;
1767 uint32_t pmac_id;
1768 } req;
1769 struct {
1770 uint32_t rsvd0;
1771 } rsp;
1772 } params;
1773};
1774
1775/* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
1776struct mbx_query_common_max_mbx_buffer_size {
1777 struct mbx_hdr hdr;
1778 struct {
1779 uint32_t max_ioctl_bufsz;
1780 } rsp;
1781};
1782
1783/* [61] OPCODE_COMMON_FUNCTION_RESET */
1784struct ioctl_common_function_reset {
1785 struct mbx_hdr hdr;
1786};
1787
| 1877/* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1878struct mbx_add_common_iface_mac {
1879 struct mbx_hdr hdr;
1880 union {
1881 struct {
1882 uint32_t if_id;
1883 uint8_t mac_address[6];
1884 uint8_t rsvd0[2];
1885 } req;
1886 struct {
1887 uint32_t pmac_id;
1888 } rsp;
1889 } params;
1890};
1891
1892/* [60] OPCODE_DEL_COMMON_IFACE_MAC */
1893struct mbx_del_common_iface_mac {
1894 struct mbx_hdr hdr;
1895 union {
1896 struct {
1897 uint32_t if_id;
1898 uint32_t pmac_id;
1899 } req;
1900 struct {
1901 uint32_t rsvd0;
1902 } rsp;
1903 } params;
1904};
1905
1906/* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
1907struct mbx_query_common_max_mbx_buffer_size {
1908 struct mbx_hdr hdr;
1909 struct {
1910 uint32_t max_ioctl_bufsz;
1911 } rsp;
1912};
1913
1914/* [61] OPCODE_COMMON_FUNCTION_RESET */
1915struct ioctl_common_function_reset {
1916 struct mbx_hdr hdr;
1917};
1918
|
| 1919/* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */
1920struct mbx_read_common_transrecv_data {
1921 struct mbx_hdr hdr;
1922 union {
1923 struct {
1924 uint32_t page_num;
1925 uint32_t port;
1926 } req;
1927 struct {
1928 uint32_t page_num;
1929 uint32_t port;
1930 uint32_t page_data[32];
1931 } rsp;
1932 } params;
1933
1934};
1935
|
1788/* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1789struct mbx_common_func_link_cfg {
1790 struct mbx_hdr hdr;
1791 union {
1792 struct {
1793 uint32_t enable;
1794 } req;
1795 struct {
1796 uint32_t rsvd0;
1797 } rsp;
1798 } params;
1799};
1800
1801/* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */
1802#define CAP_SW_TIMESTAMPS 2
1803#define CAP_BE3_NATIVE_ERX_API 4
1804
1805struct mbx_common_set_function_cap {
1806 struct mbx_hdr hdr;
1807 union {
1808 struct {
1809 uint32_t valid_capability_flags;
1810 uint32_t capability_flags;
1811 uint8_t sbz[212];
1812 } req;
1813 struct {
1814 uint32_t valid_capability_flags;
1815 uint32_t capability_flags;
1816 uint8_t sbz[212];
1817 } rsp;
1818 } params;
1819};
1820struct mbx_lowlevel_test_loopback_mode {
1821 struct mbx_hdr hdr;
1822 union {
1823 struct {
1824 uint32_t loopback_type;
1825 uint32_t num_pkts;
1826 uint64_t pattern;
1827 uint32_t src_port;
1828 uint32_t dest_port;
1829 uint32_t pkt_size;
1830 }req;
1831 struct {
1832 uint32_t status;
1833 uint32_t num_txfer;
1834 uint32_t num_rx;
1835 uint32_t miscomp_off;
1836 uint32_t ticks_compl;
1837 }rsp;
1838 } params;
1839};
1840
1841struct mbx_lowlevel_set_loopback_mode {
1842 struct mbx_hdr hdr;
1843 union {
1844 struct {
1845 uint8_t src_port;
1846 uint8_t dest_port;
1847 uint8_t loopback_type;
1848 uint8_t loopback_state;
1849 } req;
1850 struct {
1851 uint8_t rsvd0[4];
1852 } rsp;
1853 } params;
1854};
1855
1856struct flash_file_hdr {
1857 uint8_t sign[52];
1858 uint8_t ufi_version[4];
1859 uint32_t file_len;
1860 uint32_t cksum;
1861 uint32_t antidote;
1862 uint32_t num_imgs;
1863 uint8_t build[24];
1864 uint8_t rsvd[32];
1865};
1866
1867struct image_hdr {
1868 uint32_t imageid;
1869 uint32_t imageoffset;
1870 uint32_t imagelength;
1871 uint32_t image_checksum;
1872 uint8_t image_version[32];
1873};
1874
1875struct flash_section_hdr {
1876 uint32_t format_rev;
1877 uint32_t cksum;
1878 uint32_t antidote;
1879 uint32_t num_images;
1880 uint8_t id_string[128];
1881 uint32_t rsvd[4];
1882};
1883
1884struct flash_section_entry {
1885 uint32_t type;
1886 uint32_t offset;
1887 uint32_t pad_size;
1888 uint32_t image_size;
1889 uint32_t cksum;
1890 uint32_t entry_point;
1891 uint32_t rsvd0;
1892 uint32_t rsvd1;
1893 uint8_t ver_data[32];
1894};
1895
1896struct flash_sec_info {
1897 uint8_t cookie[32];
1898 struct flash_section_hdr fsec_hdr;
1899 struct flash_section_entry fsec_entry[32];
1900};
1901
1902
1903enum LOWLEVEL_SUBSYSTEM_OPCODES {
1904/* Opcodes used for lowlevel functions common to many subystems.
1905 * Some of these opcodes are used for diagnostic functions only.
1906 * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code.
1907 */
1908 OPCODE_LOWLEVEL_TEST_LOOPBACK = 18,
1909 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19,
1910 OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20
1911};
1912
1913enum LLDP_SUBSYSTEM_OPCODES {
1914/* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */
1915 OPCODE_LLDP_GET_CFG = 1,
1916 OPCODE_LLDP_SET_CFG = 2,
1917 OPCODE_LLDP_GET_STATS = 3
1918};
1919
1920enum DCBX_SUBSYSTEM_OPCODES {
1921/* Opcodes used for DCBX. */
1922 OPCODE_DCBX_GET_CFG = 1,
1923 OPCODE_DCBX_SET_CFG = 2,
1924 OPCODE_DCBX_GET_MIB_INFO = 3,
1925 OPCODE_DCBX_GET_DCBX_MODE = 4,
1926 OPCODE_DCBX_SET_MODE = 5
1927};
1928
1929enum DMTF_SUBSYSTEM_OPCODES {
1930/* Opcodes used for DCBX subsystem. */
1931 OPCODE_DMTF_EXEC_CLP_CMD = 1
1932};
1933
1934enum DIAG_SUBSYSTEM_OPCODES {
1935/* Opcodes used for diag functions common to many subsystems. */
1936 OPCODE_DIAG_RUN_DMA_TEST = 1,
1937 OPCODE_DIAG_RUN_MDIO_TEST = 2,
1938 OPCODE_DIAG_RUN_NLB_TEST = 3,
1939 OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4,
1940 OPCODE_DIAG_GET_MAC = 5
1941};
1942
1943enum VENDOR_SUBSYSTEM_OPCODES {
1944/* Opcodes used for Vendor subsystem. */
1945 OPCODE_VENDOR_SLI = 1
1946};
1947
1948/* Management Status Codes */
1949enum MGMT_STATUS_SUCCESS {
1950 MGMT_SUCCESS = 0,
1951 MGMT_FAILED = 1,
1952 MGMT_ILLEGAL_REQUEST = 2,
1953 MGMT_ILLEGAL_FIELD = 3,
1954 MGMT_INSUFFICIENT_BUFFER = 4,
1955 MGMT_UNAUTHORIZED_REQUEST = 5,
1956 MGMT_INVALID_ISNS_ADDRESS = 10,
1957 MGMT_INVALID_IPADDR = 11,
1958 MGMT_INVALID_GATEWAY = 12,
1959 MGMT_INVALID_SUBNETMASK = 13,
1960 MGMT_INVALID_TARGET_IPADDR = 16,
1961 MGMT_TGTTBL_FULL = 20,
1962 MGMT_FLASHROM_SAVE_FAILED = 23,
1963 MGMT_IOCTLHANDLE_ALLOC_FAILED = 27,
1964 MGMT_INVALID_SESSION = 31,
1965 MGMT_INVALID_CONNECTION = 32,
1966 MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33,
1967 MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34,
1968 MGMT_BTL_PATH_TGTID_OCCUPIED = 35,
1969 MGMT_BTL_NO_FREE_SLOT_PATH = 36,
1970 MGMT_BTL_NO_FREE_SLOT_TGTID = 37,
1971 MGMT_POLL_IOCTL_TIMEOUT = 40,
1972 MGMT_ERROR_ACITISCSI = 41,
1973 MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43,
1974 MGMT_REBOOT_REQUIRED = 44,
1975 MGMT_INSUFFICIENT_TIMEOUT = 45,
1976 MGMT_IPADDR_NOT_SET = 46,
1977 MGMT_IPADDR_DUP_DETECTED = 47,
1978 MGMT_CANT_REMOVE_LAST_CONNECTION = 48,
1979 MGMT_TARGET_BUSY = 49,
1980 MGMT_TGT_ERR_LISTEN_SOCKET = 50,
1981 MGMT_TGT_ERR_BIND_SOCKET = 51,
1982 MGMT_TGT_ERR_NO_SOCKET = 52,
1983 MGMT_TGT_ERR_ISNS_COMM_FAILED = 55,
1984 MGMT_CANNOT_DELETE_BOOT_TARGET = 56,
1985 MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57,
1986 MGMT_FCF_IN_USE = 58 ,
1987 MGMT_NO_CQE = 59,
1988 MGMT_TARGET_NOT_FOUND = 65,
1989 MGMT_NOT_SUPPORTED = 66,
1990 MGMT_NO_FCF_RECORDS = 67,
1991 MGMT_FEATURE_NOT_SUPPORTED = 68,
1992 MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69,
1993 MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70,
1994 MGMT_INVALID_NON_EMBEDDED_WRB = 71,
1995 MGMT_OOR = 100,
1996 MGMT_INVALID_PD = 101,
1997 MGMT_STATUS_PD_INUSE = 102,
1998 MGMT_INVALID_CQ = 103,
1999 MGMT_INVALID_QP = 104,
2000 MGMT_INVALID_STAG = 105,
2001 MGMT_ORD_EXCEEDS = 106,
2002 MGMT_IRD_EXCEEDS = 107,
2003 MGMT_SENDQ_WQE_EXCEEDS = 108,
2004 MGMT_RECVQ_RQE_EXCEEDS = 109,
2005 MGMT_SGE_SEND_EXCEEDS = 110,
2006 MGMT_SGE_WRITE_EXCEEDS = 111,
2007 MGMT_SGE_RECV_EXCEEDS = 112,
2008 MGMT_INVALID_STATE_CHANGE = 113,
2009 MGMT_MW_BOUND = 114,
2010 MGMT_INVALID_VA = 115,
2011 MGMT_INVALID_LENGTH = 116,
2012 MGMT_INVALID_FBO = 117,
2013 MGMT_INVALID_ACC_RIGHTS = 118,
2014 MGMT_INVALID_PBE_SIZE = 119,
2015 MGMT_INVALID_PBL_ENTRY = 120,
2016 MGMT_INVALID_PBL_OFFSET = 121,
2017 MGMT_ADDR_NON_EXIST = 122,
2018 MGMT_INVALID_VLANID = 123,
2019 MGMT_INVALID_MTU = 124,
2020 MGMT_INVALID_BACKLOG = 125,
2021 MGMT_CONNECTION_INPROGRESS = 126,
2022 MGMT_INVALID_RQE_SIZE = 127,
2023 MGMT_INVALID_RQE_ENTRY = 128
2024};
2025
2026/* Additional Management Status Codes */
2027enum MGMT_ADDI_STATUS {
2028 MGMT_ADDI_NO_STATUS = 0,
2029 MGMT_ADDI_INVALID_IPTYPE = 1,
2030 MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9,
2031 MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10,
2032 MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11,
2033 MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16,
2034 MGMT_ADDI_SESSION_ALREADY_OPENED = 17,
2035 MGMT_ADDI_SESSION_ALREADY_CLOSED = 18,
2036 MGMT_ADDI_DEST_HOST_UNREACHABLE = 19,
2037 MGMT_ADDI_LOGIN_IN_PROGRESS = 20,
2038 MGMT_ADDI_TCP_CONNECT_FAILED = 21,
2039 MGMT_ADDI_INSUFFICIENT_RESOURCES = 22,
2040 MGMT_ADDI_LINK_DOWN = 23,
2041 MGMT_ADDI_DHCP_ERROR = 24,
2042 MGMT_ADDI_CONNECTION_OFFLOADED = 25,
2043 MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26,
2044 MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27,
2045 MGMT_ADDI_REQUEST_REJECTED = 28,
2046 MGMT_ADDI_INVALID_SUBSYSTEM = 29,
2047 MGMT_ADDI_INVALID_OPCODE = 30,
2048 MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31,
2049 MGMT_ADDI_INVALID_KEY = 32,
2050 MGMT_ADDI_INVALID_DOMAIN = 35,
2051 MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43,
2052 MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44,
2053 MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45,
2054 MGMT_ADDI_LOGIN_NOT_FOUND = 46,
2055 MGMT_ADDI_LOGIN_TARGET_REMOVED = 47,
2056 MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48,
2057 MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49,
2058 MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50,
2059 MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51,
2060 MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52,
2061 MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53,
2062 MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54,
2063 MGMT_ADDI_LOGIN_TARGET_ERROR = 55,
2064 MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56,
2065 MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57,
2066 MGMT_ADDI_SAME_CHAP_SECRET = 58,
2067 MGMT_ADDI_INVALID_SECRET_LENGTH = 59,
2068 MGMT_ADDI_DUPLICATE_ENTRY = 60,
2069 MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63,
2070 MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64,
2071 MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65,
2072 MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66,
2073 MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67,
2074 MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68,
2075 MGMT_ADDI_INVALID_VLAN_RANGE = 69,
2076 MGMT_ADDI_ERR_SET_VLAN = 70,
2077 MGMT_ADDI_ERR_DEL_VLAN = 71,
2078 MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72,
2079 MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73,
2080 MGMT_ADDI_TOO_MANY_INTERFACES = 74,
2081 MGMT_ADDI_INVALID_REQUEST = 75
2082};
2083
2084enum NIC_SUBSYSTEM_OPCODES {
2085/**
2086 * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2)
2087 * These opcodes are used for configuring the Ethernet interfaces.
2088 * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code.
2089 */
2090 NIC_CONFIG_RSS = 1,
2091 NIC_CONFIG_ACPI = 2,
2092 NIC_CONFIG_PROMISCUOUS = 3,
2093 NIC_GET_STATS = 4,
2094 NIC_CREATE_WQ = 7,
2095 NIC_CREATE_RQ = 8,
2096 NIC_DELETE_WQ = 9,
2097 NIC_DELETE_RQ = 10,
2098 NIC_CONFIG_ACPI_WOL_MAGIC = 12,
2099 NIC_GET_NETWORK_STATS = 13,
2100 NIC_CREATE_HDS_RQ = 16,
2101 NIC_DELETE_HDS_RQ = 17,
2102 NIC_GET_PPORT_STATS = 18,
2103 NIC_GET_VPORT_STATS = 19,
2104 NIC_GET_QUEUE_STATS = 20
2105};
2106
2107/* Hash option flags for RSS enable */
2108enum RSS_ENABLE_FLAGS {
2109 RSS_ENABLE_NONE = 0x0, /* (No RSS) */
2110 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */
2111 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */
2112 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */
| 1936/* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1937struct mbx_common_func_link_cfg {
1938 struct mbx_hdr hdr;
1939 union {
1940 struct {
1941 uint32_t enable;
1942 } req;
1943 struct {
1944 uint32_t rsvd0;
1945 } rsp;
1946 } params;
1947};
1948
1949/* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */
1950#define CAP_SW_TIMESTAMPS 2
1951#define CAP_BE3_NATIVE_ERX_API 4
1952
1953struct mbx_common_set_function_cap {
1954 struct mbx_hdr hdr;
1955 union {
1956 struct {
1957 uint32_t valid_capability_flags;
1958 uint32_t capability_flags;
1959 uint8_t sbz[212];
1960 } req;
1961 struct {
1962 uint32_t valid_capability_flags;
1963 uint32_t capability_flags;
1964 uint8_t sbz[212];
1965 } rsp;
1966 } params;
1967};
1968struct mbx_lowlevel_test_loopback_mode {
1969 struct mbx_hdr hdr;
1970 union {
1971 struct {
1972 uint32_t loopback_type;
1973 uint32_t num_pkts;
1974 uint64_t pattern;
1975 uint32_t src_port;
1976 uint32_t dest_port;
1977 uint32_t pkt_size;
1978 }req;
1979 struct {
1980 uint32_t status;
1981 uint32_t num_txfer;
1982 uint32_t num_rx;
1983 uint32_t miscomp_off;
1984 uint32_t ticks_compl;
1985 }rsp;
1986 } params;
1987};
1988
1989struct mbx_lowlevel_set_loopback_mode {
1990 struct mbx_hdr hdr;
1991 union {
1992 struct {
1993 uint8_t src_port;
1994 uint8_t dest_port;
1995 uint8_t loopback_type;
1996 uint8_t loopback_state;
1997 } req;
1998 struct {
1999 uint8_t rsvd0[4];
2000 } rsp;
2001 } params;
2002};
2003
2004struct flash_file_hdr {
2005 uint8_t sign[52];
2006 uint8_t ufi_version[4];
2007 uint32_t file_len;
2008 uint32_t cksum;
2009 uint32_t antidote;
2010 uint32_t num_imgs;
2011 uint8_t build[24];
2012 uint8_t rsvd[32];
2013};
2014
2015struct image_hdr {
2016 uint32_t imageid;
2017 uint32_t imageoffset;
2018 uint32_t imagelength;
2019 uint32_t image_checksum;
2020 uint8_t image_version[32];
2021};
2022
2023struct flash_section_hdr {
2024 uint32_t format_rev;
2025 uint32_t cksum;
2026 uint32_t antidote;
2027 uint32_t num_images;
2028 uint8_t id_string[128];
2029 uint32_t rsvd[4];
2030};
2031
2032struct flash_section_entry {
2033 uint32_t type;
2034 uint32_t offset;
2035 uint32_t pad_size;
2036 uint32_t image_size;
2037 uint32_t cksum;
2038 uint32_t entry_point;
2039 uint32_t rsvd0;
2040 uint32_t rsvd1;
2041 uint8_t ver_data[32];
2042};
2043
2044struct flash_sec_info {
2045 uint8_t cookie[32];
2046 struct flash_section_hdr fsec_hdr;
2047 struct flash_section_entry fsec_entry[32];
2048};
2049
2050
2051enum LOWLEVEL_SUBSYSTEM_OPCODES {
2052/* Opcodes used for lowlevel functions common to many subystems.
2053 * Some of these opcodes are used for diagnostic functions only.
2054 * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code.
2055 */
2056 OPCODE_LOWLEVEL_TEST_LOOPBACK = 18,
2057 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19,
2058 OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20
2059};
2060
2061enum LLDP_SUBSYSTEM_OPCODES {
2062/* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */
2063 OPCODE_LLDP_GET_CFG = 1,
2064 OPCODE_LLDP_SET_CFG = 2,
2065 OPCODE_LLDP_GET_STATS = 3
2066};
2067
2068enum DCBX_SUBSYSTEM_OPCODES {
2069/* Opcodes used for DCBX. */
2070 OPCODE_DCBX_GET_CFG = 1,
2071 OPCODE_DCBX_SET_CFG = 2,
2072 OPCODE_DCBX_GET_MIB_INFO = 3,
2073 OPCODE_DCBX_GET_DCBX_MODE = 4,
2074 OPCODE_DCBX_SET_MODE = 5
2075};
2076
2077enum DMTF_SUBSYSTEM_OPCODES {
2078/* Opcodes used for DCBX subsystem. */
2079 OPCODE_DMTF_EXEC_CLP_CMD = 1
2080};
2081
2082enum DIAG_SUBSYSTEM_OPCODES {
2083/* Opcodes used for diag functions common to many subsystems. */
2084 OPCODE_DIAG_RUN_DMA_TEST = 1,
2085 OPCODE_DIAG_RUN_MDIO_TEST = 2,
2086 OPCODE_DIAG_RUN_NLB_TEST = 3,
2087 OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4,
2088 OPCODE_DIAG_GET_MAC = 5
2089};
2090
2091enum VENDOR_SUBSYSTEM_OPCODES {
2092/* Opcodes used for Vendor subsystem. */
2093 OPCODE_VENDOR_SLI = 1
2094};
2095
2096/* Management Status Codes */
2097enum MGMT_STATUS_SUCCESS {
2098 MGMT_SUCCESS = 0,
2099 MGMT_FAILED = 1,
2100 MGMT_ILLEGAL_REQUEST = 2,
2101 MGMT_ILLEGAL_FIELD = 3,
2102 MGMT_INSUFFICIENT_BUFFER = 4,
2103 MGMT_UNAUTHORIZED_REQUEST = 5,
2104 MGMT_INVALID_ISNS_ADDRESS = 10,
2105 MGMT_INVALID_IPADDR = 11,
2106 MGMT_INVALID_GATEWAY = 12,
2107 MGMT_INVALID_SUBNETMASK = 13,
2108 MGMT_INVALID_TARGET_IPADDR = 16,
2109 MGMT_TGTTBL_FULL = 20,
2110 MGMT_FLASHROM_SAVE_FAILED = 23,
2111 MGMT_IOCTLHANDLE_ALLOC_FAILED = 27,
2112 MGMT_INVALID_SESSION = 31,
2113 MGMT_INVALID_CONNECTION = 32,
2114 MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33,
2115 MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34,
2116 MGMT_BTL_PATH_TGTID_OCCUPIED = 35,
2117 MGMT_BTL_NO_FREE_SLOT_PATH = 36,
2118 MGMT_BTL_NO_FREE_SLOT_TGTID = 37,
2119 MGMT_POLL_IOCTL_TIMEOUT = 40,
2120 MGMT_ERROR_ACITISCSI = 41,
2121 MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43,
2122 MGMT_REBOOT_REQUIRED = 44,
2123 MGMT_INSUFFICIENT_TIMEOUT = 45,
2124 MGMT_IPADDR_NOT_SET = 46,
2125 MGMT_IPADDR_DUP_DETECTED = 47,
2126 MGMT_CANT_REMOVE_LAST_CONNECTION = 48,
2127 MGMT_TARGET_BUSY = 49,
2128 MGMT_TGT_ERR_LISTEN_SOCKET = 50,
2129 MGMT_TGT_ERR_BIND_SOCKET = 51,
2130 MGMT_TGT_ERR_NO_SOCKET = 52,
2131 MGMT_TGT_ERR_ISNS_COMM_FAILED = 55,
2132 MGMT_CANNOT_DELETE_BOOT_TARGET = 56,
2133 MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57,
2134 MGMT_FCF_IN_USE = 58 ,
2135 MGMT_NO_CQE = 59,
2136 MGMT_TARGET_NOT_FOUND = 65,
2137 MGMT_NOT_SUPPORTED = 66,
2138 MGMT_NO_FCF_RECORDS = 67,
2139 MGMT_FEATURE_NOT_SUPPORTED = 68,
2140 MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69,
2141 MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70,
2142 MGMT_INVALID_NON_EMBEDDED_WRB = 71,
2143 MGMT_OOR = 100,
2144 MGMT_INVALID_PD = 101,
2145 MGMT_STATUS_PD_INUSE = 102,
2146 MGMT_INVALID_CQ = 103,
2147 MGMT_INVALID_QP = 104,
2148 MGMT_INVALID_STAG = 105,
2149 MGMT_ORD_EXCEEDS = 106,
2150 MGMT_IRD_EXCEEDS = 107,
2151 MGMT_SENDQ_WQE_EXCEEDS = 108,
2152 MGMT_RECVQ_RQE_EXCEEDS = 109,
2153 MGMT_SGE_SEND_EXCEEDS = 110,
2154 MGMT_SGE_WRITE_EXCEEDS = 111,
2155 MGMT_SGE_RECV_EXCEEDS = 112,
2156 MGMT_INVALID_STATE_CHANGE = 113,
2157 MGMT_MW_BOUND = 114,
2158 MGMT_INVALID_VA = 115,
2159 MGMT_INVALID_LENGTH = 116,
2160 MGMT_INVALID_FBO = 117,
2161 MGMT_INVALID_ACC_RIGHTS = 118,
2162 MGMT_INVALID_PBE_SIZE = 119,
2163 MGMT_INVALID_PBL_ENTRY = 120,
2164 MGMT_INVALID_PBL_OFFSET = 121,
2165 MGMT_ADDR_NON_EXIST = 122,
2166 MGMT_INVALID_VLANID = 123,
2167 MGMT_INVALID_MTU = 124,
2168 MGMT_INVALID_BACKLOG = 125,
2169 MGMT_CONNECTION_INPROGRESS = 126,
2170 MGMT_INVALID_RQE_SIZE = 127,
2171 MGMT_INVALID_RQE_ENTRY = 128
2172};
2173
2174/* Additional Management Status Codes */
2175enum MGMT_ADDI_STATUS {
2176 MGMT_ADDI_NO_STATUS = 0,
2177 MGMT_ADDI_INVALID_IPTYPE = 1,
2178 MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9,
2179 MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10,
2180 MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11,
2181 MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16,
2182 MGMT_ADDI_SESSION_ALREADY_OPENED = 17,
2183 MGMT_ADDI_SESSION_ALREADY_CLOSED = 18,
2184 MGMT_ADDI_DEST_HOST_UNREACHABLE = 19,
2185 MGMT_ADDI_LOGIN_IN_PROGRESS = 20,
2186 MGMT_ADDI_TCP_CONNECT_FAILED = 21,
2187 MGMT_ADDI_INSUFFICIENT_RESOURCES = 22,
2188 MGMT_ADDI_LINK_DOWN = 23,
2189 MGMT_ADDI_DHCP_ERROR = 24,
2190 MGMT_ADDI_CONNECTION_OFFLOADED = 25,
2191 MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26,
2192 MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27,
2193 MGMT_ADDI_REQUEST_REJECTED = 28,
2194 MGMT_ADDI_INVALID_SUBSYSTEM = 29,
2195 MGMT_ADDI_INVALID_OPCODE = 30,
2196 MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31,
2197 MGMT_ADDI_INVALID_KEY = 32,
2198 MGMT_ADDI_INVALID_DOMAIN = 35,
2199 MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43,
2200 MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44,
2201 MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45,
2202 MGMT_ADDI_LOGIN_NOT_FOUND = 46,
2203 MGMT_ADDI_LOGIN_TARGET_REMOVED = 47,
2204 MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48,
2205 MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49,
2206 MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50,
2207 MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51,
2208 MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52,
2209 MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53,
2210 MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54,
2211 MGMT_ADDI_LOGIN_TARGET_ERROR = 55,
2212 MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56,
2213 MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57,
2214 MGMT_ADDI_SAME_CHAP_SECRET = 58,
2215 MGMT_ADDI_INVALID_SECRET_LENGTH = 59,
2216 MGMT_ADDI_DUPLICATE_ENTRY = 60,
2217 MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63,
2218 MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64,
2219 MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65,
2220 MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66,
2221 MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67,
2222 MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68,
2223 MGMT_ADDI_INVALID_VLAN_RANGE = 69,
2224 MGMT_ADDI_ERR_SET_VLAN = 70,
2225 MGMT_ADDI_ERR_DEL_VLAN = 71,
2226 MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72,
2227 MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73,
2228 MGMT_ADDI_TOO_MANY_INTERFACES = 74,
2229 MGMT_ADDI_INVALID_REQUEST = 75
2230};
2231
2232enum NIC_SUBSYSTEM_OPCODES {
2233/**
2234 * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2)
2235 * These opcodes are used for configuring the Ethernet interfaces.
2236 * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code.
2237 */
2238 NIC_CONFIG_RSS = 1,
2239 NIC_CONFIG_ACPI = 2,
2240 NIC_CONFIG_PROMISCUOUS = 3,
2241 NIC_GET_STATS = 4,
2242 NIC_CREATE_WQ = 7,
2243 NIC_CREATE_RQ = 8,
2244 NIC_DELETE_WQ = 9,
2245 NIC_DELETE_RQ = 10,
2246 NIC_CONFIG_ACPI_WOL_MAGIC = 12,
2247 NIC_GET_NETWORK_STATS = 13,
2248 NIC_CREATE_HDS_RQ = 16,
2249 NIC_DELETE_HDS_RQ = 17,
2250 NIC_GET_PPORT_STATS = 18,
2251 NIC_GET_VPORT_STATS = 19,
2252 NIC_GET_QUEUE_STATS = 20
2253};
2254
2255/* Hash option flags for RSS enable */
2256enum RSS_ENABLE_FLAGS {
2257 RSS_ENABLE_NONE = 0x0, /* (No RSS) */
2258 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */
2259 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */
2260 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */
|
2113 RSS_ENABLE_TCP_IPV6 = 0x8 /* (TCP IPV6 HASH */
| 2261 RSS_ENABLE_TCP_IPV6 = 0x8, /* (TCP IPV6 HASH */
2262 RSS_ENABLE_UDP_IPV4 = 0x10, /* UDP IPV4 HASH */
2263 RSS_ENABLE_UDP_IPV6 = 0x20 /* UDP IPV6 HASH */
|
2114};
2115#define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
2116#define RSS_DISABLE RSS_ENABLE_NONE
2117
2118/* NIC header WQE */
2119struct oce_nic_hdr_wqe {
2120 union {
2121 struct {
2122#ifdef _BIG_ENDIAN
2123 /* dw0 */
2124 uint32_t rsvd0;
2125
2126 /* dw1 */
2127 uint32_t last_seg_udp_len:14;
2128 uint32_t rsvd1:18;
2129
2130 /* dw2 */
2131 uint32_t lso_mss:14;
2132 uint32_t num_wqe:5;
2133 uint32_t rsvd4:2;
2134 uint32_t vlan:1;
2135 uint32_t lso:1;
2136 uint32_t tcpcs:1;
2137 uint32_t udpcs:1;
2138 uint32_t ipcs:1;
2139 uint32_t rsvd3:1;
2140 uint32_t rsvd2:1;
2141 uint32_t forward:1;
2142 uint32_t crc:1;
2143 uint32_t event:1;
2144 uint32_t complete:1;
2145
2146 /* dw3 */
2147 uint32_t vlan_tag:16;
2148 uint32_t total_length:16;
2149#else
2150 /* dw0 */
2151 uint32_t rsvd0;
2152
2153 /* dw1 */
2154 uint32_t rsvd1:18;
2155 uint32_t last_seg_udp_len:14;
2156
2157 /* dw2 */
2158 uint32_t complete:1;
2159 uint32_t event:1;
2160 uint32_t crc:1;
2161 uint32_t forward:1;
2162 uint32_t rsvd2:1;
2163 uint32_t rsvd3:1;
2164 uint32_t ipcs:1;
2165 uint32_t udpcs:1;
2166 uint32_t tcpcs:1;
2167 uint32_t lso:1;
2168 uint32_t vlan:1;
2169 uint32_t rsvd4:2;
2170 uint32_t num_wqe:5;
2171 uint32_t lso_mss:14;
2172
2173 /* dw3 */
2174 uint32_t total_length:16;
2175 uint32_t vlan_tag:16;
2176#endif
2177 } s;
2178 uint32_t dw[4];
2179 } u0;
2180};
2181
2182/* NIC fragment WQE */
2183struct oce_nic_frag_wqe {
2184 union {
2185 struct {
2186 /* dw0 */
2187 uint32_t frag_pa_hi;
2188 /* dw1 */
2189 uint32_t frag_pa_lo;
2190 /* dw2 */
2191 uint32_t rsvd0;
2192 uint32_t frag_len;
2193 } s;
2194 uint32_t dw[4];
2195 } u0;
2196};
2197
2198/* Ethernet Tx Completion Descriptor */
2199struct oce_nic_tx_cqe {
2200 union {
2201 struct {
2202#ifdef _BIG_ENDIAN
2203 /* dw 0 */
2204 uint32_t status:4;
2205 uint32_t rsvd0:8;
2206 uint32_t port:2;
2207 uint32_t ct:2;
2208 uint32_t wqe_index:16;
2209
2210 /* dw 1 */
2211 uint32_t rsvd1:5;
2212 uint32_t cast_enc:2;
2213 uint32_t lso:1;
2214 uint32_t nwh_bytes:8;
2215 uint32_t user_bytes:16;
2216
2217 /* dw 2 */
2218 uint32_t rsvd2;
2219
2220 /* dw 3 */
2221 uint32_t valid:1;
2222 uint32_t rsvd3:4;
2223 uint32_t wq_id:11;
2224 uint32_t num_pkts:16;
2225#else
2226 /* dw 0 */
2227 uint32_t wqe_index:16;
2228 uint32_t ct:2;
2229 uint32_t port:2;
2230 uint32_t rsvd0:8;
2231 uint32_t status:4;
2232
2233 /* dw 1 */
2234 uint32_t user_bytes:16;
2235 uint32_t nwh_bytes:8;
2236 uint32_t lso:1;
2237 uint32_t cast_enc:2;
2238 uint32_t rsvd1:5;
2239 /* dw 2 */
2240 uint32_t rsvd2;
2241
2242 /* dw 3 */
2243 uint32_t num_pkts:16;
2244 uint32_t wq_id:11;
2245 uint32_t rsvd3:4;
2246 uint32_t valid:1;
2247#endif
2248 } s;
2249 uint32_t dw[4];
2250 } u0;
2251};
2252#define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3])
2253#define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0)
2254
2255/* Receive Queue Entry (RQE) */
2256struct oce_nic_rqe {
2257 union {
2258 struct {
2259 uint32_t frag_pa_hi;
2260 uint32_t frag_pa_lo;
2261 } s;
2262 uint32_t dw[2];
2263 } u0;
2264};
2265
2266/* NIC Receive CQE */
2267struct oce_nic_rx_cqe {
2268 union {
2269 struct {
2270#ifdef _BIG_ENDIAN
2271 /* dw 0 */
2272 uint32_t ip_options:1;
2273 uint32_t port:1;
2274 uint32_t pkt_size:14;
2275 uint32_t vlan_tag:16;
2276
2277 /* dw 1 */
2278 uint32_t num_fragments:3;
2279 uint32_t switched:1;
2280 uint32_t ct:2;
2281 uint32_t frag_index:10;
2282 uint32_t rsvd0:1;
2283 uint32_t vlan_tag_present:1;
2284 uint32_t mac_dst:6;
2285 uint32_t ip_ver:1;
2286 uint32_t l4_cksum_pass:1;
2287 uint32_t ip_cksum_pass:1;
2288 uint32_t udpframe:1;
2289 uint32_t tcpframe:1;
2290 uint32_t ipframe:1;
2291 uint32_t rss_hp:1;
2292 uint32_t error:1;
2293
2294 /* dw 2 */
2295 uint32_t valid:1;
2296 uint32_t hds_type:2;
2297 uint32_t lro_pkt:1;
2298 uint32_t rsvd4:1;
2299 uint32_t hds_hdr_size:12;
2300 uint32_t hds_hdr_frag_index:10;
2301 uint32_t rss_bank:1;
2302 uint32_t qnq:1;
2303 uint32_t pkt_type:2;
2304 uint32_t rss_flush:1;
2305
2306 /* dw 3 */
2307 uint32_t rss_hash_value;
2308#else
2309 /* dw 0 */
2310 uint32_t vlan_tag:16;
2311 uint32_t pkt_size:14;
2312 uint32_t port:1;
2313 uint32_t ip_options:1;
2314 /* dw 1 */
2315 uint32_t error:1;
2316 uint32_t rss_hp:1;
2317 uint32_t ipframe:1;
2318 uint32_t tcpframe:1;
2319 uint32_t udpframe:1;
2320 uint32_t ip_cksum_pass:1;
2321 uint32_t l4_cksum_pass:1;
2322 uint32_t ip_ver:1;
2323 uint32_t mac_dst:6;
2324 uint32_t vlan_tag_present:1;
2325 uint32_t rsvd0:1;
2326 uint32_t frag_index:10;
2327 uint32_t ct:2;
2328 uint32_t switched:1;
2329 uint32_t num_fragments:3;
2330
2331 /* dw 2 */
2332 uint32_t rss_flush:1;
2333 uint32_t pkt_type:2;
2334 uint32_t qnq:1;
2335 uint32_t rss_bank:1;
2336 uint32_t hds_hdr_frag_index:10;
2337 uint32_t hds_hdr_size:12;
2338 uint32_t rsvd4:1;
2339 uint32_t lro_pkt:1;
2340 uint32_t hds_type:2;
2341 uint32_t valid:1;
2342 /* dw 3 */
2343 uint32_t rss_hash_value;
2344#endif
2345 } s;
2346 uint32_t dw[4];
2347 } u0;
2348};
2349/* NIC Receive CQE_v1 */
2350struct oce_nic_rx_cqe_v1 {
2351 union {
2352 struct {
2353#ifdef _BIG_ENDIAN
2354 /* dw 0 */
2355 uint32_t ip_options:1;
2356 uint32_t vlan_tag_present:1;
2357 uint32_t pkt_size:14;
2358 uint32_t vlan_tag:16;
2359
2360 /* dw 1 */
2361 uint32_t num_fragments:3;
2362 uint32_t switched:1;
2363 uint32_t ct:2;
2364 uint32_t frag_index:10;
2365 uint32_t rsvd0:1;
2366 uint32_t mac_dst:7;
2367 uint32_t ip_ver:1;
2368 uint32_t l4_cksum_pass:1;
2369 uint32_t ip_cksum_pass:1;
2370 uint32_t udpframe:1;
2371 uint32_t tcpframe:1;
2372 uint32_t ipframe:1;
2373 uint32_t rss_hp:1;
2374 uint32_t error:1;
2375
2376 /* dw 2 */
2377 uint32_t valid:1;
2378 uint32_t rsvd4:13;
2379 uint32_t hds_hdr_size:
2380 uint32_t hds_hdr_frag_index:8;
2381 uint32_t vlantag:1;
2382 uint32_t port:2;
2383 uint32_t rss_bank:1;
2384 uint32_t qnq:1;
2385 uint32_t pkt_type:2;
2386 uint32_t rss_flush:1;
2387
2388 /* dw 3 */
2389 uint32_t rss_hash_value;
2390 #else
2391 /* dw 0 */
2392 uint32_t vlan_tag:16;
2393 uint32_t pkt_size:14;
2394 uint32_t vlan_tag_present:1;
2395 uint32_t ip_options:1;
2396 /* dw 1 */
2397 uint32_t error:1;
2398 uint32_t rss_hp:1;
2399 uint32_t ipframe:1;
2400 uint32_t tcpframe:1;
2401 uint32_t udpframe:1;
2402 uint32_t ip_cksum_pass:1;
2403 uint32_t l4_cksum_pass:1;
2404 uint32_t ip_ver:1;
2405 uint32_t mac_dst:7;
2406 uint32_t rsvd0:1;
2407 uint32_t frag_index:10;
2408 uint32_t ct:2;
2409 uint32_t switched:1;
2410 uint32_t num_fragments:3;
2411
2412 /* dw 2 */
2413 uint32_t rss_flush:1;
2414 uint32_t pkt_type:2;
2415 uint32_t qnq:1;
2416 uint32_t rss_bank:1;
2417 uint32_t port:2;
2418 uint32_t vlantag:1;
2419 uint32_t hds_hdr_frag_index:8;
2420 uint32_t hds_hdr_size:2;
2421 uint32_t rsvd4:13;
2422 uint32_t valid:1;
2423 /* dw 3 */
2424 uint32_t rss_hash_value;
2425#endif
2426 } s;
2427 uint32_t dw[4];
2428 } u0;
2429};
2430
2431#define RQ_CQE_VALID_MASK 0x80
2432#define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
2433#define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
2434
2435struct mbx_config_nic_promiscuous {
2436 struct mbx_hdr hdr;
2437 union {
2438 struct {
2439#ifdef _BIG_ENDIAN
2440 uint16_t rsvd0;
2441 uint8_t port1_promisc;
2442 uint8_t port0_promisc;
2443#else
2444 uint8_t port0_promisc;
2445 uint8_t port1_promisc;
2446 uint16_t rsvd0;
2447#endif
2448 } req;
2449
2450 struct {
2451 uint32_t rsvd0;
2452 } rsp;
2453 } params;
2454};
2455
2456typedef union oce_wq_ctx_u {
2457 uint32_t dw[17];
2458 struct {
2459#ifdef _BIG_ENDIAN
2460 /* dw4 */
2461 uint32_t dw4rsvd2:8;
2462 uint32_t nic_wq_type:8;
2463 uint32_t dw4rsvd1:8;
2464 uint32_t num_pages:8;
2465 /* dw5 */
2466 uint32_t dw5rsvd2:12;
2467 uint32_t wq_size:4;
2468 uint32_t dw5rsvd1:16;
2469 /* dw6 */
2470 uint32_t valid:1;
2471 uint32_t dw6rsvd1:31;
2472 /* dw7 */
2473 uint32_t dw7rsvd1:16;
2474 uint32_t cq_id:16;
2475#else
2476 /* dw4 */
2477 uint32_t num_pages:8;
2478#if 0
2479 uint32_t dw4rsvd1:8;
2480#else
2481/* PSP: this workaround is not documented: fill 0x01 for ulp_mask */
2482 uint32_t ulp_mask:8;
2483#endif
2484 uint32_t nic_wq_type:8;
2485 uint32_t dw4rsvd2:8;
2486 /* dw5 */
2487 uint32_t dw5rsvd1:16;
2488 uint32_t wq_size:4;
2489 uint32_t dw5rsvd2:12;
2490 /* dw6 */
2491 uint32_t dw6rsvd1:31;
2492 uint32_t valid:1;
2493 /* dw7 */
2494 uint32_t cq_id:16;
2495 uint32_t dw7rsvd1:16;
2496#endif
2497 /* dw8 - dw20 */
2498 uint32_t dw8_20rsvd1[13];
2499 } v0;
2500 struct {
2501#ifdef _BIG_ENDIAN
2502 /* dw4 */
2503 uint32_t dw4rsvd2:8;
2504 uint32_t nic_wq_type:8;
2505 uint32_t dw4rsvd1:8;
2506 uint32_t num_pages:8;
2507 /* dw5 */
2508 uint32_t dw5rsvd2:12;
2509 uint32_t wq_size:4;
2510 uint32_t iface_id:16;
2511 /* dw6 */
2512 uint32_t valid:1;
2513 uint32_t dw6rsvd1:31;
2514 /* dw7 */
2515 uint32_t dw7rsvd1:16;
2516 uint32_t cq_id:16;
2517#else
2518 /* dw4 */
2519 uint32_t num_pages:8;
2520 uint32_t dw4rsvd1:8;
2521 uint32_t nic_wq_type:8;
2522 uint32_t dw4rsvd2:8;
2523 /* dw5 */
2524 uint32_t iface_id:16;
2525 uint32_t wq_size:4;
2526 uint32_t dw5rsvd2:12;
2527 /* dw6 */
2528 uint32_t dw6rsvd1:31;
2529 uint32_t valid:1;
2530 /* dw7 */
2531 uint32_t cq_id:16;
2532 uint32_t dw7rsvd1:16;
2533#endif
2534 /* dw8 - dw20 */
2535 uint32_t dw8_20rsvd1[13];
2536 } v1;
2537} oce_wq_ctx_t;
2538
2539/**
2540 * @brief [07] NIC_CREATE_WQ
2541 * @note
2542 * Lancer requires an InterfaceID to be specified with every WQ. This
2543 * is the basis for NIC IOV where the Interface maps to a vPort and maps
2544 * to both Tx and Rx sides.
2545 */
2546#define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */
2547#define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */
2548struct mbx_create_nic_wq {
2549 struct mbx_hdr hdr;
2550 union {
2551 struct {
2552 uint8_t num_pages;
2553 uint8_t ulp_num;
2554 uint16_t nic_wq_type;
2555 uint16_t if_id;
2556 uint8_t wq_size;
2557 uint8_t rsvd1;
2558 uint32_t rsvd2;
2559 uint16_t cq_id;
2560 uint16_t rsvd3;
2561 uint32_t rsvd4[13];
2562 struct phys_addr pages[8];
2563
2564 } req;
2565
2566 struct {
2567 uint16_t wq_id;
2568 uint16_t rid;
2569 uint32_t db_offset;
2570 uint8_t tc_id;
2571 uint8_t rsvd0[3];
2572 } rsp;
2573 } params;
2574};
2575
2576/* [09] NIC_DELETE_WQ */
2577struct mbx_delete_nic_wq {
2578 /* dw0 - dw3 */
2579 struct mbx_hdr hdr;
2580 union {
2581 struct {
2582#ifdef _BIG_ENDIAN
2583 /* dw4 */
2584 uint16_t rsvd0;
2585 uint16_t wq_id;
2586#else
2587 /* dw4 */
2588 uint16_t wq_id;
2589 uint16_t rsvd0;
2590#endif
2591 } req;
2592 struct {
2593 uint32_t rsvd0;
2594 } rsp;
2595 } params;
2596};
2597
2598
2599
2600struct mbx_create_nic_rq {
2601 struct mbx_hdr hdr;
2602 union {
2603 struct {
2604 uint16_t cq_id;
2605 uint8_t frag_size;
2606 uint8_t num_pages;
2607 struct phys_addr pages[2];
2608 uint32_t if_id;
2609 uint16_t max_frame_size;
2610 uint16_t page_size;
2611 uint32_t is_rss_queue;
2612 } req;
2613
2614 struct {
2615 uint16_t rq_id;
2616 uint8_t rss_cpuid;
2617 uint8_t rsvd0;
2618 } rsp;
2619
2620 } params;
2621};
2622
2623
2624
2625/* [10] NIC_DELETE_RQ */
2626struct mbx_delete_nic_rq {
2627 /* dw0 - dw3 */
2628 struct mbx_hdr hdr;
2629 union {
2630 struct {
2631#ifdef _BIG_ENDIAN
2632 /* dw4 */
2633 uint16_t bypass_flush;
2634 uint16_t rq_id;
2635#else
2636 /* dw4 */
2637 uint16_t rq_id;
2638 uint16_t bypass_flush;
2639#endif
2640 } req;
2641
2642 struct {
2643 /* dw4 */
2644 uint32_t rsvd0;
2645 } rsp;
2646 } params;
2647};
2648
2649
2650
2651
2652struct oce_port_rxf_stats_v0 {
2653 uint32_t rx_bytes_lsd; /* dword 0*/
2654 uint32_t rx_bytes_msd; /* dword 1*/
2655 uint32_t rx_total_frames; /* dword 2*/
2656 uint32_t rx_unicast_frames; /* dword 3*/
2657 uint32_t rx_multicast_frames; /* dword 4*/
2658 uint32_t rx_broadcast_frames; /* dword 5*/
2659 uint32_t rx_crc_errors; /* dword 6*/
2660 uint32_t rx_alignment_symbol_errors; /* dword 7*/
2661 uint32_t rx_pause_frames; /* dword 8*/
2662 uint32_t rx_control_frames; /* dword 9*/
2663 uint32_t rx_in_range_errors; /* dword 10*/
2664 uint32_t rx_out_range_errors; /* dword 11*/
2665 uint32_t rx_frame_too_long; /* dword 12*/
2666 uint32_t rx_address_match_errors; /* dword 13*/
2667 uint32_t rx_vlan_mismatch; /* dword 14*/
2668 uint32_t rx_dropped_too_small; /* dword 15*/
2669 uint32_t rx_dropped_too_short; /* dword 16*/
2670 uint32_t rx_dropped_header_too_small; /* dword 17*/
2671 uint32_t rx_dropped_tcp_length; /* dword 18*/
2672 uint32_t rx_dropped_runt; /* dword 19*/
2673 uint32_t rx_64_byte_packets; /* dword 20*/
2674 uint32_t rx_65_127_byte_packets; /* dword 21*/
2675 uint32_t rx_128_256_byte_packets; /* dword 22*/
2676 uint32_t rx_256_511_byte_packets; /* dword 23*/
2677 uint32_t rx_512_1023_byte_packets; /* dword 24*/
2678 uint32_t rx_1024_1518_byte_packets; /* dword 25*/
2679 uint32_t rx_1519_2047_byte_packets; /* dword 26*/
2680 uint32_t rx_2048_4095_byte_packets; /* dword 27*/
2681 uint32_t rx_4096_8191_byte_packets; /* dword 28*/
2682 uint32_t rx_8192_9216_byte_packets; /* dword 29*/
2683 uint32_t rx_ip_checksum_errs; /* dword 30*/
2684 uint32_t rx_tcp_checksum_errs; /* dword 31*/
2685 uint32_t rx_udp_checksum_errs; /* dword 32*/
2686 uint32_t rx_non_rss_packets; /* dword 33*/
2687 uint32_t rx_ipv4_packets; /* dword 34*/
2688 uint32_t rx_ipv6_packets; /* dword 35*/
2689 uint32_t rx_ipv4_bytes_lsd; /* dword 36*/
2690 uint32_t rx_ipv4_bytes_msd; /* dword 37*/
2691 uint32_t rx_ipv6_bytes_lsd; /* dword 38*/
2692 uint32_t rx_ipv6_bytes_msd; /* dword 39*/
2693 uint32_t rx_chute1_packets; /* dword 40*/
2694 uint32_t rx_chute2_packets; /* dword 41*/
2695 uint32_t rx_chute3_packets; /* dword 42*/
2696 uint32_t rx_management_packets; /* dword 43*/
2697 uint32_t rx_switched_unicast_packets; /* dword 44*/
2698 uint32_t rx_switched_multicast_packets; /* dword 45*/
2699 uint32_t rx_switched_broadcast_packets; /* dword 46*/
2700 uint32_t tx_bytes_lsd; /* dword 47*/
2701 uint32_t tx_bytes_msd; /* dword 48*/
2702 uint32_t tx_unicastframes; /* dword 49*/
2703 uint32_t tx_multicastframes; /* dword 50*/
2704 uint32_t tx_broadcastframes; /* dword 51*/
2705 uint32_t tx_pauseframes; /* dword 52*/
2706 uint32_t tx_controlframes; /* dword 53*/
2707 uint32_t tx_64_byte_packets; /* dword 54*/
2708 uint32_t tx_65_127_byte_packets; /* dword 55*/
2709 uint32_t tx_128_256_byte_packets; /* dword 56*/
2710 uint32_t tx_256_511_byte_packets; /* dword 57*/
2711 uint32_t tx_512_1023_byte_packets; /* dword 58*/
2712 uint32_t tx_1024_1518_byte_packets; /* dword 59*/
2713 uint32_t tx_1519_2047_byte_packets; /* dword 60*/
2714 uint32_t tx_2048_4095_byte_packets; /* dword 61*/
2715 uint32_t tx_4096_8191_byte_packets; /* dword 62*/
2716 uint32_t tx_8192_9216_byte_packets; /* dword 63*/
2717 uint32_t rxpp_fifo_overflow_drop; /* dword 64*/
2718 uint32_t rx_input_fifo_overflow_drop; /* dword 65*/
2719};
2720
2721
2722struct oce_rxf_stats_v0 {
2723 struct oce_port_rxf_stats_v0 port[2];
2724 uint32_t rx_drops_no_pbuf; /* dword 132*/
2725 uint32_t rx_drops_no_txpb; /* dword 133*/
2726 uint32_t rx_drops_no_erx_descr; /* dword 134*/
2727 uint32_t rx_drops_no_tpre_descr; /* dword 135*/
2728 uint32_t management_rx_port_packets; /* dword 136*/
2729 uint32_t management_rx_port_bytes; /* dword 137*/
2730 uint32_t management_rx_port_pause_frames;/* dword 138*/
2731 uint32_t management_rx_port_errors; /* dword 139*/
2732 uint32_t management_tx_port_packets; /* dword 140*/
2733 uint32_t management_tx_port_bytes; /* dword 141*/
2734 uint32_t management_tx_port_pause; /* dword 142*/
2735 uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/
2736 uint32_t rx_drops_too_many_frags; /* dword 144*/
2737 uint32_t rx_drops_invalid_ring; /* dword 145*/
2738 uint32_t forwarded_packets; /* dword 146*/
2739 uint32_t rx_drops_mtu; /* dword 147*/
2740 uint32_t rsvd0[7];
2741 uint32_t port0_jabber_events;
2742 uint32_t port1_jabber_events;
2743 uint32_t rsvd1[6];
2744};
2745
2746struct oce_port_rxf_stats_v1 {
2747 uint32_t rsvd0[12];
2748 uint32_t rx_crc_errors;
2749 uint32_t rx_alignment_symbol_errors;
2750 uint32_t rx_pause_frames;
2751 uint32_t rx_priority_pause_frames;
2752 uint32_t rx_control_frames;
2753 uint32_t rx_in_range_errors;
2754 uint32_t rx_out_range_errors;
2755 uint32_t rx_frame_too_long;
2756 uint32_t rx_address_match_errors;
2757 uint32_t rx_dropped_too_small;
2758 uint32_t rx_dropped_too_short;
2759 uint32_t rx_dropped_header_too_small;
2760 uint32_t rx_dropped_tcp_length;
2761 uint32_t rx_dropped_runt;
2762 uint32_t rsvd1[10];
2763 uint32_t rx_ip_checksum_errs;
2764 uint32_t rx_tcp_checksum_errs;
2765 uint32_t rx_udp_checksum_errs;
2766 uint32_t rsvd2[7];
2767 uint32_t rx_switched_unicast_packets;
2768 uint32_t rx_switched_multicast_packets;
2769 uint32_t rx_switched_broadcast_packets;
2770 uint32_t rsvd3[3];
2771 uint32_t tx_pauseframes;
2772 uint32_t tx_priority_pauseframes;
2773 uint32_t tx_controlframes;
2774 uint32_t rsvd4[10];
2775 uint32_t rxpp_fifo_overflow_drop;
2776 uint32_t rx_input_fifo_overflow_drop;
2777 uint32_t pmem_fifo_overflow_drop;
2778 uint32_t jabber_events;
2779 uint32_t rsvd5[3];
2780};
2781
2782
2783struct oce_rxf_stats_v1 {
2784 struct oce_port_rxf_stats_v1 port[4];
2785 uint32_t rsvd0[2];
2786 uint32_t rx_drops_no_pbuf;
2787 uint32_t rx_drops_no_txpb;
2788 uint32_t rx_drops_no_erx_descr;
2789 uint32_t rx_drops_no_tpre_descr;
2790 uint32_t rsvd1[6];
2791 uint32_t rx_drops_too_many_frags;
2792 uint32_t rx_drops_invalid_ring;
2793 uint32_t forwarded_packets;
2794 uint32_t rx_drops_mtu;
2795 uint32_t rsvd2[14];
2796};
2797
2798struct oce_erx_stats_v1 {
2799 uint32_t rx_drops_no_fragments[68];
2800 uint32_t rsvd[4];
2801};
2802
2803
2804struct oce_erx_stats_v0 {
2805 uint32_t rx_drops_no_fragments[44];
2806 uint32_t rsvd[4];
2807};
2808
2809struct oce_pmem_stats {
2810 uint32_t eth_red_drops;
2811 uint32_t rsvd[5];
2812};
2813
2814struct oce_hw_stats_v1 {
2815 struct oce_rxf_stats_v1 rxf;
2816 uint32_t rsvd0[OCE_TXP_SW_SZ];
2817 struct oce_erx_stats_v1 erx;
2818 struct oce_pmem_stats pmem;
2819 uint32_t rsvd1[18];
2820};
2821
2822struct oce_hw_stats_v0 {
2823 struct oce_rxf_stats_v0 rxf;
2824 uint32_t rsvd[48];
2825 struct oce_erx_stats_v0 erx;
2826 struct oce_pmem_stats pmem;
2827};
2828
2829struct mbx_get_nic_stats_v0 {
2830 struct mbx_hdr hdr;
2831 union {
2832 struct {
2833 uint32_t rsvd0;
2834 } req;
2835
2836 union {
2837 struct oce_hw_stats_v0 stats;
2838 } rsp;
2839 } params;
2840};
2841
2842struct mbx_get_nic_stats {
2843 struct mbx_hdr hdr;
2844 union {
2845 struct {
2846 uint32_t rsvd0;
2847 } req;
2848
2849 struct {
2850 struct oce_hw_stats_v1 stats;
2851 } rsp;
2852 } params;
2853};
2854
2855
2856/* [18(0x12)] NIC_GET_PPORT_STATS */
2857struct pport_stats {
2858 uint64_t tx_pkts;
2859 uint64_t tx_unicast_pkts;
2860 uint64_t tx_multicast_pkts;
2861 uint64_t tx_broadcast_pkts;
2862 uint64_t tx_bytes;
2863 uint64_t tx_unicast_bytes;
2864 uint64_t tx_multicast_bytes;
2865 uint64_t tx_broadcast_bytes;
2866 uint64_t tx_discards;
2867 uint64_t tx_errors;
2868 uint64_t tx_pause_frames;
2869 uint64_t tx_pause_on_frames;
2870 uint64_t tx_pause_off_frames;
2871 uint64_t tx_internal_mac_errors;
2872 uint64_t tx_control_frames;
2873 uint64_t tx_pkts_64_bytes;
2874 uint64_t tx_pkts_65_to_127_bytes;
2875 uint64_t tx_pkts_128_to_255_bytes;
2876 uint64_t tx_pkts_256_to_511_bytes;
2877 uint64_t tx_pkts_512_to_1023_bytes;
2878 uint64_t tx_pkts_1024_to_1518_bytes;
2879 uint64_t tx_pkts_1519_to_2047_bytes;
2880 uint64_t tx_pkts_2048_to_4095_bytes;
2881 uint64_t tx_pkts_4096_to_8191_bytes;
2882 uint64_t tx_pkts_8192_to_9216_bytes;
2883 uint64_t tx_lso_pkts;
2884 uint64_t rx_pkts;
2885 uint64_t rx_unicast_pkts;
2886 uint64_t rx_multicast_pkts;
2887 uint64_t rx_broadcast_pkts;
2888 uint64_t rx_bytes;
2889 uint64_t rx_unicast_bytes;
2890 uint64_t rx_multicast_bytes;
2891 uint64_t rx_broadcast_bytes;
2892 uint32_t rx_unknown_protos;
2893 uint32_t reserved_word69;
2894 uint64_t rx_discards;
2895 uint64_t rx_errors;
2896 uint64_t rx_crc_errors;
2897 uint64_t rx_alignment_errors;
2898 uint64_t rx_symbol_errors;
2899 uint64_t rx_pause_frames;
2900 uint64_t rx_pause_on_frames;
2901 uint64_t rx_pause_off_frames;
2902 uint64_t rx_frames_too_long;
2903 uint64_t rx_internal_mac_errors;
2904 uint32_t rx_undersize_pkts;
2905 uint32_t rx_oversize_pkts;
2906 uint32_t rx_fragment_pkts;
2907 uint32_t rx_jabbers;
2908 uint64_t rx_control_frames;
2909 uint64_t rx_control_frames_unknown_opcode;
2910 uint32_t rx_in_range_errors;
2911 uint32_t rx_out_of_range_errors;
2912 uint32_t rx_address_match_errors;
2913 uint32_t rx_vlan_mismatch_errors;
2914 uint32_t rx_dropped_too_small;
2915 uint32_t rx_dropped_too_short;
2916 uint32_t rx_dropped_header_too_small;
2917 uint32_t rx_dropped_invalid_tcp_length;
2918 uint32_t rx_dropped_runt;
2919 uint32_t rx_ip_checksum_errors;
2920 uint32_t rx_tcp_checksum_errors;
2921 uint32_t rx_udp_checksum_errors;
2922 uint32_t rx_non_rss_pkts;
2923 uint64_t reserved_word111;
2924 uint64_t rx_ipv4_pkts;
2925 uint64_t rx_ipv6_pkts;
2926 uint64_t rx_ipv4_bytes;
2927 uint64_t rx_ipv6_bytes;
2928 uint64_t rx_nic_pkts;
2929 uint64_t rx_tcp_pkts;
2930 uint64_t rx_iscsi_pkts;
2931 uint64_t rx_management_pkts;
2932 uint64_t rx_switched_unicast_pkts;
2933 uint64_t rx_switched_multicast_pkts;
2934 uint64_t rx_switched_broadcast_pkts;
2935 uint64_t num_forwards;
2936 uint32_t rx_fifo_overflow;
2937 uint32_t rx_input_fifo_overflow;
2938 uint64_t rx_drops_too_many_frags;
2939 uint32_t rx_drops_invalid_queue;
2940 uint32_t reserved_word141;
2941 uint64_t rx_drops_mtu;
2942 uint64_t rx_pkts_64_bytes;
2943 uint64_t rx_pkts_65_to_127_bytes;
2944 uint64_t rx_pkts_128_to_255_bytes;
2945 uint64_t rx_pkts_256_to_511_bytes;
2946 uint64_t rx_pkts_512_to_1023_bytes;
2947 uint64_t rx_pkts_1024_to_1518_bytes;
2948 uint64_t rx_pkts_1519_to_2047_bytes;
2949 uint64_t rx_pkts_2048_to_4095_bytes;
2950 uint64_t rx_pkts_4096_to_8191_bytes;
2951 uint64_t rx_pkts_8192_to_9216_bytes;
2952};
2953
2954struct mbx_get_pport_stats {
2955 /* dw0 - dw3 */
2956 struct mbx_hdr hdr;
2957 union {
2958 struct {
2959 /* dw4 */
2960#ifdef _BIG_ENDIAN
2961 uint32_t reset_stats:8;
2962 uint32_t rsvd0:8;
2963 uint32_t port_number:16;
2964#else
2965 uint32_t port_number:16;
2966 uint32_t rsvd0:8;
2967 uint32_t reset_stats:8;
2968#endif
2969 } req;
2970
2971 union {
2972 struct pport_stats pps;
2973 uint32_t pport_stats[164 - 4 + 1];
2974 } rsp;
2975 } params;
2976};
2977
2978/* [19(0x13)] NIC_GET_VPORT_STATS */
2979struct vport_stats {
2980 uint64_t tx_pkts;
2981 uint64_t tx_unicast_pkts;
2982 uint64_t tx_multicast_pkts;
2983 uint64_t tx_broadcast_pkts;
2984 uint64_t tx_bytes;
2985 uint64_t tx_unicast_bytes;
2986 uint64_t tx_multicast_bytes;
2987 uint64_t tx_broadcast_bytes;
2988 uint64_t tx_discards;
2989 uint64_t tx_errors;
2990 uint64_t tx_pkts_64_bytes;
2991 uint64_t tx_pkts_65_to_127_bytes;
2992 uint64_t tx_pkts_128_to_255_bytes;
2993 uint64_t tx_pkts_256_to_511_bytes;
2994 uint64_t tx_pkts_512_to_1023_bytes;
2995 uint64_t tx_pkts_1024_to_1518_bytes;
2996 uint64_t tx_pkts_1519_to_9699_bytes;
2997 uint64_t tx_pkts_over_9699_bytes;
2998 uint64_t rx_pkts;
2999 uint64_t rx_unicast_pkts;
3000 uint64_t rx_multicast_pkts;
3001 uint64_t rx_broadcast_pkts;
3002 uint64_t rx_bytes;
3003 uint64_t rx_unicast_bytes;
3004 uint64_t rx_multicast_bytes;
3005 uint64_t rx_broadcast_bytes;
3006 uint64_t rx_discards;
3007 uint64_t rx_errors;
3008 uint64_t rx_pkts_64_bytes;
3009 uint64_t rx_pkts_65_to_127_bytes;
3010 uint64_t rx_pkts_128_to_255_bytes;
3011 uint64_t rx_pkts_256_to_511_bytes;
3012 uint64_t rx_pkts_512_to_1023_bytes;
3013 uint64_t rx_pkts_1024_to_1518_bytes;
3014 uint64_t rx_pkts_1519_to_9699_bytes;
3015 uint64_t rx_pkts_gt_9699_bytes;
3016};
3017struct mbx_get_vport_stats {
3018 /* dw0 - dw3 */
3019 struct mbx_hdr hdr;
3020 union {
3021 struct {
3022 /* dw4 */
3023#ifdef _BIG_ENDIAN
3024 uint32_t reset_stats:8;
3025 uint32_t rsvd0:8;
3026 uint32_t vport_number:16;
3027#else
3028 uint32_t vport_number:16;
3029 uint32_t rsvd0:8;
3030 uint32_t reset_stats:8;
3031#endif
3032 } req;
3033
3034 union {
3035 struct vport_stats vps;
3036 uint32_t vport_stats[75 - 4 + 1];
3037 } rsp;
3038 } params;
3039};
3040
3041/**
3042 * @brief [20(0x14)] NIC_GET_QUEUE_STATS
3043 * The significant difference between vPort and Queue statistics is
3044 * the packet byte counters.
3045 */
3046struct queue_stats {
3047 uint64_t packets;
3048 uint64_t bytes;
3049 uint64_t errors;
3050 uint64_t drops;
3051 uint64_t buffer_errors; /* rsvd when tx */
3052};
3053
3054#define QUEUE_TYPE_WQ 0
3055#define QUEUE_TYPE_RQ 1
3056#define QUEUE_TYPE_HDS_RQ 1 /* same as RQ */
3057
3058struct mbx_get_queue_stats {
3059 /* dw0 - dw3 */
3060 struct mbx_hdr hdr;
3061 union {
3062 struct {
3063 /* dw4 */
3064#ifdef _BIG_ENDIAN
3065 uint32_t reset_stats:8;
3066 uint32_t queue_type:8;
3067 uint32_t queue_id:16;
3068#else
3069 uint32_t queue_id:16;
3070 uint32_t queue_type:8;
3071 uint32_t reset_stats:8;
3072#endif
3073 } req;
3074
3075 union {
3076 struct queue_stats qs;
3077 uint32_t queue_stats[13 - 4 + 1];
3078 } rsp;
3079 } params;
3080};
3081
3082
3083/* [01] NIC_CONFIG_RSS */
3084#define OCE_HASH_TBL_SZ 10
3085#define OCE_CPU_TBL_SZ 128
3086#define OCE_FLUSH 1 /* RSS flush completion per CQ port */
3087struct mbx_config_nic_rss {
3088 struct mbx_hdr hdr;
3089 union {
3090 struct {
3091#ifdef _BIG_ENDIAN
3092 uint32_t if_id;
3093 uint16_t cpu_tbl_sz_log2;
3094 uint16_t enable_rss;
3095 uint32_t hash[OCE_HASH_TBL_SZ];
3096 uint8_t cputable[OCE_CPU_TBL_SZ];
3097 uint8_t rsvd[3];
3098 uint8_t flush;
3099#else
3100 uint32_t if_id;
3101 uint16_t enable_rss;
3102 uint16_t cpu_tbl_sz_log2;
3103 uint32_t hash[OCE_HASH_TBL_SZ];
3104 uint8_t cputable[OCE_CPU_TBL_SZ];
3105 uint8_t flush;
3106 uint8_t rsvd[3];
3107#endif
3108 } req;
3109 struct {
3110 uint8_t rsvd[3];
3111 uint8_t rss_bank;
3112 } rsp;
3113 } params;
3114};
3115
3116
3117#pragma pack()
3118
3119
3120typedef uint32_t oce_stat_t; /* statistic counter */
3121
3122enum OCE_RXF_PORT_STATS {
3123 RXF_RX_BYTES_LSD,
3124 RXF_RX_BYTES_MSD,
3125 RXF_RX_TOTAL_FRAMES,
3126 RXF_RX_UNICAST_FRAMES,
3127 RXF_RX_MULTICAST_FRAMES,
3128 RXF_RX_BROADCAST_FRAMES,
3129 RXF_RX_CRC_ERRORS,
3130 RXF_RX_ALIGNMENT_SYMBOL_ERRORS,
3131 RXF_RX_PAUSE_FRAMES,
3132 RXF_RX_CONTROL_FRAMES,
3133 RXF_RX_IN_RANGE_ERRORS,
3134 RXF_RX_OUT_RANGE_ERRORS,
3135 RXF_RX_FRAME_TOO_LONG,
3136 RXF_RX_ADDRESS_MATCH_ERRORS,
3137 RXF_RX_VLAN_MISMATCH,
3138 RXF_RX_DROPPED_TOO_SMALL,
3139 RXF_RX_DROPPED_TOO_SHORT,
3140 RXF_RX_DROPPED_HEADER_TOO_SMALL,
3141 RXF_RX_DROPPED_TCP_LENGTH,
3142 RXF_RX_DROPPED_RUNT,
3143 RXF_RX_64_BYTE_PACKETS,
3144 RXF_RX_65_127_BYTE_PACKETS,
3145 RXF_RX_128_256_BYTE_PACKETS,
3146 RXF_RX_256_511_BYTE_PACKETS,
3147 RXF_RX_512_1023_BYTE_PACKETS,
3148 RXF_RX_1024_1518_BYTE_PACKETS,
3149 RXF_RX_1519_2047_BYTE_PACKETS,
3150 RXF_RX_2048_4095_BYTE_PACKETS,
3151 RXF_RX_4096_8191_BYTE_PACKETS,
3152 RXF_RX_8192_9216_BYTE_PACKETS,
3153 RXF_RX_IP_CHECKSUM_ERRS,
3154 RXF_RX_TCP_CHECKSUM_ERRS,
3155 RXF_RX_UDP_CHECKSUM_ERRS,
3156 RXF_RX_NON_RSS_PACKETS,
3157 RXF_RX_IPV4_PACKETS,
3158 RXF_RX_IPV6_PACKETS,
3159 RXF_RX_IPV4_BYTES_LSD,
3160 RXF_RX_IPV4_BYTES_MSD,
3161 RXF_RX_IPV6_BYTES_LSD,
3162 RXF_RX_IPV6_BYTES_MSD,
3163 RXF_RX_CHUTE1_PACKETS,
3164 RXF_RX_CHUTE2_PACKETS,
3165 RXF_RX_CHUTE3_PACKETS,
3166 RXF_RX_MANAGEMENT_PACKETS,
3167 RXF_RX_SWITCHED_UNICAST_PACKETS,
3168 RXF_RX_SWITCHED_MULTICAST_PACKETS,
3169 RXF_RX_SWITCHED_BROADCAST_PACKETS,
3170 RXF_TX_BYTES_LSD,
3171 RXF_TX_BYTES_MSD,
3172 RXF_TX_UNICAST_FRAMES,
3173 RXF_TX_MULTICAST_FRAMES,
3174 RXF_TX_BROADCAST_FRAMES,
3175 RXF_TX_PAUSE_FRAMES,
3176 RXF_TX_CONTROL_FRAMES,
3177 RXF_TX_64_BYTE_PACKETS,
3178 RXF_TX_65_127_BYTE_PACKETS,
3179 RXF_TX_128_256_BYTE_PACKETS,
3180 RXF_TX_256_511_BYTE_PACKETS,
3181 RXF_TX_512_1023_BYTE_PACKETS,
3182 RXF_TX_1024_1518_BYTE_PACKETS,
3183 RXF_TX_1519_2047_BYTE_PACKETS,
3184 RXF_TX_2048_4095_BYTE_PACKETS,
3185 RXF_TX_4096_8191_BYTE_PACKETS,
3186 RXF_TX_8192_9216_BYTE_PACKETS,
3187 RXF_RX_FIFO_OVERFLOW,
3188 RXF_RX_INPUT_FIFO_OVERFLOW,
3189 RXF_PORT_STATS_N_WORDS
3190};
3191
3192enum OCE_RXF_ADDL_STATS {
3193 RXF_RX_DROPS_NO_PBUF,
3194 RXF_RX_DROPS_NO_TXPB,
3195 RXF_RX_DROPS_NO_ERX_DESCR,
3196 RXF_RX_DROPS_NO_TPRE_DESCR,
3197 RXF_MANAGEMENT_RX_PORT_PACKETS,
3198 RXF_MANAGEMENT_RX_PORT_BYTES,
3199 RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES,
3200 RXF_MANAGEMENT_RX_PORT_ERRORS,
3201 RXF_MANAGEMENT_TX_PORT_PACKETS,
3202 RXF_MANAGEMENT_TX_PORT_BYTES,
3203 RXF_MANAGEMENT_TX_PORT_PAUSE,
3204 RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW,
3205 RXF_RX_DROPS_TOO_MANY_FRAGS,
3206 RXF_RX_DROPS_INVALID_RING,
3207 RXF_FORWARDED_PACKETS,
3208 RXF_RX_DROPS_MTU,
3209 RXF_ADDL_STATS_N_WORDS
3210};
3211
3212enum OCE_TX_CHUTE_PORT_STATS {
3213 CTPT_XMT_IPV4_PKTS,
3214 CTPT_XMT_IPV4_LSD,
3215 CTPT_XMT_IPV4_MSD,
3216 CTPT_XMT_IPV6_PKTS,
3217 CTPT_XMT_IPV6_LSD,
3218 CTPT_XMT_IPV6_MSD,
3219 CTPT_REXMT_IPV4_PKTs,
3220 CTPT_REXMT_IPV4_LSD,
3221 CTPT_REXMT_IPV4_MSD,
3222 CTPT_REXMT_IPV6_PKTs,
3223 CTPT_REXMT_IPV6_LSD,
3224 CTPT_REXMT_IPV6_MSD,
3225 CTPT_N_WORDS,
3226};
3227
3228enum OCE_RX_ERR_STATS {
3229 RX_DROPS_NO_FRAGMENTS_0,
3230 RX_DROPS_NO_FRAGMENTS_1,
3231 RX_DROPS_NO_FRAGMENTS_2,
3232 RX_DROPS_NO_FRAGMENTS_3,
3233 RX_DROPS_NO_FRAGMENTS_4,
3234 RX_DROPS_NO_FRAGMENTS_5,
3235 RX_DROPS_NO_FRAGMENTS_6,
3236 RX_DROPS_NO_FRAGMENTS_7,
3237 RX_DROPS_NO_FRAGMENTS_8,
3238 RX_DROPS_NO_FRAGMENTS_9,
3239 RX_DROPS_NO_FRAGMENTS_10,
3240 RX_DROPS_NO_FRAGMENTS_11,
3241 RX_DROPS_NO_FRAGMENTS_12,
3242 RX_DROPS_NO_FRAGMENTS_13,
3243 RX_DROPS_NO_FRAGMENTS_14,
3244 RX_DROPS_NO_FRAGMENTS_15,
3245 RX_DROPS_NO_FRAGMENTS_16,
3246 RX_DROPS_NO_FRAGMENTS_17,
3247 RX_DROPS_NO_FRAGMENTS_18,
3248 RX_DROPS_NO_FRAGMENTS_19,
3249 RX_DROPS_NO_FRAGMENTS_20,
3250 RX_DROPS_NO_FRAGMENTS_21,
3251 RX_DROPS_NO_FRAGMENTS_22,
3252 RX_DROPS_NO_FRAGMENTS_23,
3253 RX_DROPS_NO_FRAGMENTS_24,
3254 RX_DROPS_NO_FRAGMENTS_25,
3255 RX_DROPS_NO_FRAGMENTS_26,
3256 RX_DROPS_NO_FRAGMENTS_27,
3257 RX_DROPS_NO_FRAGMENTS_28,
3258 RX_DROPS_NO_FRAGMENTS_29,
3259 RX_DROPS_NO_FRAGMENTS_30,
3260 RX_DROPS_NO_FRAGMENTS_31,
3261 RX_DROPS_NO_FRAGMENTS_32,
3262 RX_DROPS_NO_FRAGMENTS_33,
3263 RX_DROPS_NO_FRAGMENTS_34,
3264 RX_DROPS_NO_FRAGMENTS_35,
3265 RX_DROPS_NO_FRAGMENTS_36,
3266 RX_DROPS_NO_FRAGMENTS_37,
3267 RX_DROPS_NO_FRAGMENTS_38,
3268 RX_DROPS_NO_FRAGMENTS_39,
3269 RX_DROPS_NO_FRAGMENTS_40,
3270 RX_DROPS_NO_FRAGMENTS_41,
3271 RX_DROPS_NO_FRAGMENTS_42,
3272 RX_DROPS_NO_FRAGMENTS_43,
3273 RX_DEBUG_WDMA_SENT_HOLD,
3274 RX_DEBUG_WDMA_PBFREE_SENT_HOLD,
3275 RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD,
3276 RX_DEBUG_PMEM_PBUF_DEALLOC,
3277 RX_ERRORS_N_WORDS
3278};
3279
3280enum OCE_PMEM_ERR_STATS {
3281 PMEM_ETH_RED_DROPS,
3282 PMEM_LRO_RED_DROPS,
3283 PMEM_ULP0_RED_DROPS,
3284 PMEM_ULP1_RED_DROPS,
3285 PMEM_GLOBAL_RED_DROPS,
3286 PMEM_ERRORS_N_WORDS
3287};
3288
3289/**
3290 * @brief Statistics for a given Physical Port
3291 * These satisfy all the required BE2 statistics and also the
3292 * following MIB objects:
3293 *
3294 * RFC 2863 - The Interfaces Group MIB
3295 * RFC 2819 - Remote Network Monitoring Management Information Base (RMON)
3296 * RFC 3635 - Managed Objects for the Ethernet-like Interface Types
3297 * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2)
3298 *
3299 */
3300enum OCE_PPORT_STATS {
3301 PPORT_TX_PKTS = 0,
3302 PPORT_TX_UNICAST_PKTS = 2,
3303 PPORT_TX_MULTICAST_PKTS = 4,
3304 PPORT_TX_BROADCAST_PKTS = 6,
3305 PPORT_TX_BYTES = 8,
3306 PPORT_TX_UNICAST_BYTES = 10,
3307 PPORT_TX_MULTICAST_BYTES = 12,
3308 PPORT_TX_BROADCAST_BYTES = 14,
3309 PPORT_TX_DISCARDS = 16,
3310 PPORT_TX_ERRORS = 18,
3311 PPORT_TX_PAUSE_FRAMES = 20,
3312 PPORT_TX_PAUSE_ON_FRAMES = 22,
3313 PPORT_TX_PAUSE_OFF_FRAMES = 24,
3314 PPORT_TX_INTERNAL_MAC_ERRORS = 26,
3315 PPORT_TX_CONTROL_FRAMES = 28,
3316 PPORT_TX_PKTS_64_BYTES = 30,
3317 PPORT_TX_PKTS_65_TO_127_BYTES = 32,
3318 PPORT_TX_PKTS_128_TO_255_BYTES = 34,
3319 PPORT_TX_PKTS_256_TO_511_BYTES = 36,
3320 PPORT_TX_PKTS_512_TO_1023_BYTES = 38,
3321 PPORT_TX_PKTS_1024_TO_1518_BYTES = 40,
3322 PPORT_TX_PKTS_1519_TO_2047_BYTES = 42,
3323 PPORT_TX_PKTS_2048_TO_4095_BYTES = 44,
3324 PPORT_TX_PKTS_4096_TO_8191_BYTES = 46,
3325 PPORT_TX_PKTS_8192_TO_9216_BYTES = 48,
3326 PPORT_TX_LSO_PKTS = 50,
3327 PPORT_RX_PKTS = 52,
3328 PPORT_RX_UNICAST_PKTS = 54,
3329 PPORT_RX_MULTICAST_PKTS = 56,
3330 PPORT_RX_BROADCAST_PKTS = 58,
3331 PPORT_RX_BYTES = 60,
3332 PPORT_RX_UNICAST_BYTES = 62,
3333 PPORT_RX_MULTICAST_BYTES = 64,
3334 PPORT_RX_BROADCAST_BYTES = 66,
3335 PPORT_RX_UNKNOWN_PROTOS = 68,
3336 PPORT_RESERVED_WORD69 = 69,
3337 PPORT_RX_DISCARDS = 70,
3338 PPORT_RX_ERRORS = 72,
3339 PPORT_RX_CRC_ERRORS = 74,
3340 PPORT_RX_ALIGNMENT_ERRORS = 76,
3341 PPORT_RX_SYMBOL_ERRORS = 78,
3342 PPORT_RX_PAUSE_FRAMES = 80,
3343 PPORT_RX_PAUSE_ON_FRAMES = 82,
3344 PPORT_RX_PAUSE_OFF_FRAMES = 84,
3345 PPORT_RX_FRAMES_TOO_LONG = 86,
3346 PPORT_RX_INTERNAL_MAC_ERRORS = 88,
3347 PPORT_RX_UNDERSIZE_PKTS = 90,
3348 PPORT_RX_OVERSIZE_PKTS = 91,
3349 PPORT_RX_FRAGMENT_PKTS = 92,
3350 PPORT_RX_JABBERS = 93,
3351 PPORT_RX_CONTROL_FRAMES = 94,
3352 PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96,
3353 PPORT_RX_IN_RANGE_ERRORS = 98,
3354 PPORT_RX_OUT_OF_RANGE_ERRORS = 99,
3355 PPORT_RX_ADDRESS_MATCH_ERRORS = 100,
3356 PPORT_RX_VLAN_MISMATCH_ERRORS = 101,
3357 PPORT_RX_DROPPED_TOO_SMALL = 102,
3358 PPORT_RX_DROPPED_TOO_SHORT = 103,
3359 PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104,
3360 PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105,
3361 PPORT_RX_DROPPED_RUNT = 106,
3362 PPORT_RX_IP_CHECKSUM_ERRORS = 107,
3363 PPORT_RX_TCP_CHECKSUM_ERRORS = 108,
3364 PPORT_RX_UDP_CHECKSUM_ERRORS = 109,
3365 PPORT_RX_NON_RSS_PKTS = 110,
3366 PPORT_RESERVED_WORD111 = 111,
3367 PPORT_RX_IPV4_PKTS = 112,
3368 PPORT_RX_IPV6_PKTS = 114,
3369 PPORT_RX_IPV4_BYTES = 116,
3370 PPORT_RX_IPV6_BYTES = 118,
3371 PPORT_RX_NIC_PKTS = 120,
3372 PPORT_RX_TCP_PKTS = 122,
3373 PPORT_RX_ISCSI_PKTS = 124,
3374 PPORT_RX_MANAGEMENT_PKTS = 126,
3375 PPORT_RX_SWITCHED_UNICAST_PKTS = 128,
3376 PPORT_RX_SWITCHED_MULTICAST_PKTS = 130,
3377 PPORT_RX_SWITCHED_BROADCAST_PKTS = 132,
3378 PPORT_NUM_FORWARDS = 134,
3379 PPORT_RX_FIFO_OVERFLOW = 136,
3380 PPORT_RX_INPUT_FIFO_OVERFLOW = 137,
3381 PPORT_RX_DROPS_TOO_MANY_FRAGS = 138,
3382 PPORT_RX_DROPS_INVALID_QUEUE = 140,
3383 PPORT_RESERVED_WORD141 = 141,
3384 PPORT_RX_DROPS_MTU = 142,
3385 PPORT_RX_PKTS_64_BYTES = 144,
3386 PPORT_RX_PKTS_65_TO_127_BYTES = 146,
3387 PPORT_RX_PKTS_128_TO_255_BYTES = 148,
3388 PPORT_RX_PKTS_256_TO_511_BYTES = 150,
3389 PPORT_RX_PKTS_512_TO_1023_BYTES = 152,
3390 PPORT_RX_PKTS_1024_TO_1518_BYTES = 154,
3391 PPORT_RX_PKTS_1519_TO_2047_BYTES = 156,
3392 PPORT_RX_PKTS_2048_TO_4095_BYTES = 158,
3393 PPORT_RX_PKTS_4096_TO_8191_BYTES = 160,
3394 PPORT_RX_PKTS_8192_TO_9216_BYTES = 162,
3395 PPORT_N_WORDS = 164
3396};
3397
3398/**
3399 * @brief Statistics for a given Virtual Port (vPort)
3400 * The following describes the vPort statistics satisfying
3401 * requirements of Linux/VMWare netdev statistics and
3402 * Microsoft Windows Statistics along with other Operating Systems.
3403 */
3404enum OCE_VPORT_STATS {
3405 VPORT_TX_PKTS = 0,
3406 VPORT_TX_UNICAST_PKTS = 2,
3407 VPORT_TX_MULTICAST_PKTS = 4,
3408 VPORT_TX_BROADCAST_PKTS = 6,
3409 VPORT_TX_BYTES = 8,
3410 VPORT_TX_UNICAST_BYTES = 10,
3411 VPORT_TX_MULTICAST_BYTES = 12,
3412 VPORT_TX_BROADCAST_BYTES = 14,
3413 VPORT_TX_DISCARDS = 16,
3414 VPORT_TX_ERRORS = 18,
3415 VPORT_TX_PKTS_64_BYTES = 20,
3416 VPORT_TX_PKTS_65_TO_127_BYTES = 22,
3417 VPORT_TX_PKTS_128_TO_255_BYTES = 24,
3418 VPORT_TX_PKTS_256_TO_511_BYTES = 26,
3419 VPORT_TX_PKTS_512_TO_1023_BYTEs = 28,
3420 VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30,
3421 VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32,
3422 VPORT_TX_PKTS_OVER_9699_BYTES = 34,
3423 VPORT_RX_PKTS = 36,
3424 VPORT_RX_UNICAST_PKTS = 38,
3425 VPORT_RX_MULTICAST_PKTS = 40,
3426 VPORT_RX_BROADCAST_PKTS = 42,
3427 VPORT_RX_BYTES = 44,
3428 VPORT_RX_UNICAST_BYTES = 46,
3429 VPORT_RX_MULTICAST_BYTES = 48,
3430 VPORT_RX_BROADCAST_BYTES = 50,
3431 VPORT_RX_DISCARDS = 52,
3432 VPORT_RX_ERRORS = 54,
3433 VPORT_RX_PKTS_64_BYTES = 56,
3434 VPORT_RX_PKTS_65_TO_127_BYTES = 58,
3435 VPORT_RX_PKTS_128_TO_255_BYTES = 60,
3436 VPORT_RX_PKTS_256_TO_511_BYTES = 62,
3437 VPORT_RX_PKTS_512_TO_1023_BYTEs = 64,
3438 VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66,
3439 VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68,
3440 VPORT_RX_PKTS_OVER_9699_BYTES = 70,
3441 VPORT_N_WORDS = 72
3442};
3443
3444/**
3445 * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ)
3446 * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ
3447 */
3448enum OCE_QUEUE_TX_STATS {
3449 QUEUE_TX_PKTS = 0,
3450 QUEUE_TX_BYTES = 2,
3451 QUEUE_TX_ERRORS = 4,
3452 QUEUE_TX_DROPS = 6,
3453 QUEUE_TX_N_WORDS = 8
3454};
3455
3456enum OCE_QUEUE_RX_STATS {
3457 QUEUE_RX_PKTS = 0,
3458 QUEUE_RX_BYTES = 2,
3459 QUEUE_RX_ERRORS = 4,
3460 QUEUE_RX_DROPS = 6,
3461 QUEUE_RX_BUFFER_ERRORS = 8,
3462 QUEUE_RX_N_WORDS = 10
3463};
3464
| 2264};
2265#define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
2266#define RSS_DISABLE RSS_ENABLE_NONE
2267
2268/* NIC header WQE */
2269struct oce_nic_hdr_wqe {
2270 union {
2271 struct {
2272#ifdef _BIG_ENDIAN
2273 /* dw0 */
2274 uint32_t rsvd0;
2275
2276 /* dw1 */
2277 uint32_t last_seg_udp_len:14;
2278 uint32_t rsvd1:18;
2279
2280 /* dw2 */
2281 uint32_t lso_mss:14;
2282 uint32_t num_wqe:5;
2283 uint32_t rsvd4:2;
2284 uint32_t vlan:1;
2285 uint32_t lso:1;
2286 uint32_t tcpcs:1;
2287 uint32_t udpcs:1;
2288 uint32_t ipcs:1;
2289 uint32_t rsvd3:1;
2290 uint32_t rsvd2:1;
2291 uint32_t forward:1;
2292 uint32_t crc:1;
2293 uint32_t event:1;
2294 uint32_t complete:1;
2295
2296 /* dw3 */
2297 uint32_t vlan_tag:16;
2298 uint32_t total_length:16;
2299#else
2300 /* dw0 */
2301 uint32_t rsvd0;
2302
2303 /* dw1 */
2304 uint32_t rsvd1:18;
2305 uint32_t last_seg_udp_len:14;
2306
2307 /* dw2 */
2308 uint32_t complete:1;
2309 uint32_t event:1;
2310 uint32_t crc:1;
2311 uint32_t forward:1;
2312 uint32_t rsvd2:1;
2313 uint32_t rsvd3:1;
2314 uint32_t ipcs:1;
2315 uint32_t udpcs:1;
2316 uint32_t tcpcs:1;
2317 uint32_t lso:1;
2318 uint32_t vlan:1;
2319 uint32_t rsvd4:2;
2320 uint32_t num_wqe:5;
2321 uint32_t lso_mss:14;
2322
2323 /* dw3 */
2324 uint32_t total_length:16;
2325 uint32_t vlan_tag:16;
2326#endif
2327 } s;
2328 uint32_t dw[4];
2329 } u0;
2330};
2331
2332/* NIC fragment WQE */
2333struct oce_nic_frag_wqe {
2334 union {
2335 struct {
2336 /* dw0 */
2337 uint32_t frag_pa_hi;
2338 /* dw1 */
2339 uint32_t frag_pa_lo;
2340 /* dw2 */
2341 uint32_t rsvd0;
2342 uint32_t frag_len;
2343 } s;
2344 uint32_t dw[4];
2345 } u0;
2346};
2347
2348/* Ethernet Tx Completion Descriptor */
2349struct oce_nic_tx_cqe {
2350 union {
2351 struct {
2352#ifdef _BIG_ENDIAN
2353 /* dw 0 */
2354 uint32_t status:4;
2355 uint32_t rsvd0:8;
2356 uint32_t port:2;
2357 uint32_t ct:2;
2358 uint32_t wqe_index:16;
2359
2360 /* dw 1 */
2361 uint32_t rsvd1:5;
2362 uint32_t cast_enc:2;
2363 uint32_t lso:1;
2364 uint32_t nwh_bytes:8;
2365 uint32_t user_bytes:16;
2366
2367 /* dw 2 */
2368 uint32_t rsvd2;
2369
2370 /* dw 3 */
2371 uint32_t valid:1;
2372 uint32_t rsvd3:4;
2373 uint32_t wq_id:11;
2374 uint32_t num_pkts:16;
2375#else
2376 /* dw 0 */
2377 uint32_t wqe_index:16;
2378 uint32_t ct:2;
2379 uint32_t port:2;
2380 uint32_t rsvd0:8;
2381 uint32_t status:4;
2382
2383 /* dw 1 */
2384 uint32_t user_bytes:16;
2385 uint32_t nwh_bytes:8;
2386 uint32_t lso:1;
2387 uint32_t cast_enc:2;
2388 uint32_t rsvd1:5;
2389 /* dw 2 */
2390 uint32_t rsvd2;
2391
2392 /* dw 3 */
2393 uint32_t num_pkts:16;
2394 uint32_t wq_id:11;
2395 uint32_t rsvd3:4;
2396 uint32_t valid:1;
2397#endif
2398 } s;
2399 uint32_t dw[4];
2400 } u0;
2401};
2402#define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3])
2403#define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0)
2404
2405/* Receive Queue Entry (RQE) */
2406struct oce_nic_rqe {
2407 union {
2408 struct {
2409 uint32_t frag_pa_hi;
2410 uint32_t frag_pa_lo;
2411 } s;
2412 uint32_t dw[2];
2413 } u0;
2414};
2415
2416/* NIC Receive CQE */
2417struct oce_nic_rx_cqe {
2418 union {
2419 struct {
2420#ifdef _BIG_ENDIAN
2421 /* dw 0 */
2422 uint32_t ip_options:1;
2423 uint32_t port:1;
2424 uint32_t pkt_size:14;
2425 uint32_t vlan_tag:16;
2426
2427 /* dw 1 */
2428 uint32_t num_fragments:3;
2429 uint32_t switched:1;
2430 uint32_t ct:2;
2431 uint32_t frag_index:10;
2432 uint32_t rsvd0:1;
2433 uint32_t vlan_tag_present:1;
2434 uint32_t mac_dst:6;
2435 uint32_t ip_ver:1;
2436 uint32_t l4_cksum_pass:1;
2437 uint32_t ip_cksum_pass:1;
2438 uint32_t udpframe:1;
2439 uint32_t tcpframe:1;
2440 uint32_t ipframe:1;
2441 uint32_t rss_hp:1;
2442 uint32_t error:1;
2443
2444 /* dw 2 */
2445 uint32_t valid:1;
2446 uint32_t hds_type:2;
2447 uint32_t lro_pkt:1;
2448 uint32_t rsvd4:1;
2449 uint32_t hds_hdr_size:12;
2450 uint32_t hds_hdr_frag_index:10;
2451 uint32_t rss_bank:1;
2452 uint32_t qnq:1;
2453 uint32_t pkt_type:2;
2454 uint32_t rss_flush:1;
2455
2456 /* dw 3 */
2457 uint32_t rss_hash_value;
2458#else
2459 /* dw 0 */
2460 uint32_t vlan_tag:16;
2461 uint32_t pkt_size:14;
2462 uint32_t port:1;
2463 uint32_t ip_options:1;
2464 /* dw 1 */
2465 uint32_t error:1;
2466 uint32_t rss_hp:1;
2467 uint32_t ipframe:1;
2468 uint32_t tcpframe:1;
2469 uint32_t udpframe:1;
2470 uint32_t ip_cksum_pass:1;
2471 uint32_t l4_cksum_pass:1;
2472 uint32_t ip_ver:1;
2473 uint32_t mac_dst:6;
2474 uint32_t vlan_tag_present:1;
2475 uint32_t rsvd0:1;
2476 uint32_t frag_index:10;
2477 uint32_t ct:2;
2478 uint32_t switched:1;
2479 uint32_t num_fragments:3;
2480
2481 /* dw 2 */
2482 uint32_t rss_flush:1;
2483 uint32_t pkt_type:2;
2484 uint32_t qnq:1;
2485 uint32_t rss_bank:1;
2486 uint32_t hds_hdr_frag_index:10;
2487 uint32_t hds_hdr_size:12;
2488 uint32_t rsvd4:1;
2489 uint32_t lro_pkt:1;
2490 uint32_t hds_type:2;
2491 uint32_t valid:1;
2492 /* dw 3 */
2493 uint32_t rss_hash_value;
2494#endif
2495 } s;
2496 uint32_t dw[4];
2497 } u0;
2498};
2499/* NIC Receive CQE_v1 */
2500struct oce_nic_rx_cqe_v1 {
2501 union {
2502 struct {
2503#ifdef _BIG_ENDIAN
2504 /* dw 0 */
2505 uint32_t ip_options:1;
2506 uint32_t vlan_tag_present:1;
2507 uint32_t pkt_size:14;
2508 uint32_t vlan_tag:16;
2509
2510 /* dw 1 */
2511 uint32_t num_fragments:3;
2512 uint32_t switched:1;
2513 uint32_t ct:2;
2514 uint32_t frag_index:10;
2515 uint32_t rsvd0:1;
2516 uint32_t mac_dst:7;
2517 uint32_t ip_ver:1;
2518 uint32_t l4_cksum_pass:1;
2519 uint32_t ip_cksum_pass:1;
2520 uint32_t udpframe:1;
2521 uint32_t tcpframe:1;
2522 uint32_t ipframe:1;
2523 uint32_t rss_hp:1;
2524 uint32_t error:1;
2525
2526 /* dw 2 */
2527 uint32_t valid:1;
2528 uint32_t rsvd4:13;
2529 uint32_t hds_hdr_size:
2530 uint32_t hds_hdr_frag_index:8;
2531 uint32_t vlantag:1;
2532 uint32_t port:2;
2533 uint32_t rss_bank:1;
2534 uint32_t qnq:1;
2535 uint32_t pkt_type:2;
2536 uint32_t rss_flush:1;
2537
2538 /* dw 3 */
2539 uint32_t rss_hash_value;
2540 #else
2541 /* dw 0 */
2542 uint32_t vlan_tag:16;
2543 uint32_t pkt_size:14;
2544 uint32_t vlan_tag_present:1;
2545 uint32_t ip_options:1;
2546 /* dw 1 */
2547 uint32_t error:1;
2548 uint32_t rss_hp:1;
2549 uint32_t ipframe:1;
2550 uint32_t tcpframe:1;
2551 uint32_t udpframe:1;
2552 uint32_t ip_cksum_pass:1;
2553 uint32_t l4_cksum_pass:1;
2554 uint32_t ip_ver:1;
2555 uint32_t mac_dst:7;
2556 uint32_t rsvd0:1;
2557 uint32_t frag_index:10;
2558 uint32_t ct:2;
2559 uint32_t switched:1;
2560 uint32_t num_fragments:3;
2561
2562 /* dw 2 */
2563 uint32_t rss_flush:1;
2564 uint32_t pkt_type:2;
2565 uint32_t qnq:1;
2566 uint32_t rss_bank:1;
2567 uint32_t port:2;
2568 uint32_t vlantag:1;
2569 uint32_t hds_hdr_frag_index:8;
2570 uint32_t hds_hdr_size:2;
2571 uint32_t rsvd4:13;
2572 uint32_t valid:1;
2573 /* dw 3 */
2574 uint32_t rss_hash_value;
2575#endif
2576 } s;
2577 uint32_t dw[4];
2578 } u0;
2579};
2580
2581#define RQ_CQE_VALID_MASK 0x80
2582#define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
2583#define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
2584
2585struct mbx_config_nic_promiscuous {
2586 struct mbx_hdr hdr;
2587 union {
2588 struct {
2589#ifdef _BIG_ENDIAN
2590 uint16_t rsvd0;
2591 uint8_t port1_promisc;
2592 uint8_t port0_promisc;
2593#else
2594 uint8_t port0_promisc;
2595 uint8_t port1_promisc;
2596 uint16_t rsvd0;
2597#endif
2598 } req;
2599
2600 struct {
2601 uint32_t rsvd0;
2602 } rsp;
2603 } params;
2604};
2605
2606typedef union oce_wq_ctx_u {
2607 uint32_t dw[17];
2608 struct {
2609#ifdef _BIG_ENDIAN
2610 /* dw4 */
2611 uint32_t dw4rsvd2:8;
2612 uint32_t nic_wq_type:8;
2613 uint32_t dw4rsvd1:8;
2614 uint32_t num_pages:8;
2615 /* dw5 */
2616 uint32_t dw5rsvd2:12;
2617 uint32_t wq_size:4;
2618 uint32_t dw5rsvd1:16;
2619 /* dw6 */
2620 uint32_t valid:1;
2621 uint32_t dw6rsvd1:31;
2622 /* dw7 */
2623 uint32_t dw7rsvd1:16;
2624 uint32_t cq_id:16;
2625#else
2626 /* dw4 */
2627 uint32_t num_pages:8;
2628#if 0
2629 uint32_t dw4rsvd1:8;
2630#else
2631/* PSP: this workaround is not documented: fill 0x01 for ulp_mask */
2632 uint32_t ulp_mask:8;
2633#endif
2634 uint32_t nic_wq_type:8;
2635 uint32_t dw4rsvd2:8;
2636 /* dw5 */
2637 uint32_t dw5rsvd1:16;
2638 uint32_t wq_size:4;
2639 uint32_t dw5rsvd2:12;
2640 /* dw6 */
2641 uint32_t dw6rsvd1:31;
2642 uint32_t valid:1;
2643 /* dw7 */
2644 uint32_t cq_id:16;
2645 uint32_t dw7rsvd1:16;
2646#endif
2647 /* dw8 - dw20 */
2648 uint32_t dw8_20rsvd1[13];
2649 } v0;
2650 struct {
2651#ifdef _BIG_ENDIAN
2652 /* dw4 */
2653 uint32_t dw4rsvd2:8;
2654 uint32_t nic_wq_type:8;
2655 uint32_t dw4rsvd1:8;
2656 uint32_t num_pages:8;
2657 /* dw5 */
2658 uint32_t dw5rsvd2:12;
2659 uint32_t wq_size:4;
2660 uint32_t iface_id:16;
2661 /* dw6 */
2662 uint32_t valid:1;
2663 uint32_t dw6rsvd1:31;
2664 /* dw7 */
2665 uint32_t dw7rsvd1:16;
2666 uint32_t cq_id:16;
2667#else
2668 /* dw4 */
2669 uint32_t num_pages:8;
2670 uint32_t dw4rsvd1:8;
2671 uint32_t nic_wq_type:8;
2672 uint32_t dw4rsvd2:8;
2673 /* dw5 */
2674 uint32_t iface_id:16;
2675 uint32_t wq_size:4;
2676 uint32_t dw5rsvd2:12;
2677 /* dw6 */
2678 uint32_t dw6rsvd1:31;
2679 uint32_t valid:1;
2680 /* dw7 */
2681 uint32_t cq_id:16;
2682 uint32_t dw7rsvd1:16;
2683#endif
2684 /* dw8 - dw20 */
2685 uint32_t dw8_20rsvd1[13];
2686 } v1;
2687} oce_wq_ctx_t;
2688
2689/**
2690 * @brief [07] NIC_CREATE_WQ
2691 * @note
2692 * Lancer requires an InterfaceID to be specified with every WQ. This
2693 * is the basis for NIC IOV where the Interface maps to a vPort and maps
2694 * to both Tx and Rx sides.
2695 */
2696#define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */
2697#define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */
2698struct mbx_create_nic_wq {
2699 struct mbx_hdr hdr;
2700 union {
2701 struct {
2702 uint8_t num_pages;
2703 uint8_t ulp_num;
2704 uint16_t nic_wq_type;
2705 uint16_t if_id;
2706 uint8_t wq_size;
2707 uint8_t rsvd1;
2708 uint32_t rsvd2;
2709 uint16_t cq_id;
2710 uint16_t rsvd3;
2711 uint32_t rsvd4[13];
2712 struct phys_addr pages[8];
2713
2714 } req;
2715
2716 struct {
2717 uint16_t wq_id;
2718 uint16_t rid;
2719 uint32_t db_offset;
2720 uint8_t tc_id;
2721 uint8_t rsvd0[3];
2722 } rsp;
2723 } params;
2724};
2725
2726/* [09] NIC_DELETE_WQ */
2727struct mbx_delete_nic_wq {
2728 /* dw0 - dw3 */
2729 struct mbx_hdr hdr;
2730 union {
2731 struct {
2732#ifdef _BIG_ENDIAN
2733 /* dw4 */
2734 uint16_t rsvd0;
2735 uint16_t wq_id;
2736#else
2737 /* dw4 */
2738 uint16_t wq_id;
2739 uint16_t rsvd0;
2740#endif
2741 } req;
2742 struct {
2743 uint32_t rsvd0;
2744 } rsp;
2745 } params;
2746};
2747
2748
2749
2750struct mbx_create_nic_rq {
2751 struct mbx_hdr hdr;
2752 union {
2753 struct {
2754 uint16_t cq_id;
2755 uint8_t frag_size;
2756 uint8_t num_pages;
2757 struct phys_addr pages[2];
2758 uint32_t if_id;
2759 uint16_t max_frame_size;
2760 uint16_t page_size;
2761 uint32_t is_rss_queue;
2762 } req;
2763
2764 struct {
2765 uint16_t rq_id;
2766 uint8_t rss_cpuid;
2767 uint8_t rsvd0;
2768 } rsp;
2769
2770 } params;
2771};
2772
2773
2774
2775/* [10] NIC_DELETE_RQ */
2776struct mbx_delete_nic_rq {
2777 /* dw0 - dw3 */
2778 struct mbx_hdr hdr;
2779 union {
2780 struct {
2781#ifdef _BIG_ENDIAN
2782 /* dw4 */
2783 uint16_t bypass_flush;
2784 uint16_t rq_id;
2785#else
2786 /* dw4 */
2787 uint16_t rq_id;
2788 uint16_t bypass_flush;
2789#endif
2790 } req;
2791
2792 struct {
2793 /* dw4 */
2794 uint32_t rsvd0;
2795 } rsp;
2796 } params;
2797};
2798
2799
2800
2801
2802struct oce_port_rxf_stats_v0 {
2803 uint32_t rx_bytes_lsd; /* dword 0*/
2804 uint32_t rx_bytes_msd; /* dword 1*/
2805 uint32_t rx_total_frames; /* dword 2*/
2806 uint32_t rx_unicast_frames; /* dword 3*/
2807 uint32_t rx_multicast_frames; /* dword 4*/
2808 uint32_t rx_broadcast_frames; /* dword 5*/
2809 uint32_t rx_crc_errors; /* dword 6*/
2810 uint32_t rx_alignment_symbol_errors; /* dword 7*/
2811 uint32_t rx_pause_frames; /* dword 8*/
2812 uint32_t rx_control_frames; /* dword 9*/
2813 uint32_t rx_in_range_errors; /* dword 10*/
2814 uint32_t rx_out_range_errors; /* dword 11*/
2815 uint32_t rx_frame_too_long; /* dword 12*/
2816 uint32_t rx_address_match_errors; /* dword 13*/
2817 uint32_t rx_vlan_mismatch; /* dword 14*/
2818 uint32_t rx_dropped_too_small; /* dword 15*/
2819 uint32_t rx_dropped_too_short; /* dword 16*/
2820 uint32_t rx_dropped_header_too_small; /* dword 17*/
2821 uint32_t rx_dropped_tcp_length; /* dword 18*/
2822 uint32_t rx_dropped_runt; /* dword 19*/
2823 uint32_t rx_64_byte_packets; /* dword 20*/
2824 uint32_t rx_65_127_byte_packets; /* dword 21*/
2825 uint32_t rx_128_256_byte_packets; /* dword 22*/
2826 uint32_t rx_256_511_byte_packets; /* dword 23*/
2827 uint32_t rx_512_1023_byte_packets; /* dword 24*/
2828 uint32_t rx_1024_1518_byte_packets; /* dword 25*/
2829 uint32_t rx_1519_2047_byte_packets; /* dword 26*/
2830 uint32_t rx_2048_4095_byte_packets; /* dword 27*/
2831 uint32_t rx_4096_8191_byte_packets; /* dword 28*/
2832 uint32_t rx_8192_9216_byte_packets; /* dword 29*/
2833 uint32_t rx_ip_checksum_errs; /* dword 30*/
2834 uint32_t rx_tcp_checksum_errs; /* dword 31*/
2835 uint32_t rx_udp_checksum_errs; /* dword 32*/
2836 uint32_t rx_non_rss_packets; /* dword 33*/
2837 uint32_t rx_ipv4_packets; /* dword 34*/
2838 uint32_t rx_ipv6_packets; /* dword 35*/
2839 uint32_t rx_ipv4_bytes_lsd; /* dword 36*/
2840 uint32_t rx_ipv4_bytes_msd; /* dword 37*/
2841 uint32_t rx_ipv6_bytes_lsd; /* dword 38*/
2842 uint32_t rx_ipv6_bytes_msd; /* dword 39*/
2843 uint32_t rx_chute1_packets; /* dword 40*/
2844 uint32_t rx_chute2_packets; /* dword 41*/
2845 uint32_t rx_chute3_packets; /* dword 42*/
2846 uint32_t rx_management_packets; /* dword 43*/
2847 uint32_t rx_switched_unicast_packets; /* dword 44*/
2848 uint32_t rx_switched_multicast_packets; /* dword 45*/
2849 uint32_t rx_switched_broadcast_packets; /* dword 46*/
2850 uint32_t tx_bytes_lsd; /* dword 47*/
2851 uint32_t tx_bytes_msd; /* dword 48*/
2852 uint32_t tx_unicastframes; /* dword 49*/
2853 uint32_t tx_multicastframes; /* dword 50*/
2854 uint32_t tx_broadcastframes; /* dword 51*/
2855 uint32_t tx_pauseframes; /* dword 52*/
2856 uint32_t tx_controlframes; /* dword 53*/
2857 uint32_t tx_64_byte_packets; /* dword 54*/
2858 uint32_t tx_65_127_byte_packets; /* dword 55*/
2859 uint32_t tx_128_256_byte_packets; /* dword 56*/
2860 uint32_t tx_256_511_byte_packets; /* dword 57*/
2861 uint32_t tx_512_1023_byte_packets; /* dword 58*/
2862 uint32_t tx_1024_1518_byte_packets; /* dword 59*/
2863 uint32_t tx_1519_2047_byte_packets; /* dword 60*/
2864 uint32_t tx_2048_4095_byte_packets; /* dword 61*/
2865 uint32_t tx_4096_8191_byte_packets; /* dword 62*/
2866 uint32_t tx_8192_9216_byte_packets; /* dword 63*/
2867 uint32_t rxpp_fifo_overflow_drop; /* dword 64*/
2868 uint32_t rx_input_fifo_overflow_drop; /* dword 65*/
2869};
2870
2871
2872struct oce_rxf_stats_v0 {
2873 struct oce_port_rxf_stats_v0 port[2];
2874 uint32_t rx_drops_no_pbuf; /* dword 132*/
2875 uint32_t rx_drops_no_txpb; /* dword 133*/
2876 uint32_t rx_drops_no_erx_descr; /* dword 134*/
2877 uint32_t rx_drops_no_tpre_descr; /* dword 135*/
2878 uint32_t management_rx_port_packets; /* dword 136*/
2879 uint32_t management_rx_port_bytes; /* dword 137*/
2880 uint32_t management_rx_port_pause_frames;/* dword 138*/
2881 uint32_t management_rx_port_errors; /* dword 139*/
2882 uint32_t management_tx_port_packets; /* dword 140*/
2883 uint32_t management_tx_port_bytes; /* dword 141*/
2884 uint32_t management_tx_port_pause; /* dword 142*/
2885 uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/
2886 uint32_t rx_drops_too_many_frags; /* dword 144*/
2887 uint32_t rx_drops_invalid_ring; /* dword 145*/
2888 uint32_t forwarded_packets; /* dword 146*/
2889 uint32_t rx_drops_mtu; /* dword 147*/
2890 uint32_t rsvd0[7];
2891 uint32_t port0_jabber_events;
2892 uint32_t port1_jabber_events;
2893 uint32_t rsvd1[6];
2894};
2895
2896struct oce_port_rxf_stats_v1 {
2897 uint32_t rsvd0[12];
2898 uint32_t rx_crc_errors;
2899 uint32_t rx_alignment_symbol_errors;
2900 uint32_t rx_pause_frames;
2901 uint32_t rx_priority_pause_frames;
2902 uint32_t rx_control_frames;
2903 uint32_t rx_in_range_errors;
2904 uint32_t rx_out_range_errors;
2905 uint32_t rx_frame_too_long;
2906 uint32_t rx_address_match_errors;
2907 uint32_t rx_dropped_too_small;
2908 uint32_t rx_dropped_too_short;
2909 uint32_t rx_dropped_header_too_small;
2910 uint32_t rx_dropped_tcp_length;
2911 uint32_t rx_dropped_runt;
2912 uint32_t rsvd1[10];
2913 uint32_t rx_ip_checksum_errs;
2914 uint32_t rx_tcp_checksum_errs;
2915 uint32_t rx_udp_checksum_errs;
2916 uint32_t rsvd2[7];
2917 uint32_t rx_switched_unicast_packets;
2918 uint32_t rx_switched_multicast_packets;
2919 uint32_t rx_switched_broadcast_packets;
2920 uint32_t rsvd3[3];
2921 uint32_t tx_pauseframes;
2922 uint32_t tx_priority_pauseframes;
2923 uint32_t tx_controlframes;
2924 uint32_t rsvd4[10];
2925 uint32_t rxpp_fifo_overflow_drop;
2926 uint32_t rx_input_fifo_overflow_drop;
2927 uint32_t pmem_fifo_overflow_drop;
2928 uint32_t jabber_events;
2929 uint32_t rsvd5[3];
2930};
2931
2932
2933struct oce_rxf_stats_v1 {
2934 struct oce_port_rxf_stats_v1 port[4];
2935 uint32_t rsvd0[2];
2936 uint32_t rx_drops_no_pbuf;
2937 uint32_t rx_drops_no_txpb;
2938 uint32_t rx_drops_no_erx_descr;
2939 uint32_t rx_drops_no_tpre_descr;
2940 uint32_t rsvd1[6];
2941 uint32_t rx_drops_too_many_frags;
2942 uint32_t rx_drops_invalid_ring;
2943 uint32_t forwarded_packets;
2944 uint32_t rx_drops_mtu;
2945 uint32_t rsvd2[14];
2946};
2947
2948struct oce_erx_stats_v1 {
2949 uint32_t rx_drops_no_fragments[68];
2950 uint32_t rsvd[4];
2951};
2952
2953
2954struct oce_erx_stats_v0 {
2955 uint32_t rx_drops_no_fragments[44];
2956 uint32_t rsvd[4];
2957};
2958
2959struct oce_pmem_stats {
2960 uint32_t eth_red_drops;
2961 uint32_t rsvd[5];
2962};
2963
2964struct oce_hw_stats_v1 {
2965 struct oce_rxf_stats_v1 rxf;
2966 uint32_t rsvd0[OCE_TXP_SW_SZ];
2967 struct oce_erx_stats_v1 erx;
2968 struct oce_pmem_stats pmem;
2969 uint32_t rsvd1[18];
2970};
2971
2972struct oce_hw_stats_v0 {
2973 struct oce_rxf_stats_v0 rxf;
2974 uint32_t rsvd[48];
2975 struct oce_erx_stats_v0 erx;
2976 struct oce_pmem_stats pmem;
2977};
2978
2979struct mbx_get_nic_stats_v0 {
2980 struct mbx_hdr hdr;
2981 union {
2982 struct {
2983 uint32_t rsvd0;
2984 } req;
2985
2986 union {
2987 struct oce_hw_stats_v0 stats;
2988 } rsp;
2989 } params;
2990};
2991
2992struct mbx_get_nic_stats {
2993 struct mbx_hdr hdr;
2994 union {
2995 struct {
2996 uint32_t rsvd0;
2997 } req;
2998
2999 struct {
3000 struct oce_hw_stats_v1 stats;
3001 } rsp;
3002 } params;
3003};
3004
3005
3006/* [18(0x12)] NIC_GET_PPORT_STATS */
3007struct pport_stats {
3008 uint64_t tx_pkts;
3009 uint64_t tx_unicast_pkts;
3010 uint64_t tx_multicast_pkts;
3011 uint64_t tx_broadcast_pkts;
3012 uint64_t tx_bytes;
3013 uint64_t tx_unicast_bytes;
3014 uint64_t tx_multicast_bytes;
3015 uint64_t tx_broadcast_bytes;
3016 uint64_t tx_discards;
3017 uint64_t tx_errors;
3018 uint64_t tx_pause_frames;
3019 uint64_t tx_pause_on_frames;
3020 uint64_t tx_pause_off_frames;
3021 uint64_t tx_internal_mac_errors;
3022 uint64_t tx_control_frames;
3023 uint64_t tx_pkts_64_bytes;
3024 uint64_t tx_pkts_65_to_127_bytes;
3025 uint64_t tx_pkts_128_to_255_bytes;
3026 uint64_t tx_pkts_256_to_511_bytes;
3027 uint64_t tx_pkts_512_to_1023_bytes;
3028 uint64_t tx_pkts_1024_to_1518_bytes;
3029 uint64_t tx_pkts_1519_to_2047_bytes;
3030 uint64_t tx_pkts_2048_to_4095_bytes;
3031 uint64_t tx_pkts_4096_to_8191_bytes;
3032 uint64_t tx_pkts_8192_to_9216_bytes;
3033 uint64_t tx_lso_pkts;
3034 uint64_t rx_pkts;
3035 uint64_t rx_unicast_pkts;
3036 uint64_t rx_multicast_pkts;
3037 uint64_t rx_broadcast_pkts;
3038 uint64_t rx_bytes;
3039 uint64_t rx_unicast_bytes;
3040 uint64_t rx_multicast_bytes;
3041 uint64_t rx_broadcast_bytes;
3042 uint32_t rx_unknown_protos;
3043 uint32_t reserved_word69;
3044 uint64_t rx_discards;
3045 uint64_t rx_errors;
3046 uint64_t rx_crc_errors;
3047 uint64_t rx_alignment_errors;
3048 uint64_t rx_symbol_errors;
3049 uint64_t rx_pause_frames;
3050 uint64_t rx_pause_on_frames;
3051 uint64_t rx_pause_off_frames;
3052 uint64_t rx_frames_too_long;
3053 uint64_t rx_internal_mac_errors;
3054 uint32_t rx_undersize_pkts;
3055 uint32_t rx_oversize_pkts;
3056 uint32_t rx_fragment_pkts;
3057 uint32_t rx_jabbers;
3058 uint64_t rx_control_frames;
3059 uint64_t rx_control_frames_unknown_opcode;
3060 uint32_t rx_in_range_errors;
3061 uint32_t rx_out_of_range_errors;
3062 uint32_t rx_address_match_errors;
3063 uint32_t rx_vlan_mismatch_errors;
3064 uint32_t rx_dropped_too_small;
3065 uint32_t rx_dropped_too_short;
3066 uint32_t rx_dropped_header_too_small;
3067 uint32_t rx_dropped_invalid_tcp_length;
3068 uint32_t rx_dropped_runt;
3069 uint32_t rx_ip_checksum_errors;
3070 uint32_t rx_tcp_checksum_errors;
3071 uint32_t rx_udp_checksum_errors;
3072 uint32_t rx_non_rss_pkts;
3073 uint64_t reserved_word111;
3074 uint64_t rx_ipv4_pkts;
3075 uint64_t rx_ipv6_pkts;
3076 uint64_t rx_ipv4_bytes;
3077 uint64_t rx_ipv6_bytes;
3078 uint64_t rx_nic_pkts;
3079 uint64_t rx_tcp_pkts;
3080 uint64_t rx_iscsi_pkts;
3081 uint64_t rx_management_pkts;
3082 uint64_t rx_switched_unicast_pkts;
3083 uint64_t rx_switched_multicast_pkts;
3084 uint64_t rx_switched_broadcast_pkts;
3085 uint64_t num_forwards;
3086 uint32_t rx_fifo_overflow;
3087 uint32_t rx_input_fifo_overflow;
3088 uint64_t rx_drops_too_many_frags;
3089 uint32_t rx_drops_invalid_queue;
3090 uint32_t reserved_word141;
3091 uint64_t rx_drops_mtu;
3092 uint64_t rx_pkts_64_bytes;
3093 uint64_t rx_pkts_65_to_127_bytes;
3094 uint64_t rx_pkts_128_to_255_bytes;
3095 uint64_t rx_pkts_256_to_511_bytes;
3096 uint64_t rx_pkts_512_to_1023_bytes;
3097 uint64_t rx_pkts_1024_to_1518_bytes;
3098 uint64_t rx_pkts_1519_to_2047_bytes;
3099 uint64_t rx_pkts_2048_to_4095_bytes;
3100 uint64_t rx_pkts_4096_to_8191_bytes;
3101 uint64_t rx_pkts_8192_to_9216_bytes;
3102};
3103
3104struct mbx_get_pport_stats {
3105 /* dw0 - dw3 */
3106 struct mbx_hdr hdr;
3107 union {
3108 struct {
3109 /* dw4 */
3110#ifdef _BIG_ENDIAN
3111 uint32_t reset_stats:8;
3112 uint32_t rsvd0:8;
3113 uint32_t port_number:16;
3114#else
3115 uint32_t port_number:16;
3116 uint32_t rsvd0:8;
3117 uint32_t reset_stats:8;
3118#endif
3119 } req;
3120
3121 union {
3122 struct pport_stats pps;
3123 uint32_t pport_stats[164 - 4 + 1];
3124 } rsp;
3125 } params;
3126};
3127
3128/* [19(0x13)] NIC_GET_VPORT_STATS */
3129struct vport_stats {
3130 uint64_t tx_pkts;
3131 uint64_t tx_unicast_pkts;
3132 uint64_t tx_multicast_pkts;
3133 uint64_t tx_broadcast_pkts;
3134 uint64_t tx_bytes;
3135 uint64_t tx_unicast_bytes;
3136 uint64_t tx_multicast_bytes;
3137 uint64_t tx_broadcast_bytes;
3138 uint64_t tx_discards;
3139 uint64_t tx_errors;
3140 uint64_t tx_pkts_64_bytes;
3141 uint64_t tx_pkts_65_to_127_bytes;
3142 uint64_t tx_pkts_128_to_255_bytes;
3143 uint64_t tx_pkts_256_to_511_bytes;
3144 uint64_t tx_pkts_512_to_1023_bytes;
3145 uint64_t tx_pkts_1024_to_1518_bytes;
3146 uint64_t tx_pkts_1519_to_9699_bytes;
3147 uint64_t tx_pkts_over_9699_bytes;
3148 uint64_t rx_pkts;
3149 uint64_t rx_unicast_pkts;
3150 uint64_t rx_multicast_pkts;
3151 uint64_t rx_broadcast_pkts;
3152 uint64_t rx_bytes;
3153 uint64_t rx_unicast_bytes;
3154 uint64_t rx_multicast_bytes;
3155 uint64_t rx_broadcast_bytes;
3156 uint64_t rx_discards;
3157 uint64_t rx_errors;
3158 uint64_t rx_pkts_64_bytes;
3159 uint64_t rx_pkts_65_to_127_bytes;
3160 uint64_t rx_pkts_128_to_255_bytes;
3161 uint64_t rx_pkts_256_to_511_bytes;
3162 uint64_t rx_pkts_512_to_1023_bytes;
3163 uint64_t rx_pkts_1024_to_1518_bytes;
3164 uint64_t rx_pkts_1519_to_9699_bytes;
3165 uint64_t rx_pkts_gt_9699_bytes;
3166};
3167struct mbx_get_vport_stats {
3168 /* dw0 - dw3 */
3169 struct mbx_hdr hdr;
3170 union {
3171 struct {
3172 /* dw4 */
3173#ifdef _BIG_ENDIAN
3174 uint32_t reset_stats:8;
3175 uint32_t rsvd0:8;
3176 uint32_t vport_number:16;
3177#else
3178 uint32_t vport_number:16;
3179 uint32_t rsvd0:8;
3180 uint32_t reset_stats:8;
3181#endif
3182 } req;
3183
3184 union {
3185 struct vport_stats vps;
3186 uint32_t vport_stats[75 - 4 + 1];
3187 } rsp;
3188 } params;
3189};
3190
3191/**
3192 * @brief [20(0x14)] NIC_GET_QUEUE_STATS
3193 * The significant difference between vPort and Queue statistics is
3194 * the packet byte counters.
3195 */
3196struct queue_stats {
3197 uint64_t packets;
3198 uint64_t bytes;
3199 uint64_t errors;
3200 uint64_t drops;
3201 uint64_t buffer_errors; /* rsvd when tx */
3202};
3203
3204#define QUEUE_TYPE_WQ 0
3205#define QUEUE_TYPE_RQ 1
3206#define QUEUE_TYPE_HDS_RQ 1 /* same as RQ */
3207
3208struct mbx_get_queue_stats {
3209 /* dw0 - dw3 */
3210 struct mbx_hdr hdr;
3211 union {
3212 struct {
3213 /* dw4 */
3214#ifdef _BIG_ENDIAN
3215 uint32_t reset_stats:8;
3216 uint32_t queue_type:8;
3217 uint32_t queue_id:16;
3218#else
3219 uint32_t queue_id:16;
3220 uint32_t queue_type:8;
3221 uint32_t reset_stats:8;
3222#endif
3223 } req;
3224
3225 union {
3226 struct queue_stats qs;
3227 uint32_t queue_stats[13 - 4 + 1];
3228 } rsp;
3229 } params;
3230};
3231
3232
3233/* [01] NIC_CONFIG_RSS */
3234#define OCE_HASH_TBL_SZ 10
3235#define OCE_CPU_TBL_SZ 128
3236#define OCE_FLUSH 1 /* RSS flush completion per CQ port */
3237struct mbx_config_nic_rss {
3238 struct mbx_hdr hdr;
3239 union {
3240 struct {
3241#ifdef _BIG_ENDIAN
3242 uint32_t if_id;
3243 uint16_t cpu_tbl_sz_log2;
3244 uint16_t enable_rss;
3245 uint32_t hash[OCE_HASH_TBL_SZ];
3246 uint8_t cputable[OCE_CPU_TBL_SZ];
3247 uint8_t rsvd[3];
3248 uint8_t flush;
3249#else
3250 uint32_t if_id;
3251 uint16_t enable_rss;
3252 uint16_t cpu_tbl_sz_log2;
3253 uint32_t hash[OCE_HASH_TBL_SZ];
3254 uint8_t cputable[OCE_CPU_TBL_SZ];
3255 uint8_t flush;
3256 uint8_t rsvd[3];
3257#endif
3258 } req;
3259 struct {
3260 uint8_t rsvd[3];
3261 uint8_t rss_bank;
3262 } rsp;
3263 } params;
3264};
3265
3266
3267#pragma pack()
3268
3269
3270typedef uint32_t oce_stat_t; /* statistic counter */
3271
3272enum OCE_RXF_PORT_STATS {
3273 RXF_RX_BYTES_LSD,
3274 RXF_RX_BYTES_MSD,
3275 RXF_RX_TOTAL_FRAMES,
3276 RXF_RX_UNICAST_FRAMES,
3277 RXF_RX_MULTICAST_FRAMES,
3278 RXF_RX_BROADCAST_FRAMES,
3279 RXF_RX_CRC_ERRORS,
3280 RXF_RX_ALIGNMENT_SYMBOL_ERRORS,
3281 RXF_RX_PAUSE_FRAMES,
3282 RXF_RX_CONTROL_FRAMES,
3283 RXF_RX_IN_RANGE_ERRORS,
3284 RXF_RX_OUT_RANGE_ERRORS,
3285 RXF_RX_FRAME_TOO_LONG,
3286 RXF_RX_ADDRESS_MATCH_ERRORS,
3287 RXF_RX_VLAN_MISMATCH,
3288 RXF_RX_DROPPED_TOO_SMALL,
3289 RXF_RX_DROPPED_TOO_SHORT,
3290 RXF_RX_DROPPED_HEADER_TOO_SMALL,
3291 RXF_RX_DROPPED_TCP_LENGTH,
3292 RXF_RX_DROPPED_RUNT,
3293 RXF_RX_64_BYTE_PACKETS,
3294 RXF_RX_65_127_BYTE_PACKETS,
3295 RXF_RX_128_256_BYTE_PACKETS,
3296 RXF_RX_256_511_BYTE_PACKETS,
3297 RXF_RX_512_1023_BYTE_PACKETS,
3298 RXF_RX_1024_1518_BYTE_PACKETS,
3299 RXF_RX_1519_2047_BYTE_PACKETS,
3300 RXF_RX_2048_4095_BYTE_PACKETS,
3301 RXF_RX_4096_8191_BYTE_PACKETS,
3302 RXF_RX_8192_9216_BYTE_PACKETS,
3303 RXF_RX_IP_CHECKSUM_ERRS,
3304 RXF_RX_TCP_CHECKSUM_ERRS,
3305 RXF_RX_UDP_CHECKSUM_ERRS,
3306 RXF_RX_NON_RSS_PACKETS,
3307 RXF_RX_IPV4_PACKETS,
3308 RXF_RX_IPV6_PACKETS,
3309 RXF_RX_IPV4_BYTES_LSD,
3310 RXF_RX_IPV4_BYTES_MSD,
3311 RXF_RX_IPV6_BYTES_LSD,
3312 RXF_RX_IPV6_BYTES_MSD,
3313 RXF_RX_CHUTE1_PACKETS,
3314 RXF_RX_CHUTE2_PACKETS,
3315 RXF_RX_CHUTE3_PACKETS,
3316 RXF_RX_MANAGEMENT_PACKETS,
3317 RXF_RX_SWITCHED_UNICAST_PACKETS,
3318 RXF_RX_SWITCHED_MULTICAST_PACKETS,
3319 RXF_RX_SWITCHED_BROADCAST_PACKETS,
3320 RXF_TX_BYTES_LSD,
3321 RXF_TX_BYTES_MSD,
3322 RXF_TX_UNICAST_FRAMES,
3323 RXF_TX_MULTICAST_FRAMES,
3324 RXF_TX_BROADCAST_FRAMES,
3325 RXF_TX_PAUSE_FRAMES,
3326 RXF_TX_CONTROL_FRAMES,
3327 RXF_TX_64_BYTE_PACKETS,
3328 RXF_TX_65_127_BYTE_PACKETS,
3329 RXF_TX_128_256_BYTE_PACKETS,
3330 RXF_TX_256_511_BYTE_PACKETS,
3331 RXF_TX_512_1023_BYTE_PACKETS,
3332 RXF_TX_1024_1518_BYTE_PACKETS,
3333 RXF_TX_1519_2047_BYTE_PACKETS,
3334 RXF_TX_2048_4095_BYTE_PACKETS,
3335 RXF_TX_4096_8191_BYTE_PACKETS,
3336 RXF_TX_8192_9216_BYTE_PACKETS,
3337 RXF_RX_FIFO_OVERFLOW,
3338 RXF_RX_INPUT_FIFO_OVERFLOW,
3339 RXF_PORT_STATS_N_WORDS
3340};
3341
3342enum OCE_RXF_ADDL_STATS {
3343 RXF_RX_DROPS_NO_PBUF,
3344 RXF_RX_DROPS_NO_TXPB,
3345 RXF_RX_DROPS_NO_ERX_DESCR,
3346 RXF_RX_DROPS_NO_TPRE_DESCR,
3347 RXF_MANAGEMENT_RX_PORT_PACKETS,
3348 RXF_MANAGEMENT_RX_PORT_BYTES,
3349 RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES,
3350 RXF_MANAGEMENT_RX_PORT_ERRORS,
3351 RXF_MANAGEMENT_TX_PORT_PACKETS,
3352 RXF_MANAGEMENT_TX_PORT_BYTES,
3353 RXF_MANAGEMENT_TX_PORT_PAUSE,
3354 RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW,
3355 RXF_RX_DROPS_TOO_MANY_FRAGS,
3356 RXF_RX_DROPS_INVALID_RING,
3357 RXF_FORWARDED_PACKETS,
3358 RXF_RX_DROPS_MTU,
3359 RXF_ADDL_STATS_N_WORDS
3360};
3361
3362enum OCE_TX_CHUTE_PORT_STATS {
3363 CTPT_XMT_IPV4_PKTS,
3364 CTPT_XMT_IPV4_LSD,
3365 CTPT_XMT_IPV4_MSD,
3366 CTPT_XMT_IPV6_PKTS,
3367 CTPT_XMT_IPV6_LSD,
3368 CTPT_XMT_IPV6_MSD,
3369 CTPT_REXMT_IPV4_PKTs,
3370 CTPT_REXMT_IPV4_LSD,
3371 CTPT_REXMT_IPV4_MSD,
3372 CTPT_REXMT_IPV6_PKTs,
3373 CTPT_REXMT_IPV6_LSD,
3374 CTPT_REXMT_IPV6_MSD,
3375 CTPT_N_WORDS,
3376};
3377
3378enum OCE_RX_ERR_STATS {
3379 RX_DROPS_NO_FRAGMENTS_0,
3380 RX_DROPS_NO_FRAGMENTS_1,
3381 RX_DROPS_NO_FRAGMENTS_2,
3382 RX_DROPS_NO_FRAGMENTS_3,
3383 RX_DROPS_NO_FRAGMENTS_4,
3384 RX_DROPS_NO_FRAGMENTS_5,
3385 RX_DROPS_NO_FRAGMENTS_6,
3386 RX_DROPS_NO_FRAGMENTS_7,
3387 RX_DROPS_NO_FRAGMENTS_8,
3388 RX_DROPS_NO_FRAGMENTS_9,
3389 RX_DROPS_NO_FRAGMENTS_10,
3390 RX_DROPS_NO_FRAGMENTS_11,
3391 RX_DROPS_NO_FRAGMENTS_12,
3392 RX_DROPS_NO_FRAGMENTS_13,
3393 RX_DROPS_NO_FRAGMENTS_14,
3394 RX_DROPS_NO_FRAGMENTS_15,
3395 RX_DROPS_NO_FRAGMENTS_16,
3396 RX_DROPS_NO_FRAGMENTS_17,
3397 RX_DROPS_NO_FRAGMENTS_18,
3398 RX_DROPS_NO_FRAGMENTS_19,
3399 RX_DROPS_NO_FRAGMENTS_20,
3400 RX_DROPS_NO_FRAGMENTS_21,
3401 RX_DROPS_NO_FRAGMENTS_22,
3402 RX_DROPS_NO_FRAGMENTS_23,
3403 RX_DROPS_NO_FRAGMENTS_24,
3404 RX_DROPS_NO_FRAGMENTS_25,
3405 RX_DROPS_NO_FRAGMENTS_26,
3406 RX_DROPS_NO_FRAGMENTS_27,
3407 RX_DROPS_NO_FRAGMENTS_28,
3408 RX_DROPS_NO_FRAGMENTS_29,
3409 RX_DROPS_NO_FRAGMENTS_30,
3410 RX_DROPS_NO_FRAGMENTS_31,
3411 RX_DROPS_NO_FRAGMENTS_32,
3412 RX_DROPS_NO_FRAGMENTS_33,
3413 RX_DROPS_NO_FRAGMENTS_34,
3414 RX_DROPS_NO_FRAGMENTS_35,
3415 RX_DROPS_NO_FRAGMENTS_36,
3416 RX_DROPS_NO_FRAGMENTS_37,
3417 RX_DROPS_NO_FRAGMENTS_38,
3418 RX_DROPS_NO_FRAGMENTS_39,
3419 RX_DROPS_NO_FRAGMENTS_40,
3420 RX_DROPS_NO_FRAGMENTS_41,
3421 RX_DROPS_NO_FRAGMENTS_42,
3422 RX_DROPS_NO_FRAGMENTS_43,
3423 RX_DEBUG_WDMA_SENT_HOLD,
3424 RX_DEBUG_WDMA_PBFREE_SENT_HOLD,
3425 RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD,
3426 RX_DEBUG_PMEM_PBUF_DEALLOC,
3427 RX_ERRORS_N_WORDS
3428};
3429
3430enum OCE_PMEM_ERR_STATS {
3431 PMEM_ETH_RED_DROPS,
3432 PMEM_LRO_RED_DROPS,
3433 PMEM_ULP0_RED_DROPS,
3434 PMEM_ULP1_RED_DROPS,
3435 PMEM_GLOBAL_RED_DROPS,
3436 PMEM_ERRORS_N_WORDS
3437};
3438
3439/**
3440 * @brief Statistics for a given Physical Port
3441 * These satisfy all the required BE2 statistics and also the
3442 * following MIB objects:
3443 *
3444 * RFC 2863 - The Interfaces Group MIB
3445 * RFC 2819 - Remote Network Monitoring Management Information Base (RMON)
3446 * RFC 3635 - Managed Objects for the Ethernet-like Interface Types
3447 * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2)
3448 *
3449 */
3450enum OCE_PPORT_STATS {
3451 PPORT_TX_PKTS = 0,
3452 PPORT_TX_UNICAST_PKTS = 2,
3453 PPORT_TX_MULTICAST_PKTS = 4,
3454 PPORT_TX_BROADCAST_PKTS = 6,
3455 PPORT_TX_BYTES = 8,
3456 PPORT_TX_UNICAST_BYTES = 10,
3457 PPORT_TX_MULTICAST_BYTES = 12,
3458 PPORT_TX_BROADCAST_BYTES = 14,
3459 PPORT_TX_DISCARDS = 16,
3460 PPORT_TX_ERRORS = 18,
3461 PPORT_TX_PAUSE_FRAMES = 20,
3462 PPORT_TX_PAUSE_ON_FRAMES = 22,
3463 PPORT_TX_PAUSE_OFF_FRAMES = 24,
3464 PPORT_TX_INTERNAL_MAC_ERRORS = 26,
3465 PPORT_TX_CONTROL_FRAMES = 28,
3466 PPORT_TX_PKTS_64_BYTES = 30,
3467 PPORT_TX_PKTS_65_TO_127_BYTES = 32,
3468 PPORT_TX_PKTS_128_TO_255_BYTES = 34,
3469 PPORT_TX_PKTS_256_TO_511_BYTES = 36,
3470 PPORT_TX_PKTS_512_TO_1023_BYTES = 38,
3471 PPORT_TX_PKTS_1024_TO_1518_BYTES = 40,
3472 PPORT_TX_PKTS_1519_TO_2047_BYTES = 42,
3473 PPORT_TX_PKTS_2048_TO_4095_BYTES = 44,
3474 PPORT_TX_PKTS_4096_TO_8191_BYTES = 46,
3475 PPORT_TX_PKTS_8192_TO_9216_BYTES = 48,
3476 PPORT_TX_LSO_PKTS = 50,
3477 PPORT_RX_PKTS = 52,
3478 PPORT_RX_UNICAST_PKTS = 54,
3479 PPORT_RX_MULTICAST_PKTS = 56,
3480 PPORT_RX_BROADCAST_PKTS = 58,
3481 PPORT_RX_BYTES = 60,
3482 PPORT_RX_UNICAST_BYTES = 62,
3483 PPORT_RX_MULTICAST_BYTES = 64,
3484 PPORT_RX_BROADCAST_BYTES = 66,
3485 PPORT_RX_UNKNOWN_PROTOS = 68,
3486 PPORT_RESERVED_WORD69 = 69,
3487 PPORT_RX_DISCARDS = 70,
3488 PPORT_RX_ERRORS = 72,
3489 PPORT_RX_CRC_ERRORS = 74,
3490 PPORT_RX_ALIGNMENT_ERRORS = 76,
3491 PPORT_RX_SYMBOL_ERRORS = 78,
3492 PPORT_RX_PAUSE_FRAMES = 80,
3493 PPORT_RX_PAUSE_ON_FRAMES = 82,
3494 PPORT_RX_PAUSE_OFF_FRAMES = 84,
3495 PPORT_RX_FRAMES_TOO_LONG = 86,
3496 PPORT_RX_INTERNAL_MAC_ERRORS = 88,
3497 PPORT_RX_UNDERSIZE_PKTS = 90,
3498 PPORT_RX_OVERSIZE_PKTS = 91,
3499 PPORT_RX_FRAGMENT_PKTS = 92,
3500 PPORT_RX_JABBERS = 93,
3501 PPORT_RX_CONTROL_FRAMES = 94,
3502 PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96,
3503 PPORT_RX_IN_RANGE_ERRORS = 98,
3504 PPORT_RX_OUT_OF_RANGE_ERRORS = 99,
3505 PPORT_RX_ADDRESS_MATCH_ERRORS = 100,
3506 PPORT_RX_VLAN_MISMATCH_ERRORS = 101,
3507 PPORT_RX_DROPPED_TOO_SMALL = 102,
3508 PPORT_RX_DROPPED_TOO_SHORT = 103,
3509 PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104,
3510 PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105,
3511 PPORT_RX_DROPPED_RUNT = 106,
3512 PPORT_RX_IP_CHECKSUM_ERRORS = 107,
3513 PPORT_RX_TCP_CHECKSUM_ERRORS = 108,
3514 PPORT_RX_UDP_CHECKSUM_ERRORS = 109,
3515 PPORT_RX_NON_RSS_PKTS = 110,
3516 PPORT_RESERVED_WORD111 = 111,
3517 PPORT_RX_IPV4_PKTS = 112,
3518 PPORT_RX_IPV6_PKTS = 114,
3519 PPORT_RX_IPV4_BYTES = 116,
3520 PPORT_RX_IPV6_BYTES = 118,
3521 PPORT_RX_NIC_PKTS = 120,
3522 PPORT_RX_TCP_PKTS = 122,
3523 PPORT_RX_ISCSI_PKTS = 124,
3524 PPORT_RX_MANAGEMENT_PKTS = 126,
3525 PPORT_RX_SWITCHED_UNICAST_PKTS = 128,
3526 PPORT_RX_SWITCHED_MULTICAST_PKTS = 130,
3527 PPORT_RX_SWITCHED_BROADCAST_PKTS = 132,
3528 PPORT_NUM_FORWARDS = 134,
3529 PPORT_RX_FIFO_OVERFLOW = 136,
3530 PPORT_RX_INPUT_FIFO_OVERFLOW = 137,
3531 PPORT_RX_DROPS_TOO_MANY_FRAGS = 138,
3532 PPORT_RX_DROPS_INVALID_QUEUE = 140,
3533 PPORT_RESERVED_WORD141 = 141,
3534 PPORT_RX_DROPS_MTU = 142,
3535 PPORT_RX_PKTS_64_BYTES = 144,
3536 PPORT_RX_PKTS_65_TO_127_BYTES = 146,
3537 PPORT_RX_PKTS_128_TO_255_BYTES = 148,
3538 PPORT_RX_PKTS_256_TO_511_BYTES = 150,
3539 PPORT_RX_PKTS_512_TO_1023_BYTES = 152,
3540 PPORT_RX_PKTS_1024_TO_1518_BYTES = 154,
3541 PPORT_RX_PKTS_1519_TO_2047_BYTES = 156,
3542 PPORT_RX_PKTS_2048_TO_4095_BYTES = 158,
3543 PPORT_RX_PKTS_4096_TO_8191_BYTES = 160,
3544 PPORT_RX_PKTS_8192_TO_9216_BYTES = 162,
3545 PPORT_N_WORDS = 164
3546};
3547
3548/**
3549 * @brief Statistics for a given Virtual Port (vPort)
3550 * The following describes the vPort statistics satisfying
3551 * requirements of Linux/VMWare netdev statistics and
3552 * Microsoft Windows Statistics along with other Operating Systems.
3553 */
3554enum OCE_VPORT_STATS {
3555 VPORT_TX_PKTS = 0,
3556 VPORT_TX_UNICAST_PKTS = 2,
3557 VPORT_TX_MULTICAST_PKTS = 4,
3558 VPORT_TX_BROADCAST_PKTS = 6,
3559 VPORT_TX_BYTES = 8,
3560 VPORT_TX_UNICAST_BYTES = 10,
3561 VPORT_TX_MULTICAST_BYTES = 12,
3562 VPORT_TX_BROADCAST_BYTES = 14,
3563 VPORT_TX_DISCARDS = 16,
3564 VPORT_TX_ERRORS = 18,
3565 VPORT_TX_PKTS_64_BYTES = 20,
3566 VPORT_TX_PKTS_65_TO_127_BYTES = 22,
3567 VPORT_TX_PKTS_128_TO_255_BYTES = 24,
3568 VPORT_TX_PKTS_256_TO_511_BYTES = 26,
3569 VPORT_TX_PKTS_512_TO_1023_BYTEs = 28,
3570 VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30,
3571 VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32,
3572 VPORT_TX_PKTS_OVER_9699_BYTES = 34,
3573 VPORT_RX_PKTS = 36,
3574 VPORT_RX_UNICAST_PKTS = 38,
3575 VPORT_RX_MULTICAST_PKTS = 40,
3576 VPORT_RX_BROADCAST_PKTS = 42,
3577 VPORT_RX_BYTES = 44,
3578 VPORT_RX_UNICAST_BYTES = 46,
3579 VPORT_RX_MULTICAST_BYTES = 48,
3580 VPORT_RX_BROADCAST_BYTES = 50,
3581 VPORT_RX_DISCARDS = 52,
3582 VPORT_RX_ERRORS = 54,
3583 VPORT_RX_PKTS_64_BYTES = 56,
3584 VPORT_RX_PKTS_65_TO_127_BYTES = 58,
3585 VPORT_RX_PKTS_128_TO_255_BYTES = 60,
3586 VPORT_RX_PKTS_256_TO_511_BYTES = 62,
3587 VPORT_RX_PKTS_512_TO_1023_BYTEs = 64,
3588 VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66,
3589 VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68,
3590 VPORT_RX_PKTS_OVER_9699_BYTES = 70,
3591 VPORT_N_WORDS = 72
3592};
3593
3594/**
3595 * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ)
3596 * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ
3597 */
3598enum OCE_QUEUE_TX_STATS {
3599 QUEUE_TX_PKTS = 0,
3600 QUEUE_TX_BYTES = 2,
3601 QUEUE_TX_ERRORS = 4,
3602 QUEUE_TX_DROPS = 6,
3603 QUEUE_TX_N_WORDS = 8
3604};
3605
3606enum OCE_QUEUE_RX_STATS {
3607 QUEUE_RX_PKTS = 0,
3608 QUEUE_RX_BYTES = 2,
3609 QUEUE_RX_ERRORS = 4,
3610 QUEUE_RX_DROPS = 6,
3611 QUEUE_RX_BUFFER_ERRORS = 8,
3612 QUEUE_RX_N_WORDS = 10
3613};
3614
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