1/*-
2 * Copyright (C) 2012 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

--- 22 unchanged lines hidden (view full) ---

31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39/* $FreeBSD: head/sys/dev/oce/oce_hw.h 231879 2012-02-17 13:55:17Z luigi $ */
40
41#include <sys/types.h>
42
43#undef _BIG_ENDIAN /* TODO */
44#pragma pack(1)
45
46#define OC_CNA_GEN2 0x2
47#define OC_CNA_GEN3 0x3
48#define DEVID_TIGERSHARK 0x700

--- 101 unchanged lines hidden (view full) ---

150#define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
151
152#define MBX_DB_READY_BIT 0x1
153#define MBX_DB_HI_BIT 0x2
154#define ASYNC_EVENT_CODE_LINK_STATE 0x1
155#define ASYNC_EVENT_LINK_UP 0x1
156#define ASYNC_EVENT_LINK_DOWN 0x0
157#define ASYNC_EVENT_GRP5 0x5
158#define ASYNC_EVENT_PVID_STATE 0x3
159#define VLAN_VID_MASK 0x0FFF
160
161/* port link_status */
162#define ASYNC_EVENT_LOGICAL 0x02
163
164/* Logical Link Status */
165#define NTWK_LOGICAL_LINK_DOWN 0
166#define NTWK_LOGICAL_LINK_UP 1

--- 535 unchanged lines hidden (view full) ---

702 uint8_t enabled;
703 uint8_t rsvd0;
704 uint16_t tag;
705 uint32_t event_tag;
706 uint32_t rsvd1;
707 uint32_t code;
708};
709
710typedef union oce_mq_ext_ctx_u {
711 uint32_t dw[6];
712 struct {
713 #ifdef _BIG_ENDIAN
714 /* dw0 */
715 uint32_t dw4rsvd1:16;
716 uint32_t num_pages:16;
717 /* dw1 */

--- 27 unchanged lines hidden (view full) ---

745 /* dw4 */
746 uint32_t async_cq_valid:1;
747 uint32_t async_cq_id:10;
748 uint32_t dw7rsvd1:21;
749 #endif
750 /* dw5 */
751 uint32_t dw8rsvd1;
752 } v0;
753} oce_mq_ext_ctx_t;
754
755
756/* MQ mailbox structure */
757struct oce_bmbx {
758 struct oce_mbx mbx;
759 struct oce_mq_cqe cqe;
760};

--- 60 unchanged lines hidden (view full) ---

821 OPCODE_COMMON_DEL_IFACE_MAC = 60,
822 OPCODE_COMMON_FUNCTION_RESET = 61,
823 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
824 OPCODE_COMMON_GET_BOOT_CONFIG = 66,
825 OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
826 OPCODE_COMMON_SET_BEACON_CONFIG = 69,
827 OPCODE_COMMON_GET_BEACON_CONFIG = 70,
828 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
829 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
830 OPCODE_COMMON_GET_PORT_NAME = 77,
831 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
832 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
833 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
834 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
835 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
836 OPCODE_COMMON_GET_RESET_NEEDED = 84,

--- 882 unchanged lines hidden (view full) ---

1719struct mbx_set_common_iface_rx_filter {
1720 struct mbx_hdr hdr;
1721 union {
1722 iface_rx_filter_ctx_t req;
1723 iface_rx_filter_ctx_t rsp;
1724 } params;
1725};
1726
1727/* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
1728struct mbx_modify_common_eq_delay {
1729 struct mbx_hdr hdr;
1730 union {
1731 struct {
1732 uint32_t num_eq;
1733 struct {
1734 uint32_t eq_id;
1735 uint32_t phase;
1736 uint32_t dm;
1737 } delay[8];
1738 } req;
1739
1740 struct {
1741 uint32_t rsvd0;
1742 } rsp;
1743 } params;
1744};
1745
1746/* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1747struct mbx_add_common_iface_mac {
1748 struct mbx_hdr hdr;
1749 union {
1750 struct {
1751 uint32_t if_id;
1752 uint8_t mac_address[6];
1753 uint8_t rsvd0[2];

--- 26 unchanged lines hidden (view full) ---

1780 } rsp;
1781};
1782
1783/* [61] OPCODE_COMMON_FUNCTION_RESET */
1784struct ioctl_common_function_reset {
1785 struct mbx_hdr hdr;
1786};
1787
1788/* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1789struct mbx_common_func_link_cfg {
1790 struct mbx_hdr hdr;
1791 union {
1792 struct {
1793 uint32_t enable;
1794 } req;
1795 struct {

--- 309 unchanged lines hidden (view full) ---

2105};
2106
2107/* Hash option flags for RSS enable */
2108enum RSS_ENABLE_FLAGS {
2109 RSS_ENABLE_NONE = 0x0, /* (No RSS) */
2110 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */
2111 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */
2112 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */
2113 RSS_ENABLE_TCP_IPV6 = 0x8 /* (TCP IPV6 HASH */
2114};
2115#define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
2116#define RSS_DISABLE RSS_ENABLE_NONE
2117
2118/* NIC header WQE */
2119struct oce_nic_hdr_wqe {
2120 union {
2121 struct {

--- 1343 unchanged lines hidden ---