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oce_hw.c (247880) oce_hw.c (252869)
1/*-
1/*-
2 * Copyright (C) 2012 Emulex
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *

--- 20 unchanged lines hidden (view full) ---

31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *

--- 20 unchanged lines hidden (view full) ---

31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39/* $FreeBSD: head/sys/dev/oce/oce_hw.c 247880 2013-03-06 09:53:38Z delphij $ */
39/* $FreeBSD: head/sys/dev/oce/oce_hw.c 252869 2013-07-06 08:30:45Z delphij $ */
40
41#include "oce_if.h"
42
43static int oce_POST(POCE_SOFTC sc);
44
45/**
46 * @brief Function to post status
47 * @param sc software handle to the device
48 */
49static int
50oce_POST(POCE_SOFTC sc)
51{
52 mpu_ep_semaphore_t post_status;
53 int tmo = 60000;
54
55 /* read semaphore CSR */
40
41#include "oce_if.h"
42
43static int oce_POST(POCE_SOFTC sc);
44
45/**
46 * @brief Function to post status
47 * @param sc software handle to the device
48 */
49static int
50oce_POST(POCE_SOFTC sc)
51{
52 mpu_ep_semaphore_t post_status;
53 int tmo = 60000;
54
55 /* read semaphore CSR */
56 post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
56 post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
57
58 /* if host is ready then wait for fw ready else send POST */
59 if (post_status.bits.stage <= POST_STAGE_AWAITING_HOST_RDY) {
60 post_status.bits.stage = POST_STAGE_CHIP_RESET;
57
58 /* if host is ready then wait for fw ready else send POST */
59 if (post_status.bits.stage <= POST_STAGE_AWAITING_HOST_RDY) {
60 post_status.bits.stage = POST_STAGE_CHIP_RESET;
61 OCE_WRITE_REG32(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
61 OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
62 }
63
64 /* wait for FW ready */
65 for (;;) {
66 if (--tmo == 0)
67 break;
68
69 DELAY(1000);
70
62 }
63
64 /* wait for FW ready */
65 for (;;) {
66 if (--tmo == 0)
67 break;
68
69 DELAY(1000);
70
71 post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
71 post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
72 if (post_status.bits.error) {
73 device_printf(sc->dev,
74 "POST failed: %x\n", post_status.dw0);
75 return ENXIO;
76 }
77 if (post_status.bits.stage == POST_STAGE_ARMFW_READY)
78 return 0;
79 }

--- 44 unchanged lines hidden (view full) ---

124
125
126 sc->macaddr.size_of_struct = 6;
127 rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK,
128 &sc->macaddr);
129 if (rc)
130 goto error;
131
72 if (post_status.bits.error) {
73 device_printf(sc->dev,
74 "POST failed: %x\n", post_status.dw0);
75 return ENXIO;
76 }
77 if (post_status.bits.stage == POST_STAGE_ARMFW_READY)
78 return 0;
79 }

--- 44 unchanged lines hidden (view full) ---

124
125
126 sc->macaddr.size_of_struct = 6;
127 rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK,
128 &sc->macaddr);
129 if (rc)
130 goto error;
131
132 if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) {
132 if ((IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) || IS_SH(sc)) {
133 rc = oce_mbox_check_native_mode(sc);
134 if (rc)
135 goto error;
136 } else
137 sc->be3_native = 0;
138
139 return rc;
140

--- 112 unchanged lines hidden (view full) ---

253 /* setup the device config region */
254 if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
255 pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
256 else
257 pci_cfg_barnum = OCE_DEV_CFG_BAR;
258
259 rr = PCIR_BAR(pci_cfg_barnum);
260
133 rc = oce_mbox_check_native_mode(sc);
134 if (rc)
135 goto error;
136 } else
137 sc->be3_native = 0;
138
139 return rc;
140

--- 112 unchanged lines hidden (view full) ---

253 /* setup the device config region */
254 if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
255 pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
256 else
257 pci_cfg_barnum = OCE_DEV_CFG_BAR;
258
259 rr = PCIR_BAR(pci_cfg_barnum);
260
261 if (IS_BE(sc))
261 if (IS_BE(sc) || IS_SH(sc))
262 sc->devcfg_res = bus_alloc_resource_any(sc->dev,
263 SYS_RES_MEMORY, &rr,
264 RF_ACTIVE|RF_SHAREABLE);
265 else
266 sc->devcfg_res = bus_alloc_resource(sc->dev,
267 SYS_RES_MEMORY, &rr,
268 0ul, ~0ul, 32768,
269 RF_ACTIVE|RF_SHAREABLE);

--- 23 unchanged lines hidden (view full) ---

293
294 if (intf.bits.sli_hint1 == OCE_INTF_FUNC_RESET_REQD)
295 sc->flags |= OCE_FLAGS_FUNCRESET_RQD;
296
297 if (intf.bits.sli_func_type == OCE_INTF_VIRT_FUNC)
298 sc->flags |= OCE_FLAGS_VIRTUAL_PORT;
299
300 /* Lancer has one BAR (CFG) but BE3 has three (CFG, CSR, DB) */
262 sc->devcfg_res = bus_alloc_resource_any(sc->dev,
263 SYS_RES_MEMORY, &rr,
264 RF_ACTIVE|RF_SHAREABLE);
265 else
266 sc->devcfg_res = bus_alloc_resource(sc->dev,
267 SYS_RES_MEMORY, &rr,
268 0ul, ~0ul, 32768,
269 RF_ACTIVE|RF_SHAREABLE);

--- 23 unchanged lines hidden (view full) ---

293
294 if (intf.bits.sli_hint1 == OCE_INTF_FUNC_RESET_REQD)
295 sc->flags |= OCE_FLAGS_FUNCRESET_RQD;
296
297 if (intf.bits.sli_func_type == OCE_INTF_VIRT_FUNC)
298 sc->flags |= OCE_FLAGS_VIRTUAL_PORT;
299
300 /* Lancer has one BAR (CFG) but BE3 has three (CFG, CSR, DB) */
301 if (IS_BE(sc)) {
301 if (IS_BE(sc) || IS_SH(sc)) {
302 /* set up CSR region */
303 rr = PCIR_BAR(OCE_PCI_CSR_BAR);
304 sc->csr_res = bus_alloc_resource_any(sc->dev,
305 SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
306 if (!sc->csr_res)
307 goto error;
308 sc->csr_btag = rman_get_bustag(sc->csr_res);
309 sc->csr_bhandle = rman_get_bushandle(sc->csr_res);

--- 72 unchanged lines hidden (view full) ---

382
383 if (IS_XE201(sc)) {
384 /* LANCER A0 workaround */
385 capab_en_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
386 capab_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
387 }
388
389 /* enable capabilities controlled via driver startup parameters */
302 /* set up CSR region */
303 rr = PCIR_BAR(OCE_PCI_CSR_BAR);
304 sc->csr_res = bus_alloc_resource_any(sc->dev,
305 SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
306 if (!sc->csr_res)
307 goto error;
308 sc->csr_btag = rman_get_bustag(sc->csr_res);
309 sc->csr_bhandle = rman_get_bushandle(sc->csr_res);

--- 72 unchanged lines hidden (view full) ---

382
383 if (IS_XE201(sc)) {
384 /* LANCER A0 workaround */
385 capab_en_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
386 capab_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
387 }
388
389 /* enable capabilities controlled via driver startup parameters */
390 if (sc->rss_enable)
390 if (is_rss_enabled(sc))
391 capab_en_flags |= MBX_RX_IFACE_FLAGS_RSS;
392 else {
393 capab_en_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
394 capab_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
395 }
396
397 rc = oce_if_create(sc,
398 capab_flags,

--- 43 unchanged lines hidden (view full) ---

442 * @returns 0 on success, error otherwise
443 */
444int
445oce_pci_soft_reset(POCE_SOFTC sc)
446{
447 int rc;
448 mpu_ep_control_t ctrl;
449
391 capab_en_flags |= MBX_RX_IFACE_FLAGS_RSS;
392 else {
393 capab_en_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
394 capab_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
395 }
396
397 rc = oce_if_create(sc,
398 capab_flags,

--- 43 unchanged lines hidden (view full) ---

442 * @returns 0 on success, error otherwise
443 */
444int
445oce_pci_soft_reset(POCE_SOFTC sc)
446{
447 int rc;
448 mpu_ep_control_t ctrl;
449
450 ctrl.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_CONTROL);
450 ctrl.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_CONTROL);
451 ctrl.bits.cpu_reset = 1;
451 ctrl.bits.cpu_reset = 1;
452 OCE_WRITE_REG32(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
452 OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
453 DELAY(50);
454 rc=oce_POST(sc);
455
456 return rc;
457}
458
459/**
460 * @brief Function for hardware start

--- 127 unchanged lines hidden --- 		453 DELAY(50);
454 rc=oce_POST(sc);
455
456 return rc;
457}
458
459/**
460 * @brief Function for hardware start

--- 127 unchanged lines hidden ---