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< * Copyright (C) 2012 Emulex
---
> * Copyright (C) 2013 Emulex
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< /* $FreeBSD: head/sys/dev/oce/oce_hw.c 247880 2013-03-06 09:53:38Z delphij $ */
---
> /* $FreeBSD: head/sys/dev/oce/oce_hw.c 252869 2013-07-06 08:30:45Z delphij $ */
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< post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
---
> post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
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< OCE_WRITE_REG32(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
---
> OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
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< post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
---
> post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
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< if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) {
---
> if ((IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) || IS_SH(sc)) {
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< if (IS_BE(sc))
---
> if (IS_BE(sc) || IS_SH(sc))
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< if (IS_BE(sc)) {
---
> if (IS_BE(sc) || IS_SH(sc)) {
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< if (sc->rss_enable)
---
> if (is_rss_enabled(sc))
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< ctrl.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_CONTROL);
---
> ctrl.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_CONTROL);
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< OCE_WRITE_REG32(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
---
> OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_CONTROL, ctrl.dw0);