29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/endian.h> 36#include <sys/malloc.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <vm/uma.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <arm/mv/mvreg.h> 45#include <arm/mv/mvvar.h> 46#include "mvs.h" 47 48/* local prototypes */ 49static int mvs_setup_interrupt(device_t dev); 50static void mvs_intr(void *data); 51static int mvs_suspend(device_t dev); 52static int mvs_resume(device_t dev); 53static int mvs_ctlr_setup(device_t dev); 54 55static struct { 56 uint32_t id; 57 uint8_t rev; 58 const char *name; 59 int ports; 60 int quirks; 61} mvs_ids[] = { 62 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 63 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 64 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 65 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 66 {0, 0x00, NULL, 0, 0} 67}; 68 69static int 70mvs_probe(device_t dev) 71{ 72 char buf[64]; 73 int i; 74 uint32_t devid, revid; 75 76 soc_id(&devid, &revid); 77 for (i = 0; mvs_ids[i].id != 0; i++) { 78 if (mvs_ids[i].id == devid && 79 mvs_ids[i].rev <= revid) { 80 snprintf(buf, sizeof(buf), "%s SATA controller", 81 mvs_ids[i].name); 82 device_set_desc_copy(dev, buf); 83 return (BUS_PROBE_VENDOR); 84 } 85 } 86 return (ENXIO); 87} 88 89static int 90mvs_attach(device_t dev) 91{ 92 struct mvs_controller *ctlr = device_get_softc(dev); 93 device_t child; 94 int error, unit, i; 95 uint32_t devid, revid; 96 97 soc_id(&devid, &revid); 98 ctlr->dev = dev; 99 i = 0; 100 while (mvs_ids[i].id != 0 && 101 (mvs_ids[i].id != devid || 102 mvs_ids[i].rev > revid)) 103 i++; 104 ctlr->channels = mvs_ids[i].ports; 105 ctlr->quirks = mvs_ids[i].quirks; 106 resource_int_value(device_get_name(dev), 107 device_get_unit(dev), "ccc", &ctlr->ccc); 108 ctlr->cccc = 8; 109 resource_int_value(device_get_name(dev), 110 device_get_unit(dev), "cccc", &ctlr->cccc); 111 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 112 ctlr->ccc = 0; 113 ctlr->cccc = 0; 114 } 115 if (ctlr->ccc > 100000) 116 ctlr->ccc = 100000; 117 device_printf(dev, 118 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 119 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 120 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 121 ctlr->channels, 122 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 123 ((ctlr->quirks & MVS_Q_GENI) ? 124 "not supported" : "supported"), 125 ((ctlr->quirks & MVS_Q_GENIIE) ? 126 " with FBS" : "")); 127 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 128 /* We should have a memory BAR(0). */ 129 ctlr->r_rid = 0; 130 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 131 &ctlr->r_rid, RF_ACTIVE))) 132 return ENXIO; 133 /* Setup our own memory management for channels. */ 134 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 135 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 136 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 137 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 138 return (error); 139 } 140 if ((error = rman_manage_region(&ctlr->sc_iomem, 141 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 142 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 143 rman_fini(&ctlr->sc_iomem); 144 return (error); 145 } 146 mvs_ctlr_setup(dev); 147 /* Setup interrupts. */ 148 if (mvs_setup_interrupt(dev)) { 149 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 150 rman_fini(&ctlr->sc_iomem); 151 return ENXIO; 152 } 153 /* Attach all channels on this controller */ 154 for (unit = 0; unit < ctlr->channels; unit++) { 155 child = device_add_child(dev, "mvsch", -1); 156 if (child == NULL) 157 device_printf(dev, "failed to add channel device\n"); 158 else 159 device_set_ivars(child, (void *)(intptr_t)unit); 160 } 161 bus_generic_attach(dev); 162 return 0; 163} 164 165static int 166mvs_detach(device_t dev) 167{ 168 struct mvs_controller *ctlr = device_get_softc(dev); 169 device_t *children; 170 int nchildren, i; 171 172 /* Detach & delete all children */ 173 if (!device_get_children(dev, &children, &nchildren)) { 174 for (i = 0; i < nchildren; i++) 175 device_delete_child(dev, children[i]); 176 free(children, M_TEMP); 177 } 178 /* Free interrupt. */ 179 if (ctlr->irq.r_irq) { 180 bus_teardown_intr(dev, ctlr->irq.r_irq, 181 ctlr->irq.handle); 182 bus_release_resource(dev, SYS_RES_IRQ, 183 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 184 } 185 /* Free memory. */ 186 rman_fini(&ctlr->sc_iomem); 187 if (ctlr->r_mem) 188 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 189 mtx_destroy(&ctlr->mtx); 190 return (0); 191} 192 193static int 194mvs_ctlr_setup(device_t dev) 195{ 196 struct mvs_controller *ctlr = device_get_softc(dev); 197 int ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 198 199 /* Mask chip interrupts */ 200 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 201 /* Clear HC interrupts */ 202 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 203 /* Clear chip interrupts */ 204 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 205 /* Configure per-HC CCC */ 206 if (ccc && bootverbose) { 207 device_printf(dev, 208 "CCC with %dus/%dcmd enabled\n", 209 ctlr->ccc, ctlr->cccc); 210 } 211 ccc *= 150; 212 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 213 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 214 if (ccc) 215 ccim |= IC_HC0_COAL_DONE; 216 /* Enable chip interrupts */ 217 ctlr->gmim = (ccc ? IC_HC0_COAL_DONE : IC_DONE_HC0) | IC_ERR_HC0; 218 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 219 return (0); 220} 221 222static void 223mvs_edma(device_t dev, device_t child, int mode) 224{ 225 struct mvs_controller *ctlr = device_get_softc(dev); 226 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 227 int bit = IC_DONE_IRQ << (unit * 2); 228 229 if (ctlr->ccc == 0) 230 return; 231 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 232 mtx_lock(&ctlr->mtx); 233 if (mode == MVS_EDMA_OFF) 234 ctlr->pmim |= bit; 235 else 236 ctlr->pmim &= ~bit; 237 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 238 mtx_unlock(&ctlr->mtx); 239} 240 241static int 242mvs_suspend(device_t dev) 243{ 244 struct mvs_controller *ctlr = device_get_softc(dev); 245 246 bus_generic_suspend(dev); 247 /* Mask chip interrupts */ 248 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 249 return 0; 250} 251 252static int 253mvs_resume(device_t dev) 254{ 255 256 mvs_ctlr_setup(dev); 257 return (bus_generic_resume(dev)); 258} 259 260static int 261mvs_setup_interrupt(device_t dev) 262{ 263 struct mvs_controller *ctlr = device_get_softc(dev); 264 265 /* Allocate all IRQs. */ 266 ctlr->irq.r_irq_rid = 0; 267 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 268 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 269 device_printf(dev, "unable to map interrupt\n"); 270 return (ENXIO); 271 } 272 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 273 mvs_intr, ctlr, &ctlr->irq.handle))) { 274 device_printf(dev, "unable to setup interrupt\n"); 275 bus_release_resource(dev, SYS_RES_IRQ, 276 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 277 ctlr->irq.r_irq = 0; 278 return (ENXIO); 279 } 280 return (0); 281} 282 283/* 284 * Common case interrupt handler. 285 */ 286static void 287mvs_intr(void *data) 288{ 289 struct mvs_controller *ctlr = data; 290 struct mvs_intr_arg arg; 291 void (*function)(void *); 292 int p; 293 u_int32_t ic, aic; 294 295 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 296//device_printf(ctlr->dev, "irq MIC:%08x\n", ic); 297 if ((ic & IC_HC0) == 0) 298 return; 299 /* Acknowledge interrupts of this HC. */ 300 aic = 0; 301 if (ic & (IC_DONE_IRQ << 0)) 302 aic |= HC_IC_DONE(0) | HC_IC_DEV(0); 303 if (ic & (IC_DONE_IRQ << 2)) 304 aic |= HC_IC_DONE(1) | HC_IC_DEV(1); 305 if (ic & (IC_DONE_IRQ << 4)) 306 aic |= HC_IC_DONE(2) | HC_IC_DEV(2); 307 if (ic & (IC_DONE_IRQ << 6)) 308 aic |= HC_IC_DONE(3) | HC_IC_DEV(3); 309 if (ic & IC_HC0_COAL_DONE) 310 aic |= HC_IC_COAL; 311 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 312 /* Call per-port interrupt handler. */ 313 for (p = 0; p < ctlr->channels; p++) { 314 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 315 if ((arg.cause != 0) && 316 (function = ctlr->interrupt[p].function)) { 317 arg.arg = ctlr->interrupt[p].argument; 318 function(&arg); 319 } 320 ic >>= 2; 321 } 322} 323 324static struct resource * 325mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 326 u_long start, u_long end, u_long count, u_int flags) 327{ 328 struct mvs_controller *ctlr = device_get_softc(dev); 329 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 330 struct resource *res = NULL; 331 int offset = PORT_BASE(unit & 0x03); 332 long st; 333 334 switch (type) { 335 case SYS_RES_MEMORY: 336 st = rman_get_start(ctlr->r_mem); 337 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 338 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 339 if (res) { 340 bus_space_handle_t bsh; 341 bus_space_tag_t bst; 342 bsh = rman_get_bushandle(ctlr->r_mem); 343 bst = rman_get_bustag(ctlr->r_mem); 344 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 345 rman_set_bushandle(res, bsh); 346 rman_set_bustag(res, bst); 347 } 348 break; 349 case SYS_RES_IRQ: 350 if (*rid == ATA_IRQ_RID) 351 res = ctlr->irq.r_irq; 352 break; 353 } 354 return (res); 355} 356 357static int 358mvs_release_resource(device_t dev, device_t child, int type, int rid, 359 struct resource *r) 360{ 361 362 switch (type) { 363 case SYS_RES_MEMORY: 364 rman_release_resource(r); 365 return (0); 366 case SYS_RES_IRQ: 367 if (rid != ATA_IRQ_RID) 368 return ENOENT; 369 return (0); 370 } 371 return (EINVAL); 372} 373 374static int 375mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 376 int flags, driver_filter_t *filter, driver_intr_t *function, 377 void *argument, void **cookiep) 378{ 379 struct mvs_controller *ctlr = device_get_softc(dev); 380 int unit = (intptr_t)device_get_ivars(child); 381 382 if (filter != NULL) { 383 printf("mvs.c: we cannot use a filter here\n"); 384 return (EINVAL); 385 } 386 ctlr->interrupt[unit].function = function; 387 ctlr->interrupt[unit].argument = argument; 388 return (0); 389} 390 391static int 392mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 393 void *cookie) 394{ 395 struct mvs_controller *ctlr = device_get_softc(dev); 396 int unit = (intptr_t)device_get_ivars(child); 397 398 ctlr->interrupt[unit].function = NULL; 399 ctlr->interrupt[unit].argument = NULL; 400 return (0); 401} 402 403static int 404mvs_print_child(device_t dev, device_t child) 405{ 406 int retval; 407 408 retval = bus_print_child_header(dev, child); 409 retval += printf(" at channel %d", 410 (int)(intptr_t)device_get_ivars(child)); 411 retval += bus_print_child_footer(dev, child); 412 413 return (retval); 414} 415
| 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/endian.h> 36#include <sys/malloc.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <vm/uma.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <arm/mv/mvreg.h> 45#include <arm/mv/mvvar.h> 46#include "mvs.h" 47 48/* local prototypes */ 49static int mvs_setup_interrupt(device_t dev); 50static void mvs_intr(void *data); 51static int mvs_suspend(device_t dev); 52static int mvs_resume(device_t dev); 53static int mvs_ctlr_setup(device_t dev); 54 55static struct { 56 uint32_t id; 57 uint8_t rev; 58 const char *name; 59 int ports; 60 int quirks; 61} mvs_ids[] = { 62 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 63 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 64 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 65 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 66 {0, 0x00, NULL, 0, 0} 67}; 68 69static int 70mvs_probe(device_t dev) 71{ 72 char buf[64]; 73 int i; 74 uint32_t devid, revid; 75 76 soc_id(&devid, &revid); 77 for (i = 0; mvs_ids[i].id != 0; i++) { 78 if (mvs_ids[i].id == devid && 79 mvs_ids[i].rev <= revid) { 80 snprintf(buf, sizeof(buf), "%s SATA controller", 81 mvs_ids[i].name); 82 device_set_desc_copy(dev, buf); 83 return (BUS_PROBE_VENDOR); 84 } 85 } 86 return (ENXIO); 87} 88 89static int 90mvs_attach(device_t dev) 91{ 92 struct mvs_controller *ctlr = device_get_softc(dev); 93 device_t child; 94 int error, unit, i; 95 uint32_t devid, revid; 96 97 soc_id(&devid, &revid); 98 ctlr->dev = dev; 99 i = 0; 100 while (mvs_ids[i].id != 0 && 101 (mvs_ids[i].id != devid || 102 mvs_ids[i].rev > revid)) 103 i++; 104 ctlr->channels = mvs_ids[i].ports; 105 ctlr->quirks = mvs_ids[i].quirks; 106 resource_int_value(device_get_name(dev), 107 device_get_unit(dev), "ccc", &ctlr->ccc); 108 ctlr->cccc = 8; 109 resource_int_value(device_get_name(dev), 110 device_get_unit(dev), "cccc", &ctlr->cccc); 111 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 112 ctlr->ccc = 0; 113 ctlr->cccc = 0; 114 } 115 if (ctlr->ccc > 100000) 116 ctlr->ccc = 100000; 117 device_printf(dev, 118 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 119 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 120 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 121 ctlr->channels, 122 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 123 ((ctlr->quirks & MVS_Q_GENI) ? 124 "not supported" : "supported"), 125 ((ctlr->quirks & MVS_Q_GENIIE) ? 126 " with FBS" : "")); 127 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 128 /* We should have a memory BAR(0). */ 129 ctlr->r_rid = 0; 130 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 131 &ctlr->r_rid, RF_ACTIVE))) 132 return ENXIO; 133 /* Setup our own memory management for channels. */ 134 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 135 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 136 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 137 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 138 return (error); 139 } 140 if ((error = rman_manage_region(&ctlr->sc_iomem, 141 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 142 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 143 rman_fini(&ctlr->sc_iomem); 144 return (error); 145 } 146 mvs_ctlr_setup(dev); 147 /* Setup interrupts. */ 148 if (mvs_setup_interrupt(dev)) { 149 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 150 rman_fini(&ctlr->sc_iomem); 151 return ENXIO; 152 } 153 /* Attach all channels on this controller */ 154 for (unit = 0; unit < ctlr->channels; unit++) { 155 child = device_add_child(dev, "mvsch", -1); 156 if (child == NULL) 157 device_printf(dev, "failed to add channel device\n"); 158 else 159 device_set_ivars(child, (void *)(intptr_t)unit); 160 } 161 bus_generic_attach(dev); 162 return 0; 163} 164 165static int 166mvs_detach(device_t dev) 167{ 168 struct mvs_controller *ctlr = device_get_softc(dev); 169 device_t *children; 170 int nchildren, i; 171 172 /* Detach & delete all children */ 173 if (!device_get_children(dev, &children, &nchildren)) { 174 for (i = 0; i < nchildren; i++) 175 device_delete_child(dev, children[i]); 176 free(children, M_TEMP); 177 } 178 /* Free interrupt. */ 179 if (ctlr->irq.r_irq) { 180 bus_teardown_intr(dev, ctlr->irq.r_irq, 181 ctlr->irq.handle); 182 bus_release_resource(dev, SYS_RES_IRQ, 183 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 184 } 185 /* Free memory. */ 186 rman_fini(&ctlr->sc_iomem); 187 if (ctlr->r_mem) 188 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 189 mtx_destroy(&ctlr->mtx); 190 return (0); 191} 192 193static int 194mvs_ctlr_setup(device_t dev) 195{ 196 struct mvs_controller *ctlr = device_get_softc(dev); 197 int ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 198 199 /* Mask chip interrupts */ 200 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 201 /* Clear HC interrupts */ 202 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 203 /* Clear chip interrupts */ 204 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 205 /* Configure per-HC CCC */ 206 if (ccc && bootverbose) { 207 device_printf(dev, 208 "CCC with %dus/%dcmd enabled\n", 209 ctlr->ccc, ctlr->cccc); 210 } 211 ccc *= 150; 212 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 213 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 214 if (ccc) 215 ccim |= IC_HC0_COAL_DONE; 216 /* Enable chip interrupts */ 217 ctlr->gmim = (ccc ? IC_HC0_COAL_DONE : IC_DONE_HC0) | IC_ERR_HC0; 218 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 219 return (0); 220} 221 222static void 223mvs_edma(device_t dev, device_t child, int mode) 224{ 225 struct mvs_controller *ctlr = device_get_softc(dev); 226 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 227 int bit = IC_DONE_IRQ << (unit * 2); 228 229 if (ctlr->ccc == 0) 230 return; 231 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 232 mtx_lock(&ctlr->mtx); 233 if (mode == MVS_EDMA_OFF) 234 ctlr->pmim |= bit; 235 else 236 ctlr->pmim &= ~bit; 237 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 238 mtx_unlock(&ctlr->mtx); 239} 240 241static int 242mvs_suspend(device_t dev) 243{ 244 struct mvs_controller *ctlr = device_get_softc(dev); 245 246 bus_generic_suspend(dev); 247 /* Mask chip interrupts */ 248 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 249 return 0; 250} 251 252static int 253mvs_resume(device_t dev) 254{ 255 256 mvs_ctlr_setup(dev); 257 return (bus_generic_resume(dev)); 258} 259 260static int 261mvs_setup_interrupt(device_t dev) 262{ 263 struct mvs_controller *ctlr = device_get_softc(dev); 264 265 /* Allocate all IRQs. */ 266 ctlr->irq.r_irq_rid = 0; 267 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 268 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 269 device_printf(dev, "unable to map interrupt\n"); 270 return (ENXIO); 271 } 272 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 273 mvs_intr, ctlr, &ctlr->irq.handle))) { 274 device_printf(dev, "unable to setup interrupt\n"); 275 bus_release_resource(dev, SYS_RES_IRQ, 276 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 277 ctlr->irq.r_irq = 0; 278 return (ENXIO); 279 } 280 return (0); 281} 282 283/* 284 * Common case interrupt handler. 285 */ 286static void 287mvs_intr(void *data) 288{ 289 struct mvs_controller *ctlr = data; 290 struct mvs_intr_arg arg; 291 void (*function)(void *); 292 int p; 293 u_int32_t ic, aic; 294 295 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 296//device_printf(ctlr->dev, "irq MIC:%08x\n", ic); 297 if ((ic & IC_HC0) == 0) 298 return; 299 /* Acknowledge interrupts of this HC. */ 300 aic = 0; 301 if (ic & (IC_DONE_IRQ << 0)) 302 aic |= HC_IC_DONE(0) | HC_IC_DEV(0); 303 if (ic & (IC_DONE_IRQ << 2)) 304 aic |= HC_IC_DONE(1) | HC_IC_DEV(1); 305 if (ic & (IC_DONE_IRQ << 4)) 306 aic |= HC_IC_DONE(2) | HC_IC_DEV(2); 307 if (ic & (IC_DONE_IRQ << 6)) 308 aic |= HC_IC_DONE(3) | HC_IC_DEV(3); 309 if (ic & IC_HC0_COAL_DONE) 310 aic |= HC_IC_COAL; 311 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 312 /* Call per-port interrupt handler. */ 313 for (p = 0; p < ctlr->channels; p++) { 314 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 315 if ((arg.cause != 0) && 316 (function = ctlr->interrupt[p].function)) { 317 arg.arg = ctlr->interrupt[p].argument; 318 function(&arg); 319 } 320 ic >>= 2; 321 } 322} 323 324static struct resource * 325mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 326 u_long start, u_long end, u_long count, u_int flags) 327{ 328 struct mvs_controller *ctlr = device_get_softc(dev); 329 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 330 struct resource *res = NULL; 331 int offset = PORT_BASE(unit & 0x03); 332 long st; 333 334 switch (type) { 335 case SYS_RES_MEMORY: 336 st = rman_get_start(ctlr->r_mem); 337 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 338 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 339 if (res) { 340 bus_space_handle_t bsh; 341 bus_space_tag_t bst; 342 bsh = rman_get_bushandle(ctlr->r_mem); 343 bst = rman_get_bustag(ctlr->r_mem); 344 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 345 rman_set_bushandle(res, bsh); 346 rman_set_bustag(res, bst); 347 } 348 break; 349 case SYS_RES_IRQ: 350 if (*rid == ATA_IRQ_RID) 351 res = ctlr->irq.r_irq; 352 break; 353 } 354 return (res); 355} 356 357static int 358mvs_release_resource(device_t dev, device_t child, int type, int rid, 359 struct resource *r) 360{ 361 362 switch (type) { 363 case SYS_RES_MEMORY: 364 rman_release_resource(r); 365 return (0); 366 case SYS_RES_IRQ: 367 if (rid != ATA_IRQ_RID) 368 return ENOENT; 369 return (0); 370 } 371 return (EINVAL); 372} 373 374static int 375mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 376 int flags, driver_filter_t *filter, driver_intr_t *function, 377 void *argument, void **cookiep) 378{ 379 struct mvs_controller *ctlr = device_get_softc(dev); 380 int unit = (intptr_t)device_get_ivars(child); 381 382 if (filter != NULL) { 383 printf("mvs.c: we cannot use a filter here\n"); 384 return (EINVAL); 385 } 386 ctlr->interrupt[unit].function = function; 387 ctlr->interrupt[unit].argument = argument; 388 return (0); 389} 390 391static int 392mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 393 void *cookie) 394{ 395 struct mvs_controller *ctlr = device_get_softc(dev); 396 int unit = (intptr_t)device_get_ivars(child); 397 398 ctlr->interrupt[unit].function = NULL; 399 ctlr->interrupt[unit].argument = NULL; 400 return (0); 401} 402 403static int 404mvs_print_child(device_t dev, device_t child) 405{ 406 int retval; 407 408 retval = bus_print_child_header(dev, child); 409 retval += printf(" at channel %d", 410 (int)(intptr_t)device_get_ivars(child)); 411 retval += bus_print_child_footer(dev, child); 412 413 return (retval); 414} 415
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