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if_msk.c (187208) if_msk.c (187325)
1/******************************************************************************
2 *
3 * Name : sky2.c
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
8 *

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94
95/*
96 * Device driver for the Marvell Yukon II Ethernet controller.
97 * Due to lack of documentation, this driver is based on the code from
98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
99 */
100
101#include <sys/cdefs.h>
1/******************************************************************************
2 *
3 * Name : sky2.c
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
8 *

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94
95/*
96 * Device driver for the Marvell Yukon II Ethernet controller.
97 * Due to lack of documentation, this driver is based on the code from
98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
99 */
100
101#include <sys/cdefs.h>
102__FBSDID("$FreeBSD: head/sys/dev/msk/if_msk.c 187208 2009-01-14 05:08:52Z yongari $");
102__FBSDID("$FreeBSD: head/sys/dev/msk/if_msk.c 187325 2009-01-16 08:06:55Z yongari $");
103
104#include <sys/param.h>
105#include <sys/systm.h>
106#include <sys/bus.h>
107#include <sys/endian.h>
108#include <sys/mbuf.h>
109#include <sys/malloc.h>
110#include <sys/kernel.h>

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286static int msk_miibus_writereg(device_t, int, int, int);
287static void msk_miibus_statchg(device_t);
288static void msk_link_task(void *, int);
289
290static void msk_setmulti(struct msk_if_softc *);
291static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
292static void msk_setpromisc(struct msk_if_softc *);
293
103
104#include <sys/param.h>
105#include <sys/systm.h>
106#include <sys/bus.h>
107#include <sys/endian.h>
108#include <sys/mbuf.h>
109#include <sys/malloc.h>
110#include <sys/kernel.h>

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286static int msk_miibus_writereg(device_t, int, int, int);
287static void msk_miibus_statchg(device_t);
288static void msk_link_task(void *, int);
289
290static void msk_setmulti(struct msk_if_softc *);
291static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
292static void msk_setpromisc(struct msk_if_softc *);
293
294static void msk_stats_clear(struct msk_if_softc *);
295static void msk_stats_update(struct msk_if_softc *);
296static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS);
297static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS);
298static void msk_sysctl_node(struct msk_if_softc *);
294static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
295static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
296
297static device_method_t mskc_methods[] = {
298 /* Device interface */
299 DEVMETHOD(device_probe, mskc_probe),
300 DEVMETHOD(device_attach, mskc_attach),
301 DEVMETHOD(device_detach, mskc_detach),

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1430 } else {
1431 sc_if->msk_txq = Q_XA2;
1432 sc_if->msk_txsq = Q_XS2;
1433 sc_if->msk_rxq = Q_R2;
1434 }
1435
1436 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1437 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if);
299static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
300static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
301
302static device_method_t mskc_methods[] = {
303 /* Device interface */
304 DEVMETHOD(device_probe, mskc_probe),
305 DEVMETHOD(device_attach, mskc_attach),
306 DEVMETHOD(device_detach, mskc_detach),

--- 1128 unchanged lines hidden (view full) ---

1435 } else {
1436 sc_if->msk_txq = Q_XA2;
1437 sc_if->msk_txsq = Q_XS2;
1438 sc_if->msk_rxq = Q_R2;
1439 }
1440
1441 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1442 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if);
1443 msk_sysctl_node(sc_if);
1438
1439 /* Disable jumbo frame for Yukon FE. */
1440 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE)
1441 sc_if->msk_flags |= MSK_FLAG_NOJUMBO;
1442
1443 if ((error = msk_txrx_dma_alloc(sc_if) != 0))
1444 goto fail;
1445 msk_rx_dma_jalloc(sc_if);

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3539 * datasheet for Yukon II I wouldn't have encountered this. :-(
3540 */
3541 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL;
3542 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
3543
3544 /* Dummy read the Interrupt Source Register. */
3545 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3546
1444
1445 /* Disable jumbo frame for Yukon FE. */
1446 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE)
1447 sc_if->msk_flags |= MSK_FLAG_NOJUMBO;
1448
1449 if ((error = msk_txrx_dma_alloc(sc_if) != 0))
1450 goto fail;
1451 msk_rx_dma_jalloc(sc_if);

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3545 * datasheet for Yukon II I wouldn't have encountered this. :-(
3546 */
3547 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL;
3548 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
3549
3550 /* Dummy read the Interrupt Source Register. */
3551 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3552
3547 /* Set MIB Clear Counter Mode. */
3548 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
3549 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
3550 /* Read all MIB Counters with Clear Mode set. */
3551 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
3552 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i);
3553 /* Clear MIB Clear Counter Mode. */
3554 gmac &= ~GM_PAR_MIB_CLR;
3555 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
3553 /* Clear MIB stats. */
3554 msk_stats_clear(sc_if);
3556
3557 /* Disable FCS. */
3558 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3559
3560 /* Setup Transmit Control Register. */
3561 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3562
3563 /* Setup Transmit Flow Control Register. */

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3833 CSR_READ_4(sc, B0_IMSK);
3834
3835 /* Disable Tx/Rx MAC. */
3836 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3837 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
3838 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
3839 /* Read again to ensure writing. */
3840 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3555
3556 /* Disable FCS. */
3557 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3558
3559 /* Setup Transmit Control Register. */
3560 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3561
3562 /* Setup Transmit Flow Control Register. */

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3832 CSR_READ_4(sc, B0_IMSK);
3833
3834 /* Disable Tx/Rx MAC. */
3835 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3836 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
3837 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
3838 /* Read again to ensure writing. */
3839 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3840 /* Update stats and clear counters. */
3841 msk_stats_update(sc_if);
3841
3842 /* Stop Tx BMU. */
3843 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
3844 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
3845 for (i = 0; i < MSK_TIMEOUT; i++) {
3846 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
3847 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
3848 BMU_STOP);

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3948
3949 /*
3950 * Mark the interface down.
3951 */
3952 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3953 sc_if->msk_link = 0;
3954}
3955
3842
3843 /* Stop Tx BMU. */
3844 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
3845 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
3846 for (i = 0; i < MSK_TIMEOUT; i++) {
3847 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
3848 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
3849 BMU_STOP);

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3949
3950 /*
3951 * Mark the interface down.
3952 */
3953 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3954 sc_if->msk_link = 0;
3955}
3956
3957/*
3958 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower
3959 * counter clears high 16 bits of the counter such that accessing
3960 * lower 16 bits should be the last operation.
3961 */
3962#define MSK_READ_MIB32(x, y) \
3963 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \
3964 (uint32_t)GMAC_READ_2(sc, x, y)
3965#define MSK_READ_MIB64(x, y) \
3966 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \
3967 (uint64_t)MSK_READ_MIB32(x, y)
3968
3969static void
3970msk_stats_clear(struct msk_if_softc *sc_if)
3971{
3972 struct msk_softc *sc;
3973 uint32_t reg;
3974 uint16_t gmac;
3975 int i;
3976
3977 MSK_IF_LOCK_ASSERT(sc_if);
3978
3979 sc = sc_if->msk_softc;
3980 /* Set MIB Clear Counter Mode. */
3981 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
3982 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
3983 /* Read all MIB Counters with Clear Mode set. */
3984 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i++)
3985 reg = MSK_READ_MIB32(sc_if->msk_port, i);
3986 /* Clear MIB Clear Counter Mode. */
3987 gmac &= ~GM_PAR_MIB_CLR;
3988 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
3989}
3990
3991static void
3992msk_stats_update(struct msk_if_softc *sc_if)
3993{
3994 struct msk_softc *sc;
3995 struct ifnet *ifp;
3996 struct msk_hw_stats *stats;
3997 uint16_t gmac;
3998 uint32_t reg;
3999
4000 MSK_IF_LOCK_ASSERT(sc_if);
4001
4002 ifp = sc_if->msk_ifp;
4003 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
4004 return;
4005 sc = sc_if->msk_softc;
4006 stats = &sc_if->msk_stats;
4007 /* Set MIB Clear Counter Mode. */
4008 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4009 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4010
4011 /* Rx stats. */
4012 stats->rx_ucast_frames +=
4013 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK);
4014 stats->rx_bcast_frames +=
4015 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK);
4016 stats->rx_pause_frames +=
4017 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE);
4018 stats->rx_mcast_frames +=
4019 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK);
4020 stats->rx_crc_errs +=
4021 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR);
4022 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1);
4023 stats->rx_good_octets +=
4024 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO);
4025 stats->rx_bad_octets +=
4026 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO);
4027 stats->rx_runts +=
4028 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT);
4029 stats->rx_runt_errs +=
4030 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG);
4031 stats->rx_pkts_64 +=
4032 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B);
4033 stats->rx_pkts_65_127 +=
4034 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B);
4035 stats->rx_pkts_128_255 +=
4036 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B);
4037 stats->rx_pkts_256_511 +=
4038 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B);
4039 stats->rx_pkts_512_1023 +=
4040 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B);
4041 stats->rx_pkts_1024_1518 +=
4042 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B);
4043 stats->rx_pkts_1519_max +=
4044 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ);
4045 stats->rx_pkts_too_long +=
4046 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR);
4047 stats->rx_pkts_jabbers +=
4048 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT);
4049 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2);
4050 stats->rx_fifo_oflows +=
4051 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV);
4052 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3);
4053
4054 /* Tx stats. */
4055 stats->tx_ucast_frames +=
4056 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK);
4057 stats->tx_bcast_frames +=
4058 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK);
4059 stats->tx_pause_frames +=
4060 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE);
4061 stats->tx_mcast_frames +=
4062 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK);
4063 stats->tx_octets +=
4064 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO);
4065 stats->tx_pkts_64 +=
4066 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B);
4067 stats->tx_pkts_65_127 +=
4068 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B);
4069 stats->tx_pkts_128_255 +=
4070 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B);
4071 stats->tx_pkts_256_511 +=
4072 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B);
4073 stats->tx_pkts_512_1023 +=
4074 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B);
4075 stats->tx_pkts_1024_1518 +=
4076 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B);
4077 stats->tx_pkts_1519_max +=
4078 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ);
4079 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1);
4080 stats->tx_colls +=
4081 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL);
4082 stats->tx_late_colls +=
4083 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL);
4084 stats->tx_excess_colls +=
4085 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL);
4086 stats->tx_multi_colls +=
4087 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL);
4088 stats->tx_single_colls +=
4089 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL);
4090 stats->tx_underflows +=
4091 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR);
4092 /* Clear MIB Clear Counter Mode. */
4093 gmac &= ~GM_PAR_MIB_CLR;
4094 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4095}
4096
3956static int
4097static int
4098msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)
4099{
4100 struct msk_softc *sc;
4101 struct msk_if_softc *sc_if;
4102 uint32_t result, *stat;
4103 int off;
4104
4105 sc_if = (struct msk_if_softc *)arg1;
4106 sc = sc_if->msk_softc;
4107 off = arg2;
4108 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off);
4109
4110 MSK_IF_LOCK(sc_if);
4111 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4112 result += *stat;
4113 MSK_IF_UNLOCK(sc_if);
4114
4115 return (sysctl_handle_int(oidp, &result, 0, req));
4116}
4117
4118static int
4119msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)
4120{
4121 struct msk_softc *sc;
4122 struct msk_if_softc *sc_if;
4123 uint64_t result, *stat;
4124 int off;
4125
4126 sc_if = (struct msk_if_softc *)arg1;
4127 sc = sc_if->msk_softc;
4128 off = arg2;
4129 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off);
4130
4131 MSK_IF_LOCK(sc_if);
4132 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4133 result += *stat;
4134 MSK_IF_UNLOCK(sc_if);
4135
4136 return (sysctl_handle_quad(oidp, &result, 0, req));
4137}
4138
4139#undef MSK_READ_MIB32
4140#undef MSK_READ_MIB64
4141
4142#define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \
4143 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \
4144 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \
4145 "IU", d)
4146#define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \
4147 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \
4148 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \
4149 "Q", d)
4150
4151static void
4152msk_sysctl_node(struct msk_if_softc *sc_if)
4153{
4154 struct sysctl_ctx_list *ctx;
4155 struct sysctl_oid_list *child, *schild;
4156 struct sysctl_oid *tree;
4157
4158 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev);
4159 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev));
4160
4161 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
4162 NULL, "MSK Statistics");
4163 schild = child = SYSCTL_CHILDREN(tree);
4164 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
4165 NULL, "MSK RX Statistics");
4166 child = SYSCTL_CHILDREN(tree);
4167 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4168 child, rx_ucast_frames, "Good unicast frames");
4169 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4170 child, rx_bcast_frames, "Good broadcast frames");
4171 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4172 child, rx_pause_frames, "Pause frames");
4173 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4174 child, rx_mcast_frames, "Multicast frames");
4175 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs",
4176 child, rx_crc_errs, "CRC errors");
4177 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets",
4178 child, rx_good_octets, "Good octets");
4179 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets",
4180 child, rx_bad_octets, "Bad octets");
4181 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4182 child, rx_pkts_64, "64 bytes frames");
4183 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4184 child, rx_pkts_65_127, "65 to 127 bytes frames");
4185 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4186 child, rx_pkts_128_255, "128 to 255 bytes frames");
4187 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4188 child, rx_pkts_256_511, "256 to 511 bytes frames");
4189 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4190 child, rx_pkts_512_1023, "512 to 1023 bytes frames");
4191 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4192 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames");
4193 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4194 child, rx_pkts_1519_max, "1519 to max frames");
4195 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long",
4196 child, rx_pkts_too_long, "frames too long");
4197 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
4198 child, rx_pkts_jabbers, "Jabber errors");
4199 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
4200 child, rx_fifo_oflows, "FIFO overflows");
4201
4202 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
4203 NULL, "MSK TX Statistics");
4204 child = SYSCTL_CHILDREN(tree);
4205 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4206 child, tx_ucast_frames, "Unicast frames");
4207 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4208 child, tx_bcast_frames, "Broadcast frames");
4209 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4210 child, tx_pause_frames, "Pause frames");
4211 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4212 child, tx_mcast_frames, "Multicast frames");
4213 MSK_SYSCTL_STAT64(sc_if, ctx, "octets",
4214 child, tx_octets, "Octets");
4215 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4216 child, tx_pkts_64, "64 bytes frames");
4217 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4218 child, tx_pkts_65_127, "65 to 127 bytes frames");
4219 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4220 child, tx_pkts_128_255, "128 to 255 bytes frames");
4221 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4222 child, tx_pkts_256_511, "256 to 511 bytes frames");
4223 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4224 child, tx_pkts_512_1023, "512 to 1023 bytes frames");
4225 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4226 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames");
4227 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4228 child, tx_pkts_1519_max, "1519 to max frames");
4229 MSK_SYSCTL_STAT32(sc_if, ctx, "colls",
4230 child, tx_colls, "Collisions");
4231 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls",
4232 child, tx_late_colls, "Late collisions");
4233 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls",
4234 child, tx_excess_colls, "Excessive collisions");
4235 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls",
4236 child, tx_multi_colls, "Multiple collisions");
4237 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls",
4238 child, tx_single_colls, "Single collisions");
4239 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows",
4240 child, tx_underflows, "FIFO underflows");
4241}
4242
4243#undef MSK_SYSCTL_STAT32
4244#undef MSK_SYSCTL_STAT64
4245
4246static int
3957sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3958{
3959 int error, value;
3960
3961 if (!arg1)
3962 return (EINVAL);
3963 value = *(int *)arg1;
3964 error = sysctl_handle_int(oidp, &value, 0, req);

--- 16 unchanged lines hidden --- 		4247sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4248{
4249 int error, value;
4250
4251 if (!arg1)
4252 return (EINVAL);
4253 value = *(int *)arg1;
4254 error = sysctl_handle_int(oidp, &value, 0, req);

--- 16 unchanged lines hidden ---