1/******************************************************************************
2 *
3 * Name : sky2.c
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
8 *
9 *****************************************************************************/
10
11/******************************************************************************
12 *
13 * LICENSE:
14 * Copyright (C) Marvell International Ltd. and/or its affiliates
15 *
16 * The computer program files contained in this folder ("Files")
17 * are provided to you under the BSD-type license terms provided
18 * below, and any use of such Files and any derivative works
19 * thereof created by you shall be governed by the following terms
20 * and conditions:
21 *
22 * - Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * - Redistributions in binary form must reproduce the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer in the documentation and/or other materials provided
27 * with the distribution.
28 * - Neither the name of Marvell nor the names of its contributors
29 * may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 * /LICENSE
45 *
46 *****************************************************************************/
47
48/*-
49 * Copyright (c) 1997, 1998, 1999, 2000
50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
51 *
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
54 * are met:
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
60 * 3. All advertising materials mentioning features or use of this software
61 * must display the following acknowledgement:
62 * This product includes software developed by Bill Paul.
63 * 4. Neither the name of the author nor the names of any co-contributors
64 * may be used to endorse or promote products derived from this software
65 * without specific prior written permission.
66 *
67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
77 * THE POSSIBILITY OF SUCH DAMAGE.
78 */
79/*-
80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
81 *
82 * Permission to use, copy, modify, and distribute this software for any
83 * purpose with or without fee is hereby granted, provided that the above
84 * copyright notice and this permission notice appear in all copies.
85 *
86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
93 */
94
95/*
96 * Device driver for the Marvell Yukon II Ethernet controller.
97 * Due to lack of documentation, this driver is based on the code from
98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
99 */
100
101#include <sys/cdefs.h>
| 1/******************************************************************************
2 *
3 * Name : sky2.c
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
8 *
9 *****************************************************************************/
10
11/******************************************************************************
12 *
13 * LICENSE:
14 * Copyright (C) Marvell International Ltd. and/or its affiliates
15 *
16 * The computer program files contained in this folder ("Files")
17 * are provided to you under the BSD-type license terms provided
18 * below, and any use of such Files and any derivative works
19 * thereof created by you shall be governed by the following terms
20 * and conditions:
21 *
22 * - Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * - Redistributions in binary form must reproduce the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer in the documentation and/or other materials provided
27 * with the distribution.
28 * - Neither the name of Marvell nor the names of its contributors
29 * may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 * /LICENSE
45 *
46 *****************************************************************************/
47
48/*-
49 * Copyright (c) 1997, 1998, 1999, 2000
50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
51 *
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
54 * are met:
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
60 * 3. All advertising materials mentioning features or use of this software
61 * must display the following acknowledgement:
62 * This product includes software developed by Bill Paul.
63 * 4. Neither the name of the author nor the names of any co-contributors
64 * may be used to endorse or promote products derived from this software
65 * without specific prior written permission.
66 *
67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
77 * THE POSSIBILITY OF SUCH DAMAGE.
78 */
79/*-
80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
81 *
82 * Permission to use, copy, modify, and distribute this software for any
83 * purpose with or without fee is hereby granted, provided that the above
84 * copyright notice and this permission notice appear in all copies.
85 *
86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
93 */
94
95/*
96 * Device driver for the Marvell Yukon II Ethernet controller.
97 * Due to lack of documentation, this driver is based on the code from
98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
99 */
100
101#include <sys/cdefs.h>
|
102__FBSDID("$FreeBSD: head/sys/dev/msk/if_msk.c 171509 2007-07-20 00:25:20Z yongari $");
| 102__FBSDID("$FreeBSD: head/sys/dev/msk/if_msk.c 173769 2007-11-20 06:20:02Z yongari $");
|
103
104#include <sys/param.h>
105#include <sys/systm.h>
106#include <sys/bus.h>
107#include <sys/endian.h>
108#include <sys/mbuf.h>
109#include <sys/malloc.h>
110#include <sys/kernel.h>
111#include <sys/module.h>
112#include <sys/socket.h>
113#include <sys/sockio.h>
114#include <sys/queue.h>
115#include <sys/sysctl.h>
116#include <sys/taskqueue.h>
117
118#include <net/bpf.h>
119#include <net/ethernet.h>
120#include <net/if.h>
121#include <net/if_arp.h>
122#include <net/if_dl.h>
123#include <net/if_media.h>
124#include <net/if_types.h>
125#include <net/if_vlan_var.h>
126
127#include <netinet/in.h>
128#include <netinet/in_systm.h>
129#include <netinet/ip.h>
130#include <netinet/tcp.h>
131#include <netinet/udp.h>
132
133#include <machine/bus.h>
134#include <machine/in_cksum.h>
135#include <machine/resource.h>
136#include <sys/rman.h>
137
138#include <dev/mii/mii.h>
139#include <dev/mii/miivar.h>
140#include <dev/mii/brgphyreg.h>
141
142#include <dev/pci/pcireg.h>
143#include <dev/pci/pcivar.h>
144
145#include <dev/msk/if_mskreg.h>
146
147MODULE_DEPEND(msk, pci, 1, 1, 1);
148MODULE_DEPEND(msk, ether, 1, 1, 1);
149MODULE_DEPEND(msk, miibus, 1, 1, 1);
150
151/* "device miibus" required. See GENERIC if you get errors here. */
152#include "miibus_if.h"
153
154/* Tunables. */
155static int msi_disable = 0;
156TUNABLE_INT("hw.msk.msi_disable", &msi_disable);
157static int legacy_intr = 0;
158TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr);
159
160#define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
161
162/*
163 * Devices supported by this driver.
164 */
165static struct msk_product {
166 uint16_t msk_vendorid;
167 uint16_t msk_deviceid;
168 const char *msk_name;
169} msk_products[] = {
170 { VENDORID_SK, DEVICEID_SK_YUKON2,
171 "SK-9Sxx Gigabit Ethernet" },
172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
173 "SK-9Exx Gigabit Ethernet"},
174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
175 "Marvell Yukon 88E8021CU Gigabit Ethernet" },
176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X,
177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
179 "Marvell Yukon 88E8022CU Gigabit Ethernet" },
180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X,
181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
183 "Marvell Yukon 88E8061CU Gigabit Ethernet" },
184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X,
185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
187 "Marvell Yukon 88E8062CU Gigabit Ethernet" },
188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X,
189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
190 { VENDORID_MARVELL, DEVICEID_MRVL_8035,
191 "Marvell Yukon 88E8035 Gigabit Ethernet" },
192 { VENDORID_MARVELL, DEVICEID_MRVL_8036,
193 "Marvell Yukon 88E8036 Gigabit Ethernet" },
194 { VENDORID_MARVELL, DEVICEID_MRVL_8038,
195 "Marvell Yukon 88E8038 Gigabit Ethernet" },
196 { VENDORID_MARVELL, DEVICEID_MRVL_4361,
197 "Marvell Yukon 88E8050 Gigabit Ethernet" },
198 { VENDORID_MARVELL, DEVICEID_MRVL_4360,
199 "Marvell Yukon 88E8052 Gigabit Ethernet" },
200 { VENDORID_MARVELL, DEVICEID_MRVL_4362,
201 "Marvell Yukon 88E8053 Gigabit Ethernet" },
202 { VENDORID_MARVELL, DEVICEID_MRVL_4363,
203 "Marvell Yukon 88E8055 Gigabit Ethernet" },
204 { VENDORID_MARVELL, DEVICEID_MRVL_4364,
205 "Marvell Yukon 88E8056 Gigabit Ethernet" },
206 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
207 "D-Link 550SX Gigabit Ethernet" },
208 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
209 "D-Link 560T Gigabit Ethernet" }
210};
211
212static const char *model_name[] = {
213 "Yukon XL",
214 "Yukon EC Ultra",
215 "Yukon Unknown",
216 "Yukon EC",
217 "Yukon FE"
218};
219
220static int mskc_probe(device_t);
221static int mskc_attach(device_t);
222static int mskc_detach(device_t);
223static void mskc_shutdown(device_t);
224static int mskc_setup_rambuffer(struct msk_softc *);
225static int mskc_suspend(device_t);
226static int mskc_resume(device_t);
227static void mskc_reset(struct msk_softc *);
228
229static int msk_probe(device_t);
230static int msk_attach(device_t);
231static int msk_detach(device_t);
232
233static void msk_tick(void *);
234static void msk_legacy_intr(void *);
235static int msk_intr(void *);
236static void msk_int_task(void *, int);
237static void msk_intr_phy(struct msk_if_softc *);
238static void msk_intr_gmac(struct msk_if_softc *);
239static __inline void msk_rxput(struct msk_if_softc *);
240static int msk_handle_events(struct msk_softc *);
241static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
242static void msk_intr_hwerr(struct msk_softc *);
243static void msk_rxeof(struct msk_if_softc *, uint32_t, int);
244static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int);
245static void msk_txeof(struct msk_if_softc *, int);
246static struct mbuf *msk_defrag(struct mbuf *, int, int);
247static int msk_encap(struct msk_if_softc *, struct mbuf **);
248static void msk_tx_task(void *, int);
249static void msk_start(struct ifnet *);
250static int msk_ioctl(struct ifnet *, u_long, caddr_t);
251static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
252static void msk_set_rambuffer(struct msk_if_softc *);
253static void msk_init(void *);
254static void msk_init_locked(struct msk_if_softc *);
255static void msk_stop(struct msk_if_softc *);
256static void msk_watchdog(struct msk_if_softc *);
257static int msk_mediachange(struct ifnet *);
258static void msk_mediastatus(struct ifnet *, struct ifmediareq *);
259static void msk_phy_power(struct msk_softc *, int);
260static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
261static int msk_status_dma_alloc(struct msk_softc *);
262static void msk_status_dma_free(struct msk_softc *);
263static int msk_txrx_dma_alloc(struct msk_if_softc *);
264static void msk_txrx_dma_free(struct msk_if_softc *);
265static void *msk_jalloc(struct msk_if_softc *);
266static void msk_jfree(void *, void *);
267static int msk_init_rx_ring(struct msk_if_softc *);
268static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
269static void msk_init_tx_ring(struct msk_if_softc *);
270static __inline void msk_discard_rxbuf(struct msk_if_softc *, int);
271static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
272static int msk_newbuf(struct msk_if_softc *, int);
273static int msk_jumbo_newbuf(struct msk_if_softc *, int);
274
275static int msk_phy_readreg(struct msk_if_softc *, int, int);
276static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
277static int msk_miibus_readreg(device_t, int, int);
278static int msk_miibus_writereg(device_t, int, int, int);
279static void msk_miibus_statchg(device_t);
280static void msk_link_task(void *, int);
281
282static void msk_setmulti(struct msk_if_softc *);
283static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
284static void msk_setpromisc(struct msk_if_softc *);
285
286static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
287static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
288
289static device_method_t mskc_methods[] = {
290 /* Device interface */
291 DEVMETHOD(device_probe, mskc_probe),
292 DEVMETHOD(device_attach, mskc_attach),
293 DEVMETHOD(device_detach, mskc_detach),
294 DEVMETHOD(device_suspend, mskc_suspend),
295 DEVMETHOD(device_resume, mskc_resume),
296 DEVMETHOD(device_shutdown, mskc_shutdown),
297
298 /* bus interface */
299 DEVMETHOD(bus_print_child, bus_generic_print_child),
300 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
301
302 { NULL, NULL }
303};
304
305static driver_t mskc_driver = {
306 "mskc",
307 mskc_methods,
308 sizeof(struct msk_softc)
309};
310
311static devclass_t mskc_devclass;
312
313static device_method_t msk_methods[] = {
314 /* Device interface */
315 DEVMETHOD(device_probe, msk_probe),
316 DEVMETHOD(device_attach, msk_attach),
317 DEVMETHOD(device_detach, msk_detach),
318 DEVMETHOD(device_shutdown, bus_generic_shutdown),
319
320 /* bus interface */
321 DEVMETHOD(bus_print_child, bus_generic_print_child),
322 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
323
324 /* MII interface */
325 DEVMETHOD(miibus_readreg, msk_miibus_readreg),
326 DEVMETHOD(miibus_writereg, msk_miibus_writereg),
327 DEVMETHOD(miibus_statchg, msk_miibus_statchg),
328
329 { NULL, NULL }
330};
331
332static driver_t msk_driver = {
333 "msk",
334 msk_methods,
335 sizeof(struct msk_if_softc)
336};
337
338static devclass_t msk_devclass;
339
340DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0);
341DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0);
342DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0);
343
344static struct resource_spec msk_res_spec_io[] = {
345 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
346 { -1, 0, 0 }
347};
348
349static struct resource_spec msk_res_spec_mem[] = {
350 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
351 { -1, 0, 0 }
352};
353
354static struct resource_spec msk_irq_spec_legacy[] = {
355 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
356 { -1, 0, 0 }
357};
358
359static struct resource_spec msk_irq_spec_msi[] = {
360 { SYS_RES_IRQ, 1, RF_ACTIVE },
361 { SYS_RES_IRQ, 2, RF_ACTIVE },
362 { -1, 0, 0 }
363};
364
365static int
366msk_miibus_readreg(device_t dev, int phy, int reg)
367{
368 struct msk_if_softc *sc_if;
369
370 sc_if = device_get_softc(dev);
371
372 return (msk_phy_readreg(sc_if, phy, reg));
373}
374
375static int
376msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
377{
378 struct msk_softc *sc;
379 int i, val;
380
381 sc = sc_if->msk_softc;
382
383 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
384 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
385
386 for (i = 0; i < MSK_TIMEOUT; i++) {
387 DELAY(1);
388 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
389 if ((val & GM_SMI_CT_RD_VAL) != 0) {
390 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
391 break;
392 }
393 }
394
395 if (i == MSK_TIMEOUT) {
396 if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
397 val = 0;
398 }
399
400 return (val);
401}
402
403static int
404msk_miibus_writereg(device_t dev, int phy, int reg, int val)
405{
406 struct msk_if_softc *sc_if;
407
408 sc_if = device_get_softc(dev);
409
410 return (msk_phy_writereg(sc_if, phy, reg, val));
411}
412
413static int
414msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
415{
416 struct msk_softc *sc;
417 int i;
418
419 sc = sc_if->msk_softc;
420
421 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
422 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
423 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
424 for (i = 0; i < MSK_TIMEOUT; i++) {
425 DELAY(1);
426 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
427 GM_SMI_CT_BUSY) == 0)
428 break;
429 }
430 if (i == MSK_TIMEOUT)
431 if_printf(sc_if->msk_ifp, "phy write timeout\n");
432
433 return (0);
434}
435
436static void
437msk_miibus_statchg(device_t dev)
438{
439 struct msk_if_softc *sc_if;
440
441 sc_if = device_get_softc(dev);
442 taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task);
443}
444
445static void
446msk_link_task(void *arg, int pending)
447{
448 struct msk_softc *sc;
449 struct msk_if_softc *sc_if;
450 struct mii_data *mii;
451 struct ifnet *ifp;
452 uint32_t gmac;
453
454 sc_if = (struct msk_if_softc *)arg;
455 sc = sc_if->msk_softc;
456
457 MSK_IF_LOCK(sc_if);
458
459 mii = device_get_softc(sc_if->msk_miibus);
460 ifp = sc_if->msk_ifp;
461 if (mii == NULL || ifp == NULL) {
462 MSK_IF_UNLOCK(sc_if);
463 return;
464 }
465
466 if (mii->mii_media_status & IFM_ACTIVE) {
467 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
468 sc_if->msk_link = 1;
469 } else
470 sc_if->msk_link = 0;
471
472 if (sc_if->msk_link != 0) {
473 /* Enable Tx FIFO Underrun. */
474 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
475 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
476 /*
477 * Because mii(4) notify msk(4) that it detected link status
478 * change, there is no need to enable automatic
479 * speed/flow-control/duplex updates.
480 */
481 gmac = GM_GPCR_AU_ALL_DIS;
482 switch (IFM_SUBTYPE(mii->mii_media_active)) {
483 case IFM_1000_SX:
484 case IFM_1000_T:
485 gmac |= GM_GPCR_SPEED_1000;
486 break;
487 case IFM_100_TX:
488 gmac |= GM_GPCR_SPEED_100;
489 break;
490 case IFM_10_T:
491 break;
492 }
493
494 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
495 gmac |= GM_GPCR_DUP_FULL;
496 /* Disable Rx flow control. */
497 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0)
498 gmac |= GM_GPCR_FC_RX_DIS;
499 /* Disable Tx flow control. */
500 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0)
501 gmac |= GM_GPCR_FC_TX_DIS;
502 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
503 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
504 /* Read again to ensure writing. */
505 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
506
507 gmac = GMC_PAUSE_ON;
508 if (((mii->mii_media_active & IFM_GMASK) &
509 (IFM_FLAG0 | IFM_FLAG1)) == 0)
510 gmac = GMC_PAUSE_OFF;
511 /* Diable pause for 10/100 Mbps in half-duplex mode. */
512 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) &&
513 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX ||
514 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T))
515 gmac = GMC_PAUSE_OFF;
516 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
517
518 /* Enable PHY interrupt for FIFO underrun/overflow. */
519 if (sc->msk_marvell_phy)
520 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
521 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
522 } else {
523 /*
524 * Link state changed to down.
525 * Disable PHY interrupts.
526 */
527 if (sc->msk_marvell_phy)
528 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
529 PHY_MARV_INT_MASK, 0);
530 /* Disable Rx/Tx MAC. */
531 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
532 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
533 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
534 /* Read again to ensure writing. */
535 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
536 }
537
538 MSK_IF_UNLOCK(sc_if);
539}
540
541static void
542msk_setmulti(struct msk_if_softc *sc_if)
543{
544 struct msk_softc *sc;
545 struct ifnet *ifp;
546 struct ifmultiaddr *ifma;
547 uint32_t mchash[2];
548 uint32_t crc;
549 uint16_t mode;
550
551 sc = sc_if->msk_softc;
552
553 MSK_IF_LOCK_ASSERT(sc_if);
554
555 ifp = sc_if->msk_ifp;
556
557 bzero(mchash, sizeof(mchash));
558 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
559 mode |= GM_RXCR_UCF_ENA;
560 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
561 if ((ifp->if_flags & IFF_PROMISC) != 0)
562 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
563 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
564 mchash[0] = 0xffff;
565 mchash[1] = 0xffff;
566 }
567 } else {
568 IF_ADDR_LOCK(ifp);
569 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
570 if (ifma->ifma_addr->sa_family != AF_LINK)
571 continue;
572 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
573 ifma->ifma_addr), ETHER_ADDR_LEN);
574 /* Just want the 6 least significant bits. */
575 crc &= 0x3f;
576 /* Set the corresponding bit in the hash table. */
577 mchash[crc >> 5] |= 1 << (crc & 0x1f);
578 }
579 IF_ADDR_UNLOCK(ifp);
580 mode |= GM_RXCR_MCF_ENA;
581 }
582
583 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
584 mchash[0] & 0xffff);
585 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
586 (mchash[0] >> 16) & 0xffff);
587 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
588 mchash[1] & 0xffff);
589 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
590 (mchash[1] >> 16) & 0xffff);
591 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
592}
593
594static void
595msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp)
596{
597 struct msk_softc *sc;
598
599 sc = sc_if->msk_softc;
600 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
601 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
602 RX_VLAN_STRIP_ON);
603 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
604 TX_VLAN_TAG_ON);
605 } else {
606 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
607 RX_VLAN_STRIP_OFF);
608 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
609 TX_VLAN_TAG_OFF);
610 }
611}
612
613static void
614msk_setpromisc(struct msk_if_softc *sc_if)
615{
616 struct msk_softc *sc;
617 struct ifnet *ifp;
618 uint16_t mode;
619
620 MSK_IF_LOCK_ASSERT(sc_if);
621
622 sc = sc_if->msk_softc;
623 ifp = sc_if->msk_ifp;
624
625 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
626 if (ifp->if_flags & IFF_PROMISC)
627 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
628 else
629 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
630 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
631}
632
633static int
634msk_init_rx_ring(struct msk_if_softc *sc_if)
635{
636 struct msk_ring_data *rd;
637 struct msk_rxdesc *rxd;
638 int i, prod;
639
640 MSK_IF_LOCK_ASSERT(sc_if);
641
642 sc_if->msk_cdata.msk_rx_cons = 0;
643 sc_if->msk_cdata.msk_rx_prod = 0;
644 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
645
646 rd = &sc_if->msk_rdata;
647 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
648 prod = sc_if->msk_cdata.msk_rx_prod;
649 for (i = 0; i < MSK_RX_RING_CNT; i++) {
650 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
651 rxd->rx_m = NULL;
652 rxd->rx_le = &rd->msk_rx_ring[prod];
653 if (msk_newbuf(sc_if, prod) != 0)
654 return (ENOBUFS);
655 MSK_INC(prod, MSK_RX_RING_CNT);
656 }
657
658 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
659 sc_if->msk_cdata.msk_rx_ring_map,
660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
661
662 /* Update prefetch unit. */
663 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1;
664 CSR_WRITE_2(sc_if->msk_softc,
665 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
666 sc_if->msk_cdata.msk_rx_prod);
667
668 return (0);
669}
670
671static int
672msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
673{
674 struct msk_ring_data *rd;
675 struct msk_rxdesc *rxd;
676 int i, prod;
677
678 MSK_IF_LOCK_ASSERT(sc_if);
679
680 sc_if->msk_cdata.msk_rx_cons = 0;
681 sc_if->msk_cdata.msk_rx_prod = 0;
682 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
683
684 rd = &sc_if->msk_rdata;
685 bzero(rd->msk_jumbo_rx_ring,
686 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
687 prod = sc_if->msk_cdata.msk_rx_prod;
688 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
689 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
690 rxd->rx_m = NULL;
691 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
692 if (msk_jumbo_newbuf(sc_if, prod) != 0)
693 return (ENOBUFS);
694 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
695 }
696
697 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
698 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
699 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
700
701 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1;
702 CSR_WRITE_2(sc_if->msk_softc,
703 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
704 sc_if->msk_cdata.msk_rx_prod);
705
706 return (0);
707}
708
709static void
710msk_init_tx_ring(struct msk_if_softc *sc_if)
711{
712 struct msk_ring_data *rd;
713 struct msk_txdesc *txd;
714 int i;
715
716 sc_if->msk_cdata.msk_tso_mtu = 0;
717 sc_if->msk_cdata.msk_tx_prod = 0;
718 sc_if->msk_cdata.msk_tx_cons = 0;
719 sc_if->msk_cdata.msk_tx_cnt = 0;
720
721 rd = &sc_if->msk_rdata;
722 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
723 for (i = 0; i < MSK_TX_RING_CNT; i++) {
724 txd = &sc_if->msk_cdata.msk_txdesc[i];
725 txd->tx_m = NULL;
726 txd->tx_le = &rd->msk_tx_ring[i];
727 }
728
729 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
730 sc_if->msk_cdata.msk_tx_ring_map,
731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
732}
733
734static __inline void
735msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
736{
737 struct msk_rx_desc *rx_le;
738 struct msk_rxdesc *rxd;
739 struct mbuf *m;
740
741 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
742 m = rxd->rx_m;
743 rx_le = rxd->rx_le;
744 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
745}
746
747static __inline void
748msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx)
749{
750 struct msk_rx_desc *rx_le;
751 struct msk_rxdesc *rxd;
752 struct mbuf *m;
753
754 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
755 m = rxd->rx_m;
756 rx_le = rxd->rx_le;
757 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
758}
759
760static int
761msk_newbuf(struct msk_if_softc *sc_if, int idx)
762{
763 struct msk_rx_desc *rx_le;
764 struct msk_rxdesc *rxd;
765 struct mbuf *m;
766 bus_dma_segment_t segs[1];
767 bus_dmamap_t map;
768 int nsegs;
769
770 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
771 if (m == NULL)
772 return (ENOBUFS);
773
774 m->m_len = m->m_pkthdr.len = MCLBYTES;
775 m_adj(m, ETHER_ALIGN);
776
777 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
778 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
779 BUS_DMA_NOWAIT) != 0) {
780 m_freem(m);
781 return (ENOBUFS);
782 }
783 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
784
785 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
786 if (rxd->rx_m != NULL) {
787 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
788 BUS_DMASYNC_POSTREAD);
789 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
790 }
791 map = rxd->rx_dmamap;
792 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
793 sc_if->msk_cdata.msk_rx_sparemap = map;
794 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
795 BUS_DMASYNC_PREREAD);
796 rxd->rx_m = m;
797 rx_le = rxd->rx_le;
798 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
799 rx_le->msk_control =
800 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
801
802 return (0);
803}
804
805static int
806msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
807{
808 struct msk_rx_desc *rx_le;
809 struct msk_rxdesc *rxd;
810 struct mbuf *m;
811 bus_dma_segment_t segs[1];
812 bus_dmamap_t map;
813 int nsegs;
814 void *buf;
815
816 MGETHDR(m, M_DONTWAIT, MT_DATA);
817 if (m == NULL)
818 return (ENOBUFS);
819 buf = msk_jalloc(sc_if);
820 if (buf == NULL) {
821 m_freem(m);
822 return (ENOBUFS);
823 }
824 /* Attach the buffer to the mbuf. */
825 MEXTADD(m, buf, MSK_JLEN, msk_jfree, (struct msk_if_softc *)sc_if, 0,
826 EXT_NET_DRV);
827 if ((m->m_flags & M_EXT) == 0) {
828 m_freem(m);
829 return (ENOBUFS);
830 }
831 m->m_pkthdr.len = m->m_len = MSK_JLEN;
832 m_adj(m, ETHER_ALIGN);
833
834 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
835 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
836 BUS_DMA_NOWAIT) != 0) {
837 m_freem(m);
838 return (ENOBUFS);
839 }
840 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
841
842 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
843 if (rxd->rx_m != NULL) {
844 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
845 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
846 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
847 rxd->rx_dmamap);
848 }
849 map = rxd->rx_dmamap;
850 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
851 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
852 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
853 BUS_DMASYNC_PREREAD);
854 rxd->rx_m = m;
855 rx_le = rxd->rx_le;
856 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
857 rx_le->msk_control =
858 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
859
860 return (0);
861}
862
863/*
864 * Set media options.
865 */
866static int
867msk_mediachange(struct ifnet *ifp)
868{
869 struct msk_if_softc *sc_if;
870 struct mii_data *mii;
871
872 sc_if = ifp->if_softc;
873
874 MSK_IF_LOCK(sc_if);
875 mii = device_get_softc(sc_if->msk_miibus);
876 mii_mediachg(mii);
877 MSK_IF_UNLOCK(sc_if);
878
879 return (0);
880}
881
882/*
883 * Report current media status.
884 */
885static void
886msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
887{
888 struct msk_if_softc *sc_if;
889 struct mii_data *mii;
890
891 sc_if = ifp->if_softc;
892 MSK_IF_LOCK(sc_if);
893 mii = device_get_softc(sc_if->msk_miibus);
894
895 mii_pollstat(mii);
896 MSK_IF_UNLOCK(sc_if);
897 ifmr->ifm_active = mii->mii_media_active;
898 ifmr->ifm_status = mii->mii_media_status;
899}
900
901static int
902msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
903{
904 struct msk_if_softc *sc_if;
905 struct ifreq *ifr;
906 struct mii_data *mii;
907 int error, mask;
908
909 sc_if = ifp->if_softc;
910 ifr = (struct ifreq *)data;
911 error = 0;
912
913 switch(command) {
914 case SIOCSIFMTU:
915 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) {
916 error = EINVAL;
917 break;
918 }
| 103
104#include <sys/param.h>
105#include <sys/systm.h>
106#include <sys/bus.h>
107#include <sys/endian.h>
108#include <sys/mbuf.h>
109#include <sys/malloc.h>
110#include <sys/kernel.h>
111#include <sys/module.h>
112#include <sys/socket.h>
113#include <sys/sockio.h>
114#include <sys/queue.h>
115#include <sys/sysctl.h>
116#include <sys/taskqueue.h>
117
118#include <net/bpf.h>
119#include <net/ethernet.h>
120#include <net/if.h>
121#include <net/if_arp.h>
122#include <net/if_dl.h>
123#include <net/if_media.h>
124#include <net/if_types.h>
125#include <net/if_vlan_var.h>
126
127#include <netinet/in.h>
128#include <netinet/in_systm.h>
129#include <netinet/ip.h>
130#include <netinet/tcp.h>
131#include <netinet/udp.h>
132
133#include <machine/bus.h>
134#include <machine/in_cksum.h>
135#include <machine/resource.h>
136#include <sys/rman.h>
137
138#include <dev/mii/mii.h>
139#include <dev/mii/miivar.h>
140#include <dev/mii/brgphyreg.h>
141
142#include <dev/pci/pcireg.h>
143#include <dev/pci/pcivar.h>
144
145#include <dev/msk/if_mskreg.h>
146
147MODULE_DEPEND(msk, pci, 1, 1, 1);
148MODULE_DEPEND(msk, ether, 1, 1, 1);
149MODULE_DEPEND(msk, miibus, 1, 1, 1);
150
151/* "device miibus" required. See GENERIC if you get errors here. */
152#include "miibus_if.h"
153
154/* Tunables. */
155static int msi_disable = 0;
156TUNABLE_INT("hw.msk.msi_disable", &msi_disable);
157static int legacy_intr = 0;
158TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr);
159
160#define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
161
162/*
163 * Devices supported by this driver.
164 */
165static struct msk_product {
166 uint16_t msk_vendorid;
167 uint16_t msk_deviceid;
168 const char *msk_name;
169} msk_products[] = {
170 { VENDORID_SK, DEVICEID_SK_YUKON2,
171 "SK-9Sxx Gigabit Ethernet" },
172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
173 "SK-9Exx Gigabit Ethernet"},
174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
175 "Marvell Yukon 88E8021CU Gigabit Ethernet" },
176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X,
177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
179 "Marvell Yukon 88E8022CU Gigabit Ethernet" },
180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X,
181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
183 "Marvell Yukon 88E8061CU Gigabit Ethernet" },
184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X,
185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
187 "Marvell Yukon 88E8062CU Gigabit Ethernet" },
188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X,
189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
190 { VENDORID_MARVELL, DEVICEID_MRVL_8035,
191 "Marvell Yukon 88E8035 Gigabit Ethernet" },
192 { VENDORID_MARVELL, DEVICEID_MRVL_8036,
193 "Marvell Yukon 88E8036 Gigabit Ethernet" },
194 { VENDORID_MARVELL, DEVICEID_MRVL_8038,
195 "Marvell Yukon 88E8038 Gigabit Ethernet" },
196 { VENDORID_MARVELL, DEVICEID_MRVL_4361,
197 "Marvell Yukon 88E8050 Gigabit Ethernet" },
198 { VENDORID_MARVELL, DEVICEID_MRVL_4360,
199 "Marvell Yukon 88E8052 Gigabit Ethernet" },
200 { VENDORID_MARVELL, DEVICEID_MRVL_4362,
201 "Marvell Yukon 88E8053 Gigabit Ethernet" },
202 { VENDORID_MARVELL, DEVICEID_MRVL_4363,
203 "Marvell Yukon 88E8055 Gigabit Ethernet" },
204 { VENDORID_MARVELL, DEVICEID_MRVL_4364,
205 "Marvell Yukon 88E8056 Gigabit Ethernet" },
206 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
207 "D-Link 550SX Gigabit Ethernet" },
208 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
209 "D-Link 560T Gigabit Ethernet" }
210};
211
212static const char *model_name[] = {
213 "Yukon XL",
214 "Yukon EC Ultra",
215 "Yukon Unknown",
216 "Yukon EC",
217 "Yukon FE"
218};
219
220static int mskc_probe(device_t);
221static int mskc_attach(device_t);
222static int mskc_detach(device_t);
223static void mskc_shutdown(device_t);
224static int mskc_setup_rambuffer(struct msk_softc *);
225static int mskc_suspend(device_t);
226static int mskc_resume(device_t);
227static void mskc_reset(struct msk_softc *);
228
229static int msk_probe(device_t);
230static int msk_attach(device_t);
231static int msk_detach(device_t);
232
233static void msk_tick(void *);
234static void msk_legacy_intr(void *);
235static int msk_intr(void *);
236static void msk_int_task(void *, int);
237static void msk_intr_phy(struct msk_if_softc *);
238static void msk_intr_gmac(struct msk_if_softc *);
239static __inline void msk_rxput(struct msk_if_softc *);
240static int msk_handle_events(struct msk_softc *);
241static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
242static void msk_intr_hwerr(struct msk_softc *);
243static void msk_rxeof(struct msk_if_softc *, uint32_t, int);
244static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int);
245static void msk_txeof(struct msk_if_softc *, int);
246static struct mbuf *msk_defrag(struct mbuf *, int, int);
247static int msk_encap(struct msk_if_softc *, struct mbuf **);
248static void msk_tx_task(void *, int);
249static void msk_start(struct ifnet *);
250static int msk_ioctl(struct ifnet *, u_long, caddr_t);
251static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
252static void msk_set_rambuffer(struct msk_if_softc *);
253static void msk_init(void *);
254static void msk_init_locked(struct msk_if_softc *);
255static void msk_stop(struct msk_if_softc *);
256static void msk_watchdog(struct msk_if_softc *);
257static int msk_mediachange(struct ifnet *);
258static void msk_mediastatus(struct ifnet *, struct ifmediareq *);
259static void msk_phy_power(struct msk_softc *, int);
260static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
261static int msk_status_dma_alloc(struct msk_softc *);
262static void msk_status_dma_free(struct msk_softc *);
263static int msk_txrx_dma_alloc(struct msk_if_softc *);
264static void msk_txrx_dma_free(struct msk_if_softc *);
265static void *msk_jalloc(struct msk_if_softc *);
266static void msk_jfree(void *, void *);
267static int msk_init_rx_ring(struct msk_if_softc *);
268static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
269static void msk_init_tx_ring(struct msk_if_softc *);
270static __inline void msk_discard_rxbuf(struct msk_if_softc *, int);
271static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
272static int msk_newbuf(struct msk_if_softc *, int);
273static int msk_jumbo_newbuf(struct msk_if_softc *, int);
274
275static int msk_phy_readreg(struct msk_if_softc *, int, int);
276static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
277static int msk_miibus_readreg(device_t, int, int);
278static int msk_miibus_writereg(device_t, int, int, int);
279static void msk_miibus_statchg(device_t);
280static void msk_link_task(void *, int);
281
282static void msk_setmulti(struct msk_if_softc *);
283static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
284static void msk_setpromisc(struct msk_if_softc *);
285
286static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
287static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
288
289static device_method_t mskc_methods[] = {
290 /* Device interface */
291 DEVMETHOD(device_probe, mskc_probe),
292 DEVMETHOD(device_attach, mskc_attach),
293 DEVMETHOD(device_detach, mskc_detach),
294 DEVMETHOD(device_suspend, mskc_suspend),
295 DEVMETHOD(device_resume, mskc_resume),
296 DEVMETHOD(device_shutdown, mskc_shutdown),
297
298 /* bus interface */
299 DEVMETHOD(bus_print_child, bus_generic_print_child),
300 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
301
302 { NULL, NULL }
303};
304
305static driver_t mskc_driver = {
306 "mskc",
307 mskc_methods,
308 sizeof(struct msk_softc)
309};
310
311static devclass_t mskc_devclass;
312
313static device_method_t msk_methods[] = {
314 /* Device interface */
315 DEVMETHOD(device_probe, msk_probe),
316 DEVMETHOD(device_attach, msk_attach),
317 DEVMETHOD(device_detach, msk_detach),
318 DEVMETHOD(device_shutdown, bus_generic_shutdown),
319
320 /* bus interface */
321 DEVMETHOD(bus_print_child, bus_generic_print_child),
322 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
323
324 /* MII interface */
325 DEVMETHOD(miibus_readreg, msk_miibus_readreg),
326 DEVMETHOD(miibus_writereg, msk_miibus_writereg),
327 DEVMETHOD(miibus_statchg, msk_miibus_statchg),
328
329 { NULL, NULL }
330};
331
332static driver_t msk_driver = {
333 "msk",
334 msk_methods,
335 sizeof(struct msk_if_softc)
336};
337
338static devclass_t msk_devclass;
339
340DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0);
341DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0);
342DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0);
343
344static struct resource_spec msk_res_spec_io[] = {
345 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
346 { -1, 0, 0 }
347};
348
349static struct resource_spec msk_res_spec_mem[] = {
350 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
351 { -1, 0, 0 }
352};
353
354static struct resource_spec msk_irq_spec_legacy[] = {
355 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
356 { -1, 0, 0 }
357};
358
359static struct resource_spec msk_irq_spec_msi[] = {
360 { SYS_RES_IRQ, 1, RF_ACTIVE },
361 { SYS_RES_IRQ, 2, RF_ACTIVE },
362 { -1, 0, 0 }
363};
364
365static int
366msk_miibus_readreg(device_t dev, int phy, int reg)
367{
368 struct msk_if_softc *sc_if;
369
370 sc_if = device_get_softc(dev);
371
372 return (msk_phy_readreg(sc_if, phy, reg));
373}
374
375static int
376msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
377{
378 struct msk_softc *sc;
379 int i, val;
380
381 sc = sc_if->msk_softc;
382
383 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
384 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
385
386 for (i = 0; i < MSK_TIMEOUT; i++) {
387 DELAY(1);
388 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
389 if ((val & GM_SMI_CT_RD_VAL) != 0) {
390 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
391 break;
392 }
393 }
394
395 if (i == MSK_TIMEOUT) {
396 if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
397 val = 0;
398 }
399
400 return (val);
401}
402
403static int
404msk_miibus_writereg(device_t dev, int phy, int reg, int val)
405{
406 struct msk_if_softc *sc_if;
407
408 sc_if = device_get_softc(dev);
409
410 return (msk_phy_writereg(sc_if, phy, reg, val));
411}
412
413static int
414msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
415{
416 struct msk_softc *sc;
417 int i;
418
419 sc = sc_if->msk_softc;
420
421 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
422 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
423 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
424 for (i = 0; i < MSK_TIMEOUT; i++) {
425 DELAY(1);
426 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
427 GM_SMI_CT_BUSY) == 0)
428 break;
429 }
430 if (i == MSK_TIMEOUT)
431 if_printf(sc_if->msk_ifp, "phy write timeout\n");
432
433 return (0);
434}
435
436static void
437msk_miibus_statchg(device_t dev)
438{
439 struct msk_if_softc *sc_if;
440
441 sc_if = device_get_softc(dev);
442 taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task);
443}
444
445static void
446msk_link_task(void *arg, int pending)
447{
448 struct msk_softc *sc;
449 struct msk_if_softc *sc_if;
450 struct mii_data *mii;
451 struct ifnet *ifp;
452 uint32_t gmac;
453
454 sc_if = (struct msk_if_softc *)arg;
455 sc = sc_if->msk_softc;
456
457 MSK_IF_LOCK(sc_if);
458
459 mii = device_get_softc(sc_if->msk_miibus);
460 ifp = sc_if->msk_ifp;
461 if (mii == NULL || ifp == NULL) {
462 MSK_IF_UNLOCK(sc_if);
463 return;
464 }
465
466 if (mii->mii_media_status & IFM_ACTIVE) {
467 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
468 sc_if->msk_link = 1;
469 } else
470 sc_if->msk_link = 0;
471
472 if (sc_if->msk_link != 0) {
473 /* Enable Tx FIFO Underrun. */
474 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
475 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
476 /*
477 * Because mii(4) notify msk(4) that it detected link status
478 * change, there is no need to enable automatic
479 * speed/flow-control/duplex updates.
480 */
481 gmac = GM_GPCR_AU_ALL_DIS;
482 switch (IFM_SUBTYPE(mii->mii_media_active)) {
483 case IFM_1000_SX:
484 case IFM_1000_T:
485 gmac |= GM_GPCR_SPEED_1000;
486 break;
487 case IFM_100_TX:
488 gmac |= GM_GPCR_SPEED_100;
489 break;
490 case IFM_10_T:
491 break;
492 }
493
494 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
495 gmac |= GM_GPCR_DUP_FULL;
496 /* Disable Rx flow control. */
497 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0)
498 gmac |= GM_GPCR_FC_RX_DIS;
499 /* Disable Tx flow control. */
500 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0)
501 gmac |= GM_GPCR_FC_TX_DIS;
502 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
503 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
504 /* Read again to ensure writing. */
505 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
506
507 gmac = GMC_PAUSE_ON;
508 if (((mii->mii_media_active & IFM_GMASK) &
509 (IFM_FLAG0 | IFM_FLAG1)) == 0)
510 gmac = GMC_PAUSE_OFF;
511 /* Diable pause for 10/100 Mbps in half-duplex mode. */
512 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) &&
513 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX ||
514 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T))
515 gmac = GMC_PAUSE_OFF;
516 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
517
518 /* Enable PHY interrupt for FIFO underrun/overflow. */
519 if (sc->msk_marvell_phy)
520 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
521 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
522 } else {
523 /*
524 * Link state changed to down.
525 * Disable PHY interrupts.
526 */
527 if (sc->msk_marvell_phy)
528 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
529 PHY_MARV_INT_MASK, 0);
530 /* Disable Rx/Tx MAC. */
531 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
532 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
533 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
534 /* Read again to ensure writing. */
535 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
536 }
537
538 MSK_IF_UNLOCK(sc_if);
539}
540
541static void
542msk_setmulti(struct msk_if_softc *sc_if)
543{
544 struct msk_softc *sc;
545 struct ifnet *ifp;
546 struct ifmultiaddr *ifma;
547 uint32_t mchash[2];
548 uint32_t crc;
549 uint16_t mode;
550
551 sc = sc_if->msk_softc;
552
553 MSK_IF_LOCK_ASSERT(sc_if);
554
555 ifp = sc_if->msk_ifp;
556
557 bzero(mchash, sizeof(mchash));
558 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
559 mode |= GM_RXCR_UCF_ENA;
560 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
561 if ((ifp->if_flags & IFF_PROMISC) != 0)
562 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
563 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
564 mchash[0] = 0xffff;
565 mchash[1] = 0xffff;
566 }
567 } else {
568 IF_ADDR_LOCK(ifp);
569 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
570 if (ifma->ifma_addr->sa_family != AF_LINK)
571 continue;
572 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
573 ifma->ifma_addr), ETHER_ADDR_LEN);
574 /* Just want the 6 least significant bits. */
575 crc &= 0x3f;
576 /* Set the corresponding bit in the hash table. */
577 mchash[crc >> 5] |= 1 << (crc & 0x1f);
578 }
579 IF_ADDR_UNLOCK(ifp);
580 mode |= GM_RXCR_MCF_ENA;
581 }
582
583 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
584 mchash[0] & 0xffff);
585 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
586 (mchash[0] >> 16) & 0xffff);
587 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
588 mchash[1] & 0xffff);
589 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
590 (mchash[1] >> 16) & 0xffff);
591 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
592}
593
594static void
595msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp)
596{
597 struct msk_softc *sc;
598
599 sc = sc_if->msk_softc;
600 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
601 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
602 RX_VLAN_STRIP_ON);
603 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
604 TX_VLAN_TAG_ON);
605 } else {
606 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
607 RX_VLAN_STRIP_OFF);
608 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
609 TX_VLAN_TAG_OFF);
610 }
611}
612
613static void
614msk_setpromisc(struct msk_if_softc *sc_if)
615{
616 struct msk_softc *sc;
617 struct ifnet *ifp;
618 uint16_t mode;
619
620 MSK_IF_LOCK_ASSERT(sc_if);
621
622 sc = sc_if->msk_softc;
623 ifp = sc_if->msk_ifp;
624
625 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
626 if (ifp->if_flags & IFF_PROMISC)
627 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
628 else
629 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
630 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
631}
632
633static int
634msk_init_rx_ring(struct msk_if_softc *sc_if)
635{
636 struct msk_ring_data *rd;
637 struct msk_rxdesc *rxd;
638 int i, prod;
639
640 MSK_IF_LOCK_ASSERT(sc_if);
641
642 sc_if->msk_cdata.msk_rx_cons = 0;
643 sc_if->msk_cdata.msk_rx_prod = 0;
644 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
645
646 rd = &sc_if->msk_rdata;
647 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
648 prod = sc_if->msk_cdata.msk_rx_prod;
649 for (i = 0; i < MSK_RX_RING_CNT; i++) {
650 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
651 rxd->rx_m = NULL;
652 rxd->rx_le = &rd->msk_rx_ring[prod];
653 if (msk_newbuf(sc_if, prod) != 0)
654 return (ENOBUFS);
655 MSK_INC(prod, MSK_RX_RING_CNT);
656 }
657
658 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
659 sc_if->msk_cdata.msk_rx_ring_map,
660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
661
662 /* Update prefetch unit. */
663 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1;
664 CSR_WRITE_2(sc_if->msk_softc,
665 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
666 sc_if->msk_cdata.msk_rx_prod);
667
668 return (0);
669}
670
671static int
672msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
673{
674 struct msk_ring_data *rd;
675 struct msk_rxdesc *rxd;
676 int i, prod;
677
678 MSK_IF_LOCK_ASSERT(sc_if);
679
680 sc_if->msk_cdata.msk_rx_cons = 0;
681 sc_if->msk_cdata.msk_rx_prod = 0;
682 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
683
684 rd = &sc_if->msk_rdata;
685 bzero(rd->msk_jumbo_rx_ring,
686 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
687 prod = sc_if->msk_cdata.msk_rx_prod;
688 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
689 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
690 rxd->rx_m = NULL;
691 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
692 if (msk_jumbo_newbuf(sc_if, prod) != 0)
693 return (ENOBUFS);
694 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
695 }
696
697 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
698 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
699 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
700
701 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1;
702 CSR_WRITE_2(sc_if->msk_softc,
703 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
704 sc_if->msk_cdata.msk_rx_prod);
705
706 return (0);
707}
708
709static void
710msk_init_tx_ring(struct msk_if_softc *sc_if)
711{
712 struct msk_ring_data *rd;
713 struct msk_txdesc *txd;
714 int i;
715
716 sc_if->msk_cdata.msk_tso_mtu = 0;
717 sc_if->msk_cdata.msk_tx_prod = 0;
718 sc_if->msk_cdata.msk_tx_cons = 0;
719 sc_if->msk_cdata.msk_tx_cnt = 0;
720
721 rd = &sc_if->msk_rdata;
722 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
723 for (i = 0; i < MSK_TX_RING_CNT; i++) {
724 txd = &sc_if->msk_cdata.msk_txdesc[i];
725 txd->tx_m = NULL;
726 txd->tx_le = &rd->msk_tx_ring[i];
727 }
728
729 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
730 sc_if->msk_cdata.msk_tx_ring_map,
731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
732}
733
734static __inline void
735msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
736{
737 struct msk_rx_desc *rx_le;
738 struct msk_rxdesc *rxd;
739 struct mbuf *m;
740
741 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
742 m = rxd->rx_m;
743 rx_le = rxd->rx_le;
744 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
745}
746
747static __inline void
748msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx)
749{
750 struct msk_rx_desc *rx_le;
751 struct msk_rxdesc *rxd;
752 struct mbuf *m;
753
754 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
755 m = rxd->rx_m;
756 rx_le = rxd->rx_le;
757 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
758}
759
760static int
761msk_newbuf(struct msk_if_softc *sc_if, int idx)
762{
763 struct msk_rx_desc *rx_le;
764 struct msk_rxdesc *rxd;
765 struct mbuf *m;
766 bus_dma_segment_t segs[1];
767 bus_dmamap_t map;
768 int nsegs;
769
770 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
771 if (m == NULL)
772 return (ENOBUFS);
773
774 m->m_len = m->m_pkthdr.len = MCLBYTES;
775 m_adj(m, ETHER_ALIGN);
776
777 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
778 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
779 BUS_DMA_NOWAIT) != 0) {
780 m_freem(m);
781 return (ENOBUFS);
782 }
783 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
784
785 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
786 if (rxd->rx_m != NULL) {
787 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
788 BUS_DMASYNC_POSTREAD);
789 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
790 }
791 map = rxd->rx_dmamap;
792 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
793 sc_if->msk_cdata.msk_rx_sparemap = map;
794 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
795 BUS_DMASYNC_PREREAD);
796 rxd->rx_m = m;
797 rx_le = rxd->rx_le;
798 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
799 rx_le->msk_control =
800 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
801
802 return (0);
803}
804
805static int
806msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
807{
808 struct msk_rx_desc *rx_le;
809 struct msk_rxdesc *rxd;
810 struct mbuf *m;
811 bus_dma_segment_t segs[1];
812 bus_dmamap_t map;
813 int nsegs;
814 void *buf;
815
816 MGETHDR(m, M_DONTWAIT, MT_DATA);
817 if (m == NULL)
818 return (ENOBUFS);
819 buf = msk_jalloc(sc_if);
820 if (buf == NULL) {
821 m_freem(m);
822 return (ENOBUFS);
823 }
824 /* Attach the buffer to the mbuf. */
825 MEXTADD(m, buf, MSK_JLEN, msk_jfree, (struct msk_if_softc *)sc_if, 0,
826 EXT_NET_DRV);
827 if ((m->m_flags & M_EXT) == 0) {
828 m_freem(m);
829 return (ENOBUFS);
830 }
831 m->m_pkthdr.len = m->m_len = MSK_JLEN;
832 m_adj(m, ETHER_ALIGN);
833
834 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
835 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
836 BUS_DMA_NOWAIT) != 0) {
837 m_freem(m);
838 return (ENOBUFS);
839 }
840 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
841
842 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
843 if (rxd->rx_m != NULL) {
844 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
845 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
846 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
847 rxd->rx_dmamap);
848 }
849 map = rxd->rx_dmamap;
850 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
851 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
852 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
853 BUS_DMASYNC_PREREAD);
854 rxd->rx_m = m;
855 rx_le = rxd->rx_le;
856 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
857 rx_le->msk_control =
858 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
859
860 return (0);
861}
862
863/*
864 * Set media options.
865 */
866static int
867msk_mediachange(struct ifnet *ifp)
868{
869 struct msk_if_softc *sc_if;
870 struct mii_data *mii;
871
872 sc_if = ifp->if_softc;
873
874 MSK_IF_LOCK(sc_if);
875 mii = device_get_softc(sc_if->msk_miibus);
876 mii_mediachg(mii);
877 MSK_IF_UNLOCK(sc_if);
878
879 return (0);
880}
881
882/*
883 * Report current media status.
884 */
885static void
886msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
887{
888 struct msk_if_softc *sc_if;
889 struct mii_data *mii;
890
891 sc_if = ifp->if_softc;
892 MSK_IF_LOCK(sc_if);
893 mii = device_get_softc(sc_if->msk_miibus);
894
895 mii_pollstat(mii);
896 MSK_IF_UNLOCK(sc_if);
897 ifmr->ifm_active = mii->mii_media_active;
898 ifmr->ifm_status = mii->mii_media_status;
899}
900
901static int
902msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
903{
904 struct msk_if_softc *sc_if;
905 struct ifreq *ifr;
906 struct mii_data *mii;
907 int error, mask;
908
909 sc_if = ifp->if_softc;
910 ifr = (struct ifreq *)data;
911 error = 0;
912
913 switch(command) {
914 case SIOCSIFMTU:
915 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) {
916 error = EINVAL;
917 break;
918 }
|
919 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
| 919 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE &&
|
920 ifr->ifr_mtu > MSK_MAX_FRAMELEN) {
921 error = EINVAL;
922 break;
923 }
924 MSK_IF_LOCK(sc_if);
925 ifp->if_mtu = ifr->ifr_mtu;
926 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
927 msk_init_locked(sc_if);
928 MSK_IF_UNLOCK(sc_if);
929 break;
930 case SIOCSIFFLAGS:
931 MSK_IF_LOCK(sc_if);
932 if ((ifp->if_flags & IFF_UP) != 0) {
933 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
934 if (((ifp->if_flags ^ sc_if->msk_if_flags)
935 & IFF_PROMISC) != 0) {
936 msk_setpromisc(sc_if);
937 msk_setmulti(sc_if);
938 }
939 } else {
940 if (sc_if->msk_detach == 0)
941 msk_init_locked(sc_if);
942 }
943 } else {
944 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
945 msk_stop(sc_if);
946 }
947 sc_if->msk_if_flags = ifp->if_flags;
948 MSK_IF_UNLOCK(sc_if);
949 break;
950 case SIOCADDMULTI:
951 case SIOCDELMULTI:
952 MSK_IF_LOCK(sc_if);
953 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
954 msk_setmulti(sc_if);
955 MSK_IF_UNLOCK(sc_if);
956 break;
957 case SIOCGIFMEDIA:
958 case SIOCSIFMEDIA:
959 mii = device_get_softc(sc_if->msk_miibus);
960 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
961 break;
962 case SIOCSIFCAP:
963 MSK_IF_LOCK(sc_if);
964 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
965 if ((mask & IFCAP_TXCSUM) != 0) {
966 ifp->if_capenable ^= IFCAP_TXCSUM;
967 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 &&
968 (IFCAP_TXCSUM & ifp->if_capabilities) != 0)
969 ifp->if_hwassist |= MSK_CSUM_FEATURES;
970 else
971 ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
972 }
973 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
974 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
975 msk_setvlan(sc_if, ifp);
976 }
977
978 if ((mask & IFCAP_TSO4) != 0) {
979 ifp->if_capenable ^= IFCAP_TSO4;
980 if ((IFCAP_TSO4 & ifp->if_capenable) != 0 &&
981 (IFCAP_TSO4 & ifp->if_capabilities) != 0)
982 ifp->if_hwassist |= CSUM_TSO;
983 else
984 ifp->if_hwassist &= ~CSUM_TSO;
985 }
| 920 ifr->ifr_mtu > MSK_MAX_FRAMELEN) {
921 error = EINVAL;
922 break;
923 }
924 MSK_IF_LOCK(sc_if);
925 ifp->if_mtu = ifr->ifr_mtu;
926 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
927 msk_init_locked(sc_if);
928 MSK_IF_UNLOCK(sc_if);
929 break;
930 case SIOCSIFFLAGS:
931 MSK_IF_LOCK(sc_if);
932 if ((ifp->if_flags & IFF_UP) != 0) {
933 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
934 if (((ifp->if_flags ^ sc_if->msk_if_flags)
935 & IFF_PROMISC) != 0) {
936 msk_setpromisc(sc_if);
937 msk_setmulti(sc_if);
938 }
939 } else {
940 if (sc_if->msk_detach == 0)
941 msk_init_locked(sc_if);
942 }
943 } else {
944 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
945 msk_stop(sc_if);
946 }
947 sc_if->msk_if_flags = ifp->if_flags;
948 MSK_IF_UNLOCK(sc_if);
949 break;
950 case SIOCADDMULTI:
951 case SIOCDELMULTI:
952 MSK_IF_LOCK(sc_if);
953 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
954 msk_setmulti(sc_if);
955 MSK_IF_UNLOCK(sc_if);
956 break;
957 case SIOCGIFMEDIA:
958 case SIOCSIFMEDIA:
959 mii = device_get_softc(sc_if->msk_miibus);
960 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
961 break;
962 case SIOCSIFCAP:
963 MSK_IF_LOCK(sc_if);
964 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
965 if ((mask & IFCAP_TXCSUM) != 0) {
966 ifp->if_capenable ^= IFCAP_TXCSUM;
967 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 &&
968 (IFCAP_TXCSUM & ifp->if_capabilities) != 0)
969 ifp->if_hwassist |= MSK_CSUM_FEATURES;
970 else
971 ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
972 }
973 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
974 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
975 msk_setvlan(sc_if, ifp);
976 }
977
978 if ((mask & IFCAP_TSO4) != 0) {
979 ifp->if_capenable ^= IFCAP_TSO4;
980 if ((IFCAP_TSO4 & ifp->if_capenable) != 0 &&
981 (IFCAP_TSO4 & ifp->if_capabilities) != 0)
982 ifp->if_hwassist |= CSUM_TSO;
983 else
984 ifp->if_hwassist &= ~CSUM_TSO;
985 }
|
| 986 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
987 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
988 /*
989 * In Yukon EC Ultra, TSO & checksum offload is not
990 * supported for jumbo frame.
991 */
992 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
993 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
994 }
995
|
986 VLAN_CAPABILITIES(ifp);
987 MSK_IF_UNLOCK(sc_if);
988 break;
989 default:
990 error = ether_ioctl(ifp, command, data);
991 break;
992 }
993
994 return (error);
995}
996
997static int
998mskc_probe(device_t dev)
999{
1000 struct msk_product *mp;
1001 uint16_t vendor, devid;
1002 int i;
1003
1004 vendor = pci_get_vendor(dev);
1005 devid = pci_get_device(dev);
1006 mp = msk_products;
1007 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]);
1008 i++, mp++) {
1009 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
1010 device_set_desc(dev, mp->msk_name);
1011 return (BUS_PROBE_DEFAULT);
1012 }
1013 }
1014
1015 return (ENXIO);
1016}
1017
1018static int
1019mskc_setup_rambuffer(struct msk_softc *sc)
1020{
1021 int totqsize, minqsize;
1022 int avail, next;
1023 int i;
1024 uint8_t val;
1025
1026 /* Get adapter SRAM size. */
1027 val = CSR_READ_1(sc, B2_E_0);
1028 sc->msk_ramsize = (val == 0) ? 128 : val * 4;
1029 if (sc->msk_hw_id == CHIP_ID_YUKON_FE)
1030 sc->msk_ramsize = 4 * 4;
1031 if (bootverbose)
1032 device_printf(sc->msk_dev,
1033 "RAM buffer size : %dKB\n", sc->msk_ramsize);
1034
1035 totqsize = sc->msk_ramsize * sc->msk_num_port;
1036 minqsize = MSK_MIN_RXQ_SIZE + MSK_MIN_TXQ_SIZE;
1037 if (minqsize > sc->msk_ramsize)
1038 minqsize = sc->msk_ramsize;
1039
1040 if (minqsize * sc->msk_num_port > totqsize) {
1041 device_printf(sc->msk_dev,
1042 "not enough RAM buffer memory : %d/%dKB\n",
1043 minqsize * sc->msk_num_port, totqsize);
1044 return (ENOSPC);
1045 }
1046
1047 avail = totqsize;
1048 if (sc->msk_num_port > 1) {
1049 /*
1050 * Divide up the memory evenly so that everyone gets a
1051 * fair share for dual port adapters.
1052 */
1053 avail = sc->msk_ramsize;
1054 }
1055
1056 /* Take away the minimum memory for active queues. */
1057 avail -= minqsize;
1058 /* Rx queue gets the minimum + 80% of the rest. */
1059 sc->msk_rxqsize =
1060 (avail * MSK_RAM_QUOTA_RX) / 100 + MSK_MIN_RXQ_SIZE;
1061 avail -= (sc->msk_rxqsize - MSK_MIN_RXQ_SIZE);
1062 sc->msk_txqsize = avail + MSK_MIN_TXQ_SIZE;
1063
1064 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
1065 sc->msk_rxqstart[i] = next;
1066 sc->msk_rxqend[i] = next + (sc->msk_rxqsize * 1024) - 1;
1067 next = sc->msk_rxqend[i] + 1;
1068 sc->msk_txqstart[i] = next;
1069 sc->msk_txqend[i] = next + (sc->msk_txqsize * 1024) - 1;
1070 next = sc->msk_txqend[i] + 1;
1071 if (bootverbose) {
1072 device_printf(sc->msk_dev,
1073 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
1074 sc->msk_rxqsize, sc->msk_rxqstart[i],
1075 sc->msk_rxqend[i]);
1076 device_printf(sc->msk_dev,
1077 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1078 sc->msk_txqsize, sc->msk_txqstart[i],
1079 sc->msk_txqend[i]);
1080 }
1081 }
1082
1083 return (0);
1084}
1085
1086static void
1087msk_phy_power(struct msk_softc *sc, int mode)
1088{
1089 uint32_t val;
1090 int i;
1091
1092 switch (mode) {
1093 case MSK_PHY_POWERUP:
1094 /* Switch power to VCC (WA for VAUX problem). */
1095 CSR_WRITE_1(sc, B0_POWER_CTRL,
1096 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1097 /* Disable Core Clock Division, set Clock Select to 0. */
1098 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1099
1100 val = 0;
1101 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1102 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1103 /* Enable bits are inverted. */
1104 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1105 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1106 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1107 }
1108 /*
1109 * Enable PCI & Core Clock, enable clock gating for both Links.
1110 */
1111 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1112
1113 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1114 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1115 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1116 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1117 /* Deassert Low Power for 1st PHY. */
1118 val |= PCI_Y2_PHY1_COMA;
1119 if (sc->msk_num_port > 1)
1120 val |= PCI_Y2_PHY2_COMA;
1121 } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
1122 uint32_t our;
1123
1124 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1125
1126 /* Enable all clocks. */
1127 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4);
1128 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4);
1129 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
1130 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
1131 /* Set all bits to 0 except bits 15..12. */
1132 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4);
1133 /* Set to default value. */
1134 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4);
1135 }
1136 /* Release PHY from PowerDown/COMA mode. */
1137 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1138 for (i = 0; i < sc->msk_num_port; i++) {
1139 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1140 GMLC_RST_SET);
1141 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1142 GMLC_RST_CLR);
1143 }
1144 break;
1145 case MSK_PHY_POWERDOWN:
1146 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1147 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
1148 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1149 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1150 val &= ~PCI_Y2_PHY1_COMA;
1151 if (sc->msk_num_port > 1)
1152 val &= ~PCI_Y2_PHY2_COMA;
1153 }
1154 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1155
1156 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1157 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1158 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1159 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1160 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1161 /* Enable bits are inverted. */
1162 val = 0;
1163 }
1164 /*
1165 * Disable PCI & Core Clock, disable clock gating for
1166 * both Links.
1167 */
1168 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1169 CSR_WRITE_1(sc, B0_POWER_CTRL,
1170 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
1171 break;
1172 default:
1173 break;
1174 }
1175}
1176
1177static void
1178mskc_reset(struct msk_softc *sc)
1179{
1180 bus_addr_t addr;
1181 uint16_t status;
1182 uint32_t val;
1183 int i;
1184
1185 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1186
1187 /* Disable ASF. */
1188 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) {
1189 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1190 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1191 }
1192 /*
1193 * Since we disabled ASF, S/W reset is required for Power Management.
1194 */
1195 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1196 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1197
1198 /* Clear all error bits in the PCI status register. */
1199 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1200 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1201
1202 pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1203 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1204 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2);
1205 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
1206
1207 switch (sc->msk_bustype) {
1208 case MSK_PEX_BUS:
1209 /* Clear all PEX errors. */
1210 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
1211 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
1212 if ((val & PEX_RX_OV) != 0) {
1213 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1214 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1215 }
1216 break;
1217 case MSK_PCI_BUS:
1218 case MSK_PCIX_BUS:
1219 /* Set Cache Line Size to 2(8bytes) if configured to 0. */
1220 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1221 if (val == 0)
1222 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1223 if (sc->msk_bustype == MSK_PCIX_BUS) {
1224 /* Set Cache Line Size opt. */
1225 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1226 val |= PCI_CLS_OPT;
1227 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1228 }
1229 break;
1230 }
1231 /* Set PHY power state. */
1232 msk_phy_power(sc, MSK_PHY_POWERUP);
1233
1234 /* Reset GPHY/GMAC Control */
1235 for (i = 0; i < sc->msk_num_port; i++) {
1236 /* GPHY Control reset. */
1237 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1238 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1239 /* GMAC Control reset. */
1240 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1241 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1242 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1243 }
1244 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1245
1246 /* LED On. */
1247 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
1248
1249 /* Clear TWSI IRQ. */
1250 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1251
1252 /* Turn off hardware timer. */
1253 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
1254 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
1255
1256 /* Turn off descriptor polling. */
1257 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
1258
1259 /* Turn off time stamps. */
1260 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1261 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1262
1263 /* Configure timeout values. */
1264 for (i = 0; i < sc->msk_num_port; i++) {
1265 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
1266 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1267 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
1268 MSK_RI_TO_53);
1269 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
1270 MSK_RI_TO_53);
1271 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
1272 MSK_RI_TO_53);
1273 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
1274 MSK_RI_TO_53);
1275 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
1276 MSK_RI_TO_53);
1277 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
1278 MSK_RI_TO_53);
1279 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
1280 MSK_RI_TO_53);
1281 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
1282 MSK_RI_TO_53);
1283 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
1284 MSK_RI_TO_53);
1285 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
1286 MSK_RI_TO_53);
1287 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
1288 MSK_RI_TO_53);
1289 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
1290 MSK_RI_TO_53);
1291 }
1292
1293 /* Disable all interrupts. */
1294 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1295 CSR_READ_4(sc, B0_HWE_IMSK);
1296 CSR_WRITE_4(sc, B0_IMSK, 0);
1297 CSR_READ_4(sc, B0_IMSK);
1298
1299 /*
1300 * On dual port PCI-X card, there is an problem where status
1301 * can be received out of order due to split transactions.
1302 */
1303 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) {
1304 int pcix;
1305 uint16_t pcix_cmd;
1306
1307 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) {
1308 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2);
1309 /* Clear Max Outstanding Split Transactions. */
1310 pcix_cmd &= ~0x70;
1311 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1312 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2);
1313 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1314 }
1315 }
1316 if (sc->msk_bustype == MSK_PEX_BUS) {
1317 uint16_t v, width;
1318
1319 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2);
1320 /* Change Max. Read Request Size to 4096 bytes. */
1321 v &= ~PEX_DC_MAX_RRS_MSK;
1322 v |= PEX_DC_MAX_RD_RQ_SIZE(5);
1323 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2);
1324 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2);
1325 width = (width & PEX_LS_LINK_WI_MSK) >> 4;
1326 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2);
1327 v = (v & PEX_LS_LINK_WI_MSK) >> 4;
1328 if (v != width)
1329 device_printf(sc->msk_dev,
1330 "negotiated width of link(x%d) != "
1331 "max. width of link(x%d)\n", width, v);
1332 }
1333
1334 /* Clear status list. */
1335 bzero(sc->msk_stat_ring,
1336 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT);
1337 sc->msk_stat_cons = 0;
1338 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
1339 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1340 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1341 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1342 /* Set the status list base address. */
1343 addr = sc->msk_stat_ring_paddr;
1344 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1345 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1346 /* Set the status list last index. */
1347 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
1348 if (HW_FEATURE(sc, HWF_WA_DEV_43_418)) {
1349 /* WA for dev. #4.3 */
1350 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1351 /* WA for dev. #4.18 */
1352 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
1353 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
1354 } else {
1355 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
1356 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1357 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM,
1358 HW_FEATURE(sc, HWF_WA_DEV_4109) ? 0x10 : 0x04);
1359 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1360 }
1361 /*
1362 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
1363 */
1364 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1365
1366 /* Enable status unit. */
1367 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
1368
1369 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
1370 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
1371 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
1372}
1373
1374static int
1375msk_probe(device_t dev)
1376{
1377 struct msk_softc *sc;
1378 char desc[100];
1379
1380 sc = device_get_softc(device_get_parent(dev));
1381 /*
1382 * Not much to do here. We always know there will be
1383 * at least one GMAC present, and if there are two,
1384 * mskc_attach() will create a second device instance
1385 * for us.
1386 */
1387 snprintf(desc, sizeof(desc),
1388 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
1389 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1390 sc->msk_hw_rev);
1391 device_set_desc_copy(dev, desc);
1392
1393 return (BUS_PROBE_DEFAULT);
1394}
1395
1396static int
1397msk_attach(device_t dev)
1398{
1399 struct msk_softc *sc;
1400 struct msk_if_softc *sc_if;
1401 struct ifnet *ifp;
1402 int i, port, error;
1403 uint8_t eaddr[6];
1404
1405 if (dev == NULL)
1406 return (EINVAL);
1407
1408 error = 0;
1409 sc_if = device_get_softc(dev);
1410 sc = device_get_softc(device_get_parent(dev));
1411 port = *(int *)device_get_ivars(dev);
1412
1413 sc_if->msk_if_dev = dev;
1414 sc_if->msk_port = port;
1415 sc_if->msk_softc = sc;
1416 sc->msk_if[port] = sc_if;
1417 /* Setup Tx/Rx queue register offsets. */
1418 if (port == MSK_PORT_A) {
1419 sc_if->msk_txq = Q_XA1;
1420 sc_if->msk_txsq = Q_XS1;
1421 sc_if->msk_rxq = Q_R1;
1422 } else {
1423 sc_if->msk_txq = Q_XA2;
1424 sc_if->msk_txsq = Q_XS2;
1425 sc_if->msk_rxq = Q_R2;
1426 }
1427
1428 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1429 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if);
1430
1431 if ((error = msk_txrx_dma_alloc(sc_if) != 0))
1432 goto fail;
1433
1434 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER);
1435 if (ifp == NULL) {
1436 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n");
1437 error = ENOSPC;
1438 goto fail;
1439 }
1440 ifp->if_softc = sc_if;
1441 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1442 ifp->if_mtu = ETHERMTU;
1443 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1444 /*
1445 * IFCAP_RXCSUM capability is intentionally disabled as the hardware
1446 * has serious bug in Rx checksum offload for all Yukon II family
1447 * hardware. It seems there is a workaround to make it work somtimes.
1448 * However, the workaround also have to check OP code sequences to
1449 * verify whether the OP code is correct. Sometimes it should compute
1450 * IP/TCP/UDP checksum in driver in order to verify correctness of
1451 * checksum computed by hardware. If you have to compute checksum
1452 * with software to verify the hardware's checksum why have hardware
1453 * compute the checksum? I think there is no reason to spend time to
1454 * make Rx checksum offload work on Yukon II hardware.
1455 */
| 996 VLAN_CAPABILITIES(ifp);
997 MSK_IF_UNLOCK(sc_if);
998 break;
999 default:
1000 error = ether_ioctl(ifp, command, data);
1001 break;
1002 }
1003
1004 return (error);
1005}
1006
1007static int
1008mskc_probe(device_t dev)
1009{
1010 struct msk_product *mp;
1011 uint16_t vendor, devid;
1012 int i;
1013
1014 vendor = pci_get_vendor(dev);
1015 devid = pci_get_device(dev);
1016 mp = msk_products;
1017 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]);
1018 i++, mp++) {
1019 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
1020 device_set_desc(dev, mp->msk_name);
1021 return (BUS_PROBE_DEFAULT);
1022 }
1023 }
1024
1025 return (ENXIO);
1026}
1027
1028static int
1029mskc_setup_rambuffer(struct msk_softc *sc)
1030{
1031 int totqsize, minqsize;
1032 int avail, next;
1033 int i;
1034 uint8_t val;
1035
1036 /* Get adapter SRAM size. */
1037 val = CSR_READ_1(sc, B2_E_0);
1038 sc->msk_ramsize = (val == 0) ? 128 : val * 4;
1039 if (sc->msk_hw_id == CHIP_ID_YUKON_FE)
1040 sc->msk_ramsize = 4 * 4;
1041 if (bootverbose)
1042 device_printf(sc->msk_dev,
1043 "RAM buffer size : %dKB\n", sc->msk_ramsize);
1044
1045 totqsize = sc->msk_ramsize * sc->msk_num_port;
1046 minqsize = MSK_MIN_RXQ_SIZE + MSK_MIN_TXQ_SIZE;
1047 if (minqsize > sc->msk_ramsize)
1048 minqsize = sc->msk_ramsize;
1049
1050 if (minqsize * sc->msk_num_port > totqsize) {
1051 device_printf(sc->msk_dev,
1052 "not enough RAM buffer memory : %d/%dKB\n",
1053 minqsize * sc->msk_num_port, totqsize);
1054 return (ENOSPC);
1055 }
1056
1057 avail = totqsize;
1058 if (sc->msk_num_port > 1) {
1059 /*
1060 * Divide up the memory evenly so that everyone gets a
1061 * fair share for dual port adapters.
1062 */
1063 avail = sc->msk_ramsize;
1064 }
1065
1066 /* Take away the minimum memory for active queues. */
1067 avail -= minqsize;
1068 /* Rx queue gets the minimum + 80% of the rest. */
1069 sc->msk_rxqsize =
1070 (avail * MSK_RAM_QUOTA_RX) / 100 + MSK_MIN_RXQ_SIZE;
1071 avail -= (sc->msk_rxqsize - MSK_MIN_RXQ_SIZE);
1072 sc->msk_txqsize = avail + MSK_MIN_TXQ_SIZE;
1073
1074 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
1075 sc->msk_rxqstart[i] = next;
1076 sc->msk_rxqend[i] = next + (sc->msk_rxqsize * 1024) - 1;
1077 next = sc->msk_rxqend[i] + 1;
1078 sc->msk_txqstart[i] = next;
1079 sc->msk_txqend[i] = next + (sc->msk_txqsize * 1024) - 1;
1080 next = sc->msk_txqend[i] + 1;
1081 if (bootverbose) {
1082 device_printf(sc->msk_dev,
1083 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
1084 sc->msk_rxqsize, sc->msk_rxqstart[i],
1085 sc->msk_rxqend[i]);
1086 device_printf(sc->msk_dev,
1087 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1088 sc->msk_txqsize, sc->msk_txqstart[i],
1089 sc->msk_txqend[i]);
1090 }
1091 }
1092
1093 return (0);
1094}
1095
1096static void
1097msk_phy_power(struct msk_softc *sc, int mode)
1098{
1099 uint32_t val;
1100 int i;
1101
1102 switch (mode) {
1103 case MSK_PHY_POWERUP:
1104 /* Switch power to VCC (WA for VAUX problem). */
1105 CSR_WRITE_1(sc, B0_POWER_CTRL,
1106 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1107 /* Disable Core Clock Division, set Clock Select to 0. */
1108 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1109
1110 val = 0;
1111 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1112 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1113 /* Enable bits are inverted. */
1114 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1115 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1116 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1117 }
1118 /*
1119 * Enable PCI & Core Clock, enable clock gating for both Links.
1120 */
1121 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1122
1123 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1124 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1125 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1126 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1127 /* Deassert Low Power for 1st PHY. */
1128 val |= PCI_Y2_PHY1_COMA;
1129 if (sc->msk_num_port > 1)
1130 val |= PCI_Y2_PHY2_COMA;
1131 } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
1132 uint32_t our;
1133
1134 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1135
1136 /* Enable all clocks. */
1137 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4);
1138 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4);
1139 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
1140 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
1141 /* Set all bits to 0 except bits 15..12. */
1142 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4);
1143 /* Set to default value. */
1144 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4);
1145 }
1146 /* Release PHY from PowerDown/COMA mode. */
1147 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1148 for (i = 0; i < sc->msk_num_port; i++) {
1149 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1150 GMLC_RST_SET);
1151 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1152 GMLC_RST_CLR);
1153 }
1154 break;
1155 case MSK_PHY_POWERDOWN:
1156 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1157 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
1158 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1159 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1160 val &= ~PCI_Y2_PHY1_COMA;
1161 if (sc->msk_num_port > 1)
1162 val &= ~PCI_Y2_PHY2_COMA;
1163 }
1164 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1165
1166 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1167 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1168 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1169 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1170 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1171 /* Enable bits are inverted. */
1172 val = 0;
1173 }
1174 /*
1175 * Disable PCI & Core Clock, disable clock gating for
1176 * both Links.
1177 */
1178 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1179 CSR_WRITE_1(sc, B0_POWER_CTRL,
1180 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
1181 break;
1182 default:
1183 break;
1184 }
1185}
1186
1187static void
1188mskc_reset(struct msk_softc *sc)
1189{
1190 bus_addr_t addr;
1191 uint16_t status;
1192 uint32_t val;
1193 int i;
1194
1195 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1196
1197 /* Disable ASF. */
1198 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) {
1199 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1200 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1201 }
1202 /*
1203 * Since we disabled ASF, S/W reset is required for Power Management.
1204 */
1205 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1206 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1207
1208 /* Clear all error bits in the PCI status register. */
1209 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1210 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1211
1212 pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1213 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1214 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2);
1215 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
1216
1217 switch (sc->msk_bustype) {
1218 case MSK_PEX_BUS:
1219 /* Clear all PEX errors. */
1220 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
1221 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
1222 if ((val & PEX_RX_OV) != 0) {
1223 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1224 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1225 }
1226 break;
1227 case MSK_PCI_BUS:
1228 case MSK_PCIX_BUS:
1229 /* Set Cache Line Size to 2(8bytes) if configured to 0. */
1230 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1231 if (val == 0)
1232 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1233 if (sc->msk_bustype == MSK_PCIX_BUS) {
1234 /* Set Cache Line Size opt. */
1235 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1236 val |= PCI_CLS_OPT;
1237 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1238 }
1239 break;
1240 }
1241 /* Set PHY power state. */
1242 msk_phy_power(sc, MSK_PHY_POWERUP);
1243
1244 /* Reset GPHY/GMAC Control */
1245 for (i = 0; i < sc->msk_num_port; i++) {
1246 /* GPHY Control reset. */
1247 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1248 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1249 /* GMAC Control reset. */
1250 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1251 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1252 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1253 }
1254 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1255
1256 /* LED On. */
1257 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
1258
1259 /* Clear TWSI IRQ. */
1260 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1261
1262 /* Turn off hardware timer. */
1263 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
1264 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
1265
1266 /* Turn off descriptor polling. */
1267 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
1268
1269 /* Turn off time stamps. */
1270 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1271 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1272
1273 /* Configure timeout values. */
1274 for (i = 0; i < sc->msk_num_port; i++) {
1275 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
1276 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1277 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
1278 MSK_RI_TO_53);
1279 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
1280 MSK_RI_TO_53);
1281 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
1282 MSK_RI_TO_53);
1283 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
1284 MSK_RI_TO_53);
1285 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
1286 MSK_RI_TO_53);
1287 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
1288 MSK_RI_TO_53);
1289 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
1290 MSK_RI_TO_53);
1291 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
1292 MSK_RI_TO_53);
1293 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
1294 MSK_RI_TO_53);
1295 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
1296 MSK_RI_TO_53);
1297 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
1298 MSK_RI_TO_53);
1299 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
1300 MSK_RI_TO_53);
1301 }
1302
1303 /* Disable all interrupts. */
1304 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1305 CSR_READ_4(sc, B0_HWE_IMSK);
1306 CSR_WRITE_4(sc, B0_IMSK, 0);
1307 CSR_READ_4(sc, B0_IMSK);
1308
1309 /*
1310 * On dual port PCI-X card, there is an problem where status
1311 * can be received out of order due to split transactions.
1312 */
1313 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) {
1314 int pcix;
1315 uint16_t pcix_cmd;
1316
1317 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) {
1318 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2);
1319 /* Clear Max Outstanding Split Transactions. */
1320 pcix_cmd &= ~0x70;
1321 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1322 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2);
1323 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1324 }
1325 }
1326 if (sc->msk_bustype == MSK_PEX_BUS) {
1327 uint16_t v, width;
1328
1329 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2);
1330 /* Change Max. Read Request Size to 4096 bytes. */
1331 v &= ~PEX_DC_MAX_RRS_MSK;
1332 v |= PEX_DC_MAX_RD_RQ_SIZE(5);
1333 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2);
1334 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2);
1335 width = (width & PEX_LS_LINK_WI_MSK) >> 4;
1336 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2);
1337 v = (v & PEX_LS_LINK_WI_MSK) >> 4;
1338 if (v != width)
1339 device_printf(sc->msk_dev,
1340 "negotiated width of link(x%d) != "
1341 "max. width of link(x%d)\n", width, v);
1342 }
1343
1344 /* Clear status list. */
1345 bzero(sc->msk_stat_ring,
1346 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT);
1347 sc->msk_stat_cons = 0;
1348 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
1349 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1350 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1351 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1352 /* Set the status list base address. */
1353 addr = sc->msk_stat_ring_paddr;
1354 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1355 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1356 /* Set the status list last index. */
1357 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
1358 if (HW_FEATURE(sc, HWF_WA_DEV_43_418)) {
1359 /* WA for dev. #4.3 */
1360 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1361 /* WA for dev. #4.18 */
1362 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
1363 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
1364 } else {
1365 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
1366 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1367 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM,
1368 HW_FEATURE(sc, HWF_WA_DEV_4109) ? 0x10 : 0x04);
1369 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1370 }
1371 /*
1372 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
1373 */
1374 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1375
1376 /* Enable status unit. */
1377 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
1378
1379 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
1380 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
1381 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
1382}
1383
1384static int
1385msk_probe(device_t dev)
1386{
1387 struct msk_softc *sc;
1388 char desc[100];
1389
1390 sc = device_get_softc(device_get_parent(dev));
1391 /*
1392 * Not much to do here. We always know there will be
1393 * at least one GMAC present, and if there are two,
1394 * mskc_attach() will create a second device instance
1395 * for us.
1396 */
1397 snprintf(desc, sizeof(desc),
1398 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
1399 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1400 sc->msk_hw_rev);
1401 device_set_desc_copy(dev, desc);
1402
1403 return (BUS_PROBE_DEFAULT);
1404}
1405
1406static int
1407msk_attach(device_t dev)
1408{
1409 struct msk_softc *sc;
1410 struct msk_if_softc *sc_if;
1411 struct ifnet *ifp;
1412 int i, port, error;
1413 uint8_t eaddr[6];
1414
1415 if (dev == NULL)
1416 return (EINVAL);
1417
1418 error = 0;
1419 sc_if = device_get_softc(dev);
1420 sc = device_get_softc(device_get_parent(dev));
1421 port = *(int *)device_get_ivars(dev);
1422
1423 sc_if->msk_if_dev = dev;
1424 sc_if->msk_port = port;
1425 sc_if->msk_softc = sc;
1426 sc->msk_if[port] = sc_if;
1427 /* Setup Tx/Rx queue register offsets. */
1428 if (port == MSK_PORT_A) {
1429 sc_if->msk_txq = Q_XA1;
1430 sc_if->msk_txsq = Q_XS1;
1431 sc_if->msk_rxq = Q_R1;
1432 } else {
1433 sc_if->msk_txq = Q_XA2;
1434 sc_if->msk_txsq = Q_XS2;
1435 sc_if->msk_rxq = Q_R2;
1436 }
1437
1438 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1439 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if);
1440
1441 if ((error = msk_txrx_dma_alloc(sc_if) != 0))
1442 goto fail;
1443
1444 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER);
1445 if (ifp == NULL) {
1446 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n");
1447 error = ENOSPC;
1448 goto fail;
1449 }
1450 ifp->if_softc = sc_if;
1451 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1452 ifp->if_mtu = ETHERMTU;
1453 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1454 /*
1455 * IFCAP_RXCSUM capability is intentionally disabled as the hardware
1456 * has serious bug in Rx checksum offload for all Yukon II family
1457 * hardware. It seems there is a workaround to make it work somtimes.
1458 * However, the workaround also have to check OP code sequences to
1459 * verify whether the OP code is correct. Sometimes it should compute
1460 * IP/TCP/UDP checksum in driver in order to verify correctness of
1461 * checksum computed by hardware. If you have to compute checksum
1462 * with software to verify the hardware's checksum why have hardware
1463 * compute the checksum? I think there is no reason to spend time to
1464 * make Rx checksum offload work on Yukon II hardware.
1465 */
|
1456 ifp->if_capabilities = IFCAP_TXCSUM;
1457 ifp->if_hwassist = MSK_CSUM_FEATURES;
1458 if (sc->msk_hw_id != CHIP_ID_YUKON_EC_U) {
1459 /* It seems Yukon EC Ultra doesn't support TSO. */
1460 ifp->if_capabilities |= IFCAP_TSO4;
1461 ifp->if_hwassist |= CSUM_TSO;
1462 }
| 1466 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
1467 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO;
|
1463 ifp->if_capenable = ifp->if_capabilities;
1464 ifp->if_ioctl = msk_ioctl;
1465 ifp->if_start = msk_start;
1466 ifp->if_timer = 0;
1467 ifp->if_watchdog = NULL;
1468 ifp->if_init = msk_init;
1469 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1);
1470 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1;
1471 IFQ_SET_READY(&ifp->if_snd);
1472
1473 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp);
1474
1475 /*
1476 * Get station address for this interface. Note that
1477 * dual port cards actually come with three station
1478 * addresses: one for each port, plus an extra. The
1479 * extra one is used by the SysKonnect driver software
1480 * as a 'virtual' station address for when both ports
1481 * are operating in failover mode. Currently we don't
1482 * use this extra address.
1483 */
1484 MSK_IF_LOCK(sc_if);
1485 for (i = 0; i < ETHER_ADDR_LEN; i++)
1486 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1487
1488 /*
1489 * Call MI attach routine. Can't hold locks when calling into ether_*.
1490 */
1491 MSK_IF_UNLOCK(sc_if);
1492 ether_ifattach(ifp, eaddr);
1493 MSK_IF_LOCK(sc_if);
1494
1495 /* VLAN capability setup */
1496 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1497 if (ifp->if_capabilities & IFCAP_HWCSUM)
1498 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1499 ifp->if_capenable = ifp->if_capabilities;
1500
1501 /*
1502 * Tell the upper layer(s) we support long frames.
1503 * Must appear after the call to ether_ifattach() because
1504 * ether_ifattach() sets ifi_hdrlen to the default value.
1505 */
1506 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1507
| 1468 ifp->if_capenable = ifp->if_capabilities;
1469 ifp->if_ioctl = msk_ioctl;
1470 ifp->if_start = msk_start;
1471 ifp->if_timer = 0;
1472 ifp->if_watchdog = NULL;
1473 ifp->if_init = msk_init;
1474 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1);
1475 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1;
1476 IFQ_SET_READY(&ifp->if_snd);
1477
1478 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp);
1479
1480 /*
1481 * Get station address for this interface. Note that
1482 * dual port cards actually come with three station
1483 * addresses: one for each port, plus an extra. The
1484 * extra one is used by the SysKonnect driver software
1485 * as a 'virtual' station address for when both ports
1486 * are operating in failover mode. Currently we don't
1487 * use this extra address.
1488 */
1489 MSK_IF_LOCK(sc_if);
1490 for (i = 0; i < ETHER_ADDR_LEN; i++)
1491 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1492
1493 /*
1494 * Call MI attach routine. Can't hold locks when calling into ether_*.
1495 */
1496 MSK_IF_UNLOCK(sc_if);
1497 ether_ifattach(ifp, eaddr);
1498 MSK_IF_LOCK(sc_if);
1499
1500 /* VLAN capability setup */
1501 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1502 if (ifp->if_capabilities & IFCAP_HWCSUM)
1503 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1504 ifp->if_capenable = ifp->if_capabilities;
1505
1506 /*
1507 * Tell the upper layer(s) we support long frames.
1508 * Must appear after the call to ether_ifattach() because
1509 * ether_ifattach() sets ifi_hdrlen to the default value.
1510 */
1511 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1512
|
| 1513 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN +
1514 ETHER_VLAN_ENCAP_LEN;
1515
|
1508 /*
1509 * Do miibus setup.
1510 */
1511 MSK_IF_UNLOCK(sc_if);
1512 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange,
1513 msk_mediastatus);
1514 if (error != 0) {
1515 device_printf(sc_if->msk_if_dev, "no PHY found!\n");
1516 ether_ifdetach(ifp);
1517 error = ENXIO;
1518 goto fail;
1519 }
1520 /* Check whether PHY Id is MARVELL. */
1521 if (msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_ID0)
1522 == PHY_MARV_ID0_VAL)
1523 sc->msk_marvell_phy = 1;
1524
1525fail:
1526 if (error != 0) {
1527 /* Access should be ok even though lock has been dropped */
1528 sc->msk_if[port] = NULL;
1529 msk_detach(dev);
1530 }
1531
1532 return (error);
1533}
1534
1535/*
1536 * Attach the interface. Allocate softc structures, do ifmedia
1537 * setup and ethernet/BPF attach.
1538 */
1539static int
1540mskc_attach(device_t dev)
1541{
1542 struct msk_softc *sc;
1543 int error, msic, *port, reg;
1544
1545 sc = device_get_softc(dev);
1546 sc->msk_dev = dev;
1547 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1548 MTX_DEF);
1549
1550 /*
1551 * Map control/status registers.
1552 */
1553 pci_enable_busmaster(dev);
1554
1555 /* Allocate I/O resource */
1556#ifdef MSK_USEIOSPACE
1557 sc->msk_res_spec = msk_res_spec_io;
1558#else
1559 sc->msk_res_spec = msk_res_spec_mem;
1560#endif
1561 sc->msk_irq_spec = msk_irq_spec_legacy;
1562 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1563 if (error) {
1564 if (sc->msk_res_spec == msk_res_spec_mem)
1565 sc->msk_res_spec = msk_res_spec_io;
1566 else
1567 sc->msk_res_spec = msk_res_spec_mem;
1568 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1569 if (error) {
1570 device_printf(dev, "couldn't allocate %s resources\n",
1571 sc->msk_res_spec == msk_res_spec_mem ? "memory" :
1572 "I/O");
1573 mtx_destroy(&sc->msk_mtx);
1574 return (ENXIO);
1575 }
1576 }
1577
1578 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1579 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1580 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1581 /* Bail out if chip is not recognized. */
1582 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1583 sc->msk_hw_id > CHIP_ID_YUKON_FE) {
1584 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
1585 sc->msk_hw_id, sc->msk_hw_rev);
1586 mtx_destroy(&sc->msk_mtx);
1587 return (ENXIO);
1588 }
1589
1590 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1591 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1592 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
1593 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I",
1594 "max number of Rx events to process");
1595
1596 sc->msk_process_limit = MSK_PROC_DEFAULT;
1597 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1598 "process_limit", &sc->msk_process_limit);
1599 if (error == 0) {
1600 if (sc->msk_process_limit < MSK_PROC_MIN ||
1601 sc->msk_process_limit > MSK_PROC_MAX) {
1602 device_printf(dev, "process_limit value out of range; "
1603 "using default: %d\n", MSK_PROC_DEFAULT);
1604 sc->msk_process_limit = MSK_PROC_DEFAULT;
1605 }
1606 }
1607
1608 /* Soft reset. */
1609 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1610 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1611 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1612 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1613 sc->msk_coppertype = 0;
1614 else
1615 sc->msk_coppertype = 1;
1616 /* Check number of MACs. */
1617 sc->msk_num_port = 1;
1618 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1619 CFG_DUAL_MAC_MSK) {
1620 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1621 sc->msk_num_port++;
1622 }
1623
1624 /* Check bus type. */
1625 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0)
1626 sc->msk_bustype = MSK_PEX_BUS;
1627 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0)
1628 sc->msk_bustype = MSK_PCIX_BUS;
1629 else
1630 sc->msk_bustype = MSK_PCI_BUS;
1631
1632 /* Get H/W features(bugs). */
1633 switch (sc->msk_hw_id) {
1634 case CHIP_ID_YUKON_EC:
1635 sc->msk_clock = 125; /* 125 Mhz */
1636 if (sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1637 sc->msk_hw_feature =
1638 HWF_WA_DEV_42 | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 |
1639 HWF_WA_DEV_420 | HWF_WA_DEV_423 |
1640 HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
1641 HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1642 HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1643 } else {
1644 /* A2/A3 */
1645 sc->msk_hw_feature =
1646 HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
1647 HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1648 HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1649 }
1650 break;
1651 case CHIP_ID_YUKON_EC_U:
1652 sc->msk_clock = 125; /* 125 Mhz */
1653 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
1654 sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_483 |
1655 HWF_WA_DEV_4109;
1656 } else if (sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1657 uint16_t v;
1658
1659 sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
1660 HWF_WA_DEV_4185;
1661 v = CSR_READ_2(sc, Q_ADDR(Q_XA1, Q_WM));
1662 if (v == 0)
1663 sc->msk_hw_feature |= HWF_WA_DEV_4185CS |
1664 HWF_WA_DEV_4200;
1665 }
1666 break;
1667 case CHIP_ID_YUKON_FE:
1668 sc->msk_clock = 100; /* 100 Mhz */
1669 sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
1670 HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1671 break;
1672 case CHIP_ID_YUKON_XL:
1673 sc->msk_clock = 156; /* 156 Mhz */
1674 switch (sc->msk_hw_rev) {
1675 case CHIP_REV_YU_XL_A0:
1676 sc->msk_hw_feature =
1677 HWF_WA_DEV_427 | HWF_WA_DEV_463 | HWF_WA_DEV_472 |
1678 HWF_WA_DEV_479 | HWF_WA_DEV_483 | HWF_WA_DEV_4115 |
1679 HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1680 break;
1681 case CHIP_REV_YU_XL_A1:
1682 sc->msk_hw_feature =
1683 HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1684 HWF_WA_DEV_4115 | HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1685 break;
1686 case CHIP_REV_YU_XL_A2:
1687 sc->msk_hw_feature =
1688 HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1689 HWF_WA_DEV_4115 | HWF_WA_DEV_4167;
1690 break;
1691 case CHIP_REV_YU_XL_A3:
1692 sc->msk_hw_feature =
1693 HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1694 HWF_WA_DEV_4115;
1695 }
1696 break;
1697 default:
1698 sc->msk_clock = 156; /* 156 Mhz */
1699 sc->msk_hw_feature = 0;
1700 }
1701
1702 /* Allocate IRQ resources. */
1703 msic = pci_msi_count(dev);
1704 if (bootverbose)
1705 device_printf(dev, "MSI count : %d\n", msic);
1706 /*
1707 * The Yukon II reports it can handle two messages, one for each
1708 * possible port. We go ahead and allocate two messages and only
1709 * setup a handler for both if we have a dual port card.
1710 *
1711 * XXX: I haven't untangled the interrupt handler to handle dual
1712 * port cards with separate MSI messages, so for now I disable MSI
1713 * on dual port cards.
1714 */
1715 if (legacy_intr != 0)
1716 msi_disable = 1;
1717 if (msic == 2 && msi_disable == 0 && sc->msk_num_port == 1 &&
1718 pci_alloc_msi(dev, &msic) == 0) {
1719 if (msic == 2) {
1720 sc->msk_msi = 1;
1721 sc->msk_irq_spec = msk_irq_spec_msi;
1722 } else
1723 pci_release_msi(dev);
1724 }
1725
1726 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1727 if (error) {
1728 device_printf(dev, "couldn't allocate IRQ resources\n");
1729 goto fail;
1730 }
1731
1732 if ((error = msk_status_dma_alloc(sc)) != 0)
1733 goto fail;
1734
1735 /* Set base interrupt mask. */
1736 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1737 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1738 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1739
1740 /* Reset the adapter. */
1741 mskc_reset(sc);
1742
1743 if ((error = mskc_setup_rambuffer(sc)) != 0)
1744 goto fail;
1745
1746 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1);
1747 if (sc->msk_devs[MSK_PORT_A] == NULL) {
1748 device_printf(dev, "failed to add child for PORT_A\n");
1749 error = ENXIO;
1750 goto fail;
1751 }
1752 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1753 if (port == NULL) {
1754 device_printf(dev, "failed to allocate memory for "
1755 "ivars of PORT_A\n");
1756 error = ENXIO;
1757 goto fail;
1758 }
1759 *port = MSK_PORT_A;
1760 device_set_ivars(sc->msk_devs[MSK_PORT_A], port);
1761
1762 if (sc->msk_num_port > 1) {
1763 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1);
1764 if (sc->msk_devs[MSK_PORT_B] == NULL) {
1765 device_printf(dev, "failed to add child for PORT_B\n");
1766 error = ENXIO;
1767 goto fail;
1768 }
1769 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1770 if (port == NULL) {
1771 device_printf(dev, "failed to allocate memory for "
1772 "ivars of PORT_B\n");
1773 error = ENXIO;
1774 goto fail;
1775 }
1776 *port = MSK_PORT_B;
1777 device_set_ivars(sc->msk_devs[MSK_PORT_B], port);
1778 }
1779
1780 error = bus_generic_attach(dev);
1781 if (error) {
1782 device_printf(dev, "failed to attach port(s)\n");
1783 goto fail;
1784 }
1785
1786 /* Hook interrupt last to avoid having to lock softc. */
1787 if (legacy_intr)
1788 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1789 INTR_MPSAFE, NULL, msk_legacy_intr, sc,
1790 &sc->msk_intrhand[0]);
1791 else {
1792 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc);
1793 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK,
1794 taskqueue_thread_enqueue, &sc->msk_tq);
1795 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq",
1796 device_get_nameunit(sc->msk_dev));
1797 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1798 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]);
1799 }
1800
1801 if (error != 0) {
1802 device_printf(dev, "couldn't set up interrupt handler\n");
1803 if (legacy_intr == 0)
1804 taskqueue_free(sc->msk_tq);
1805 sc->msk_tq = NULL;
1806 goto fail;
1807 }
1808fail:
1809 if (error != 0)
1810 mskc_detach(dev);
1811
1812 return (error);
1813}
1814
1815/*
1816 * Shutdown hardware and free up resources. This can be called any
1817 * time after the mutex has been initialized. It is called in both
1818 * the error case in attach and the normal detach case so it needs
1819 * to be careful about only freeing resources that have actually been
1820 * allocated.
1821 */
1822static int
1823msk_detach(device_t dev)
1824{
1825 struct msk_softc *sc;
1826 struct msk_if_softc *sc_if;
1827 struct ifnet *ifp;
1828
1829 sc_if = device_get_softc(dev);
1830 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx),
1831 ("msk mutex not initialized in msk_detach"));
1832 MSK_IF_LOCK(sc_if);
1833
1834 ifp = sc_if->msk_ifp;
1835 if (device_is_attached(dev)) {
1836 /* XXX */
1837 sc_if->msk_detach = 1;
1838 msk_stop(sc_if);
1839 /* Can't hold locks while calling detach. */
1840 MSK_IF_UNLOCK(sc_if);
1841 callout_drain(&sc_if->msk_tick_ch);
1842 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task);
1843 taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task);
1844 ether_ifdetach(ifp);
1845 MSK_IF_LOCK(sc_if);
1846 }
1847
1848 /*
1849 * We're generally called from mskc_detach() which is using
1850 * device_delete_child() to get to here. It's already trashed
1851 * miibus for us, so don't do it here or we'll panic.
1852 *
1853 * if (sc_if->msk_miibus != NULL) {
1854 * device_delete_child(dev, sc_if->msk_miibus);
1855 * sc_if->msk_miibus = NULL;
1856 * }
1857 */
1858
1859 msk_txrx_dma_free(sc_if);
1860 bus_generic_detach(dev);
1861
1862 if (ifp)
1863 if_free(ifp);
1864 sc = sc_if->msk_softc;
1865 sc->msk_if[sc_if->msk_port] = NULL;
1866 MSK_IF_UNLOCK(sc_if);
1867
1868 return (0);
1869}
1870
1871static int
1872mskc_detach(device_t dev)
1873{
1874 struct msk_softc *sc;
1875
1876 sc = device_get_softc(dev);
1877 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized"));
1878
1879 if (device_is_alive(dev)) {
1880 if (sc->msk_devs[MSK_PORT_A] != NULL) {
1881 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]),
1882 M_DEVBUF);
1883 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]);
1884 }
1885 if (sc->msk_devs[MSK_PORT_B] != NULL) {
1886 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]),
1887 M_DEVBUF);
1888 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]);
1889 }
1890 bus_generic_detach(dev);
1891 }
1892
1893 /* Disable all interrupts. */
1894 CSR_WRITE_4(sc, B0_IMSK, 0);
1895 CSR_READ_4(sc, B0_IMSK);
1896 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1897 CSR_READ_4(sc, B0_HWE_IMSK);
1898
1899 /* LED Off. */
1900 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
1901
1902 /* Put hardware reset. */
1903 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1904
1905 msk_status_dma_free(sc);
1906
1907 if (legacy_intr == 0 && sc->msk_tq != NULL) {
1908 taskqueue_drain(sc->msk_tq, &sc->msk_int_task);
1909 taskqueue_free(sc->msk_tq);
1910 sc->msk_tq = NULL;
1911 }
1912 if (sc->msk_intrhand[0]) {
1913 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]);
1914 sc->msk_intrhand[0] = NULL;
1915 }
1916 if (sc->msk_intrhand[1]) {
1917 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]);
1918 sc->msk_intrhand[1] = NULL;
1919 }
1920 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1921 if (sc->msk_msi)
1922 pci_release_msi(dev);
1923 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res);
1924 mtx_destroy(&sc->msk_mtx);
1925
1926 return (0);
1927}
1928
1929struct msk_dmamap_arg {
1930 bus_addr_t msk_busaddr;
1931};
1932
1933static void
1934msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1935{
1936 struct msk_dmamap_arg *ctx;
1937
1938 if (error != 0)
1939 return;
1940 ctx = arg;
1941 ctx->msk_busaddr = segs[0].ds_addr;
1942}
1943
1944/* Create status DMA region. */
1945static int
1946msk_status_dma_alloc(struct msk_softc *sc)
1947{
1948 struct msk_dmamap_arg ctx;
1949 int error;
1950
1951 error = bus_dma_tag_create(
1952 bus_get_dma_tag(sc->msk_dev), /* parent */
1953 MSK_STAT_ALIGN, 0, /* alignment, boundary */
1954 BUS_SPACE_MAXADDR, /* lowaddr */
1955 BUS_SPACE_MAXADDR, /* highaddr */
1956 NULL, NULL, /* filter, filterarg */
1957 MSK_STAT_RING_SZ, /* maxsize */
1958 1, /* nsegments */
1959 MSK_STAT_RING_SZ, /* maxsegsize */
1960 0, /* flags */
1961 NULL, NULL, /* lockfunc, lockarg */
1962 &sc->msk_stat_tag);
1963 if (error != 0) {
1964 device_printf(sc->msk_dev,
1965 "failed to create status DMA tag\n");
1966 return (error);
1967 }
1968
1969 /* Allocate DMA'able memory and load the DMA map for status ring. */
1970 error = bus_dmamem_alloc(sc->msk_stat_tag,
1971 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
1972 BUS_DMA_ZERO, &sc->msk_stat_map);
1973 if (error != 0) {
1974 device_printf(sc->msk_dev,
1975 "failed to allocate DMA'able memory for status ring\n");
1976 return (error);
1977 }
1978
1979 ctx.msk_busaddr = 0;
1980 error = bus_dmamap_load(sc->msk_stat_tag,
1981 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ,
1982 msk_dmamap_cb, &ctx, 0);
1983 if (error != 0) {
1984 device_printf(sc->msk_dev,
1985 "failed to load DMA'able memory for status ring\n");
1986 return (error);
1987 }
1988 sc->msk_stat_ring_paddr = ctx.msk_busaddr;
1989
1990 return (0);
1991}
1992
1993static void
1994msk_status_dma_free(struct msk_softc *sc)
1995{
1996
1997 /* Destroy status block. */
1998 if (sc->msk_stat_tag) {
1999 if (sc->msk_stat_map) {
2000 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
2001 if (sc->msk_stat_ring) {
2002 bus_dmamem_free(sc->msk_stat_tag,
2003 sc->msk_stat_ring, sc->msk_stat_map);
2004 sc->msk_stat_ring = NULL;
2005 }
2006 sc->msk_stat_map = NULL;
2007 }
2008 bus_dma_tag_destroy(sc->msk_stat_tag);
2009 sc->msk_stat_tag = NULL;
2010 }
2011}
2012
2013static int
2014msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
2015{
2016 struct msk_dmamap_arg ctx;
2017 struct msk_txdesc *txd;
2018 struct msk_rxdesc *rxd;
2019 struct msk_rxdesc *jrxd;
2020 struct msk_jpool_entry *entry;
2021 uint8_t *ptr;
2022 int error, i;
2023
2024 mtx_init(&sc_if->msk_jlist_mtx, "msk_jlist_mtx", NULL, MTX_DEF);
2025 SLIST_INIT(&sc_if->msk_jfree_listhead);
2026 SLIST_INIT(&sc_if->msk_jinuse_listhead);
2027
2028 /* Create parent DMA tag. */
2029 /*
2030 * XXX
2031 * It seems that Yukon II supports full 64bits DMA operations. But
2032 * it needs two descriptors(list elements) for 64bits DMA operations.
2033 * Since we don't know what DMA address mappings(32bits or 64bits)
2034 * would be used in advance for each mbufs, we limits its DMA space
2035 * to be in range of 32bits address space. Otherwise, we should check
2036 * what DMA address is used and chain another descriptor for the
2037 * 64bits DMA operation. This also means descriptor ring size is
2038 * variable. Limiting DMA address to be in 32bit address space greatly
2039 * simplyfies descriptor handling and possibly would increase
2040 * performance a bit due to efficient handling of descriptors.
2041 * Apart from harassing checksum offloading mechanisms, it seems
2042 * it's really bad idea to use a seperate descriptor for 64bit
2043 * DMA operation to save small descriptor memory. Anyway, I've
2044 * never seen these exotic scheme on ethernet interface hardware.
2045 */
2046 error = bus_dma_tag_create(
2047 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */
2048 1, 0, /* alignment, boundary */
2049 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2050 BUS_SPACE_MAXADDR, /* highaddr */
2051 NULL, NULL, /* filter, filterarg */
2052 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
2053 0, /* nsegments */
2054 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2055 0, /* flags */
2056 NULL, NULL, /* lockfunc, lockarg */
2057 &sc_if->msk_cdata.msk_parent_tag);
2058 if (error != 0) {
2059 device_printf(sc_if->msk_if_dev,
2060 "failed to create parent DMA tag\n");
2061 goto fail;
2062 }
2063 /* Create tag for Tx ring. */
2064 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2065 MSK_RING_ALIGN, 0, /* alignment, boundary */
2066 BUS_SPACE_MAXADDR, /* lowaddr */
2067 BUS_SPACE_MAXADDR, /* highaddr */
2068 NULL, NULL, /* filter, filterarg */
2069 MSK_TX_RING_SZ, /* maxsize */
2070 1, /* nsegments */
2071 MSK_TX_RING_SZ, /* maxsegsize */
2072 0, /* flags */
2073 NULL, NULL, /* lockfunc, lockarg */
2074 &sc_if->msk_cdata.msk_tx_ring_tag);
2075 if (error != 0) {
2076 device_printf(sc_if->msk_if_dev,
2077 "failed to create Tx ring DMA tag\n");
2078 goto fail;
2079 }
2080
2081 /* Create tag for Rx ring. */
2082 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2083 MSK_RING_ALIGN, 0, /* alignment, boundary */
2084 BUS_SPACE_MAXADDR, /* lowaddr */
2085 BUS_SPACE_MAXADDR, /* highaddr */
2086 NULL, NULL, /* filter, filterarg */
2087 MSK_RX_RING_SZ, /* maxsize */
2088 1, /* nsegments */
2089 MSK_RX_RING_SZ, /* maxsegsize */
2090 0, /* flags */
2091 NULL, NULL, /* lockfunc, lockarg */
2092 &sc_if->msk_cdata.msk_rx_ring_tag);
2093 if (error != 0) {
2094 device_printf(sc_if->msk_if_dev,
2095 "failed to create Rx ring DMA tag\n");
2096 goto fail;
2097 }
2098
2099 /* Create tag for jumbo Rx ring. */
2100 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2101 MSK_RING_ALIGN, 0, /* alignment, boundary */
2102 BUS_SPACE_MAXADDR, /* lowaddr */
2103 BUS_SPACE_MAXADDR, /* highaddr */
2104 NULL, NULL, /* filter, filterarg */
2105 MSK_JUMBO_RX_RING_SZ, /* maxsize */
2106 1, /* nsegments */
2107 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */
2108 0, /* flags */
2109 NULL, NULL, /* lockfunc, lockarg */
2110 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2111 if (error != 0) {
2112 device_printf(sc_if->msk_if_dev,
2113 "failed to create jumbo Rx ring DMA tag\n");
2114 goto fail;
2115 }
2116
2117 /* Create tag for jumbo buffer blocks. */
2118 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2119 PAGE_SIZE, 0, /* alignment, boundary */
2120 BUS_SPACE_MAXADDR, /* lowaddr */
2121 BUS_SPACE_MAXADDR, /* highaddr */
2122 NULL, NULL, /* filter, filterarg */
2123 MSK_JMEM, /* maxsize */
2124 1, /* nsegments */
2125 MSK_JMEM, /* maxsegsize */
2126 0, /* flags */
2127 NULL, NULL, /* lockfunc, lockarg */
2128 &sc_if->msk_cdata.msk_jumbo_tag);
2129 if (error != 0) {
2130 device_printf(sc_if->msk_if_dev,
2131 "failed to create jumbo Rx buffer block DMA tag\n");
2132 goto fail;
2133 }
2134
2135 /* Create tag for Tx buffers. */
2136 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2137 1, 0, /* alignment, boundary */
2138 BUS_SPACE_MAXADDR, /* lowaddr */
2139 BUS_SPACE_MAXADDR, /* highaddr */
2140 NULL, NULL, /* filter, filterarg */
2141 MSK_TSO_MAXSIZE, /* maxsize */
2142 MSK_MAXTXSEGS, /* nsegments */
2143 MSK_TSO_MAXSGSIZE, /* maxsegsize */
2144 0, /* flags */
2145 NULL, NULL, /* lockfunc, lockarg */
2146 &sc_if->msk_cdata.msk_tx_tag);
2147 if (error != 0) {
2148 device_printf(sc_if->msk_if_dev,
2149 "failed to create Tx DMA tag\n");
2150 goto fail;
2151 }
2152
2153 /* Create tag for Rx buffers. */
2154 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2155 1, 0, /* alignment, boundary */
2156 BUS_SPACE_MAXADDR, /* lowaddr */
2157 BUS_SPACE_MAXADDR, /* highaddr */
2158 NULL, NULL, /* filter, filterarg */
2159 MCLBYTES, /* maxsize */
2160 1, /* nsegments */
2161 MCLBYTES, /* maxsegsize */
2162 0, /* flags */
2163 NULL, NULL, /* lockfunc, lockarg */
2164 &sc_if->msk_cdata.msk_rx_tag);
2165 if (error != 0) {
2166 device_printf(sc_if->msk_if_dev,
2167 "failed to create Rx DMA tag\n");
2168 goto fail;
2169 }
2170
2171 /* Create tag for jumbo Rx buffers. */
2172 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2173 PAGE_SIZE, 0, /* alignment, boundary */
2174 BUS_SPACE_MAXADDR, /* lowaddr */
2175 BUS_SPACE_MAXADDR, /* highaddr */
2176 NULL, NULL, /* filter, filterarg */
2177 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */
2178 MSK_MAXRXSEGS, /* nsegments */
2179 MSK_JLEN, /* maxsegsize */
2180 0, /* flags */
2181 NULL, NULL, /* lockfunc, lockarg */
2182 &sc_if->msk_cdata.msk_jumbo_rx_tag);
2183 if (error != 0) {
2184 device_printf(sc_if->msk_if_dev,
2185 "failed to create jumbo Rx DMA tag\n");
2186 goto fail;
2187 }
2188
2189 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2190 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag,
2191 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK |
2192 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map);
2193 if (error != 0) {
2194 device_printf(sc_if->msk_if_dev,
2195 "failed to allocate DMA'able memory for Tx ring\n");
2196 goto fail;
2197 }
2198
2199 ctx.msk_busaddr = 0;
2200 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag,
2201 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring,
2202 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0);
2203 if (error != 0) {
2204 device_printf(sc_if->msk_if_dev,
2205 "failed to load DMA'able memory for Tx ring\n");
2206 goto fail;
2207 }
2208 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr;
2209
2210 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2211 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag,
2212 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK |
2213 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map);
2214 if (error != 0) {
2215 device_printf(sc_if->msk_if_dev,
2216 "failed to allocate DMA'able memory for Rx ring\n");
2217 goto fail;
2218 }
2219
2220 ctx.msk_busaddr = 0;
2221 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag,
2222 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring,
2223 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0);
2224 if (error != 0) {
2225 device_printf(sc_if->msk_if_dev,
2226 "failed to load DMA'able memory for Rx ring\n");
2227 goto fail;
2228 }
2229 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr;
2230
2231 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
2232 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2233 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2234 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2235 &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2236 if (error != 0) {
2237 device_printf(sc_if->msk_if_dev,
2238 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2239 goto fail;
2240 }
2241
2242 ctx.msk_busaddr = 0;
2243 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2244 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2245 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2246 msk_dmamap_cb, &ctx, 0);
2247 if (error != 0) {
2248 device_printf(sc_if->msk_if_dev,
2249 "failed to load DMA'able memory for jumbo Rx ring\n");
2250 goto fail;
2251 }
2252 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2253
2254 /* Create DMA maps for Tx buffers. */
2255 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2256 txd = &sc_if->msk_cdata.msk_txdesc[i];
2257 txd->tx_m = NULL;
2258 txd->tx_dmamap = NULL;
2259 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
2260 &txd->tx_dmamap);
2261 if (error != 0) {
2262 device_printf(sc_if->msk_if_dev,
2263 "failed to create Tx dmamap\n");
2264 goto fail;
2265 }
2266 }
2267 /* Create DMA maps for Rx buffers. */
2268 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2269 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) {
2270 device_printf(sc_if->msk_if_dev,
2271 "failed to create spare Rx dmamap\n");
2272 goto fail;
2273 }
2274 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2275 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2276 rxd->rx_m = NULL;
2277 rxd->rx_dmamap = NULL;
2278 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2279 &rxd->rx_dmamap);
2280 if (error != 0) {
2281 device_printf(sc_if->msk_if_dev,
2282 "failed to create Rx dmamap\n");
2283 goto fail;
2284 }
2285 }
2286 /* Create DMA maps for jumbo Rx buffers. */
2287 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2288 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2289 device_printf(sc_if->msk_if_dev,
2290 "failed to create spare jumbo Rx dmamap\n");
2291 goto fail;
2292 }
2293 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2294 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2295 jrxd->rx_m = NULL;
2296 jrxd->rx_dmamap = NULL;
2297 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2298 &jrxd->rx_dmamap);
2299 if (error != 0) {
2300 device_printf(sc_if->msk_if_dev,
2301 "failed to create jumbo Rx dmamap\n");
2302 goto fail;
2303 }
2304 }
2305
2306 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */
2307 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag,
2308 (void **)&sc_if->msk_rdata.msk_jumbo_buf,
2309 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2310 &sc_if->msk_cdata.msk_jumbo_map);
2311 if (error != 0) {
2312 device_printf(sc_if->msk_if_dev,
2313 "failed to allocate DMA'able memory for jumbo buf\n");
2314 goto fail;
2315 }
2316
2317 ctx.msk_busaddr = 0;
2318 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag,
2319 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf,
2320 MSK_JMEM, msk_dmamap_cb, &ctx, 0);
2321 if (error != 0) {
2322 device_printf(sc_if->msk_if_dev,
2323 "failed to load DMA'able memory for jumbobuf\n");
2324 goto fail;
2325 }
2326 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr;
2327
2328 /*
2329 * Now divide it up into 9K pieces and save the addresses
2330 * in an array.
2331 */
2332 ptr = sc_if->msk_rdata.msk_jumbo_buf;
2333 for (i = 0; i < MSK_JSLOTS; i++) {
2334 sc_if->msk_cdata.msk_jslots[i] = ptr;
2335 ptr += MSK_JLEN;
2336 entry = malloc(sizeof(struct msk_jpool_entry),
2337 M_DEVBUF, M_WAITOK);
2338 if (entry == NULL) {
2339 device_printf(sc_if->msk_if_dev,
2340 "no memory for jumbo buffers!\n");
2341 error = ENOMEM;
2342 goto fail;
2343 }
2344 entry->slot = i;
2345 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry,
2346 jpool_entries);
2347 }
2348
2349fail:
2350 return (error);
2351}
2352
2353static void
2354msk_txrx_dma_free(struct msk_if_softc *sc_if)
2355{
2356 struct msk_txdesc *txd;
2357 struct msk_rxdesc *rxd;
2358 struct msk_rxdesc *jrxd;
2359 struct msk_jpool_entry *entry;
2360 int i;
2361
2362 MSK_JLIST_LOCK(sc_if);
2363 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) {
2364 device_printf(sc_if->msk_if_dev,
2365 "asked to free buffer that is in use!\n");
2366 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries);
2367 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry,
2368 jpool_entries);
2369 }
2370
2371 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) {
2372 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead);
2373 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries);
2374 free(entry, M_DEVBUF);
2375 }
2376 MSK_JLIST_UNLOCK(sc_if);
2377
2378 /* Destroy jumbo buffer block. */
2379 if (sc_if->msk_cdata.msk_jumbo_map)
2380 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag,
2381 sc_if->msk_cdata.msk_jumbo_map);
2382
2383 if (sc_if->msk_rdata.msk_jumbo_buf) {
2384 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag,
2385 sc_if->msk_rdata.msk_jumbo_buf,
2386 sc_if->msk_cdata.msk_jumbo_map);
2387 sc_if->msk_rdata.msk_jumbo_buf = NULL;
2388 sc_if->msk_cdata.msk_jumbo_map = NULL;
2389 }
2390
2391 /* Tx ring. */
2392 if (sc_if->msk_cdata.msk_tx_ring_tag) {
2393 if (sc_if->msk_cdata.msk_tx_ring_map)
2394 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag,
2395 sc_if->msk_cdata.msk_tx_ring_map);
2396 if (sc_if->msk_cdata.msk_tx_ring_map &&
2397 sc_if->msk_rdata.msk_tx_ring)
2398 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag,
2399 sc_if->msk_rdata.msk_tx_ring,
2400 sc_if->msk_cdata.msk_tx_ring_map);
2401 sc_if->msk_rdata.msk_tx_ring = NULL;
2402 sc_if->msk_cdata.msk_tx_ring_map = NULL;
2403 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag);
2404 sc_if->msk_cdata.msk_tx_ring_tag = NULL;
2405 }
2406 /* Rx ring. */
2407 if (sc_if->msk_cdata.msk_rx_ring_tag) {
2408 if (sc_if->msk_cdata.msk_rx_ring_map)
2409 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag,
2410 sc_if->msk_cdata.msk_rx_ring_map);
2411 if (sc_if->msk_cdata.msk_rx_ring_map &&
2412 sc_if->msk_rdata.msk_rx_ring)
2413 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag,
2414 sc_if->msk_rdata.msk_rx_ring,
2415 sc_if->msk_cdata.msk_rx_ring_map);
2416 sc_if->msk_rdata.msk_rx_ring = NULL;
2417 sc_if->msk_cdata.msk_rx_ring_map = NULL;
2418 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag);
2419 sc_if->msk_cdata.msk_rx_ring_tag = NULL;
2420 }
2421 /* Jumbo Rx ring. */
2422 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2423 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map)
2424 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2425 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2426 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map &&
2427 sc_if->msk_rdata.msk_jumbo_rx_ring)
2428 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2429 sc_if->msk_rdata.msk_jumbo_rx_ring,
2430 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2431 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2432 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL;
2433 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2434 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2435 }
2436 /* Tx buffers. */
2437 if (sc_if->msk_cdata.msk_tx_tag) {
2438 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2439 txd = &sc_if->msk_cdata.msk_txdesc[i];
2440 if (txd->tx_dmamap) {
2441 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2442 txd->tx_dmamap);
2443 txd->tx_dmamap = NULL;
2444 }
2445 }
2446 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2447 sc_if->msk_cdata.msk_tx_tag = NULL;
2448 }
2449 /* Rx buffers. */
2450 if (sc_if->msk_cdata.msk_rx_tag) {
2451 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2452 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2453 if (rxd->rx_dmamap) {
2454 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2455 rxd->rx_dmamap);
2456 rxd->rx_dmamap = NULL;
2457 }
2458 }
2459 if (sc_if->msk_cdata.msk_rx_sparemap) {
2460 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2461 sc_if->msk_cdata.msk_rx_sparemap);
2462 sc_if->msk_cdata.msk_rx_sparemap = 0;
2463 }
2464 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2465 sc_if->msk_cdata.msk_rx_tag = NULL;
2466 }
2467 /* Jumbo Rx buffers. */
2468 if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2469 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2470 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2471 if (jrxd->rx_dmamap) {
2472 bus_dmamap_destroy(
2473 sc_if->msk_cdata.msk_jumbo_rx_tag,
2474 jrxd->rx_dmamap);
2475 jrxd->rx_dmamap = NULL;
2476 }
2477 }
2478 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2479 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2480 sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2481 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2482 }
2483 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2484 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2485 }
2486
2487 if (sc_if->msk_cdata.msk_parent_tag) {
2488 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2489 sc_if->msk_cdata.msk_parent_tag = NULL;
2490 }
2491 mtx_destroy(&sc_if->msk_jlist_mtx);
2492}
2493
2494/*
2495 * Allocate a jumbo buffer.
2496 */
2497static void *
2498msk_jalloc(struct msk_if_softc *sc_if)
2499{
2500 struct msk_jpool_entry *entry;
2501
2502 MSK_JLIST_LOCK(sc_if);
2503
2504 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead);
2505
2506 if (entry == NULL) {
2507 MSK_JLIST_UNLOCK(sc_if);
2508 return (NULL);
2509 }
2510
2511 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries);
2512 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries);
2513
2514 MSK_JLIST_UNLOCK(sc_if);
2515
2516 return (sc_if->msk_cdata.msk_jslots[entry->slot]);
2517}
2518
2519/*
2520 * Release a jumbo buffer.
2521 */
2522static void
2523msk_jfree(void *buf, void *args)
2524{
2525 struct msk_if_softc *sc_if;
2526 struct msk_jpool_entry *entry;
2527 int i;
2528
2529 /* Extract the softc struct pointer. */
2530 sc_if = (struct msk_if_softc *)args;
2531 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__));
2532
2533 MSK_JLIST_LOCK(sc_if);
2534 /* Calculate the slot this buffer belongs to. */
2535 i = ((vm_offset_t)buf
2536 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN;
2537 KASSERT(i >= 0 && i < MSK_JSLOTS,
2538 ("%s: asked to free buffer that we don't manage!", __func__));
2539
2540 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead);
2541 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__));
2542 entry->slot = i;
2543 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries);
2544 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries);
2545 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead))
2546 wakeup(sc_if);
2547
2548 MSK_JLIST_UNLOCK(sc_if);
2549}
2550
2551/*
2552 * It's copy of ath_defrag(ath(4)).
2553 *
2554 * Defragment an mbuf chain, returning at most maxfrags separate
2555 * mbufs+clusters. If this is not possible NULL is returned and
2556 * the original mbuf chain is left in it's present (potentially
2557 * modified) state. We use two techniques: collapsing consecutive
2558 * mbufs and replacing consecutive mbufs by a cluster.
2559 */
2560static struct mbuf *
2561msk_defrag(struct mbuf *m0, int how, int maxfrags)
2562{
2563 struct mbuf *m, *n, *n2, **prev;
2564 u_int curfrags;
2565
2566 /*
2567 * Calculate the current number of frags.
2568 */
2569 curfrags = 0;
2570 for (m = m0; m != NULL; m = m->m_next)
2571 curfrags++;
2572 /*
2573 * First, try to collapse mbufs. Note that we always collapse
2574 * towards the front so we don't need to deal with moving the
2575 * pkthdr. This may be suboptimal if the first mbuf has much
2576 * less data than the following.
2577 */
2578 m = m0;
2579again:
2580 for (;;) {
2581 n = m->m_next;
2582 if (n == NULL)
2583 break;
2584 if ((m->m_flags & M_RDONLY) == 0 &&
2585 n->m_len < M_TRAILINGSPACE(m)) {
2586 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
2587 n->m_len);
2588 m->m_len += n->m_len;
2589 m->m_next = n->m_next;
2590 m_free(n);
2591 if (--curfrags <= maxfrags)
2592 return (m0);
2593 } else
2594 m = n;
2595 }
2596 KASSERT(maxfrags > 1,
2597 ("maxfrags %u, but normal collapse failed", maxfrags));
2598 /*
2599 * Collapse consecutive mbufs to a cluster.
2600 */
2601 prev = &m0->m_next; /* NB: not the first mbuf */
2602 while ((n = *prev) != NULL) {
2603 if ((n2 = n->m_next) != NULL &&
2604 n->m_len + n2->m_len < MCLBYTES) {
2605 m = m_getcl(how, MT_DATA, 0);
2606 if (m == NULL)
2607 goto bad;
2608 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
2609 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
2610 n2->m_len);
2611 m->m_len = n->m_len + n2->m_len;
2612 m->m_next = n2->m_next;
2613 *prev = m;
2614 m_free(n);
2615 m_free(n2);
2616 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
2617 return m0;
2618 /*
2619 * Still not there, try the normal collapse
2620 * again before we allocate another cluster.
2621 */
2622 goto again;
2623 }
2624 prev = &n->m_next;
2625 }
2626 /*
2627 * No place where we can collapse to a cluster; punt.
2628 * This can occur if, for example, you request 2 frags
2629 * but the packet requires that both be clusters (we
2630 * never reallocate the first mbuf to avoid moving the
2631 * packet header).
2632 */
2633bad:
2634 return (NULL);
2635}
2636
2637static int
2638msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
2639{
2640 struct msk_txdesc *txd, *txd_last;
2641 struct msk_tx_desc *tx_le;
2642 struct mbuf *m;
2643 bus_dmamap_t map;
2644 bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
2645 uint32_t control, prod, si;
2646 uint16_t offset, tcp_offset, tso_mtu;
2647 int error, i, nseg, tso;
2648
2649 MSK_IF_LOCK_ASSERT(sc_if);
2650
2651 tcp_offset = offset = 0;
2652 m = *m_head;
2653 if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) {
2654 /*
2655 * Since mbuf has no protocol specific structure information
2656 * in it we have to inspect protocol information here to
2657 * setup TSO and checksum offload. I don't know why Marvell
2658 * made a such decision in chip design because other GigE
2659 * hardwares normally takes care of all these chores in
2660 * hardware. However, TSO performance of Yukon II is very
2661 * good such that it's worth to implement it.
2662 */
2663 struct ether_header *eh;
2664 struct ip *ip;
2665 struct tcphdr *tcp;
2666
2667 /* TODO check for M_WRITABLE(m) */
2668
2669 offset = sizeof(struct ether_header);
2670 m = m_pullup(m, offset);
2671 if (m == NULL) {
2672 *m_head = NULL;
2673 return (ENOBUFS);
2674 }
2675 eh = mtod(m, struct ether_header *);
2676 /* Check if hardware VLAN insertion is off. */
2677 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2678 offset = sizeof(struct ether_vlan_header);
2679 m = m_pullup(m, offset);
2680 if (m == NULL) {
2681 *m_head = NULL;
2682 return (ENOBUFS);
2683 }
2684 }
2685 m = m_pullup(m, offset + sizeof(struct ip));
2686 if (m == NULL) {
2687 *m_head = NULL;
2688 return (ENOBUFS);
2689 }
2690 ip = (struct ip *)(mtod(m, char *) + offset);
2691 offset += (ip->ip_hl << 2);
2692 tcp_offset = offset;
2693 /*
2694 * It seems that Yukon II has Tx checksum offload bug for
2695 * small TCP packets that's less than 60 bytes in size
2696 * (e.g. TCP window probe packet, pure ACK packet).
2697 * Common work around like padding with zeros to make the
2698 * frame minimum ethernet frame size didn't work at all.
2699 * Instead of disabling checksum offload completely we
2700 * resort to S/W checksum routine when we encounter short
2701 * TCP frames.
2702 * Short UDP packets appear to be handled correctly by
2703 * Yukon II.
2704 */
2705 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN &&
2706 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2707 uint16_t csum;
2708
2709 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset -
2710 (ip->ip_hl << 2), offset);
2711 *(uint16_t *)(m->m_data + offset +
2712 m->m_pkthdr.csum_data) = csum;
2713 m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2714 }
2715 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2716 m = m_pullup(m, offset + sizeof(struct tcphdr));
2717 if (m == NULL) {
2718 *m_head = NULL;
2719 return (ENOBUFS);
2720 }
2721 tcp = (struct tcphdr *)(mtod(m, char *) + offset);
2722 offset += (tcp->th_off << 2);
2723 }
2724 *m_head = m;
2725 }
2726
2727 prod = sc_if->msk_cdata.msk_tx_prod;
2728 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2729 txd_last = txd;
2730 map = txd->tx_dmamap;
2731 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map,
2732 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2733 if (error == EFBIG) {
2734 m = msk_defrag(*m_head, M_DONTWAIT, MSK_MAXTXSEGS);
2735 if (m == NULL) {
2736 m_freem(*m_head);
2737 *m_head = NULL;
2738 return (ENOBUFS);
2739 }
2740 *m_head = m;
2741 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag,
2742 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2743 if (error != 0) {
2744 m_freem(*m_head);
2745 *m_head = NULL;
2746 return (error);
2747 }
2748 } else if (error != 0)
2749 return (error);
2750 if (nseg == 0) {
2751 m_freem(*m_head);
2752 *m_head = NULL;
2753 return (EIO);
2754 }
2755
2756 /* Check number of available descriptors. */
2757 if (sc_if->msk_cdata.msk_tx_cnt + nseg >=
2758 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
2759 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2760 return (ENOBUFS);
2761 }
2762
2763 control = 0;
2764 tso = 0;
2765 tx_le = NULL;
2766
2767 /* Check TSO support. */
2768 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2769 tso_mtu = offset + m->m_pkthdr.tso_segsz;
2770 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
2771 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2772 tx_le->msk_addr = htole32(tso_mtu);
2773 tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER);
2774 sc_if->msk_cdata.msk_tx_cnt++;
2775 MSK_INC(prod, MSK_TX_RING_CNT);
2776 sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
2777 }
2778 tso++;
2779 }
2780 /* Check if we have a VLAN tag to insert. */
2781 if ((m->m_flags & M_VLANTAG) != 0) {
2782 if (tso == 0) {
2783 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2784 tx_le->msk_addr = htole32(0);
2785 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2786 htons(m->m_pkthdr.ether_vtag));
2787 sc_if->msk_cdata.msk_tx_cnt++;
2788 MSK_INC(prod, MSK_TX_RING_CNT);
2789 } else {
2790 tx_le->msk_control |= htole32(OP_VLAN |
2791 htons(m->m_pkthdr.ether_vtag));
2792 }
2793 control |= INS_VLAN;
2794 }
2795 /* Check if we have to handle checksum offload. */
2796 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
2797 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2798 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data)
2799 & 0xffff) | ((uint32_t)tcp_offset << 16));
2800 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER));
2801 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2802 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2803 control |= UDPTCP;
2804 sc_if->msk_cdata.msk_tx_cnt++;
2805 MSK_INC(prod, MSK_TX_RING_CNT);
2806 }
2807
2808 si = prod;
2809 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2810 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2811 if (tso == 0)
2812 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2813 OP_PACKET);
2814 else
2815 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2816 OP_LARGESEND);
2817 sc_if->msk_cdata.msk_tx_cnt++;
2818 MSK_INC(prod, MSK_TX_RING_CNT);
2819
2820 for (i = 1; i < nseg; i++) {
2821 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2822 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2823 tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2824 OP_BUFFER | HW_OWNER);
2825 sc_if->msk_cdata.msk_tx_cnt++;
2826 MSK_INC(prod, MSK_TX_RING_CNT);
2827 }
2828 /* Update producer index. */
2829 sc_if->msk_cdata.msk_tx_prod = prod;
2830
2831 /* Set EOP on the last desciptor. */
2832 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2833 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2834 tx_le->msk_control |= htole32(EOP);
2835
2836 /* Turn the first descriptor ownership to hardware. */
2837 tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2838 tx_le->msk_control |= htole32(HW_OWNER);
2839
2840 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2841 map = txd_last->tx_dmamap;
2842 txd_last->tx_dmamap = txd->tx_dmamap;
2843 txd->tx_dmamap = map;
2844 txd->tx_m = m;
2845
2846 /* Sync descriptors. */
2847 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2848 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2849 sc_if->msk_cdata.msk_tx_ring_map,
2850 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2851
2852 return (0);
2853}
2854
2855static void
2856msk_tx_task(void *arg, int pending)
2857{
2858 struct ifnet *ifp;
2859
2860 ifp = arg;
2861 msk_start(ifp);
2862}
2863
2864static void
2865msk_start(struct ifnet *ifp)
2866{
2867 struct msk_if_softc *sc_if;
2868 struct mbuf *m_head;
2869 int enq;
2870
2871 sc_if = ifp->if_softc;
2872
2873 MSK_IF_LOCK(sc_if);
2874
2875 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2876 IFF_DRV_RUNNING || sc_if->msk_link == 0) {
2877 MSK_IF_UNLOCK(sc_if);
2878 return;
2879 }
2880
2881 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2882 sc_if->msk_cdata.msk_tx_cnt <
2883 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
2884 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2885 if (m_head == NULL)
2886 break;
2887 /*
2888 * Pack the data into the transmit ring. If we
2889 * don't have room, set the OACTIVE flag and wait
2890 * for the NIC to drain the ring.
2891 */
2892 if (msk_encap(sc_if, &m_head) != 0) {
2893 if (m_head == NULL)
2894 break;
2895 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2896 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2897 break;
2898 }
2899
2900 enq++;
2901 /*
2902 * If there's a BPF listener, bounce a copy of this frame
2903 * to him.
2904 */
2905 ETHER_BPF_MTAP(ifp, m_head);
2906 }
2907
2908 if (enq > 0) {
2909 /* Transmit */
2910 CSR_WRITE_2(sc_if->msk_softc,
2911 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2912 sc_if->msk_cdata.msk_tx_prod);
2913
2914 /* Set a timeout in case the chip goes out to lunch. */
2915 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
2916 }
2917
2918 MSK_IF_UNLOCK(sc_if);
2919}
2920
2921static void
2922msk_watchdog(struct msk_if_softc *sc_if)
2923{
2924 struct ifnet *ifp;
2925 uint32_t ridx;
2926 int idx;
2927
2928 MSK_IF_LOCK_ASSERT(sc_if);
2929
2930 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
2931 return;
2932 ifp = sc_if->msk_ifp;
2933 if (sc_if->msk_link == 0) {
2934 if (bootverbose)
2935 if_printf(sc_if->msk_ifp, "watchdog timeout "
2936 "(missed link)\n");
2937 ifp->if_oerrors++;
2938 msk_init_locked(sc_if);
2939 return;
2940 }
2941
2942 /*
2943 * Reclaim first as there is a possibility of losing Tx completion
2944 * interrupts.
2945 */
2946 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX;
2947 idx = CSR_READ_2(sc_if->msk_softc, ridx);
2948 if (sc_if->msk_cdata.msk_tx_cons != idx) {
2949 msk_txeof(sc_if, idx);
2950 if (sc_if->msk_cdata.msk_tx_cnt == 0) {
2951 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
2952 "-- recovering\n");
2953 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2954 taskqueue_enqueue(taskqueue_fast,
2955 &sc_if->msk_tx_task);
2956 return;
2957 }
2958 }
2959
2960 if_printf(ifp, "watchdog timeout\n");
2961 ifp->if_oerrors++;
2962 msk_init_locked(sc_if);
2963 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2964 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task);
2965}
2966
2967static void
2968mskc_shutdown(device_t dev)
2969{
2970 struct msk_softc *sc;
2971 int i;
2972
2973 sc = device_get_softc(dev);
2974 MSK_LOCK(sc);
2975 for (i = 0; i < sc->msk_num_port; i++) {
2976 if (sc->msk_if[i] != NULL)
2977 msk_stop(sc->msk_if[i]);
2978 }
2979
2980 /* Disable all interrupts. */
2981 CSR_WRITE_4(sc, B0_IMSK, 0);
2982 CSR_READ_4(sc, B0_IMSK);
2983 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2984 CSR_READ_4(sc, B0_HWE_IMSK);
2985
2986 /* Put hardware reset. */
2987 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2988
2989 MSK_UNLOCK(sc);
2990}
2991
2992static int
2993mskc_suspend(device_t dev)
2994{
2995 struct msk_softc *sc;
2996 int i;
2997
2998 sc = device_get_softc(dev);
2999
3000 MSK_LOCK(sc);
3001
3002 for (i = 0; i < sc->msk_num_port; i++) {
3003 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3004 ((sc->msk_if[i]->msk_ifp->if_drv_flags &
3005 IFF_DRV_RUNNING) != 0))
3006 msk_stop(sc->msk_if[i]);
3007 }
3008
3009 /* Disable all interrupts. */
3010 CSR_WRITE_4(sc, B0_IMSK, 0);
3011 CSR_READ_4(sc, B0_IMSK);
3012 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
3013 CSR_READ_4(sc, B0_HWE_IMSK);
3014
3015 msk_phy_power(sc, MSK_PHY_POWERDOWN);
3016
3017 /* Put hardware reset. */
3018 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3019 sc->msk_suspended = 1;
3020
3021 MSK_UNLOCK(sc);
3022
3023 return (0);
3024}
3025
3026static int
3027mskc_resume(device_t dev)
3028{
3029 struct msk_softc *sc;
3030 int i;
3031
3032 sc = device_get_softc(dev);
3033
3034 MSK_LOCK(sc);
3035
3036 mskc_reset(sc);
3037 for (i = 0; i < sc->msk_num_port; i++) {
3038 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3039 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0))
3040 msk_init_locked(sc->msk_if[i]);
3041 }
3042 sc->msk_suspended = 0;
3043
3044 MSK_UNLOCK(sc);
3045
3046 return (0);
3047}
3048
3049static void
3050msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
3051{
3052 struct mbuf *m;
3053 struct ifnet *ifp;
3054 struct msk_rxdesc *rxd;
3055 int cons, rxlen;
3056
3057 ifp = sc_if->msk_ifp;
3058
3059 MSK_IF_LOCK_ASSERT(sc_if);
3060
3061 cons = sc_if->msk_cdata.msk_rx_cons;
3062 do {
3063 rxlen = status >> 16;
3064 if ((status & GMR_FS_VLAN) != 0 &&
3065 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3066 rxlen -= ETHER_VLAN_ENCAP_LEN;
3067 if (len > sc_if->msk_framesize ||
3068 ((status & GMR_FS_ANY_ERR) != 0) ||
3069 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3070 /* Don't count flow-control packet as errors. */
3071 if ((status & GMR_FS_GOOD_FC) == 0)
3072 ifp->if_ierrors++;
3073 msk_discard_rxbuf(sc_if, cons);
3074 break;
3075 }
3076 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
3077 m = rxd->rx_m;
3078 if (msk_newbuf(sc_if, cons) != 0) {
3079 ifp->if_iqdrops++;
3080 /* Reuse old buffer. */
3081 msk_discard_rxbuf(sc_if, cons);
3082 break;
3083 }
3084 m->m_pkthdr.rcvif = ifp;
3085 m->m_pkthdr.len = m->m_len = len;
3086 ifp->if_ipackets++;
3087 /* Check for VLAN tagged packets. */
3088 if ((status & GMR_FS_VLAN) != 0 &&
3089 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
3090 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3091 m->m_flags |= M_VLANTAG;
3092 }
3093 MSK_IF_UNLOCK(sc_if);
3094 (*ifp->if_input)(ifp, m);
3095 MSK_IF_LOCK(sc_if);
3096 } while (0);
3097
3098 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
3099 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
3100}
3101
3102static void
3103msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
3104{
3105 struct mbuf *m;
3106 struct ifnet *ifp;
3107 struct msk_rxdesc *jrxd;
3108 int cons, rxlen;
3109
3110 ifp = sc_if->msk_ifp;
3111
3112 MSK_IF_LOCK_ASSERT(sc_if);
3113
3114 cons = sc_if->msk_cdata.msk_rx_cons;
3115 do {
3116 rxlen = status >> 16;
3117 if ((status & GMR_FS_VLAN) != 0 &&
3118 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3119 rxlen -= ETHER_VLAN_ENCAP_LEN;
3120 if (len > sc_if->msk_framesize ||
3121 ((status & GMR_FS_ANY_ERR) != 0) ||
3122 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3123 /* Don't count flow-control packet as errors. */
3124 if ((status & GMR_FS_GOOD_FC) == 0)
3125 ifp->if_ierrors++;
3126 msk_discard_jumbo_rxbuf(sc_if, cons);
3127 break;
3128 }
3129 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
3130 m = jrxd->rx_m;
3131 if (msk_jumbo_newbuf(sc_if, cons) != 0) {
3132 ifp->if_iqdrops++;
3133 /* Reuse old buffer. */
3134 msk_discard_jumbo_rxbuf(sc_if, cons);
3135 break;
3136 }
3137 m->m_pkthdr.rcvif = ifp;
3138 m->m_pkthdr.len = m->m_len = len;
3139 ifp->if_ipackets++;
3140 /* Check for VLAN tagged packets. */
3141 if ((status & GMR_FS_VLAN) != 0 &&
3142 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
3143 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3144 m->m_flags |= M_VLANTAG;
3145 }
3146 MSK_IF_UNLOCK(sc_if);
3147 (*ifp->if_input)(ifp, m);
3148 MSK_IF_LOCK(sc_if);
3149 } while (0);
3150
3151 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
3152 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
3153}
3154
3155static void
3156msk_txeof(struct msk_if_softc *sc_if, int idx)
3157{
3158 struct msk_txdesc *txd;
3159 struct msk_tx_desc *cur_tx;
3160 struct ifnet *ifp;
3161 uint32_t control;
3162 int cons, prog;
3163
3164 MSK_IF_LOCK_ASSERT(sc_if);
3165
3166 ifp = sc_if->msk_ifp;
3167
3168 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
3169 sc_if->msk_cdata.msk_tx_ring_map,
3170 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3171 /*
3172 * Go through our tx ring and free mbufs for those
3173 * frames that have been sent.
3174 */
3175 cons = sc_if->msk_cdata.msk_tx_cons;
3176 prog = 0;
3177 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
3178 if (sc_if->msk_cdata.msk_tx_cnt <= 0)
3179 break;
3180 prog++;
3181 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
3182 control = le32toh(cur_tx->msk_control);
3183 sc_if->msk_cdata.msk_tx_cnt--;
3184 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3185 if ((control & EOP) == 0)
3186 continue;
3187 txd = &sc_if->msk_cdata.msk_txdesc[cons];
3188 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
3189 BUS_DMASYNC_POSTWRITE);
3190 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
3191
3192 ifp->if_opackets++;
3193 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
3194 __func__));
3195 m_freem(txd->tx_m);
3196 txd->tx_m = NULL;
3197 }
3198
3199 if (prog > 0) {
3200 sc_if->msk_cdata.msk_tx_cons = cons;
3201 if (sc_if->msk_cdata.msk_tx_cnt == 0)
3202 sc_if->msk_watchdog_timer = 0;
3203 /* No need to sync LEs as we didn't update LEs. */
3204 }
3205}
3206
3207static void
3208msk_tick(void *xsc_if)
3209{
3210 struct msk_if_softc *sc_if;
3211 struct mii_data *mii;
3212
3213 sc_if = xsc_if;
3214
3215 MSK_IF_LOCK_ASSERT(sc_if);
3216
3217 mii = device_get_softc(sc_if->msk_miibus);
3218
3219 mii_tick(mii);
3220 msk_watchdog(sc_if);
3221 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3222}
3223
3224static void
3225msk_intr_phy(struct msk_if_softc *sc_if)
3226{
3227 uint16_t status;
3228
3229 if (sc_if->msk_softc->msk_marvell_phy) {
3230 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3231 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV,
3232 PHY_MARV_INT_STAT);
3233 /* Handle FIFO Underrun/Overflow? */
3234 if ((status & PHY_M_IS_FIFO_ERROR))
3235 device_printf(sc_if->msk_if_dev,
3236 "PHY FIFO underrun/overflow.\n");
3237 }
3238}
3239
3240static void
3241msk_intr_gmac(struct msk_if_softc *sc_if)
3242{
3243 struct msk_softc *sc;
3244 uint8_t status;
3245
3246 sc = sc_if->msk_softc;
3247 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3248
3249 /* GMAC Rx FIFO overrun. */
3250 if ((status & GM_IS_RX_FF_OR) != 0) {
3251 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3252 GMF_CLI_RX_FO);
3253 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n");
3254 }
3255 /* GMAC Tx FIFO underrun. */
3256 if ((status & GM_IS_TX_FF_UR) != 0) {
3257 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3258 GMF_CLI_TX_FU);
3259 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
3260 /*
3261 * XXX
3262 * In case of Tx underrun, we may need to flush/reset
3263 * Tx MAC but that would also require resynchronization
3264 * with status LEs. Reintializing status LEs would
3265 * affect other port in dual MAC configuration so it
3266 * should be avoided as possible as we can.
3267 * Due to lack of documentation it's all vague guess but
3268 * it needs more investigation.
3269 */
3270 }
3271}
3272
3273static void
3274msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
3275{
3276 struct msk_softc *sc;
3277
3278 sc = sc_if->msk_softc;
3279 if ((status & Y2_IS_PAR_RD1) != 0) {
3280 device_printf(sc_if->msk_if_dev,
3281 "RAM buffer read parity error\n");
3282 /* Clear IRQ. */
3283 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3284 RI_CLR_RD_PERR);
3285 }
3286 if ((status & Y2_IS_PAR_WR1) != 0) {
3287 device_printf(sc_if->msk_if_dev,
3288 "RAM buffer write parity error\n");
3289 /* Clear IRQ. */
3290 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3291 RI_CLR_WR_PERR);
3292 }
3293 if ((status & Y2_IS_PAR_MAC1) != 0) {
3294 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3295 /* Clear IRQ. */
3296 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3297 GMF_CLI_TX_PE);
3298 }
3299 if ((status & Y2_IS_PAR_RX1) != 0) {
3300 device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3301 /* Clear IRQ. */
3302 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3303 }
3304 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
3305 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3306 /* Clear IRQ. */
3307 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3308 }
3309}
3310
3311static void
3312msk_intr_hwerr(struct msk_softc *sc)
3313{
3314 uint32_t status;
3315 uint32_t tlphead[4];
3316
3317 status = CSR_READ_4(sc, B0_HWE_ISRC);
3318 /* Time Stamp timer overflow. */
3319 if ((status & Y2_IS_TIST_OV) != 0)
3320 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3321 if ((status & Y2_IS_PCI_NEXP) != 0) {
3322 /*
3323 * PCI Express Error occured which is not described in PEX
3324 * spec.
3325 * This error is also mapped either to Master Abort(
3326 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
3327 * can only be cleared there.
3328 */
3329 device_printf(sc->msk_dev,
3330 "PCI Express protocol violation error\n");
3331 }
3332
3333 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
3334 uint16_t v16;
3335
3336 if ((status & Y2_IS_MST_ERR) != 0)
3337 device_printf(sc->msk_dev,
3338 "unexpected IRQ Status error\n");
3339 else
3340 device_printf(sc->msk_dev,
3341 "unexpected IRQ Master error\n");
3342 /* Reset all bits in the PCI status register. */
3343 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3344 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3345 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3346 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3347 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2);
3348 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3349 }
3350
3351 /* Check for PCI Express Uncorrectable Error. */
3352 if ((status & Y2_IS_PCI_EXP) != 0) {
3353 uint32_t v32;
3354
3355 /*
3356 * On PCI Express bus bridges are called root complexes (RC).
3357 * PCI Express errors are recognized by the root complex too,
3358 * which requests the system to handle the problem. After
3359 * error occurence it may be that no access to the adapter
3360 * may be performed any longer.
3361 */
3362
3363 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
3364 if ((v32 & PEX_UNSUP_REQ) != 0) {
3365 /* Ignore unsupported request error. */
3366 device_printf(sc->msk_dev,
3367 "Uncorrectable PCI Express error\n");
3368 }
3369 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
3370 int i;
3371
3372 /* Get TLP header form Log Registers. */
3373 for (i = 0; i < 4; i++)
3374 tlphead[i] = CSR_PCI_READ_4(sc,
3375 PEX_HEADER_LOG + i * 4);
3376 /* Check for vendor defined broadcast message. */
3377 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
3378 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3379 CSR_WRITE_4(sc, B0_HWE_IMSK,
3380 sc->msk_intrhwemask);
3381 CSR_READ_4(sc, B0_HWE_IMSK);
3382 }
3383 }
3384 /* Clear the interrupt. */
3385 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3386 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
3387 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3388 }
3389
3390 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3391 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3392 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3393 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3394}
3395
3396static __inline void
3397msk_rxput(struct msk_if_softc *sc_if)
3398{
3399 struct msk_softc *sc;
3400
3401 sc = sc_if->msk_softc;
3402 if (sc_if->msk_framesize >(MCLBYTES - ETHER_HDR_LEN))
3403 bus_dmamap_sync(
3404 sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3405 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3406 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3407 else
3408 bus_dmamap_sync(
3409 sc_if->msk_cdata.msk_rx_ring_tag,
3410 sc_if->msk_cdata.msk_rx_ring_map,
3411 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3412 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3413 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3414}
3415
3416static int
3417msk_handle_events(struct msk_softc *sc)
3418{
3419 struct msk_if_softc *sc_if;
3420 int rxput[2];
3421 struct msk_stat_desc *sd;
3422 uint32_t control, status;
3423 int cons, idx, len, port, rxprog;
3424
3425 idx = CSR_READ_2(sc, STAT_PUT_IDX);
3426 if (idx == sc->msk_stat_cons)
3427 return (0);
3428
3429 /* Sync status LEs. */
3430 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3431 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3432 /* XXX Sync Rx LEs here. */
3433
3434 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
3435
3436 rxprog = 0;
3437 for (cons = sc->msk_stat_cons; cons != idx;) {
3438 sd = &sc->msk_stat_ring[cons];
3439 control = le32toh(sd->msk_control);
3440 if ((control & HW_OWNER) == 0)
3441 break;
3442 /*
3443 * Marvell's FreeBSD driver updates status LE after clearing
3444 * HW_OWNER. However we don't have a way to sync single LE
3445 * with bus_dma(9) API. bus_dma(9) provides a way to sync
3446 * an entire DMA map. So don't sync LE until we have a better
3447 * way to sync LEs.
3448 */
3449 control &= ~HW_OWNER;
3450 sd->msk_control = htole32(control);
3451 status = le32toh(sd->msk_status);
3452 len = control & STLE_LEN_MASK;
3453 port = (control >> 16) & 0x01;
3454 sc_if = sc->msk_if[port];
3455 if (sc_if == NULL) {
3456 device_printf(sc->msk_dev, "invalid port opcode "
3457 "0x%08x\n", control & STLE_OP_MASK);
3458 continue;
3459 }
3460
3461 switch (control & STLE_OP_MASK) {
3462 case OP_RXVLAN:
3463 sc_if->msk_vtag = ntohs(len);
3464 break;
3465 case OP_RXCHKSVLAN:
3466 sc_if->msk_vtag = ntohs(len);
3467 break;
3468 case OP_RXSTAT:
3469 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN))
3470 msk_jumbo_rxeof(sc_if, status, len);
3471 else
3472 msk_rxeof(sc_if, status, len);
3473 rxprog++;
3474 /*
3475 * Because there is no way to sync single Rx LE
3476 * put the DMA sync operation off until the end of
3477 * event processing.
3478 */
3479 rxput[port]++;
3480 /* Update prefetch unit if we've passed water mark. */
3481 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3482 msk_rxput(sc_if);
3483 rxput[port] = 0;
3484 }
3485 break;
3486 case OP_TXINDEXLE:
3487 if (sc->msk_if[MSK_PORT_A] != NULL)
3488 msk_txeof(sc->msk_if[MSK_PORT_A],
3489 status & STLE_TXA1_MSKL);
3490 if (sc->msk_if[MSK_PORT_B] != NULL)
3491 msk_txeof(sc->msk_if[MSK_PORT_B],
3492 ((status & STLE_TXA2_MSKL) >>
3493 STLE_TXA2_SHIFTL) |
3494 ((len & STLE_TXA2_MSKH) <<
3495 STLE_TXA2_SHIFTH));
3496 break;
3497 default:
3498 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3499 control & STLE_OP_MASK);
3500 break;
3501 }
3502 MSK_INC(cons, MSK_STAT_RING_CNT);
3503 if (rxprog > sc->msk_process_limit)
3504 break;
3505 }
3506
3507 sc->msk_stat_cons = cons;
3508 /* XXX We should sync status LEs here. See above notes. */
3509
3510 if (rxput[MSK_PORT_A] > 0)
3511 msk_rxput(sc->msk_if[MSK_PORT_A]);
3512 if (rxput[MSK_PORT_B] > 0)
3513 msk_rxput(sc->msk_if[MSK_PORT_B]);
3514
3515 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3516}
3517
3518/* Legacy interrupt handler for shared interrupt. */
3519static void
3520msk_legacy_intr(void *xsc)
3521{
3522 struct msk_softc *sc;
3523 struct msk_if_softc *sc_if0, *sc_if1;
3524 struct ifnet *ifp0, *ifp1;
3525 uint32_t status;
3526
3527 sc = xsc;
3528 MSK_LOCK(sc);
3529
3530 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3531 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3532 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 ||
3533 (status & sc->msk_intrmask) == 0) {
3534 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3535 return;
3536 }
3537
3538 sc_if0 = sc->msk_if[MSK_PORT_A];
3539 sc_if1 = sc->msk_if[MSK_PORT_B];
3540 ifp0 = ifp1 = NULL;
3541 if (sc_if0 != NULL)
3542 ifp0 = sc_if0->msk_ifp;
3543 if (sc_if1 != NULL)
3544 ifp1 = sc_if1->msk_ifp;
3545
3546 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3547 msk_intr_phy(sc_if0);
3548 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3549 msk_intr_phy(sc_if1);
3550 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3551 msk_intr_gmac(sc_if0);
3552 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3553 msk_intr_gmac(sc_if1);
3554 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3555 device_printf(sc->msk_dev, "Rx descriptor error\n");
3556 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3557 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3558 CSR_READ_4(sc, B0_IMSK);
3559 }
3560 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3561 device_printf(sc->msk_dev, "Tx descriptor error\n");
3562 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3563 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3564 CSR_READ_4(sc, B0_IMSK);
3565 }
3566 if ((status & Y2_IS_HW_ERR) != 0)
3567 msk_intr_hwerr(sc);
3568
3569 while (msk_handle_events(sc) != 0)
3570 ;
3571 if ((status & Y2_IS_STAT_BMU) != 0)
3572 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3573
3574 /* Reenable interrupts. */
3575 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3576
3577 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3578 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3579 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task);
3580 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3581 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3582 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task);
3583
3584 MSK_UNLOCK(sc);
3585}
3586
3587static int
3588msk_intr(void *xsc)
3589{
3590 struct msk_softc *sc;
3591 uint32_t status;
3592
3593 sc = xsc;
3594 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3595 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3596 if (status == 0 || status == 0xffffffff) {
3597 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3598 return (FILTER_STRAY);
3599 }
3600
3601 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task);
3602 return (FILTER_HANDLED);
3603}
3604
3605static void
3606msk_int_task(void *arg, int pending)
3607{
3608 struct msk_softc *sc;
3609 struct msk_if_softc *sc_if0, *sc_if1;
3610 struct ifnet *ifp0, *ifp1;
3611 uint32_t status;
3612 int domore;
3613
3614 sc = arg;
3615 MSK_LOCK(sc);
3616
3617 /* Get interrupt source. */
3618 status = CSR_READ_4(sc, B0_ISRC);
3619 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 ||
3620 (status & sc->msk_intrmask) == 0)
3621 goto done;
3622
3623 sc_if0 = sc->msk_if[MSK_PORT_A];
3624 sc_if1 = sc->msk_if[MSK_PORT_B];
3625 ifp0 = ifp1 = NULL;
3626 if (sc_if0 != NULL)
3627 ifp0 = sc_if0->msk_ifp;
3628 if (sc_if1 != NULL)
3629 ifp1 = sc_if1->msk_ifp;
3630
3631 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3632 msk_intr_phy(sc_if0);
3633 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3634 msk_intr_phy(sc_if1);
3635 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3636 msk_intr_gmac(sc_if0);
3637 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3638 msk_intr_gmac(sc_if1);
3639 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3640 device_printf(sc->msk_dev, "Rx descriptor error\n");
3641 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3642 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3643 CSR_READ_4(sc, B0_IMSK);
3644 }
3645 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3646 device_printf(sc->msk_dev, "Tx descriptor error\n");
3647 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3648 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3649 CSR_READ_4(sc, B0_IMSK);
3650 }
3651 if ((status & Y2_IS_HW_ERR) != 0)
3652 msk_intr_hwerr(sc);
3653
3654 domore = msk_handle_events(sc);
3655 if ((status & Y2_IS_STAT_BMU) != 0)
3656 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3657
3658 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3659 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3660 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task);
3661 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3662 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3663 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task);
3664
3665 if (domore > 0) {
3666 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task);
3667 MSK_UNLOCK(sc);
3668 return;
3669 }
3670done:
3671 MSK_UNLOCK(sc);
3672
3673 /* Reenable interrupts. */
3674 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3675}
3676
3677static void
3678msk_init(void *xsc)
3679{
3680 struct msk_if_softc *sc_if = xsc;
3681
3682 MSK_IF_LOCK(sc_if);
3683 msk_init_locked(sc_if);
3684 MSK_IF_UNLOCK(sc_if);
3685}
3686
3687static void
3688msk_init_locked(struct msk_if_softc *sc_if)
3689{
3690 struct msk_softc *sc;
3691 struct ifnet *ifp;
3692 struct mii_data *mii;
3693 uint16_t eaddr[ETHER_ADDR_LEN / 2];
3694 uint16_t gmac;
3695 int error, i;
3696
3697 MSK_IF_LOCK_ASSERT(sc_if);
3698
3699 ifp = sc_if->msk_ifp;
3700 sc = sc_if->msk_softc;
3701 mii = device_get_softc(sc_if->msk_miibus);
3702
3703 error = 0;
3704 /* Cancel pending I/O and free all Rx/Tx buffers. */
3705 msk_stop(sc_if);
3706
3707 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN +
3708 ETHER_VLAN_ENCAP_LEN;
| 1516 /*
1517 * Do miibus setup.
1518 */
1519 MSK_IF_UNLOCK(sc_if);
1520 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange,
1521 msk_mediastatus);
1522 if (error != 0) {
1523 device_printf(sc_if->msk_if_dev, "no PHY found!\n");
1524 ether_ifdetach(ifp);
1525 error = ENXIO;
1526 goto fail;
1527 }
1528 /* Check whether PHY Id is MARVELL. */
1529 if (msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_ID0)
1530 == PHY_MARV_ID0_VAL)
1531 sc->msk_marvell_phy = 1;
1532
1533fail:
1534 if (error != 0) {
1535 /* Access should be ok even though lock has been dropped */
1536 sc->msk_if[port] = NULL;
1537 msk_detach(dev);
1538 }
1539
1540 return (error);
1541}
1542
1543/*
1544 * Attach the interface. Allocate softc structures, do ifmedia
1545 * setup and ethernet/BPF attach.
1546 */
1547static int
1548mskc_attach(device_t dev)
1549{
1550 struct msk_softc *sc;
1551 int error, msic, *port, reg;
1552
1553 sc = device_get_softc(dev);
1554 sc->msk_dev = dev;
1555 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1556 MTX_DEF);
1557
1558 /*
1559 * Map control/status registers.
1560 */
1561 pci_enable_busmaster(dev);
1562
1563 /* Allocate I/O resource */
1564#ifdef MSK_USEIOSPACE
1565 sc->msk_res_spec = msk_res_spec_io;
1566#else
1567 sc->msk_res_spec = msk_res_spec_mem;
1568#endif
1569 sc->msk_irq_spec = msk_irq_spec_legacy;
1570 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1571 if (error) {
1572 if (sc->msk_res_spec == msk_res_spec_mem)
1573 sc->msk_res_spec = msk_res_spec_io;
1574 else
1575 sc->msk_res_spec = msk_res_spec_mem;
1576 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1577 if (error) {
1578 device_printf(dev, "couldn't allocate %s resources\n",
1579 sc->msk_res_spec == msk_res_spec_mem ? "memory" :
1580 "I/O");
1581 mtx_destroy(&sc->msk_mtx);
1582 return (ENXIO);
1583 }
1584 }
1585
1586 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1587 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1588 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1589 /* Bail out if chip is not recognized. */
1590 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1591 sc->msk_hw_id > CHIP_ID_YUKON_FE) {
1592 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
1593 sc->msk_hw_id, sc->msk_hw_rev);
1594 mtx_destroy(&sc->msk_mtx);
1595 return (ENXIO);
1596 }
1597
1598 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1599 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1600 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
1601 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I",
1602 "max number of Rx events to process");
1603
1604 sc->msk_process_limit = MSK_PROC_DEFAULT;
1605 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1606 "process_limit", &sc->msk_process_limit);
1607 if (error == 0) {
1608 if (sc->msk_process_limit < MSK_PROC_MIN ||
1609 sc->msk_process_limit > MSK_PROC_MAX) {
1610 device_printf(dev, "process_limit value out of range; "
1611 "using default: %d\n", MSK_PROC_DEFAULT);
1612 sc->msk_process_limit = MSK_PROC_DEFAULT;
1613 }
1614 }
1615
1616 /* Soft reset. */
1617 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1618 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1619 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1620 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1621 sc->msk_coppertype = 0;
1622 else
1623 sc->msk_coppertype = 1;
1624 /* Check number of MACs. */
1625 sc->msk_num_port = 1;
1626 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1627 CFG_DUAL_MAC_MSK) {
1628 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1629 sc->msk_num_port++;
1630 }
1631
1632 /* Check bus type. */
1633 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0)
1634 sc->msk_bustype = MSK_PEX_BUS;
1635 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0)
1636 sc->msk_bustype = MSK_PCIX_BUS;
1637 else
1638 sc->msk_bustype = MSK_PCI_BUS;
1639
1640 /* Get H/W features(bugs). */
1641 switch (sc->msk_hw_id) {
1642 case CHIP_ID_YUKON_EC:
1643 sc->msk_clock = 125; /* 125 Mhz */
1644 if (sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1645 sc->msk_hw_feature =
1646 HWF_WA_DEV_42 | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 |
1647 HWF_WA_DEV_420 | HWF_WA_DEV_423 |
1648 HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
1649 HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1650 HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1651 } else {
1652 /* A2/A3 */
1653 sc->msk_hw_feature =
1654 HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
1655 HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1656 HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1657 }
1658 break;
1659 case CHIP_ID_YUKON_EC_U:
1660 sc->msk_clock = 125; /* 125 Mhz */
1661 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
1662 sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_483 |
1663 HWF_WA_DEV_4109;
1664 } else if (sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1665 uint16_t v;
1666
1667 sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
1668 HWF_WA_DEV_4185;
1669 v = CSR_READ_2(sc, Q_ADDR(Q_XA1, Q_WM));
1670 if (v == 0)
1671 sc->msk_hw_feature |= HWF_WA_DEV_4185CS |
1672 HWF_WA_DEV_4200;
1673 }
1674 break;
1675 case CHIP_ID_YUKON_FE:
1676 sc->msk_clock = 100; /* 100 Mhz */
1677 sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
1678 HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1679 break;
1680 case CHIP_ID_YUKON_XL:
1681 sc->msk_clock = 156; /* 156 Mhz */
1682 switch (sc->msk_hw_rev) {
1683 case CHIP_REV_YU_XL_A0:
1684 sc->msk_hw_feature =
1685 HWF_WA_DEV_427 | HWF_WA_DEV_463 | HWF_WA_DEV_472 |
1686 HWF_WA_DEV_479 | HWF_WA_DEV_483 | HWF_WA_DEV_4115 |
1687 HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1688 break;
1689 case CHIP_REV_YU_XL_A1:
1690 sc->msk_hw_feature =
1691 HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1692 HWF_WA_DEV_4115 | HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
1693 break;
1694 case CHIP_REV_YU_XL_A2:
1695 sc->msk_hw_feature =
1696 HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1697 HWF_WA_DEV_4115 | HWF_WA_DEV_4167;
1698 break;
1699 case CHIP_REV_YU_XL_A3:
1700 sc->msk_hw_feature =
1701 HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
1702 HWF_WA_DEV_4115;
1703 }
1704 break;
1705 default:
1706 sc->msk_clock = 156; /* 156 Mhz */
1707 sc->msk_hw_feature = 0;
1708 }
1709
1710 /* Allocate IRQ resources. */
1711 msic = pci_msi_count(dev);
1712 if (bootverbose)
1713 device_printf(dev, "MSI count : %d\n", msic);
1714 /*
1715 * The Yukon II reports it can handle two messages, one for each
1716 * possible port. We go ahead and allocate two messages and only
1717 * setup a handler for both if we have a dual port card.
1718 *
1719 * XXX: I haven't untangled the interrupt handler to handle dual
1720 * port cards with separate MSI messages, so for now I disable MSI
1721 * on dual port cards.
1722 */
1723 if (legacy_intr != 0)
1724 msi_disable = 1;
1725 if (msic == 2 && msi_disable == 0 && sc->msk_num_port == 1 &&
1726 pci_alloc_msi(dev, &msic) == 0) {
1727 if (msic == 2) {
1728 sc->msk_msi = 1;
1729 sc->msk_irq_spec = msk_irq_spec_msi;
1730 } else
1731 pci_release_msi(dev);
1732 }
1733
1734 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1735 if (error) {
1736 device_printf(dev, "couldn't allocate IRQ resources\n");
1737 goto fail;
1738 }
1739
1740 if ((error = msk_status_dma_alloc(sc)) != 0)
1741 goto fail;
1742
1743 /* Set base interrupt mask. */
1744 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1745 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1746 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1747
1748 /* Reset the adapter. */
1749 mskc_reset(sc);
1750
1751 if ((error = mskc_setup_rambuffer(sc)) != 0)
1752 goto fail;
1753
1754 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1);
1755 if (sc->msk_devs[MSK_PORT_A] == NULL) {
1756 device_printf(dev, "failed to add child for PORT_A\n");
1757 error = ENXIO;
1758 goto fail;
1759 }
1760 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1761 if (port == NULL) {
1762 device_printf(dev, "failed to allocate memory for "
1763 "ivars of PORT_A\n");
1764 error = ENXIO;
1765 goto fail;
1766 }
1767 *port = MSK_PORT_A;
1768 device_set_ivars(sc->msk_devs[MSK_PORT_A], port);
1769
1770 if (sc->msk_num_port > 1) {
1771 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1);
1772 if (sc->msk_devs[MSK_PORT_B] == NULL) {
1773 device_printf(dev, "failed to add child for PORT_B\n");
1774 error = ENXIO;
1775 goto fail;
1776 }
1777 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1778 if (port == NULL) {
1779 device_printf(dev, "failed to allocate memory for "
1780 "ivars of PORT_B\n");
1781 error = ENXIO;
1782 goto fail;
1783 }
1784 *port = MSK_PORT_B;
1785 device_set_ivars(sc->msk_devs[MSK_PORT_B], port);
1786 }
1787
1788 error = bus_generic_attach(dev);
1789 if (error) {
1790 device_printf(dev, "failed to attach port(s)\n");
1791 goto fail;
1792 }
1793
1794 /* Hook interrupt last to avoid having to lock softc. */
1795 if (legacy_intr)
1796 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1797 INTR_MPSAFE, NULL, msk_legacy_intr, sc,
1798 &sc->msk_intrhand[0]);
1799 else {
1800 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc);
1801 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK,
1802 taskqueue_thread_enqueue, &sc->msk_tq);
1803 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq",
1804 device_get_nameunit(sc->msk_dev));
1805 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1806 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]);
1807 }
1808
1809 if (error != 0) {
1810 device_printf(dev, "couldn't set up interrupt handler\n");
1811 if (legacy_intr == 0)
1812 taskqueue_free(sc->msk_tq);
1813 sc->msk_tq = NULL;
1814 goto fail;
1815 }
1816fail:
1817 if (error != 0)
1818 mskc_detach(dev);
1819
1820 return (error);
1821}
1822
1823/*
1824 * Shutdown hardware and free up resources. This can be called any
1825 * time after the mutex has been initialized. It is called in both
1826 * the error case in attach and the normal detach case so it needs
1827 * to be careful about only freeing resources that have actually been
1828 * allocated.
1829 */
1830static int
1831msk_detach(device_t dev)
1832{
1833 struct msk_softc *sc;
1834 struct msk_if_softc *sc_if;
1835 struct ifnet *ifp;
1836
1837 sc_if = device_get_softc(dev);
1838 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx),
1839 ("msk mutex not initialized in msk_detach"));
1840 MSK_IF_LOCK(sc_if);
1841
1842 ifp = sc_if->msk_ifp;
1843 if (device_is_attached(dev)) {
1844 /* XXX */
1845 sc_if->msk_detach = 1;
1846 msk_stop(sc_if);
1847 /* Can't hold locks while calling detach. */
1848 MSK_IF_UNLOCK(sc_if);
1849 callout_drain(&sc_if->msk_tick_ch);
1850 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task);
1851 taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task);
1852 ether_ifdetach(ifp);
1853 MSK_IF_LOCK(sc_if);
1854 }
1855
1856 /*
1857 * We're generally called from mskc_detach() which is using
1858 * device_delete_child() to get to here. It's already trashed
1859 * miibus for us, so don't do it here or we'll panic.
1860 *
1861 * if (sc_if->msk_miibus != NULL) {
1862 * device_delete_child(dev, sc_if->msk_miibus);
1863 * sc_if->msk_miibus = NULL;
1864 * }
1865 */
1866
1867 msk_txrx_dma_free(sc_if);
1868 bus_generic_detach(dev);
1869
1870 if (ifp)
1871 if_free(ifp);
1872 sc = sc_if->msk_softc;
1873 sc->msk_if[sc_if->msk_port] = NULL;
1874 MSK_IF_UNLOCK(sc_if);
1875
1876 return (0);
1877}
1878
1879static int
1880mskc_detach(device_t dev)
1881{
1882 struct msk_softc *sc;
1883
1884 sc = device_get_softc(dev);
1885 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized"));
1886
1887 if (device_is_alive(dev)) {
1888 if (sc->msk_devs[MSK_PORT_A] != NULL) {
1889 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]),
1890 M_DEVBUF);
1891 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]);
1892 }
1893 if (sc->msk_devs[MSK_PORT_B] != NULL) {
1894 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]),
1895 M_DEVBUF);
1896 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]);
1897 }
1898 bus_generic_detach(dev);
1899 }
1900
1901 /* Disable all interrupts. */
1902 CSR_WRITE_4(sc, B0_IMSK, 0);
1903 CSR_READ_4(sc, B0_IMSK);
1904 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1905 CSR_READ_4(sc, B0_HWE_IMSK);
1906
1907 /* LED Off. */
1908 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
1909
1910 /* Put hardware reset. */
1911 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1912
1913 msk_status_dma_free(sc);
1914
1915 if (legacy_intr == 0 && sc->msk_tq != NULL) {
1916 taskqueue_drain(sc->msk_tq, &sc->msk_int_task);
1917 taskqueue_free(sc->msk_tq);
1918 sc->msk_tq = NULL;
1919 }
1920 if (sc->msk_intrhand[0]) {
1921 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]);
1922 sc->msk_intrhand[0] = NULL;
1923 }
1924 if (sc->msk_intrhand[1]) {
1925 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]);
1926 sc->msk_intrhand[1] = NULL;
1927 }
1928 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1929 if (sc->msk_msi)
1930 pci_release_msi(dev);
1931 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res);
1932 mtx_destroy(&sc->msk_mtx);
1933
1934 return (0);
1935}
1936
1937struct msk_dmamap_arg {
1938 bus_addr_t msk_busaddr;
1939};
1940
1941static void
1942msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1943{
1944 struct msk_dmamap_arg *ctx;
1945
1946 if (error != 0)
1947 return;
1948 ctx = arg;
1949 ctx->msk_busaddr = segs[0].ds_addr;
1950}
1951
1952/* Create status DMA region. */
1953static int
1954msk_status_dma_alloc(struct msk_softc *sc)
1955{
1956 struct msk_dmamap_arg ctx;
1957 int error;
1958
1959 error = bus_dma_tag_create(
1960 bus_get_dma_tag(sc->msk_dev), /* parent */
1961 MSK_STAT_ALIGN, 0, /* alignment, boundary */
1962 BUS_SPACE_MAXADDR, /* lowaddr */
1963 BUS_SPACE_MAXADDR, /* highaddr */
1964 NULL, NULL, /* filter, filterarg */
1965 MSK_STAT_RING_SZ, /* maxsize */
1966 1, /* nsegments */
1967 MSK_STAT_RING_SZ, /* maxsegsize */
1968 0, /* flags */
1969 NULL, NULL, /* lockfunc, lockarg */
1970 &sc->msk_stat_tag);
1971 if (error != 0) {
1972 device_printf(sc->msk_dev,
1973 "failed to create status DMA tag\n");
1974 return (error);
1975 }
1976
1977 /* Allocate DMA'able memory and load the DMA map for status ring. */
1978 error = bus_dmamem_alloc(sc->msk_stat_tag,
1979 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
1980 BUS_DMA_ZERO, &sc->msk_stat_map);
1981 if (error != 0) {
1982 device_printf(sc->msk_dev,
1983 "failed to allocate DMA'able memory for status ring\n");
1984 return (error);
1985 }
1986
1987 ctx.msk_busaddr = 0;
1988 error = bus_dmamap_load(sc->msk_stat_tag,
1989 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ,
1990 msk_dmamap_cb, &ctx, 0);
1991 if (error != 0) {
1992 device_printf(sc->msk_dev,
1993 "failed to load DMA'able memory for status ring\n");
1994 return (error);
1995 }
1996 sc->msk_stat_ring_paddr = ctx.msk_busaddr;
1997
1998 return (0);
1999}
2000
2001static void
2002msk_status_dma_free(struct msk_softc *sc)
2003{
2004
2005 /* Destroy status block. */
2006 if (sc->msk_stat_tag) {
2007 if (sc->msk_stat_map) {
2008 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
2009 if (sc->msk_stat_ring) {
2010 bus_dmamem_free(sc->msk_stat_tag,
2011 sc->msk_stat_ring, sc->msk_stat_map);
2012 sc->msk_stat_ring = NULL;
2013 }
2014 sc->msk_stat_map = NULL;
2015 }
2016 bus_dma_tag_destroy(sc->msk_stat_tag);
2017 sc->msk_stat_tag = NULL;
2018 }
2019}
2020
2021static int
2022msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
2023{
2024 struct msk_dmamap_arg ctx;
2025 struct msk_txdesc *txd;
2026 struct msk_rxdesc *rxd;
2027 struct msk_rxdesc *jrxd;
2028 struct msk_jpool_entry *entry;
2029 uint8_t *ptr;
2030 int error, i;
2031
2032 mtx_init(&sc_if->msk_jlist_mtx, "msk_jlist_mtx", NULL, MTX_DEF);
2033 SLIST_INIT(&sc_if->msk_jfree_listhead);
2034 SLIST_INIT(&sc_if->msk_jinuse_listhead);
2035
2036 /* Create parent DMA tag. */
2037 /*
2038 * XXX
2039 * It seems that Yukon II supports full 64bits DMA operations. But
2040 * it needs two descriptors(list elements) for 64bits DMA operations.
2041 * Since we don't know what DMA address mappings(32bits or 64bits)
2042 * would be used in advance for each mbufs, we limits its DMA space
2043 * to be in range of 32bits address space. Otherwise, we should check
2044 * what DMA address is used and chain another descriptor for the
2045 * 64bits DMA operation. This also means descriptor ring size is
2046 * variable. Limiting DMA address to be in 32bit address space greatly
2047 * simplyfies descriptor handling and possibly would increase
2048 * performance a bit due to efficient handling of descriptors.
2049 * Apart from harassing checksum offloading mechanisms, it seems
2050 * it's really bad idea to use a seperate descriptor for 64bit
2051 * DMA operation to save small descriptor memory. Anyway, I've
2052 * never seen these exotic scheme on ethernet interface hardware.
2053 */
2054 error = bus_dma_tag_create(
2055 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */
2056 1, 0, /* alignment, boundary */
2057 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2058 BUS_SPACE_MAXADDR, /* highaddr */
2059 NULL, NULL, /* filter, filterarg */
2060 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
2061 0, /* nsegments */
2062 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2063 0, /* flags */
2064 NULL, NULL, /* lockfunc, lockarg */
2065 &sc_if->msk_cdata.msk_parent_tag);
2066 if (error != 0) {
2067 device_printf(sc_if->msk_if_dev,
2068 "failed to create parent DMA tag\n");
2069 goto fail;
2070 }
2071 /* Create tag for Tx ring. */
2072 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2073 MSK_RING_ALIGN, 0, /* alignment, boundary */
2074 BUS_SPACE_MAXADDR, /* lowaddr */
2075 BUS_SPACE_MAXADDR, /* highaddr */
2076 NULL, NULL, /* filter, filterarg */
2077 MSK_TX_RING_SZ, /* maxsize */
2078 1, /* nsegments */
2079 MSK_TX_RING_SZ, /* maxsegsize */
2080 0, /* flags */
2081 NULL, NULL, /* lockfunc, lockarg */
2082 &sc_if->msk_cdata.msk_tx_ring_tag);
2083 if (error != 0) {
2084 device_printf(sc_if->msk_if_dev,
2085 "failed to create Tx ring DMA tag\n");
2086 goto fail;
2087 }
2088
2089 /* Create tag for Rx ring. */
2090 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2091 MSK_RING_ALIGN, 0, /* alignment, boundary */
2092 BUS_SPACE_MAXADDR, /* lowaddr */
2093 BUS_SPACE_MAXADDR, /* highaddr */
2094 NULL, NULL, /* filter, filterarg */
2095 MSK_RX_RING_SZ, /* maxsize */
2096 1, /* nsegments */
2097 MSK_RX_RING_SZ, /* maxsegsize */
2098 0, /* flags */
2099 NULL, NULL, /* lockfunc, lockarg */
2100 &sc_if->msk_cdata.msk_rx_ring_tag);
2101 if (error != 0) {
2102 device_printf(sc_if->msk_if_dev,
2103 "failed to create Rx ring DMA tag\n");
2104 goto fail;
2105 }
2106
2107 /* Create tag for jumbo Rx ring. */
2108 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2109 MSK_RING_ALIGN, 0, /* alignment, boundary */
2110 BUS_SPACE_MAXADDR, /* lowaddr */
2111 BUS_SPACE_MAXADDR, /* highaddr */
2112 NULL, NULL, /* filter, filterarg */
2113 MSK_JUMBO_RX_RING_SZ, /* maxsize */
2114 1, /* nsegments */
2115 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */
2116 0, /* flags */
2117 NULL, NULL, /* lockfunc, lockarg */
2118 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2119 if (error != 0) {
2120 device_printf(sc_if->msk_if_dev,
2121 "failed to create jumbo Rx ring DMA tag\n");
2122 goto fail;
2123 }
2124
2125 /* Create tag for jumbo buffer blocks. */
2126 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2127 PAGE_SIZE, 0, /* alignment, boundary */
2128 BUS_SPACE_MAXADDR, /* lowaddr */
2129 BUS_SPACE_MAXADDR, /* highaddr */
2130 NULL, NULL, /* filter, filterarg */
2131 MSK_JMEM, /* maxsize */
2132 1, /* nsegments */
2133 MSK_JMEM, /* maxsegsize */
2134 0, /* flags */
2135 NULL, NULL, /* lockfunc, lockarg */
2136 &sc_if->msk_cdata.msk_jumbo_tag);
2137 if (error != 0) {
2138 device_printf(sc_if->msk_if_dev,
2139 "failed to create jumbo Rx buffer block DMA tag\n");
2140 goto fail;
2141 }
2142
2143 /* Create tag for Tx buffers. */
2144 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2145 1, 0, /* alignment, boundary */
2146 BUS_SPACE_MAXADDR, /* lowaddr */
2147 BUS_SPACE_MAXADDR, /* highaddr */
2148 NULL, NULL, /* filter, filterarg */
2149 MSK_TSO_MAXSIZE, /* maxsize */
2150 MSK_MAXTXSEGS, /* nsegments */
2151 MSK_TSO_MAXSGSIZE, /* maxsegsize */
2152 0, /* flags */
2153 NULL, NULL, /* lockfunc, lockarg */
2154 &sc_if->msk_cdata.msk_tx_tag);
2155 if (error != 0) {
2156 device_printf(sc_if->msk_if_dev,
2157 "failed to create Tx DMA tag\n");
2158 goto fail;
2159 }
2160
2161 /* Create tag for Rx buffers. */
2162 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2163 1, 0, /* alignment, boundary */
2164 BUS_SPACE_MAXADDR, /* lowaddr */
2165 BUS_SPACE_MAXADDR, /* highaddr */
2166 NULL, NULL, /* filter, filterarg */
2167 MCLBYTES, /* maxsize */
2168 1, /* nsegments */
2169 MCLBYTES, /* maxsegsize */
2170 0, /* flags */
2171 NULL, NULL, /* lockfunc, lockarg */
2172 &sc_if->msk_cdata.msk_rx_tag);
2173 if (error != 0) {
2174 device_printf(sc_if->msk_if_dev,
2175 "failed to create Rx DMA tag\n");
2176 goto fail;
2177 }
2178
2179 /* Create tag for jumbo Rx buffers. */
2180 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2181 PAGE_SIZE, 0, /* alignment, boundary */
2182 BUS_SPACE_MAXADDR, /* lowaddr */
2183 BUS_SPACE_MAXADDR, /* highaddr */
2184 NULL, NULL, /* filter, filterarg */
2185 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */
2186 MSK_MAXRXSEGS, /* nsegments */
2187 MSK_JLEN, /* maxsegsize */
2188 0, /* flags */
2189 NULL, NULL, /* lockfunc, lockarg */
2190 &sc_if->msk_cdata.msk_jumbo_rx_tag);
2191 if (error != 0) {
2192 device_printf(sc_if->msk_if_dev,
2193 "failed to create jumbo Rx DMA tag\n");
2194 goto fail;
2195 }
2196
2197 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2198 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag,
2199 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK |
2200 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map);
2201 if (error != 0) {
2202 device_printf(sc_if->msk_if_dev,
2203 "failed to allocate DMA'able memory for Tx ring\n");
2204 goto fail;
2205 }
2206
2207 ctx.msk_busaddr = 0;
2208 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag,
2209 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring,
2210 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0);
2211 if (error != 0) {
2212 device_printf(sc_if->msk_if_dev,
2213 "failed to load DMA'able memory for Tx ring\n");
2214 goto fail;
2215 }
2216 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr;
2217
2218 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2219 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag,
2220 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK |
2221 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map);
2222 if (error != 0) {
2223 device_printf(sc_if->msk_if_dev,
2224 "failed to allocate DMA'able memory for Rx ring\n");
2225 goto fail;
2226 }
2227
2228 ctx.msk_busaddr = 0;
2229 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag,
2230 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring,
2231 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0);
2232 if (error != 0) {
2233 device_printf(sc_if->msk_if_dev,
2234 "failed to load DMA'able memory for Rx ring\n");
2235 goto fail;
2236 }
2237 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr;
2238
2239 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
2240 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2241 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2242 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2243 &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2244 if (error != 0) {
2245 device_printf(sc_if->msk_if_dev,
2246 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2247 goto fail;
2248 }
2249
2250 ctx.msk_busaddr = 0;
2251 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2252 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2253 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2254 msk_dmamap_cb, &ctx, 0);
2255 if (error != 0) {
2256 device_printf(sc_if->msk_if_dev,
2257 "failed to load DMA'able memory for jumbo Rx ring\n");
2258 goto fail;
2259 }
2260 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2261
2262 /* Create DMA maps for Tx buffers. */
2263 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2264 txd = &sc_if->msk_cdata.msk_txdesc[i];
2265 txd->tx_m = NULL;
2266 txd->tx_dmamap = NULL;
2267 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
2268 &txd->tx_dmamap);
2269 if (error != 0) {
2270 device_printf(sc_if->msk_if_dev,
2271 "failed to create Tx dmamap\n");
2272 goto fail;
2273 }
2274 }
2275 /* Create DMA maps for Rx buffers. */
2276 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2277 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) {
2278 device_printf(sc_if->msk_if_dev,
2279 "failed to create spare Rx dmamap\n");
2280 goto fail;
2281 }
2282 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2283 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2284 rxd->rx_m = NULL;
2285 rxd->rx_dmamap = NULL;
2286 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2287 &rxd->rx_dmamap);
2288 if (error != 0) {
2289 device_printf(sc_if->msk_if_dev,
2290 "failed to create Rx dmamap\n");
2291 goto fail;
2292 }
2293 }
2294 /* Create DMA maps for jumbo Rx buffers. */
2295 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2296 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2297 device_printf(sc_if->msk_if_dev,
2298 "failed to create spare jumbo Rx dmamap\n");
2299 goto fail;
2300 }
2301 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2302 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2303 jrxd->rx_m = NULL;
2304 jrxd->rx_dmamap = NULL;
2305 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2306 &jrxd->rx_dmamap);
2307 if (error != 0) {
2308 device_printf(sc_if->msk_if_dev,
2309 "failed to create jumbo Rx dmamap\n");
2310 goto fail;
2311 }
2312 }
2313
2314 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */
2315 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag,
2316 (void **)&sc_if->msk_rdata.msk_jumbo_buf,
2317 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2318 &sc_if->msk_cdata.msk_jumbo_map);
2319 if (error != 0) {
2320 device_printf(sc_if->msk_if_dev,
2321 "failed to allocate DMA'able memory for jumbo buf\n");
2322 goto fail;
2323 }
2324
2325 ctx.msk_busaddr = 0;
2326 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag,
2327 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf,
2328 MSK_JMEM, msk_dmamap_cb, &ctx, 0);
2329 if (error != 0) {
2330 device_printf(sc_if->msk_if_dev,
2331 "failed to load DMA'able memory for jumbobuf\n");
2332 goto fail;
2333 }
2334 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr;
2335
2336 /*
2337 * Now divide it up into 9K pieces and save the addresses
2338 * in an array.
2339 */
2340 ptr = sc_if->msk_rdata.msk_jumbo_buf;
2341 for (i = 0; i < MSK_JSLOTS; i++) {
2342 sc_if->msk_cdata.msk_jslots[i] = ptr;
2343 ptr += MSK_JLEN;
2344 entry = malloc(sizeof(struct msk_jpool_entry),
2345 M_DEVBUF, M_WAITOK);
2346 if (entry == NULL) {
2347 device_printf(sc_if->msk_if_dev,
2348 "no memory for jumbo buffers!\n");
2349 error = ENOMEM;
2350 goto fail;
2351 }
2352 entry->slot = i;
2353 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry,
2354 jpool_entries);
2355 }
2356
2357fail:
2358 return (error);
2359}
2360
2361static void
2362msk_txrx_dma_free(struct msk_if_softc *sc_if)
2363{
2364 struct msk_txdesc *txd;
2365 struct msk_rxdesc *rxd;
2366 struct msk_rxdesc *jrxd;
2367 struct msk_jpool_entry *entry;
2368 int i;
2369
2370 MSK_JLIST_LOCK(sc_if);
2371 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) {
2372 device_printf(sc_if->msk_if_dev,
2373 "asked to free buffer that is in use!\n");
2374 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries);
2375 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry,
2376 jpool_entries);
2377 }
2378
2379 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) {
2380 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead);
2381 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries);
2382 free(entry, M_DEVBUF);
2383 }
2384 MSK_JLIST_UNLOCK(sc_if);
2385
2386 /* Destroy jumbo buffer block. */
2387 if (sc_if->msk_cdata.msk_jumbo_map)
2388 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag,
2389 sc_if->msk_cdata.msk_jumbo_map);
2390
2391 if (sc_if->msk_rdata.msk_jumbo_buf) {
2392 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag,
2393 sc_if->msk_rdata.msk_jumbo_buf,
2394 sc_if->msk_cdata.msk_jumbo_map);
2395 sc_if->msk_rdata.msk_jumbo_buf = NULL;
2396 sc_if->msk_cdata.msk_jumbo_map = NULL;
2397 }
2398
2399 /* Tx ring. */
2400 if (sc_if->msk_cdata.msk_tx_ring_tag) {
2401 if (sc_if->msk_cdata.msk_tx_ring_map)
2402 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag,
2403 sc_if->msk_cdata.msk_tx_ring_map);
2404 if (sc_if->msk_cdata.msk_tx_ring_map &&
2405 sc_if->msk_rdata.msk_tx_ring)
2406 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag,
2407 sc_if->msk_rdata.msk_tx_ring,
2408 sc_if->msk_cdata.msk_tx_ring_map);
2409 sc_if->msk_rdata.msk_tx_ring = NULL;
2410 sc_if->msk_cdata.msk_tx_ring_map = NULL;
2411 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag);
2412 sc_if->msk_cdata.msk_tx_ring_tag = NULL;
2413 }
2414 /* Rx ring. */
2415 if (sc_if->msk_cdata.msk_rx_ring_tag) {
2416 if (sc_if->msk_cdata.msk_rx_ring_map)
2417 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag,
2418 sc_if->msk_cdata.msk_rx_ring_map);
2419 if (sc_if->msk_cdata.msk_rx_ring_map &&
2420 sc_if->msk_rdata.msk_rx_ring)
2421 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag,
2422 sc_if->msk_rdata.msk_rx_ring,
2423 sc_if->msk_cdata.msk_rx_ring_map);
2424 sc_if->msk_rdata.msk_rx_ring = NULL;
2425 sc_if->msk_cdata.msk_rx_ring_map = NULL;
2426 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag);
2427 sc_if->msk_cdata.msk_rx_ring_tag = NULL;
2428 }
2429 /* Jumbo Rx ring. */
2430 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2431 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map)
2432 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2433 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2434 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map &&
2435 sc_if->msk_rdata.msk_jumbo_rx_ring)
2436 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2437 sc_if->msk_rdata.msk_jumbo_rx_ring,
2438 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2439 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2440 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL;
2441 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2442 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2443 }
2444 /* Tx buffers. */
2445 if (sc_if->msk_cdata.msk_tx_tag) {
2446 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2447 txd = &sc_if->msk_cdata.msk_txdesc[i];
2448 if (txd->tx_dmamap) {
2449 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2450 txd->tx_dmamap);
2451 txd->tx_dmamap = NULL;
2452 }
2453 }
2454 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2455 sc_if->msk_cdata.msk_tx_tag = NULL;
2456 }
2457 /* Rx buffers. */
2458 if (sc_if->msk_cdata.msk_rx_tag) {
2459 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2460 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2461 if (rxd->rx_dmamap) {
2462 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2463 rxd->rx_dmamap);
2464 rxd->rx_dmamap = NULL;
2465 }
2466 }
2467 if (sc_if->msk_cdata.msk_rx_sparemap) {
2468 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2469 sc_if->msk_cdata.msk_rx_sparemap);
2470 sc_if->msk_cdata.msk_rx_sparemap = 0;
2471 }
2472 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2473 sc_if->msk_cdata.msk_rx_tag = NULL;
2474 }
2475 /* Jumbo Rx buffers. */
2476 if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2477 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2478 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2479 if (jrxd->rx_dmamap) {
2480 bus_dmamap_destroy(
2481 sc_if->msk_cdata.msk_jumbo_rx_tag,
2482 jrxd->rx_dmamap);
2483 jrxd->rx_dmamap = NULL;
2484 }
2485 }
2486 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2487 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2488 sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2489 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2490 }
2491 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2492 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2493 }
2494
2495 if (sc_if->msk_cdata.msk_parent_tag) {
2496 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2497 sc_if->msk_cdata.msk_parent_tag = NULL;
2498 }
2499 mtx_destroy(&sc_if->msk_jlist_mtx);
2500}
2501
2502/*
2503 * Allocate a jumbo buffer.
2504 */
2505static void *
2506msk_jalloc(struct msk_if_softc *sc_if)
2507{
2508 struct msk_jpool_entry *entry;
2509
2510 MSK_JLIST_LOCK(sc_if);
2511
2512 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead);
2513
2514 if (entry == NULL) {
2515 MSK_JLIST_UNLOCK(sc_if);
2516 return (NULL);
2517 }
2518
2519 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries);
2520 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries);
2521
2522 MSK_JLIST_UNLOCK(sc_if);
2523
2524 return (sc_if->msk_cdata.msk_jslots[entry->slot]);
2525}
2526
2527/*
2528 * Release a jumbo buffer.
2529 */
2530static void
2531msk_jfree(void *buf, void *args)
2532{
2533 struct msk_if_softc *sc_if;
2534 struct msk_jpool_entry *entry;
2535 int i;
2536
2537 /* Extract the softc struct pointer. */
2538 sc_if = (struct msk_if_softc *)args;
2539 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__));
2540
2541 MSK_JLIST_LOCK(sc_if);
2542 /* Calculate the slot this buffer belongs to. */
2543 i = ((vm_offset_t)buf
2544 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN;
2545 KASSERT(i >= 0 && i < MSK_JSLOTS,
2546 ("%s: asked to free buffer that we don't manage!", __func__));
2547
2548 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead);
2549 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__));
2550 entry->slot = i;
2551 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries);
2552 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries);
2553 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead))
2554 wakeup(sc_if);
2555
2556 MSK_JLIST_UNLOCK(sc_if);
2557}
2558
2559/*
2560 * It's copy of ath_defrag(ath(4)).
2561 *
2562 * Defragment an mbuf chain, returning at most maxfrags separate
2563 * mbufs+clusters. If this is not possible NULL is returned and
2564 * the original mbuf chain is left in it's present (potentially
2565 * modified) state. We use two techniques: collapsing consecutive
2566 * mbufs and replacing consecutive mbufs by a cluster.
2567 */
2568static struct mbuf *
2569msk_defrag(struct mbuf *m0, int how, int maxfrags)
2570{
2571 struct mbuf *m, *n, *n2, **prev;
2572 u_int curfrags;
2573
2574 /*
2575 * Calculate the current number of frags.
2576 */
2577 curfrags = 0;
2578 for (m = m0; m != NULL; m = m->m_next)
2579 curfrags++;
2580 /*
2581 * First, try to collapse mbufs. Note that we always collapse
2582 * towards the front so we don't need to deal with moving the
2583 * pkthdr. This may be suboptimal if the first mbuf has much
2584 * less data than the following.
2585 */
2586 m = m0;
2587again:
2588 for (;;) {
2589 n = m->m_next;
2590 if (n == NULL)
2591 break;
2592 if ((m->m_flags & M_RDONLY) == 0 &&
2593 n->m_len < M_TRAILINGSPACE(m)) {
2594 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
2595 n->m_len);
2596 m->m_len += n->m_len;
2597 m->m_next = n->m_next;
2598 m_free(n);
2599 if (--curfrags <= maxfrags)
2600 return (m0);
2601 } else
2602 m = n;
2603 }
2604 KASSERT(maxfrags > 1,
2605 ("maxfrags %u, but normal collapse failed", maxfrags));
2606 /*
2607 * Collapse consecutive mbufs to a cluster.
2608 */
2609 prev = &m0->m_next; /* NB: not the first mbuf */
2610 while ((n = *prev) != NULL) {
2611 if ((n2 = n->m_next) != NULL &&
2612 n->m_len + n2->m_len < MCLBYTES) {
2613 m = m_getcl(how, MT_DATA, 0);
2614 if (m == NULL)
2615 goto bad;
2616 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
2617 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
2618 n2->m_len);
2619 m->m_len = n->m_len + n2->m_len;
2620 m->m_next = n2->m_next;
2621 *prev = m;
2622 m_free(n);
2623 m_free(n2);
2624 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
2625 return m0;
2626 /*
2627 * Still not there, try the normal collapse
2628 * again before we allocate another cluster.
2629 */
2630 goto again;
2631 }
2632 prev = &n->m_next;
2633 }
2634 /*
2635 * No place where we can collapse to a cluster; punt.
2636 * This can occur if, for example, you request 2 frags
2637 * but the packet requires that both be clusters (we
2638 * never reallocate the first mbuf to avoid moving the
2639 * packet header).
2640 */
2641bad:
2642 return (NULL);
2643}
2644
2645static int
2646msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
2647{
2648 struct msk_txdesc *txd, *txd_last;
2649 struct msk_tx_desc *tx_le;
2650 struct mbuf *m;
2651 bus_dmamap_t map;
2652 bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
2653 uint32_t control, prod, si;
2654 uint16_t offset, tcp_offset, tso_mtu;
2655 int error, i, nseg, tso;
2656
2657 MSK_IF_LOCK_ASSERT(sc_if);
2658
2659 tcp_offset = offset = 0;
2660 m = *m_head;
2661 if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) {
2662 /*
2663 * Since mbuf has no protocol specific structure information
2664 * in it we have to inspect protocol information here to
2665 * setup TSO and checksum offload. I don't know why Marvell
2666 * made a such decision in chip design because other GigE
2667 * hardwares normally takes care of all these chores in
2668 * hardware. However, TSO performance of Yukon II is very
2669 * good such that it's worth to implement it.
2670 */
2671 struct ether_header *eh;
2672 struct ip *ip;
2673 struct tcphdr *tcp;
2674
2675 /* TODO check for M_WRITABLE(m) */
2676
2677 offset = sizeof(struct ether_header);
2678 m = m_pullup(m, offset);
2679 if (m == NULL) {
2680 *m_head = NULL;
2681 return (ENOBUFS);
2682 }
2683 eh = mtod(m, struct ether_header *);
2684 /* Check if hardware VLAN insertion is off. */
2685 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2686 offset = sizeof(struct ether_vlan_header);
2687 m = m_pullup(m, offset);
2688 if (m == NULL) {
2689 *m_head = NULL;
2690 return (ENOBUFS);
2691 }
2692 }
2693 m = m_pullup(m, offset + sizeof(struct ip));
2694 if (m == NULL) {
2695 *m_head = NULL;
2696 return (ENOBUFS);
2697 }
2698 ip = (struct ip *)(mtod(m, char *) + offset);
2699 offset += (ip->ip_hl << 2);
2700 tcp_offset = offset;
2701 /*
2702 * It seems that Yukon II has Tx checksum offload bug for
2703 * small TCP packets that's less than 60 bytes in size
2704 * (e.g. TCP window probe packet, pure ACK packet).
2705 * Common work around like padding with zeros to make the
2706 * frame minimum ethernet frame size didn't work at all.
2707 * Instead of disabling checksum offload completely we
2708 * resort to S/W checksum routine when we encounter short
2709 * TCP frames.
2710 * Short UDP packets appear to be handled correctly by
2711 * Yukon II.
2712 */
2713 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN &&
2714 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2715 uint16_t csum;
2716
2717 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset -
2718 (ip->ip_hl << 2), offset);
2719 *(uint16_t *)(m->m_data + offset +
2720 m->m_pkthdr.csum_data) = csum;
2721 m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2722 }
2723 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2724 m = m_pullup(m, offset + sizeof(struct tcphdr));
2725 if (m == NULL) {
2726 *m_head = NULL;
2727 return (ENOBUFS);
2728 }
2729 tcp = (struct tcphdr *)(mtod(m, char *) + offset);
2730 offset += (tcp->th_off << 2);
2731 }
2732 *m_head = m;
2733 }
2734
2735 prod = sc_if->msk_cdata.msk_tx_prod;
2736 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2737 txd_last = txd;
2738 map = txd->tx_dmamap;
2739 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map,
2740 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2741 if (error == EFBIG) {
2742 m = msk_defrag(*m_head, M_DONTWAIT, MSK_MAXTXSEGS);
2743 if (m == NULL) {
2744 m_freem(*m_head);
2745 *m_head = NULL;
2746 return (ENOBUFS);
2747 }
2748 *m_head = m;
2749 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag,
2750 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2751 if (error != 0) {
2752 m_freem(*m_head);
2753 *m_head = NULL;
2754 return (error);
2755 }
2756 } else if (error != 0)
2757 return (error);
2758 if (nseg == 0) {
2759 m_freem(*m_head);
2760 *m_head = NULL;
2761 return (EIO);
2762 }
2763
2764 /* Check number of available descriptors. */
2765 if (sc_if->msk_cdata.msk_tx_cnt + nseg >=
2766 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
2767 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2768 return (ENOBUFS);
2769 }
2770
2771 control = 0;
2772 tso = 0;
2773 tx_le = NULL;
2774
2775 /* Check TSO support. */
2776 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2777 tso_mtu = offset + m->m_pkthdr.tso_segsz;
2778 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
2779 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2780 tx_le->msk_addr = htole32(tso_mtu);
2781 tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER);
2782 sc_if->msk_cdata.msk_tx_cnt++;
2783 MSK_INC(prod, MSK_TX_RING_CNT);
2784 sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
2785 }
2786 tso++;
2787 }
2788 /* Check if we have a VLAN tag to insert. */
2789 if ((m->m_flags & M_VLANTAG) != 0) {
2790 if (tso == 0) {
2791 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2792 tx_le->msk_addr = htole32(0);
2793 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2794 htons(m->m_pkthdr.ether_vtag));
2795 sc_if->msk_cdata.msk_tx_cnt++;
2796 MSK_INC(prod, MSK_TX_RING_CNT);
2797 } else {
2798 tx_le->msk_control |= htole32(OP_VLAN |
2799 htons(m->m_pkthdr.ether_vtag));
2800 }
2801 control |= INS_VLAN;
2802 }
2803 /* Check if we have to handle checksum offload. */
2804 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
2805 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2806 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data)
2807 & 0xffff) | ((uint32_t)tcp_offset << 16));
2808 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER));
2809 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2810 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2811 control |= UDPTCP;
2812 sc_if->msk_cdata.msk_tx_cnt++;
2813 MSK_INC(prod, MSK_TX_RING_CNT);
2814 }
2815
2816 si = prod;
2817 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2818 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2819 if (tso == 0)
2820 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2821 OP_PACKET);
2822 else
2823 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2824 OP_LARGESEND);
2825 sc_if->msk_cdata.msk_tx_cnt++;
2826 MSK_INC(prod, MSK_TX_RING_CNT);
2827
2828 for (i = 1; i < nseg; i++) {
2829 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2830 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2831 tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2832 OP_BUFFER | HW_OWNER);
2833 sc_if->msk_cdata.msk_tx_cnt++;
2834 MSK_INC(prod, MSK_TX_RING_CNT);
2835 }
2836 /* Update producer index. */
2837 sc_if->msk_cdata.msk_tx_prod = prod;
2838
2839 /* Set EOP on the last desciptor. */
2840 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2841 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2842 tx_le->msk_control |= htole32(EOP);
2843
2844 /* Turn the first descriptor ownership to hardware. */
2845 tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2846 tx_le->msk_control |= htole32(HW_OWNER);
2847
2848 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2849 map = txd_last->tx_dmamap;
2850 txd_last->tx_dmamap = txd->tx_dmamap;
2851 txd->tx_dmamap = map;
2852 txd->tx_m = m;
2853
2854 /* Sync descriptors. */
2855 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2856 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2857 sc_if->msk_cdata.msk_tx_ring_map,
2858 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2859
2860 return (0);
2861}
2862
2863static void
2864msk_tx_task(void *arg, int pending)
2865{
2866 struct ifnet *ifp;
2867
2868 ifp = arg;
2869 msk_start(ifp);
2870}
2871
2872static void
2873msk_start(struct ifnet *ifp)
2874{
2875 struct msk_if_softc *sc_if;
2876 struct mbuf *m_head;
2877 int enq;
2878
2879 sc_if = ifp->if_softc;
2880
2881 MSK_IF_LOCK(sc_if);
2882
2883 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2884 IFF_DRV_RUNNING || sc_if->msk_link == 0) {
2885 MSK_IF_UNLOCK(sc_if);
2886 return;
2887 }
2888
2889 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2890 sc_if->msk_cdata.msk_tx_cnt <
2891 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
2892 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2893 if (m_head == NULL)
2894 break;
2895 /*
2896 * Pack the data into the transmit ring. If we
2897 * don't have room, set the OACTIVE flag and wait
2898 * for the NIC to drain the ring.
2899 */
2900 if (msk_encap(sc_if, &m_head) != 0) {
2901 if (m_head == NULL)
2902 break;
2903 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2904 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2905 break;
2906 }
2907
2908 enq++;
2909 /*
2910 * If there's a BPF listener, bounce a copy of this frame
2911 * to him.
2912 */
2913 ETHER_BPF_MTAP(ifp, m_head);
2914 }
2915
2916 if (enq > 0) {
2917 /* Transmit */
2918 CSR_WRITE_2(sc_if->msk_softc,
2919 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2920 sc_if->msk_cdata.msk_tx_prod);
2921
2922 /* Set a timeout in case the chip goes out to lunch. */
2923 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
2924 }
2925
2926 MSK_IF_UNLOCK(sc_if);
2927}
2928
2929static void
2930msk_watchdog(struct msk_if_softc *sc_if)
2931{
2932 struct ifnet *ifp;
2933 uint32_t ridx;
2934 int idx;
2935
2936 MSK_IF_LOCK_ASSERT(sc_if);
2937
2938 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
2939 return;
2940 ifp = sc_if->msk_ifp;
2941 if (sc_if->msk_link == 0) {
2942 if (bootverbose)
2943 if_printf(sc_if->msk_ifp, "watchdog timeout "
2944 "(missed link)\n");
2945 ifp->if_oerrors++;
2946 msk_init_locked(sc_if);
2947 return;
2948 }
2949
2950 /*
2951 * Reclaim first as there is a possibility of losing Tx completion
2952 * interrupts.
2953 */
2954 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX;
2955 idx = CSR_READ_2(sc_if->msk_softc, ridx);
2956 if (sc_if->msk_cdata.msk_tx_cons != idx) {
2957 msk_txeof(sc_if, idx);
2958 if (sc_if->msk_cdata.msk_tx_cnt == 0) {
2959 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
2960 "-- recovering\n");
2961 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2962 taskqueue_enqueue(taskqueue_fast,
2963 &sc_if->msk_tx_task);
2964 return;
2965 }
2966 }
2967
2968 if_printf(ifp, "watchdog timeout\n");
2969 ifp->if_oerrors++;
2970 msk_init_locked(sc_if);
2971 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2972 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task);
2973}
2974
2975static void
2976mskc_shutdown(device_t dev)
2977{
2978 struct msk_softc *sc;
2979 int i;
2980
2981 sc = device_get_softc(dev);
2982 MSK_LOCK(sc);
2983 for (i = 0; i < sc->msk_num_port; i++) {
2984 if (sc->msk_if[i] != NULL)
2985 msk_stop(sc->msk_if[i]);
2986 }
2987
2988 /* Disable all interrupts. */
2989 CSR_WRITE_4(sc, B0_IMSK, 0);
2990 CSR_READ_4(sc, B0_IMSK);
2991 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2992 CSR_READ_4(sc, B0_HWE_IMSK);
2993
2994 /* Put hardware reset. */
2995 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2996
2997 MSK_UNLOCK(sc);
2998}
2999
3000static int
3001mskc_suspend(device_t dev)
3002{
3003 struct msk_softc *sc;
3004 int i;
3005
3006 sc = device_get_softc(dev);
3007
3008 MSK_LOCK(sc);
3009
3010 for (i = 0; i < sc->msk_num_port; i++) {
3011 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3012 ((sc->msk_if[i]->msk_ifp->if_drv_flags &
3013 IFF_DRV_RUNNING) != 0))
3014 msk_stop(sc->msk_if[i]);
3015 }
3016
3017 /* Disable all interrupts. */
3018 CSR_WRITE_4(sc, B0_IMSK, 0);
3019 CSR_READ_4(sc, B0_IMSK);
3020 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
3021 CSR_READ_4(sc, B0_HWE_IMSK);
3022
3023 msk_phy_power(sc, MSK_PHY_POWERDOWN);
3024
3025 /* Put hardware reset. */
3026 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3027 sc->msk_suspended = 1;
3028
3029 MSK_UNLOCK(sc);
3030
3031 return (0);
3032}
3033
3034static int
3035mskc_resume(device_t dev)
3036{
3037 struct msk_softc *sc;
3038 int i;
3039
3040 sc = device_get_softc(dev);
3041
3042 MSK_LOCK(sc);
3043
3044 mskc_reset(sc);
3045 for (i = 0; i < sc->msk_num_port; i++) {
3046 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3047 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0))
3048 msk_init_locked(sc->msk_if[i]);
3049 }
3050 sc->msk_suspended = 0;
3051
3052 MSK_UNLOCK(sc);
3053
3054 return (0);
3055}
3056
3057static void
3058msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
3059{
3060 struct mbuf *m;
3061 struct ifnet *ifp;
3062 struct msk_rxdesc *rxd;
3063 int cons, rxlen;
3064
3065 ifp = sc_if->msk_ifp;
3066
3067 MSK_IF_LOCK_ASSERT(sc_if);
3068
3069 cons = sc_if->msk_cdata.msk_rx_cons;
3070 do {
3071 rxlen = status >> 16;
3072 if ((status & GMR_FS_VLAN) != 0 &&
3073 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3074 rxlen -= ETHER_VLAN_ENCAP_LEN;
3075 if (len > sc_if->msk_framesize ||
3076 ((status & GMR_FS_ANY_ERR) != 0) ||
3077 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3078 /* Don't count flow-control packet as errors. */
3079 if ((status & GMR_FS_GOOD_FC) == 0)
3080 ifp->if_ierrors++;
3081 msk_discard_rxbuf(sc_if, cons);
3082 break;
3083 }
3084 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
3085 m = rxd->rx_m;
3086 if (msk_newbuf(sc_if, cons) != 0) {
3087 ifp->if_iqdrops++;
3088 /* Reuse old buffer. */
3089 msk_discard_rxbuf(sc_if, cons);
3090 break;
3091 }
3092 m->m_pkthdr.rcvif = ifp;
3093 m->m_pkthdr.len = m->m_len = len;
3094 ifp->if_ipackets++;
3095 /* Check for VLAN tagged packets. */
3096 if ((status & GMR_FS_VLAN) != 0 &&
3097 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
3098 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3099 m->m_flags |= M_VLANTAG;
3100 }
3101 MSK_IF_UNLOCK(sc_if);
3102 (*ifp->if_input)(ifp, m);
3103 MSK_IF_LOCK(sc_if);
3104 } while (0);
3105
3106 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
3107 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
3108}
3109
3110static void
3111msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
3112{
3113 struct mbuf *m;
3114 struct ifnet *ifp;
3115 struct msk_rxdesc *jrxd;
3116 int cons, rxlen;
3117
3118 ifp = sc_if->msk_ifp;
3119
3120 MSK_IF_LOCK_ASSERT(sc_if);
3121
3122 cons = sc_if->msk_cdata.msk_rx_cons;
3123 do {
3124 rxlen = status >> 16;
3125 if ((status & GMR_FS_VLAN) != 0 &&
3126 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3127 rxlen -= ETHER_VLAN_ENCAP_LEN;
3128 if (len > sc_if->msk_framesize ||
3129 ((status & GMR_FS_ANY_ERR) != 0) ||
3130 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3131 /* Don't count flow-control packet as errors. */
3132 if ((status & GMR_FS_GOOD_FC) == 0)
3133 ifp->if_ierrors++;
3134 msk_discard_jumbo_rxbuf(sc_if, cons);
3135 break;
3136 }
3137 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
3138 m = jrxd->rx_m;
3139 if (msk_jumbo_newbuf(sc_if, cons) != 0) {
3140 ifp->if_iqdrops++;
3141 /* Reuse old buffer. */
3142 msk_discard_jumbo_rxbuf(sc_if, cons);
3143 break;
3144 }
3145 m->m_pkthdr.rcvif = ifp;
3146 m->m_pkthdr.len = m->m_len = len;
3147 ifp->if_ipackets++;
3148 /* Check for VLAN tagged packets. */
3149 if ((status & GMR_FS_VLAN) != 0 &&
3150 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
3151 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3152 m->m_flags |= M_VLANTAG;
3153 }
3154 MSK_IF_UNLOCK(sc_if);
3155 (*ifp->if_input)(ifp, m);
3156 MSK_IF_LOCK(sc_if);
3157 } while (0);
3158
3159 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
3160 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
3161}
3162
3163static void
3164msk_txeof(struct msk_if_softc *sc_if, int idx)
3165{
3166 struct msk_txdesc *txd;
3167 struct msk_tx_desc *cur_tx;
3168 struct ifnet *ifp;
3169 uint32_t control;
3170 int cons, prog;
3171
3172 MSK_IF_LOCK_ASSERT(sc_if);
3173
3174 ifp = sc_if->msk_ifp;
3175
3176 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
3177 sc_if->msk_cdata.msk_tx_ring_map,
3178 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3179 /*
3180 * Go through our tx ring and free mbufs for those
3181 * frames that have been sent.
3182 */
3183 cons = sc_if->msk_cdata.msk_tx_cons;
3184 prog = 0;
3185 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
3186 if (sc_if->msk_cdata.msk_tx_cnt <= 0)
3187 break;
3188 prog++;
3189 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
3190 control = le32toh(cur_tx->msk_control);
3191 sc_if->msk_cdata.msk_tx_cnt--;
3192 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3193 if ((control & EOP) == 0)
3194 continue;
3195 txd = &sc_if->msk_cdata.msk_txdesc[cons];
3196 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
3197 BUS_DMASYNC_POSTWRITE);
3198 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
3199
3200 ifp->if_opackets++;
3201 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
3202 __func__));
3203 m_freem(txd->tx_m);
3204 txd->tx_m = NULL;
3205 }
3206
3207 if (prog > 0) {
3208 sc_if->msk_cdata.msk_tx_cons = cons;
3209 if (sc_if->msk_cdata.msk_tx_cnt == 0)
3210 sc_if->msk_watchdog_timer = 0;
3211 /* No need to sync LEs as we didn't update LEs. */
3212 }
3213}
3214
3215static void
3216msk_tick(void *xsc_if)
3217{
3218 struct msk_if_softc *sc_if;
3219 struct mii_data *mii;
3220
3221 sc_if = xsc_if;
3222
3223 MSK_IF_LOCK_ASSERT(sc_if);
3224
3225 mii = device_get_softc(sc_if->msk_miibus);
3226
3227 mii_tick(mii);
3228 msk_watchdog(sc_if);
3229 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3230}
3231
3232static void
3233msk_intr_phy(struct msk_if_softc *sc_if)
3234{
3235 uint16_t status;
3236
3237 if (sc_if->msk_softc->msk_marvell_phy) {
3238 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3239 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV,
3240 PHY_MARV_INT_STAT);
3241 /* Handle FIFO Underrun/Overflow? */
3242 if ((status & PHY_M_IS_FIFO_ERROR))
3243 device_printf(sc_if->msk_if_dev,
3244 "PHY FIFO underrun/overflow.\n");
3245 }
3246}
3247
3248static void
3249msk_intr_gmac(struct msk_if_softc *sc_if)
3250{
3251 struct msk_softc *sc;
3252 uint8_t status;
3253
3254 sc = sc_if->msk_softc;
3255 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3256
3257 /* GMAC Rx FIFO overrun. */
3258 if ((status & GM_IS_RX_FF_OR) != 0) {
3259 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3260 GMF_CLI_RX_FO);
3261 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n");
3262 }
3263 /* GMAC Tx FIFO underrun. */
3264 if ((status & GM_IS_TX_FF_UR) != 0) {
3265 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3266 GMF_CLI_TX_FU);
3267 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
3268 /*
3269 * XXX
3270 * In case of Tx underrun, we may need to flush/reset
3271 * Tx MAC but that would also require resynchronization
3272 * with status LEs. Reintializing status LEs would
3273 * affect other port in dual MAC configuration so it
3274 * should be avoided as possible as we can.
3275 * Due to lack of documentation it's all vague guess but
3276 * it needs more investigation.
3277 */
3278 }
3279}
3280
3281static void
3282msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
3283{
3284 struct msk_softc *sc;
3285
3286 sc = sc_if->msk_softc;
3287 if ((status & Y2_IS_PAR_RD1) != 0) {
3288 device_printf(sc_if->msk_if_dev,
3289 "RAM buffer read parity error\n");
3290 /* Clear IRQ. */
3291 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3292 RI_CLR_RD_PERR);
3293 }
3294 if ((status & Y2_IS_PAR_WR1) != 0) {
3295 device_printf(sc_if->msk_if_dev,
3296 "RAM buffer write parity error\n");
3297 /* Clear IRQ. */
3298 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3299 RI_CLR_WR_PERR);
3300 }
3301 if ((status & Y2_IS_PAR_MAC1) != 0) {
3302 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3303 /* Clear IRQ. */
3304 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3305 GMF_CLI_TX_PE);
3306 }
3307 if ((status & Y2_IS_PAR_RX1) != 0) {
3308 device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3309 /* Clear IRQ. */
3310 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3311 }
3312 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
3313 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3314 /* Clear IRQ. */
3315 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3316 }
3317}
3318
3319static void
3320msk_intr_hwerr(struct msk_softc *sc)
3321{
3322 uint32_t status;
3323 uint32_t tlphead[4];
3324
3325 status = CSR_READ_4(sc, B0_HWE_ISRC);
3326 /* Time Stamp timer overflow. */
3327 if ((status & Y2_IS_TIST_OV) != 0)
3328 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3329 if ((status & Y2_IS_PCI_NEXP) != 0) {
3330 /*
3331 * PCI Express Error occured which is not described in PEX
3332 * spec.
3333 * This error is also mapped either to Master Abort(
3334 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
3335 * can only be cleared there.
3336 */
3337 device_printf(sc->msk_dev,
3338 "PCI Express protocol violation error\n");
3339 }
3340
3341 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
3342 uint16_t v16;
3343
3344 if ((status & Y2_IS_MST_ERR) != 0)
3345 device_printf(sc->msk_dev,
3346 "unexpected IRQ Status error\n");
3347 else
3348 device_printf(sc->msk_dev,
3349 "unexpected IRQ Master error\n");
3350 /* Reset all bits in the PCI status register. */
3351 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3352 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3353 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3354 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3355 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2);
3356 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3357 }
3358
3359 /* Check for PCI Express Uncorrectable Error. */
3360 if ((status & Y2_IS_PCI_EXP) != 0) {
3361 uint32_t v32;
3362
3363 /*
3364 * On PCI Express bus bridges are called root complexes (RC).
3365 * PCI Express errors are recognized by the root complex too,
3366 * which requests the system to handle the problem. After
3367 * error occurence it may be that no access to the adapter
3368 * may be performed any longer.
3369 */
3370
3371 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
3372 if ((v32 & PEX_UNSUP_REQ) != 0) {
3373 /* Ignore unsupported request error. */
3374 device_printf(sc->msk_dev,
3375 "Uncorrectable PCI Express error\n");
3376 }
3377 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
3378 int i;
3379
3380 /* Get TLP header form Log Registers. */
3381 for (i = 0; i < 4; i++)
3382 tlphead[i] = CSR_PCI_READ_4(sc,
3383 PEX_HEADER_LOG + i * 4);
3384 /* Check for vendor defined broadcast message. */
3385 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
3386 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3387 CSR_WRITE_4(sc, B0_HWE_IMSK,
3388 sc->msk_intrhwemask);
3389 CSR_READ_4(sc, B0_HWE_IMSK);
3390 }
3391 }
3392 /* Clear the interrupt. */
3393 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3394 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
3395 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3396 }
3397
3398 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3399 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3400 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3401 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3402}
3403
3404static __inline void
3405msk_rxput(struct msk_if_softc *sc_if)
3406{
3407 struct msk_softc *sc;
3408
3409 sc = sc_if->msk_softc;
3410 if (sc_if->msk_framesize >(MCLBYTES - ETHER_HDR_LEN))
3411 bus_dmamap_sync(
3412 sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3413 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3414 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3415 else
3416 bus_dmamap_sync(
3417 sc_if->msk_cdata.msk_rx_ring_tag,
3418 sc_if->msk_cdata.msk_rx_ring_map,
3419 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3420 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3421 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3422}
3423
3424static int
3425msk_handle_events(struct msk_softc *sc)
3426{
3427 struct msk_if_softc *sc_if;
3428 int rxput[2];
3429 struct msk_stat_desc *sd;
3430 uint32_t control, status;
3431 int cons, idx, len, port, rxprog;
3432
3433 idx = CSR_READ_2(sc, STAT_PUT_IDX);
3434 if (idx == sc->msk_stat_cons)
3435 return (0);
3436
3437 /* Sync status LEs. */
3438 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3439 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3440 /* XXX Sync Rx LEs here. */
3441
3442 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
3443
3444 rxprog = 0;
3445 for (cons = sc->msk_stat_cons; cons != idx;) {
3446 sd = &sc->msk_stat_ring[cons];
3447 control = le32toh(sd->msk_control);
3448 if ((control & HW_OWNER) == 0)
3449 break;
3450 /*
3451 * Marvell's FreeBSD driver updates status LE after clearing
3452 * HW_OWNER. However we don't have a way to sync single LE
3453 * with bus_dma(9) API. bus_dma(9) provides a way to sync
3454 * an entire DMA map. So don't sync LE until we have a better
3455 * way to sync LEs.
3456 */
3457 control &= ~HW_OWNER;
3458 sd->msk_control = htole32(control);
3459 status = le32toh(sd->msk_status);
3460 len = control & STLE_LEN_MASK;
3461 port = (control >> 16) & 0x01;
3462 sc_if = sc->msk_if[port];
3463 if (sc_if == NULL) {
3464 device_printf(sc->msk_dev, "invalid port opcode "
3465 "0x%08x\n", control & STLE_OP_MASK);
3466 continue;
3467 }
3468
3469 switch (control & STLE_OP_MASK) {
3470 case OP_RXVLAN:
3471 sc_if->msk_vtag = ntohs(len);
3472 break;
3473 case OP_RXCHKSVLAN:
3474 sc_if->msk_vtag = ntohs(len);
3475 break;
3476 case OP_RXSTAT:
3477 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN))
3478 msk_jumbo_rxeof(sc_if, status, len);
3479 else
3480 msk_rxeof(sc_if, status, len);
3481 rxprog++;
3482 /*
3483 * Because there is no way to sync single Rx LE
3484 * put the DMA sync operation off until the end of
3485 * event processing.
3486 */
3487 rxput[port]++;
3488 /* Update prefetch unit if we've passed water mark. */
3489 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3490 msk_rxput(sc_if);
3491 rxput[port] = 0;
3492 }
3493 break;
3494 case OP_TXINDEXLE:
3495 if (sc->msk_if[MSK_PORT_A] != NULL)
3496 msk_txeof(sc->msk_if[MSK_PORT_A],
3497 status & STLE_TXA1_MSKL);
3498 if (sc->msk_if[MSK_PORT_B] != NULL)
3499 msk_txeof(sc->msk_if[MSK_PORT_B],
3500 ((status & STLE_TXA2_MSKL) >>
3501 STLE_TXA2_SHIFTL) |
3502 ((len & STLE_TXA2_MSKH) <<
3503 STLE_TXA2_SHIFTH));
3504 break;
3505 default:
3506 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3507 control & STLE_OP_MASK);
3508 break;
3509 }
3510 MSK_INC(cons, MSK_STAT_RING_CNT);
3511 if (rxprog > sc->msk_process_limit)
3512 break;
3513 }
3514
3515 sc->msk_stat_cons = cons;
3516 /* XXX We should sync status LEs here. See above notes. */
3517
3518 if (rxput[MSK_PORT_A] > 0)
3519 msk_rxput(sc->msk_if[MSK_PORT_A]);
3520 if (rxput[MSK_PORT_B] > 0)
3521 msk_rxput(sc->msk_if[MSK_PORT_B]);
3522
3523 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3524}
3525
3526/* Legacy interrupt handler for shared interrupt. */
3527static void
3528msk_legacy_intr(void *xsc)
3529{
3530 struct msk_softc *sc;
3531 struct msk_if_softc *sc_if0, *sc_if1;
3532 struct ifnet *ifp0, *ifp1;
3533 uint32_t status;
3534
3535 sc = xsc;
3536 MSK_LOCK(sc);
3537
3538 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3539 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3540 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 ||
3541 (status & sc->msk_intrmask) == 0) {
3542 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3543 return;
3544 }
3545
3546 sc_if0 = sc->msk_if[MSK_PORT_A];
3547 sc_if1 = sc->msk_if[MSK_PORT_B];
3548 ifp0 = ifp1 = NULL;
3549 if (sc_if0 != NULL)
3550 ifp0 = sc_if0->msk_ifp;
3551 if (sc_if1 != NULL)
3552 ifp1 = sc_if1->msk_ifp;
3553
3554 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3555 msk_intr_phy(sc_if0);
3556 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3557 msk_intr_phy(sc_if1);
3558 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3559 msk_intr_gmac(sc_if0);
3560 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3561 msk_intr_gmac(sc_if1);
3562 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3563 device_printf(sc->msk_dev, "Rx descriptor error\n");
3564 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3565 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3566 CSR_READ_4(sc, B0_IMSK);
3567 }
3568 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3569 device_printf(sc->msk_dev, "Tx descriptor error\n");
3570 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3571 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3572 CSR_READ_4(sc, B0_IMSK);
3573 }
3574 if ((status & Y2_IS_HW_ERR) != 0)
3575 msk_intr_hwerr(sc);
3576
3577 while (msk_handle_events(sc) != 0)
3578 ;
3579 if ((status & Y2_IS_STAT_BMU) != 0)
3580 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3581
3582 /* Reenable interrupts. */
3583 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3584
3585 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3586 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3587 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task);
3588 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3589 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3590 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task);
3591
3592 MSK_UNLOCK(sc);
3593}
3594
3595static int
3596msk_intr(void *xsc)
3597{
3598 struct msk_softc *sc;
3599 uint32_t status;
3600
3601 sc = xsc;
3602 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3603 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3604 if (status == 0 || status == 0xffffffff) {
3605 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3606 return (FILTER_STRAY);
3607 }
3608
3609 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task);
3610 return (FILTER_HANDLED);
3611}
3612
3613static void
3614msk_int_task(void *arg, int pending)
3615{
3616 struct msk_softc *sc;
3617 struct msk_if_softc *sc_if0, *sc_if1;
3618 struct ifnet *ifp0, *ifp1;
3619 uint32_t status;
3620 int domore;
3621
3622 sc = arg;
3623 MSK_LOCK(sc);
3624
3625 /* Get interrupt source. */
3626 status = CSR_READ_4(sc, B0_ISRC);
3627 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 ||
3628 (status & sc->msk_intrmask) == 0)
3629 goto done;
3630
3631 sc_if0 = sc->msk_if[MSK_PORT_A];
3632 sc_if1 = sc->msk_if[MSK_PORT_B];
3633 ifp0 = ifp1 = NULL;
3634 if (sc_if0 != NULL)
3635 ifp0 = sc_if0->msk_ifp;
3636 if (sc_if1 != NULL)
3637 ifp1 = sc_if1->msk_ifp;
3638
3639 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3640 msk_intr_phy(sc_if0);
3641 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3642 msk_intr_phy(sc_if1);
3643 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3644 msk_intr_gmac(sc_if0);
3645 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3646 msk_intr_gmac(sc_if1);
3647 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3648 device_printf(sc->msk_dev, "Rx descriptor error\n");
3649 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3650 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3651 CSR_READ_4(sc, B0_IMSK);
3652 }
3653 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3654 device_printf(sc->msk_dev, "Tx descriptor error\n");
3655 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3656 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3657 CSR_READ_4(sc, B0_IMSK);
3658 }
3659 if ((status & Y2_IS_HW_ERR) != 0)
3660 msk_intr_hwerr(sc);
3661
3662 domore = msk_handle_events(sc);
3663 if ((status & Y2_IS_STAT_BMU) != 0)
3664 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3665
3666 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3667 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3668 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task);
3669 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3670 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3671 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task);
3672
3673 if (domore > 0) {
3674 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task);
3675 MSK_UNLOCK(sc);
3676 return;
3677 }
3678done:
3679 MSK_UNLOCK(sc);
3680
3681 /* Reenable interrupts. */
3682 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3683}
3684
3685static void
3686msk_init(void *xsc)
3687{
3688 struct msk_if_softc *sc_if = xsc;
3689
3690 MSK_IF_LOCK(sc_if);
3691 msk_init_locked(sc_if);
3692 MSK_IF_UNLOCK(sc_if);
3693}
3694
3695static void
3696msk_init_locked(struct msk_if_softc *sc_if)
3697{
3698 struct msk_softc *sc;
3699 struct ifnet *ifp;
3700 struct mii_data *mii;
3701 uint16_t eaddr[ETHER_ADDR_LEN / 2];
3702 uint16_t gmac;
3703 int error, i;
3704
3705 MSK_IF_LOCK_ASSERT(sc_if);
3706
3707 ifp = sc_if->msk_ifp;
3708 sc = sc_if->msk_softc;
3709 mii = device_get_softc(sc_if->msk_miibus);
3710
3711 error = 0;
3712 /* Cancel pending I/O and free all Rx/Tx buffers. */
3713 msk_stop(sc_if);
3714
3715 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN +
3716 ETHER_VLAN_ENCAP_LEN;
|
| 3717 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
3718 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
3719 /*
3720 * In Yukon EC Ultra, TSO & checksum offload is not
3721 * supported for jumbo frame.
3722 */
3723 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
3724 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
3725 }
|
3709
3710 /*
3711 * Initialize GMAC first.
3712 * Without this initialization, Rx MAC did not work as expected
3713 * and Rx MAC garbled status LEs and it resulted in out-of-order
3714 * or duplicated frame delivery which in turn showed very poor
3715 * Rx performance.(I had to write a packet analysis code that
3716 * could be embeded in driver to diagnose this issue.)
3717 * I've spent almost 2 months to fix this issue. If I have had
3718 * datasheet for Yukon II I wouldn't have encountered this. :-(
3719 */
3720 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL;
3721 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
3722
3723 /* Dummy read the Interrupt Source Register. */
3724 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3725
3726 /* Set MIB Clear Counter Mode. */
3727 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
3728 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
3729 /* Read all MIB Counters with Clear Mode set. */
3730 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
3731 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i);
3732 /* Clear MIB Clear Counter Mode. */
3733 gmac &= ~GM_PAR_MIB_CLR;
3734 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
3735
3736 /* Disable FCS. */
3737 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3738
3739 /* Setup Transmit Control Register. */
3740 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3741
3742 /* Setup Transmit Flow Control Register. */
3743 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3744
3745 /* Setup Transmit Parameter Register. */
3746 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3747 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
3748 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
3749
3750 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
3751 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
3752
3753 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN)
3754 gmac |= GM_SMOD_JUMBO_ENA;
3755 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3756
3757 /* Set station address. */
3758 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
3759 for (i = 0; i < ETHER_ADDR_LEN /2; i++)
3760 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4,
3761 eaddr[i]);
3762 for (i = 0; i < ETHER_ADDR_LEN /2; i++)
3763 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4,
3764 eaddr[i]);
3765
3766 /* Disable interrupts for counter overflows. */
3767 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3768 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3769 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3770
3771 /* Configure Rx MAC FIFO. */
3772 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3773 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3774 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3775 GMF_OPER_ON | GMF_RX_F_FL_ON);
3776
3777 /* Set promiscuous mode. */
3778 msk_setpromisc(sc_if);
3779
3780 /* Set multicast filter. */
3781 msk_setmulti(sc_if);
3782
3783 /* Flush Rx MAC FIFO on any flow control or error. */
3784 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3785 GMR_FS_ANY_ERR);
3786
3787 /* Set Rx FIFO flush threshold to 64 bytes. */
3788 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR),
3789 RX_GMF_FL_THR_DEF);
3790
3791 /* Configure Tx MAC FIFO. */
3792 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3793 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3794 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3795
3796 /* Configure hardware VLAN tag insertion/stripping. */
3797 msk_setvlan(sc_if, ifp);
3798
| 3726
3727 /*
3728 * Initialize GMAC first.
3729 * Without this initialization, Rx MAC did not work as expected
3730 * and Rx MAC garbled status LEs and it resulted in out-of-order
3731 * or duplicated frame delivery which in turn showed very poor
3732 * Rx performance.(I had to write a packet analysis code that
3733 * could be embeded in driver to diagnose this issue.)
3734 * I've spent almost 2 months to fix this issue. If I have had
3735 * datasheet for Yukon II I wouldn't have encountered this. :-(
3736 */
3737 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL;
3738 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
3739
3740 /* Dummy read the Interrupt Source Register. */
3741 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3742
3743 /* Set MIB Clear Counter Mode. */
3744 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
3745 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
3746 /* Read all MIB Counters with Clear Mode set. */
3747 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
3748 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i);
3749 /* Clear MIB Clear Counter Mode. */
3750 gmac &= ~GM_PAR_MIB_CLR;
3751 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
3752
3753 /* Disable FCS. */
3754 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3755
3756 /* Setup Transmit Control Register. */
3757 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3758
3759 /* Setup Transmit Flow Control Register. */
3760 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3761
3762 /* Setup Transmit Parameter Register. */
3763 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3764 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
3765 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
3766
3767 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
3768 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
3769
3770 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN)
3771 gmac |= GM_SMOD_JUMBO_ENA;
3772 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3773
3774 /* Set station address. */
3775 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
3776 for (i = 0; i < ETHER_ADDR_LEN /2; i++)
3777 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4,
3778 eaddr[i]);
3779 for (i = 0; i < ETHER_ADDR_LEN /2; i++)
3780 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4,
3781 eaddr[i]);
3782
3783 /* Disable interrupts for counter overflows. */
3784 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3785 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3786 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3787
3788 /* Configure Rx MAC FIFO. */
3789 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3790 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3791 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3792 GMF_OPER_ON | GMF_RX_F_FL_ON);
3793
3794 /* Set promiscuous mode. */
3795 msk_setpromisc(sc_if);
3796
3797 /* Set multicast filter. */
3798 msk_setmulti(sc_if);
3799
3800 /* Flush Rx MAC FIFO on any flow control or error. */
3801 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3802 GMR_FS_ANY_ERR);
3803
3804 /* Set Rx FIFO flush threshold to 64 bytes. */
3805 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR),
3806 RX_GMF_FL_THR_DEF);
3807
3808 /* Configure Tx MAC FIFO. */
3809 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3810 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3811 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3812
3813 /* Configure hardware VLAN tag insertion/stripping. */
3814 msk_setvlan(sc_if, ifp);
3815
|
3799 /* XXX It seems STFW is requried for all cases. */
3800 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), TX_STFW_ENA);
3801
| |
3802 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
3803 /* Set Rx Pause threshould. */
3804 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3805 MSK_ECU_LLPP);
3806 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3807 MSK_ECU_ULPP);
3808 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) {
3809 /*
| 3816 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
3817 /* Set Rx Pause threshould. */
3818 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3819 MSK_ECU_LLPP);
3820 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3821 MSK_ECU_ULPP);
3822 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) {
3823 /*
|
3810 * Can't sure the following code is needed as Yukon
3811 * Yukon EC Ultra may not support jumbo frames.
3812 *
| |
3813 * Set Tx GMAC FIFO Almost Empty Threshold.
3814 */
3815 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
| 3824 * Set Tx GMAC FIFO Almost Empty Threshold.
3825 */
3826 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
|
3816 MSK_ECU_AE_THR);
| 3827 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
|
3817 /* Disable Store & Forward mode for Tx. */
3818 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
| 3828 /* Disable Store & Forward mode for Tx. */
3829 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
|
3819 TX_STFW_DIS);
| 3830 TX_JUMBO_ENA | TX_STFW_DIS);
3831 } else {
3832 /* Enable Store & Forward mode for Tx. */
3833 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3834 TX_JUMBO_DIS | TX_STFW_ENA);
|
3820 }
3821 }
3822
3823 /*
3824 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3825 * arbiter as we don't use Sync Tx queue.
3826 */
3827 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3828 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
3829 /* Enable the RAM Interface Arbiter. */
3830 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3831
3832 /* Setup RAM buffer. */
3833 msk_set_rambuffer(sc_if);
3834
3835 /* Disable Tx sync Queue. */
3836 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3837
3838 /* Setup Tx Queue Bus Memory Interface. */
3839 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3840 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3841 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3842 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3843 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3844 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3845 /* Fix for Yukon-EC Ultra: set BMU FIFO level */
3846 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV);
3847 }
3848
3849 /* Setup Rx Queue Bus Memory Interface. */
3850 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3851 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3852 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3853 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3854 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3855 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
3856 /* MAC Rx RAM Read is controlled by hardware. */
3857 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
3858 }
3859
3860 msk_set_prefetch(sc, sc_if->msk_txq,
3861 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
3862 msk_init_tx_ring(sc_if);
3863
3864 /* Disable Rx checksum offload and RSS hash. */
3865 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
3866 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH);
3867 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) {
3868 msk_set_prefetch(sc, sc_if->msk_rxq,
3869 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
3870 MSK_JUMBO_RX_RING_CNT - 1);
3871 error = msk_init_jumbo_rx_ring(sc_if);
3872 } else {
3873 msk_set_prefetch(sc, sc_if->msk_rxq,
3874 sc_if->msk_rdata.msk_rx_ring_paddr,
3875 MSK_RX_RING_CNT - 1);
3876 error = msk_init_rx_ring(sc_if);
3877 }
3878 if (error != 0) {
3879 device_printf(sc_if->msk_if_dev,
3880 "initialization failed: no memory for Rx buffers\n");
3881 msk_stop(sc_if);
3882 return;
3883 }
3884
3885 /* Configure interrupt handling. */
3886 if (sc_if->msk_port == MSK_PORT_A) {
3887 sc->msk_intrmask |= Y2_IS_PORT_A;
3888 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
3889 } else {
3890 sc->msk_intrmask |= Y2_IS_PORT_B;
3891 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
3892 }
3893 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
3894 CSR_READ_4(sc, B0_HWE_IMSK);
3895 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3896 CSR_READ_4(sc, B0_IMSK);
3897
3898 sc_if->msk_link = 0;
3899 mii_mediachg(mii);
3900
3901 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3902 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3903
3904 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3905}
3906
3907static void
3908msk_set_rambuffer(struct msk_if_softc *sc_if)
3909{
3910 struct msk_softc *sc;
3911 int ltpp, utpp;
3912
3913 sc = sc_if->msk_softc;
3914
3915 /* Setup Rx Queue. */
3916 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
3917 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
3918 sc->msk_rxqstart[sc_if->msk_port] / 8);
3919 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
3920 sc->msk_rxqend[sc_if->msk_port] / 8);
3921 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
3922 sc->msk_rxqstart[sc_if->msk_port] / 8);
3923 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
3924 sc->msk_rxqstart[sc_if->msk_port] / 8);
3925
3926 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
3927 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
3928 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
3929 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
3930 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
3931 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
3932 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
3933 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
3934 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
3935
3936 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
3937 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
3938
3939 /* Setup Tx Queue. */
3940 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
3941 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
3942 sc->msk_txqstart[sc_if->msk_port] / 8);
3943 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
3944 sc->msk_txqend[sc_if->msk_port] / 8);
3945 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
3946 sc->msk_txqstart[sc_if->msk_port] / 8);
3947 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
3948 sc->msk_txqstart[sc_if->msk_port] / 8);
3949 /* Enable Store & Forward for Tx side. */
3950 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
3951 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
3952 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
3953}
3954
3955static void
3956msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
3957 uint32_t count)
3958{
3959
3960 /* Reset the prefetch unit. */
3961 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3962 PREF_UNIT_RST_SET);
3963 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3964 PREF_UNIT_RST_CLR);
3965 /* Set LE base address. */
3966 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
3967 MSK_ADDR_LO(addr));
3968 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
3969 MSK_ADDR_HI(addr));
3970 /* Set the list last index. */
3971 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
3972 count);
3973 /* Turn on prefetch unit. */
3974 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3975 PREF_UNIT_OP_ON);
3976 /* Dummy read to ensure write. */
3977 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
3978}
3979
3980static void
3981msk_stop(struct msk_if_softc *sc_if)
3982{
3983 struct msk_softc *sc;
3984 struct msk_txdesc *txd;
3985 struct msk_rxdesc *rxd;
3986 struct msk_rxdesc *jrxd;
3987 struct ifnet *ifp;
3988 uint32_t val;
3989 int i;
3990
3991 MSK_IF_LOCK_ASSERT(sc_if);
3992 sc = sc_if->msk_softc;
3993 ifp = sc_if->msk_ifp;
3994
3995 callout_stop(&sc_if->msk_tick_ch);
3996 sc_if->msk_watchdog_timer = 0;
3997
3998 /* Disable interrupts. */
3999 if (sc_if->msk_port == MSK_PORT_A) {
4000 sc->msk_intrmask &= ~Y2_IS_PORT_A;
4001 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
4002 } else {
4003 sc->msk_intrmask &= ~Y2_IS_PORT_B;
4004 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
4005 }
4006 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4007 CSR_READ_4(sc, B0_HWE_IMSK);
4008 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4009 CSR_READ_4(sc, B0_IMSK);
4010
4011 /* Disable Tx/Rx MAC. */
4012 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4013 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
4014 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
4015 /* Read again to ensure writing. */
4016 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4017
4018 /* Stop Tx BMU. */
4019 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4020 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4021 for (i = 0; i < MSK_TIMEOUT; i++) {
4022 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
4023 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4024 BMU_STOP);
4025 CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4026 } else
4027 break;
4028 DELAY(1);
4029 }
4030 if (i == MSK_TIMEOUT)
4031 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
4032 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
4033 RB_RST_SET | RB_DIS_OP_MD);
4034
4035 /* Disable all GMAC interrupt. */
4036 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
4037 /* Disable PHY interrupt. */
4038 if (sc->msk_marvell_phy)
4039 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
4040
4041 /* Disable the RAM Interface Arbiter. */
4042 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
4043
4044 /* Reset the PCI FIFO of the async Tx queue */
4045 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4046 BMU_RST_SET | BMU_FIFO_RST);
4047
4048 /* Reset the Tx prefetch units. */
4049 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4050 PREF_UNIT_RST_SET);
4051
4052 /* Reset the RAM Buffer async Tx queue. */
4053 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
4054
4055 /* Reset Tx MAC FIFO. */
4056 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
4057 /* Set Pause Off. */
4058 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
4059
4060 /*
4061 * The Rx Stop command will not work for Yukon-2 if the BMU does not
4062 * reach the end of packet and since we can't make sure that we have
4063 * incoming data, we must reset the BMU while it is not during a DMA
4064 * transfer. Since it is possible that the Rx path is still active,
4065 * the Rx RAM buffer will be stopped first, so any possible incoming
4066 * data will not trigger a DMA. After the RAM buffer is stopped, the
4067 * BMU is polled until any DMA in progress is ended and only then it
4068 * will be reset.
4069 */
4070
4071 /* Disable the RAM Buffer receive queue. */
4072 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
4073 for (i = 0; i < MSK_TIMEOUT; i++) {
4074 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
4075 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
4076 break;
4077 DELAY(1);
4078 }
4079 if (i == MSK_TIMEOUT)
4080 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
4081 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4082 BMU_RST_SET | BMU_FIFO_RST);
4083 /* Reset the Rx prefetch unit. */
4084 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4085 PREF_UNIT_RST_SET);
4086 /* Reset the RAM Buffer receive queue. */
4087 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
4088 /* Reset Rx MAC FIFO. */
4089 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
4090
4091 /* Free Rx and Tx mbufs still in the queues. */
4092 for (i = 0; i < MSK_RX_RING_CNT; i++) {
4093 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
4094 if (rxd->rx_m != NULL) {
4095 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
4096 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4097 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
4098 rxd->rx_dmamap);
4099 m_freem(rxd->rx_m);
4100 rxd->rx_m = NULL;
4101 }
4102 }
4103 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
4104 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
4105 if (jrxd->rx_m != NULL) {
4106 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
4107 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4108 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
4109 jrxd->rx_dmamap);
4110 m_freem(jrxd->rx_m);
4111 jrxd->rx_m = NULL;
4112 }
4113 }
4114 for (i = 0; i < MSK_TX_RING_CNT; i++) {
4115 txd = &sc_if->msk_cdata.msk_txdesc[i];
4116 if (txd->tx_m != NULL) {
4117 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
4118 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4119 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
4120 txd->tx_dmamap);
4121 m_freem(txd->tx_m);
4122 txd->tx_m = NULL;
4123 }
4124 }
4125
4126 /*
4127 * Mark the interface down.
4128 */
4129 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4130 sc_if->msk_link = 0;
4131}
4132
4133static int
4134sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4135{
4136 int error, value;
4137
4138 if (!arg1)
4139 return (EINVAL);
4140 value = *(int *)arg1;
4141 error = sysctl_handle_int(oidp, &value, 0, req);
4142 if (error || !req->newptr)
4143 return (error);
4144 if (value < low || value > high)
4145 return (EINVAL);
4146 *(int *)arg1 = value;
4147
4148 return (0);
4149}
4150
4151static int
4152sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)
4153{
4154
4155 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN,
4156 MSK_PROC_MAX));
4157}
| 3835 }
3836 }
3837
3838 /*
3839 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3840 * arbiter as we don't use Sync Tx queue.
3841 */
3842 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3843 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
3844 /* Enable the RAM Interface Arbiter. */
3845 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3846
3847 /* Setup RAM buffer. */
3848 msk_set_rambuffer(sc_if);
3849
3850 /* Disable Tx sync Queue. */
3851 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3852
3853 /* Setup Tx Queue Bus Memory Interface. */
3854 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3855 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3856 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3857 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3858 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3859 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3860 /* Fix for Yukon-EC Ultra: set BMU FIFO level */
3861 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV);
3862 }
3863
3864 /* Setup Rx Queue Bus Memory Interface. */
3865 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3866 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3867 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3868 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3869 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3870 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
3871 /* MAC Rx RAM Read is controlled by hardware. */
3872 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
3873 }
3874
3875 msk_set_prefetch(sc, sc_if->msk_txq,
3876 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
3877 msk_init_tx_ring(sc_if);
3878
3879 /* Disable Rx checksum offload and RSS hash. */
3880 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
3881 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH);
3882 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) {
3883 msk_set_prefetch(sc, sc_if->msk_rxq,
3884 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
3885 MSK_JUMBO_RX_RING_CNT - 1);
3886 error = msk_init_jumbo_rx_ring(sc_if);
3887 } else {
3888 msk_set_prefetch(sc, sc_if->msk_rxq,
3889 sc_if->msk_rdata.msk_rx_ring_paddr,
3890 MSK_RX_RING_CNT - 1);
3891 error = msk_init_rx_ring(sc_if);
3892 }
3893 if (error != 0) {
3894 device_printf(sc_if->msk_if_dev,
3895 "initialization failed: no memory for Rx buffers\n");
3896 msk_stop(sc_if);
3897 return;
3898 }
3899
3900 /* Configure interrupt handling. */
3901 if (sc_if->msk_port == MSK_PORT_A) {
3902 sc->msk_intrmask |= Y2_IS_PORT_A;
3903 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
3904 } else {
3905 sc->msk_intrmask |= Y2_IS_PORT_B;
3906 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
3907 }
3908 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
3909 CSR_READ_4(sc, B0_HWE_IMSK);
3910 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3911 CSR_READ_4(sc, B0_IMSK);
3912
3913 sc_if->msk_link = 0;
3914 mii_mediachg(mii);
3915
3916 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3917 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3918
3919 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3920}
3921
3922static void
3923msk_set_rambuffer(struct msk_if_softc *sc_if)
3924{
3925 struct msk_softc *sc;
3926 int ltpp, utpp;
3927
3928 sc = sc_if->msk_softc;
3929
3930 /* Setup Rx Queue. */
3931 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
3932 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
3933 sc->msk_rxqstart[sc_if->msk_port] / 8);
3934 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
3935 sc->msk_rxqend[sc_if->msk_port] / 8);
3936 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
3937 sc->msk_rxqstart[sc_if->msk_port] / 8);
3938 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
3939 sc->msk_rxqstart[sc_if->msk_port] / 8);
3940
3941 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
3942 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
3943 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
3944 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
3945 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
3946 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
3947 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
3948 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
3949 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
3950
3951 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
3952 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
3953
3954 /* Setup Tx Queue. */
3955 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
3956 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
3957 sc->msk_txqstart[sc_if->msk_port] / 8);
3958 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
3959 sc->msk_txqend[sc_if->msk_port] / 8);
3960 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
3961 sc->msk_txqstart[sc_if->msk_port] / 8);
3962 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
3963 sc->msk_txqstart[sc_if->msk_port] / 8);
3964 /* Enable Store & Forward for Tx side. */
3965 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
3966 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
3967 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
3968}
3969
3970static void
3971msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
3972 uint32_t count)
3973{
3974
3975 /* Reset the prefetch unit. */
3976 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3977 PREF_UNIT_RST_SET);
3978 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3979 PREF_UNIT_RST_CLR);
3980 /* Set LE base address. */
3981 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
3982 MSK_ADDR_LO(addr));
3983 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
3984 MSK_ADDR_HI(addr));
3985 /* Set the list last index. */
3986 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
3987 count);
3988 /* Turn on prefetch unit. */
3989 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3990 PREF_UNIT_OP_ON);
3991 /* Dummy read to ensure write. */
3992 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
3993}
3994
3995static void
3996msk_stop(struct msk_if_softc *sc_if)
3997{
3998 struct msk_softc *sc;
3999 struct msk_txdesc *txd;
4000 struct msk_rxdesc *rxd;
4001 struct msk_rxdesc *jrxd;
4002 struct ifnet *ifp;
4003 uint32_t val;
4004 int i;
4005
4006 MSK_IF_LOCK_ASSERT(sc_if);
4007 sc = sc_if->msk_softc;
4008 ifp = sc_if->msk_ifp;
4009
4010 callout_stop(&sc_if->msk_tick_ch);
4011 sc_if->msk_watchdog_timer = 0;
4012
4013 /* Disable interrupts. */
4014 if (sc_if->msk_port == MSK_PORT_A) {
4015 sc->msk_intrmask &= ~Y2_IS_PORT_A;
4016 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
4017 } else {
4018 sc->msk_intrmask &= ~Y2_IS_PORT_B;
4019 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
4020 }
4021 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4022 CSR_READ_4(sc, B0_HWE_IMSK);
4023 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4024 CSR_READ_4(sc, B0_IMSK);
4025
4026 /* Disable Tx/Rx MAC. */
4027 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4028 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
4029 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
4030 /* Read again to ensure writing. */
4031 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4032
4033 /* Stop Tx BMU. */
4034 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4035 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4036 for (i = 0; i < MSK_TIMEOUT; i++) {
4037 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
4038 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4039 BMU_STOP);
4040 CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4041 } else
4042 break;
4043 DELAY(1);
4044 }
4045 if (i == MSK_TIMEOUT)
4046 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
4047 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
4048 RB_RST_SET | RB_DIS_OP_MD);
4049
4050 /* Disable all GMAC interrupt. */
4051 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
4052 /* Disable PHY interrupt. */
4053 if (sc->msk_marvell_phy)
4054 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
4055
4056 /* Disable the RAM Interface Arbiter. */
4057 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
4058
4059 /* Reset the PCI FIFO of the async Tx queue */
4060 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4061 BMU_RST_SET | BMU_FIFO_RST);
4062
4063 /* Reset the Tx prefetch units. */
4064 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4065 PREF_UNIT_RST_SET);
4066
4067 /* Reset the RAM Buffer async Tx queue. */
4068 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
4069
4070 /* Reset Tx MAC FIFO. */
4071 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
4072 /* Set Pause Off. */
4073 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
4074
4075 /*
4076 * The Rx Stop command will not work for Yukon-2 if the BMU does not
4077 * reach the end of packet and since we can't make sure that we have
4078 * incoming data, we must reset the BMU while it is not during a DMA
4079 * transfer. Since it is possible that the Rx path is still active,
4080 * the Rx RAM buffer will be stopped first, so any possible incoming
4081 * data will not trigger a DMA. After the RAM buffer is stopped, the
4082 * BMU is polled until any DMA in progress is ended and only then it
4083 * will be reset.
4084 */
4085
4086 /* Disable the RAM Buffer receive queue. */
4087 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
4088 for (i = 0; i < MSK_TIMEOUT; i++) {
4089 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
4090 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
4091 break;
4092 DELAY(1);
4093 }
4094 if (i == MSK_TIMEOUT)
4095 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
4096 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4097 BMU_RST_SET | BMU_FIFO_RST);
4098 /* Reset the Rx prefetch unit. */
4099 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4100 PREF_UNIT_RST_SET);
4101 /* Reset the RAM Buffer receive queue. */
4102 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
4103 /* Reset Rx MAC FIFO. */
4104 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
4105
4106 /* Free Rx and Tx mbufs still in the queues. */
4107 for (i = 0; i < MSK_RX_RING_CNT; i++) {
4108 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
4109 if (rxd->rx_m != NULL) {
4110 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
4111 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4112 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
4113 rxd->rx_dmamap);
4114 m_freem(rxd->rx_m);
4115 rxd->rx_m = NULL;
4116 }
4117 }
4118 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
4119 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
4120 if (jrxd->rx_m != NULL) {
4121 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
4122 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4123 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
4124 jrxd->rx_dmamap);
4125 m_freem(jrxd->rx_m);
4126 jrxd->rx_m = NULL;
4127 }
4128 }
4129 for (i = 0; i < MSK_TX_RING_CNT; i++) {
4130 txd = &sc_if->msk_cdata.msk_txdesc[i];
4131 if (txd->tx_m != NULL) {
4132 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
4133 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4134 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
4135 txd->tx_dmamap);
4136 m_freem(txd->tx_m);
4137 txd->tx_m = NULL;
4138 }
4139 }
4140
4141 /*
4142 * Mark the interface down.
4143 */
4144 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4145 sc_if->msk_link = 0;
4146}
4147
4148static int
4149sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4150{
4151 int error, value;
4152
4153 if (!arg1)
4154 return (EINVAL);
4155 value = *(int *)arg1;
4156 error = sysctl_handle_int(oidp, &value, 0, req);
4157 if (error || !req->newptr)
4158 return (error);
4159 if (value < low || value > high)
4160 return (EINVAL);
4161 *(int *)arg1 = value;
4162
4163 return (0);
4164}
4165
4166static int
4167sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)
4168{
4169
4170 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN,
4171 MSK_PROC_MAX));
4172}
|