1/******************************************************************************
2 *
3 * Name : sky2.c
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
8 *

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94
95/*
96 * Device driver for the Marvell Yukon II Ethernet controller.
97 * Due to lack of documentation, this driver is based on the code from
98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
99 */
100
101#include <sys/cdefs.h>
102__FBSDID("$FreeBSD: head/sys/dev/msk/if_msk.c 187208 2009-01-14 05:08:52Z yongari $");
103
104#include <sys/param.h>
105#include <sys/systm.h>
106#include <sys/bus.h>
107#include <sys/endian.h>
108#include <sys/mbuf.h>
109#include <sys/malloc.h>
110#include <sys/kernel.h>

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286static int msk_miibus_writereg(device_t, int, int, int);
287static void msk_miibus_statchg(device_t);
288static void msk_link_task(void *, int);
289
290static void msk_setmulti(struct msk_if_softc *);
291static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
292static void msk_setpromisc(struct msk_if_softc *);
293
294static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
295static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
296
297static device_method_t mskc_methods[] = {
298 /* Device interface */
299 DEVMETHOD(device_probe, mskc_probe),
300 DEVMETHOD(device_attach, mskc_attach),
301 DEVMETHOD(device_detach, mskc_detach),

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1430 } else {
1431 sc_if->msk_txq = Q_XA2;
1432 sc_if->msk_txsq = Q_XS2;
1433 sc_if->msk_rxq = Q_R2;
1434 }
1435
1436 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1437 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if);
1438
1439 /* Disable jumbo frame for Yukon FE. */
1440 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE)
1441 sc_if->msk_flags |= MSK_FLAG_NOJUMBO;
1442
1443 if ((error = msk_txrx_dma_alloc(sc_if) != 0))
1444 goto fail;
1445 msk_rx_dma_jalloc(sc_if);

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3539 * datasheet for Yukon II I wouldn't have encountered this. :-(
3540 */
3541 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL;
3542 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
3543
3544 /* Dummy read the Interrupt Source Register. */
3545 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3546
3547 /* Set MIB Clear Counter Mode. */
3548 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
3549 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
3550 /* Read all MIB Counters with Clear Mode set. */
3551 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
3552 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i);
3553 /* Clear MIB Clear Counter Mode. */
3554 gmac &= ~GM_PAR_MIB_CLR;
3555 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
3556
3557 /* Disable FCS. */
3558 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3559
3560 /* Setup Transmit Control Register. */
3561 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3562
3563 /* Setup Transmit Flow Control Register. */

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3833 CSR_READ_4(sc, B0_IMSK);
3834
3835 /* Disable Tx/Rx MAC. */
3836 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3837 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
3838 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
3839 /* Read again to ensure writing. */
3840 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3841
3842 /* Stop Tx BMU. */
3843 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
3844 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
3845 for (i = 0; i < MSK_TIMEOUT; i++) {
3846 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
3847 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
3848 BMU_STOP);

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3948
3949 /*
3950 * Mark the interface down.
3951 */
3952 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3953 sc_if->msk_link = 0;
3954}
3955
3956static int
3957sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3958{
3959 int error, value;
3960
3961 if (!arg1)
3962 return (EINVAL);
3963 value = *(int *)arg1;
3964 error = sysctl_handle_int(oidp, &value, 0, req);

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