27
28/*
29 * Stuff to describe the MUNIC32X and FALC54 chips.
30 */
31
32#define M32_CHAN 32 /* We have 32 channels */
33#define M32_TS 32 /* We have 32 timeslots */
34
35#define NG_MN_NODE_TYPE "mn"
36
37#include <sys/param.h>
38#include <sys/kernel.h>
39#include <sys/sysctl.h>
40#include <sys/bus.h>
41#include <sys/mbuf.h>
42#include <sys/systm.h>
43#include <sys/malloc.h>
44
45#include <dev/pci/pcireg.h>
46#include <dev/pci/pcivar.h>
47#include "pci_if.h"
48
49#include <machine/bus.h>
50#include <machine/resource.h>
51
52#include <sys/rman.h>
53
54#include <vm/vm.h>
55#include <vm/pmap.h>
56
57#include <netgraph/ng_message.h>
58#include <netgraph/netgraph.h>
59
60
61static int mn_maxlatency = 1000;
62SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
63 &mn_maxlatency, 0,
64 "The number of milliseconds a packet is allowed to spend in the output queue. "
65 "If the output queue is longer than this number of milliseconds when the packet "
66 "arrives for output, the packet will be dropped."
67);
68
69#ifndef NMN
70/* Most machines don't support more than 4 busmaster PCI slots, if even that many */
71#define NMN 4
72#endif
73
74/* From: PEB 20321 data sheet, p187, table 22 */
75struct m32xreg {
76 u_int32_t conf, cmd, stat, imask;
77 u_int32_t fill10, piqba, piql, fill1c;
78 u_int32_t mode1, mode2, ccba, txpoll;
79 u_int32_t tiqba, tiql, riqba, riql;
80 u_int32_t lconf, lccba, fill48, ltran;
81 u_int32_t ltiqba, ltiql, lriqba, lriql;
82 u_int32_t lreg0, lreg1, lreg2, lreg3;
83 u_int32_t lreg4, lreg5, lre6, lstat;
84 u_int32_t gpdir, gpdata, gpod, fill8c;
85 u_int32_t ssccon, sscbr, ssctb, sscrb;
86 u_int32_t ssccse, sscim, fillab, fillac;
87 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
88 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
89 u_int32_t iomtmo, iomrmo, filld8, filldc;
90 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
91 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
92};
93
94/* From: PEB 2254 data sheet, p80, table 10 */
95struct f54wreg {
96 u_int16_t xfifo;
97 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
98 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
99 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
100 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
101 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
102 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
103 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
104 u_int8_t lim2, fill39[7];
105 u_int8_t fill40[8];
106 u_int8_t fill48[8];
107 u_int8_t fill50[8];
108 u_int8_t fill58[8];
109 u_int8_t dec, fill61, test2, fill63[5];
110 u_int8_t fill68[8];
111 u_int8_t xs[16];
112};
113
114/* From: PEB 2254 data sheet, p117, table 10 */
115struct f54rreg {
116 u_int16_t rfifo;
117 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
118 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
119 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
120 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
121 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
122 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
123 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
124 u_int8_t lim2, fill39[7];
125 u_int8_t fill40[8];
126 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
127 u_int16_t fec, cvc, cec1, ebc;
128 u_int16_t cec2, cec3;
129 u_int8_t rsa4, rsa5, rsa6, rsa7;
130 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
131 u_int16_t rbc;
132 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
133 u_int8_t rs[16];
134};
135
136/* Transmit & receive descriptors */
137struct trxd {
138 u_int32_t flags;
139 vm_offset_t next;
140 vm_offset_t data;
141 u_int32_t status; /* only used for receive */
142 struct mbuf *m; /* software use only */
143 struct trxd *vnext; /* software use only */
144};
145
146/* Channel specification */
147struct cspec {
148 u_int32_t flags;
149 vm_offset_t rdesc;
150 vm_offset_t tdesc;
151 u_int32_t itbs;
152};
153
154struct m32_mem {
155 vm_offset_t csa;
156 u_int32_t ccb;
157 u_int32_t reserve1[2];
158 u_int32_t ts[M32_TS];
159 struct cspec cs[M32_CHAN];
160 vm_offset_t crxd[M32_CHAN];
161 vm_offset_t ctxd[M32_CHAN];
162};
163
164struct mn_softc;
165struct sockaddr;
166struct rtentry;
167
168static int mn_probe(device_t self);
169static int mn_attach(device_t self);
170static void mn_create_channel(struct mn_softc *sc, int chan);
171static int mn_reset(struct mn_softc *sc);
172static struct trxd * mn_alloc_desc(void);
173static void mn_free_desc(struct trxd *dp);
174static void mn_intr(void *xsc);
175static u_int32_t mn_parse_ts(const char *s, int *nbit);
176#ifdef notyet
177static void m32_dump(struct mn_softc *sc);
178static void f54_dump(struct mn_softc *sc);
179static void mn_fmt_ts(char *p, u_int32_t ts);
180#endif /* notyet */
181static void f54_init(struct mn_softc *sc);
182
183static ng_constructor_t ngmn_constructor;
184static ng_rcvmsg_t ngmn_rcvmsg;
185static ng_shutdown_t ngmn_shutdown;
186static ng_newhook_t ngmn_newhook;
187static ng_connect_t ngmn_connect;
188static ng_rcvdata_t ngmn_rcvdata;
189static ng_disconnect_t ngmn_disconnect;
190
191static struct ng_type mntypestruct = {
192 .version = NG_ABI_VERSION,
193 .name = NG_MN_NODE_TYPE,
194 .constructor = ngmn_constructor,
195 .rcvmsg = ngmn_rcvmsg,
196 .shutdown = ngmn_shutdown,
197 .newhook = ngmn_newhook,
198 .connect = ngmn_connect,
199 .rcvdata = ngmn_rcvdata,
200 .disconnect = ngmn_disconnect,
201};
202
203static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
204
205#define NIQB 64
206
207struct schan {
208 enum {DOWN, UP} state;
209 struct mn_softc *sc;
210 int chan;
211 u_int32_t ts;
212 char name[8];
213 struct trxd *r1, *rl;
214 struct trxd *x1, *xl;
215 hook_p hook;
216
217 time_t last_recv;
218 time_t last_rxerr;
219 time_t last_xmit;
220
221 u_long rx_error;
222
223 u_long short_error;
224 u_long crc_error;
225 u_long dribble_error;
226 u_long long_error;
227 u_long abort_error;
228 u_long overflow_error;
229
230 int last_error;
231 int prev_error;
232
233 u_long tx_pending;
234 u_long tx_limit;
235};
236
237enum framing {WHOKNOWS, E1, E1U, T1, T1U};
238
239struct mn_softc {
240 int unit;
241 device_t dev;
242 struct resource *irq;
243 void *intrhand;
244 enum framing framing;
245 int nhooks;
246 void *m0v, *m1v;
247 vm_offset_t m0p, m1p;
248 struct m32xreg *m32x;
249 struct f54wreg *f54w;
250 struct f54rreg *f54r;
251 struct m32_mem m32_mem;
252 u_int32_t tiqb[NIQB];
253 u_int32_t riqb[NIQB];
254 u_int32_t piqb[NIQB];
255 u_int32_t ltiqb[NIQB];
256 u_int32_t lriqb[NIQB];
257 char name[8];
258 u_int32_t falc_irq, falc_state, framer_state;
259 struct schan *ch[M32_CHAN];
260 char nodename[NG_NODESIZ];
261 node_p node;
262
263 u_long cnt_fec;
264 u_long cnt_cvc;
265 u_long cnt_cec1;
266 u_long cnt_ebc;
267 u_long cnt_cec2;
268 u_long cnt_cec3;
269 u_long cnt_rbc;
270};
271
272static int
273ngmn_constructor(node_p node)
274{
275
276 return (EINVAL);
277}
278
279static int
280ngmn_shutdown(node_p nodep)
281{
282
283 return (EINVAL);
284}
285
286static void
287ngmn_config(node_p node, char *set, char *ret)
288{
289 struct mn_softc *sc;
290 enum framing wframing;
291
292 sc = NG_NODE_PRIVATE(node);
293
294 if (set != NULL) {
295 if (!strncmp(set, "line ", 5)) {
296 wframing = sc->framing;
297 if (!strcmp(set, "line e1")) {
298 wframing = E1;
299 } else if (!strcmp(set, "line e1u")) {
300 wframing = E1U;
301 } else {
302 strcat(ret, "ENOGROK\n");
303 return;
304 }
305 if (wframing == sc->framing)
306 return;
307 if (sc->nhooks > 0) {
308 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks);
309 return;
310 }
311 sc->framing = wframing;
312#if 1
313 f54_init(sc);
314#else
315 mn_reset(sc);
316#endif
317 } else {
318 printf("%s CONFIG SET [%s]\n", sc->nodename, set);
319 strcat(ret, "ENOGROK\n");
320 return;
321 }
322 }
323
324}
325
326static int
327ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook)
328{
329 struct mn_softc *sc;
330 struct ng_mesg *resp = NULL;
331 struct schan *sch;
332 char *s, *r;
333 int pos, i;
334 struct ng_mesg *msg;
335
336 NGI_GET_MSG(item, msg);
337 sc = NG_NODE_PRIVATE(node);
338
339 if (msg->header.typecookie != NGM_GENERIC_COOKIE) {
340 NG_FREE_ITEM(item);
341 NG_FREE_MSG(msg);
342 return (EINVAL);
343 }
344
345 if (msg->header.cmd != NGM_TEXT_CONFIG &&
346 msg->header.cmd != NGM_TEXT_STATUS) {
347 NG_FREE_ITEM(item);
348 NG_FREE_MSG(msg);
349 return (EINVAL);
350 }
351
352 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
353 M_NOWAIT);
354 if (resp == NULL) {
355 NG_FREE_ITEM(item);
356 NG_FREE_MSG(msg);
357 return (ENOMEM);
358 }
359
360 if (msg->header.arglen)
361 s = (char *)msg->data;
362 else
363 s = NULL;
364 r = (char *)resp->data;
365 *r = '\0';
366
367 if (msg->header.cmd == NGM_TEXT_CONFIG) {
368 ngmn_config(node, s, r);
369 resp->header.arglen = strlen(r) + 1;
370 NG_RESPOND_MSG(i, node, item, resp);
371 NG_FREE_MSG(msg);
372 return (0);
373 }
374 pos = 0;
375 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20"
376 "\40LOS\37AIS\36LFA\35RRA"
377 "\34AUXP\33NMF\32LMFA\31frs0.0"
378 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
379 "\24TS16LFA\23frs1.2\22XLS\21XLO"
380 "\20RS1\17rsw.6\16RRA\15RY0"
381 "\14RY1\13RY2\12RY3\11RY4"
382 "\10SI1\7SI2\6rsp.5\5rsp.4"
383 "\4rsp.3\3RSIF\2RS13\1RS15");
384 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec);
385 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc);
386
387 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20"
388 "\40LOS\37AIS\36LFA\35RRA"
389 "\34AUXP\33NMF\32LMFA\31frs0.0"
390 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
391 "\24TS16LFA\23frs1.2\22XLS\21XLO"
392 "\20RS1\17rsw.6\16RRA\15RY0"
393 "\14RY1\13RY2\12RY3\11RY4"
394 "\10SI1\7SI2\6rsp.5\5rsp.4"
395 "\4rsp.3\3RSIF\2RS13\1RS15");
396 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20"
397 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
398 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
399 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
400 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
401 for (i = 0; i < M32_CHAN; i++) {
402 if (!sc->ch[i])
403 continue;
404 sch = sc->ch[i];
405
406 pos += sprintf(r + pos, " Chan %d <%s> ",
407 i, NG_HOOK_NAME(sch->hook));
408
409 pos += sprintf(r + pos, " Last Rx: ");
410 if (sch->last_recv)
411 pos += sprintf(r + pos, "%lu s",
412 (unsigned long)(time_second - sch->last_recv));
413 else
414 pos += sprintf(r + pos, "never");
415
416 pos += sprintf(r + pos, ", last RxErr: ");
417 if (sch->last_rxerr)
418 pos += sprintf(r + pos, "%lu s",
419 (unsigned long)(time_second - sch->last_rxerr));
420 else
421 pos += sprintf(r + pos, "never");
422
423 pos += sprintf(r + pos, ", last Tx: ");
424 if (sch->last_xmit)
425 pos += sprintf(r + pos, "%lu s\n",
426 (unsigned long)(time_second - sch->last_xmit));
427 else
428 pos += sprintf(r + pos, "never\n");
429
430 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error);
431 pos += sprintf(r + pos, " Short: %lu", sch->short_error);
432 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error);
433 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error);
434 pos += sprintf(r + pos, " Long: %lu", sch->long_error);
435 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error);
436 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error);
437
438 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n",
439 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
440 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
441 pos += sprintf(r + pos, " Xmit bytes pending %ld\n",
442 sch->tx_pending);
443 }
444 resp->header.arglen = pos + 1;
445
446 /* Take care of synchronous response, if any */
447 NG_RESPOND_MSG(i, node, item, resp);
448 NG_FREE_MSG(msg);
449 return (0);
450}
451
452static int
453ngmn_newhook(node_p node, hook_p hook, const char *name)
454{
455 u_int32_t ts, chan;
456 struct mn_softc *sc;
457 int nbit;
458
459 sc = NG_NODE_PRIVATE(node);
460
461 if (name[0] != 't' || name[1] != 's')
462 return (EINVAL);
463
464 ts = mn_parse_ts(name + 2, &nbit);
465 printf("%d bits %x\n", nbit, ts);
466 if (sc->framing == E1 && (ts & 1))
467 return (EINVAL);
468 if (sc->framing == E1U && nbit != 32)
469 return (EINVAL);
470 if (ts == 0)
471 return (EINVAL);
472 if (sc->framing == E1)
473 chan = ffs(ts) - 1;
474 else
475 chan = 1;
476 if (!sc->ch[chan])
477 mn_create_channel(sc, chan);
478 else if (sc->ch[chan]->state == UP)
479 return (EBUSY);
480 sc->ch[chan]->ts = ts;
481 sc->ch[chan]->hook = hook;
482 sc->ch[chan]->tx_limit = nbit * 8;
483 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]);
484 sc->nhooks++;
485 return(0);
486}
487
488
489static struct trxd *mn_desc_free;
490
491static struct trxd *
492mn_alloc_desc(void)
493{
494 struct trxd *dp;
495
496 dp = mn_desc_free;
497 if (dp)
498 mn_desc_free = dp->vnext;
499 else
500 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT);
501 return (dp);
502}
503
504static void
505mn_free_desc(struct trxd *dp)
506{
507 dp->vnext = mn_desc_free;
508 mn_desc_free = dp;
509}
510
511static u_int32_t
512mn_parse_ts(const char *s, int *nbit)
513{
514 unsigned r;
515 int i, j;
516 char *p;
517
518 r = 0;
519 j = -1;
520 *nbit = 0;
521 while(*s) {
522 i = strtol(s, &p, 0);
523 if (i < 0 || i > 31)
524 return (0);
525 while (j != -1 && j < i) {
526 r |= 1 << j++;
527 (*nbit)++;
528 }
529 j = -1;
530 r |= 1 << i;
531 (*nbit)++;
532 if (*p == ',') {
533 s = p + 1;
534 continue;
535 } else if (*p == '-') {
536 j = i + 1;
537 s = p + 1;
538 continue;
539 } else if (!*p) {
540 break;
541 } else {
542 return (0);
543 }
544 }
545 return (r);
546}
547
548#ifdef notyet
549static void
550mn_fmt_ts(char *p, u_int32_t ts)
551{
552 char *s;
553 int j;
554
555 s = "";
556 ts &= 0xffffffff;
557 for (j = 0; j < 32; j++) {
558 if (!(ts & (1 << j)))
559 continue;
560 sprintf(p, "%s%d", s, j);
561 p += strlen(p);
562 s = ",";
563 if (!(ts & (1 << (j+1))))
564 continue;
565 for (; j < 32; j++)
566 if (!(ts & (1 << (j+1))))
567 break;
568 sprintf(p, "-%d", j);
569 p += strlen(p);
570 s = ",";
571 }
572}
573#endif /* notyet */
574
575/*
576 * OUTPUT
577 */
578
579static int
580ngmn_rcvdata(hook_p hook, item_p item)
581{
582 struct mbuf *m2;
583 struct trxd *dp, *dp2;
584 struct schan *sch;
585 struct mn_softc *sc;
586 int chan, pitch, len;
587 struct mbuf *m;
588
589 sch = NG_HOOK_PRIVATE(hook);
590 sc = sch->sc;
591 chan = sch->chan;
592
593 if (sch->state != UP) {
594 NG_FREE_ITEM(item);
595 return (0);
596 }
597 NGI_GET_M(item, m);
598 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
599 NG_FREE_M(m);
600 NG_FREE_ITEM(item);
601 return (0);
602 }
603 NG_FREE_ITEM(item);
604 pitch = 0;
605 m2 = m;
606 dp2 = sc->ch[chan]->xl;
607 len = m->m_pkthdr.len;
608 while (len) {
609 dp = mn_alloc_desc();
610 if (!dp) {
611 pitch++;
612 m_freem(m);
613 sc->ch[chan]->xl = dp2;
614 dp = dp2->vnext;
615 while (dp) {
616 dp2 = dp->vnext;
617 mn_free_desc(dp);
618 dp = dp2;
619 }
620 sc->ch[chan]->xl->vnext = 0;
621 break;
622 }
623 dp->data = vtophys(m2->m_data);
624 dp->flags = m2->m_len << 16;
625 dp->flags += 1;
626 len -= m2->m_len;
627 dp->next = vtophys(dp);
628 dp->vnext = 0;
629 sc->ch[chan]->xl->next = vtophys(dp);
630 sc->ch[chan]->xl->vnext = dp;
631 sc->ch[chan]->xl = dp;
632 if (!len) {
633 dp->m = m;
634 dp->flags |= 0xc0000000;
635 dp2->flags &= ~0x40000000;
636 } else {
637 dp->m = 0;
638 m2 = m2->m_next;
639 }
640 }
641 if (pitch)
642 printf("%s%d: Short on mem, pitched %d packets\n",
643 sc->name, chan, pitch);
644 else {
645#if 0
646 printf("%d = %d + %d (%p)\n",
647 sch->tx_pending + m->m_pkthdr.len,
648 sch->tx_pending , m->m_pkthdr.len, m);
649#endif
650 sch->tx_pending += m->m_pkthdr.len;
651 sc->m32x->txpoll &= ~(1 << chan);
652 }
653 return (0);
654}
655
656/*
657 * OPEN
658 */
659static int
660ngmn_connect(hook_p hook)
661{
662 int i, nts, chan;
663 struct trxd *dp, *dp2;
664 struct mbuf *m;
665 struct mn_softc *sc;
666 struct schan *sch;
667 u_int32_t u;
668
669 sch = NG_HOOK_PRIVATE(hook);
670 chan = sch->chan;
671 sc = sch->sc;
672
673 if (sch->state == UP)
674 return (0);
675 sch->state = UP;
676
677 /* Count and configure the timeslots for this channel */
678 for (nts = i = 0; i < 32; i++)
679 if (sch->ts & (1 << i)) {
680 sc->m32_mem.ts[i] = 0x00ff00ff |
681 (chan << 24) | (chan << 8);
682 nts++;
683 }
684
685 /* Init the receiver & xmitter to HDLC */
686 sc->m32_mem.cs[chan].flags = 0x80e90006;
687 /* Allocate two buffers per timeslot */
688 if (nts == 32)
689 sc->m32_mem.cs[chan].itbs = 63;
690 else
691 sc->m32_mem.cs[chan].itbs = nts * 2;
692
693 /* Setup a transmit chain with one descriptor */
694 /* XXX: we actually send a 1 byte packet */
695 dp = mn_alloc_desc();
| 27
28/*
29 * Stuff to describe the MUNIC32X and FALC54 chips.
30 */
31
32#define M32_CHAN 32 /* We have 32 channels */
33#define M32_TS 32 /* We have 32 timeslots */
34
35#define NG_MN_NODE_TYPE "mn"
36
37#include <sys/param.h>
38#include <sys/kernel.h>
39#include <sys/sysctl.h>
40#include <sys/bus.h>
41#include <sys/mbuf.h>
42#include <sys/systm.h>
43#include <sys/malloc.h>
44
45#include <dev/pci/pcireg.h>
46#include <dev/pci/pcivar.h>
47#include "pci_if.h"
48
49#include <machine/bus.h>
50#include <machine/resource.h>
51
52#include <sys/rman.h>
53
54#include <vm/vm.h>
55#include <vm/pmap.h>
56
57#include <netgraph/ng_message.h>
58#include <netgraph/netgraph.h>
59
60
61static int mn_maxlatency = 1000;
62SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
63 &mn_maxlatency, 0,
64 "The number of milliseconds a packet is allowed to spend in the output queue. "
65 "If the output queue is longer than this number of milliseconds when the packet "
66 "arrives for output, the packet will be dropped."
67);
68
69#ifndef NMN
70/* Most machines don't support more than 4 busmaster PCI slots, if even that many */
71#define NMN 4
72#endif
73
74/* From: PEB 20321 data sheet, p187, table 22 */
75struct m32xreg {
76 u_int32_t conf, cmd, stat, imask;
77 u_int32_t fill10, piqba, piql, fill1c;
78 u_int32_t mode1, mode2, ccba, txpoll;
79 u_int32_t tiqba, tiql, riqba, riql;
80 u_int32_t lconf, lccba, fill48, ltran;
81 u_int32_t ltiqba, ltiql, lriqba, lriql;
82 u_int32_t lreg0, lreg1, lreg2, lreg3;
83 u_int32_t lreg4, lreg5, lre6, lstat;
84 u_int32_t gpdir, gpdata, gpod, fill8c;
85 u_int32_t ssccon, sscbr, ssctb, sscrb;
86 u_int32_t ssccse, sscim, fillab, fillac;
87 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
88 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
89 u_int32_t iomtmo, iomrmo, filld8, filldc;
90 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
91 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
92};
93
94/* From: PEB 2254 data sheet, p80, table 10 */
95struct f54wreg {
96 u_int16_t xfifo;
97 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
98 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
99 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
100 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
101 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
102 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
103 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
104 u_int8_t lim2, fill39[7];
105 u_int8_t fill40[8];
106 u_int8_t fill48[8];
107 u_int8_t fill50[8];
108 u_int8_t fill58[8];
109 u_int8_t dec, fill61, test2, fill63[5];
110 u_int8_t fill68[8];
111 u_int8_t xs[16];
112};
113
114/* From: PEB 2254 data sheet, p117, table 10 */
115struct f54rreg {
116 u_int16_t rfifo;
117 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
118 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
119 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
120 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
121 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
122 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
123 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
124 u_int8_t lim2, fill39[7];
125 u_int8_t fill40[8];
126 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
127 u_int16_t fec, cvc, cec1, ebc;
128 u_int16_t cec2, cec3;
129 u_int8_t rsa4, rsa5, rsa6, rsa7;
130 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
131 u_int16_t rbc;
132 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
133 u_int8_t rs[16];
134};
135
136/* Transmit & receive descriptors */
137struct trxd {
138 u_int32_t flags;
139 vm_offset_t next;
140 vm_offset_t data;
141 u_int32_t status; /* only used for receive */
142 struct mbuf *m; /* software use only */
143 struct trxd *vnext; /* software use only */
144};
145
146/* Channel specification */
147struct cspec {
148 u_int32_t flags;
149 vm_offset_t rdesc;
150 vm_offset_t tdesc;
151 u_int32_t itbs;
152};
153
154struct m32_mem {
155 vm_offset_t csa;
156 u_int32_t ccb;
157 u_int32_t reserve1[2];
158 u_int32_t ts[M32_TS];
159 struct cspec cs[M32_CHAN];
160 vm_offset_t crxd[M32_CHAN];
161 vm_offset_t ctxd[M32_CHAN];
162};
163
164struct mn_softc;
165struct sockaddr;
166struct rtentry;
167
168static int mn_probe(device_t self);
169static int mn_attach(device_t self);
170static void mn_create_channel(struct mn_softc *sc, int chan);
171static int mn_reset(struct mn_softc *sc);
172static struct trxd * mn_alloc_desc(void);
173static void mn_free_desc(struct trxd *dp);
174static void mn_intr(void *xsc);
175static u_int32_t mn_parse_ts(const char *s, int *nbit);
176#ifdef notyet
177static void m32_dump(struct mn_softc *sc);
178static void f54_dump(struct mn_softc *sc);
179static void mn_fmt_ts(char *p, u_int32_t ts);
180#endif /* notyet */
181static void f54_init(struct mn_softc *sc);
182
183static ng_constructor_t ngmn_constructor;
184static ng_rcvmsg_t ngmn_rcvmsg;
185static ng_shutdown_t ngmn_shutdown;
186static ng_newhook_t ngmn_newhook;
187static ng_connect_t ngmn_connect;
188static ng_rcvdata_t ngmn_rcvdata;
189static ng_disconnect_t ngmn_disconnect;
190
191static struct ng_type mntypestruct = {
192 .version = NG_ABI_VERSION,
193 .name = NG_MN_NODE_TYPE,
194 .constructor = ngmn_constructor,
195 .rcvmsg = ngmn_rcvmsg,
196 .shutdown = ngmn_shutdown,
197 .newhook = ngmn_newhook,
198 .connect = ngmn_connect,
199 .rcvdata = ngmn_rcvdata,
200 .disconnect = ngmn_disconnect,
201};
202
203static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
204
205#define NIQB 64
206
207struct schan {
208 enum {DOWN, UP} state;
209 struct mn_softc *sc;
210 int chan;
211 u_int32_t ts;
212 char name[8];
213 struct trxd *r1, *rl;
214 struct trxd *x1, *xl;
215 hook_p hook;
216
217 time_t last_recv;
218 time_t last_rxerr;
219 time_t last_xmit;
220
221 u_long rx_error;
222
223 u_long short_error;
224 u_long crc_error;
225 u_long dribble_error;
226 u_long long_error;
227 u_long abort_error;
228 u_long overflow_error;
229
230 int last_error;
231 int prev_error;
232
233 u_long tx_pending;
234 u_long tx_limit;
235};
236
237enum framing {WHOKNOWS, E1, E1U, T1, T1U};
238
239struct mn_softc {
240 int unit;
241 device_t dev;
242 struct resource *irq;
243 void *intrhand;
244 enum framing framing;
245 int nhooks;
246 void *m0v, *m1v;
247 vm_offset_t m0p, m1p;
248 struct m32xreg *m32x;
249 struct f54wreg *f54w;
250 struct f54rreg *f54r;
251 struct m32_mem m32_mem;
252 u_int32_t tiqb[NIQB];
253 u_int32_t riqb[NIQB];
254 u_int32_t piqb[NIQB];
255 u_int32_t ltiqb[NIQB];
256 u_int32_t lriqb[NIQB];
257 char name[8];
258 u_int32_t falc_irq, falc_state, framer_state;
259 struct schan *ch[M32_CHAN];
260 char nodename[NG_NODESIZ];
261 node_p node;
262
263 u_long cnt_fec;
264 u_long cnt_cvc;
265 u_long cnt_cec1;
266 u_long cnt_ebc;
267 u_long cnt_cec2;
268 u_long cnt_cec3;
269 u_long cnt_rbc;
270};
271
272static int
273ngmn_constructor(node_p node)
274{
275
276 return (EINVAL);
277}
278
279static int
280ngmn_shutdown(node_p nodep)
281{
282
283 return (EINVAL);
284}
285
286static void
287ngmn_config(node_p node, char *set, char *ret)
288{
289 struct mn_softc *sc;
290 enum framing wframing;
291
292 sc = NG_NODE_PRIVATE(node);
293
294 if (set != NULL) {
295 if (!strncmp(set, "line ", 5)) {
296 wframing = sc->framing;
297 if (!strcmp(set, "line e1")) {
298 wframing = E1;
299 } else if (!strcmp(set, "line e1u")) {
300 wframing = E1U;
301 } else {
302 strcat(ret, "ENOGROK\n");
303 return;
304 }
305 if (wframing == sc->framing)
306 return;
307 if (sc->nhooks > 0) {
308 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks);
309 return;
310 }
311 sc->framing = wframing;
312#if 1
313 f54_init(sc);
314#else
315 mn_reset(sc);
316#endif
317 } else {
318 printf("%s CONFIG SET [%s]\n", sc->nodename, set);
319 strcat(ret, "ENOGROK\n");
320 return;
321 }
322 }
323
324}
325
326static int
327ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook)
328{
329 struct mn_softc *sc;
330 struct ng_mesg *resp = NULL;
331 struct schan *sch;
332 char *s, *r;
333 int pos, i;
334 struct ng_mesg *msg;
335
336 NGI_GET_MSG(item, msg);
337 sc = NG_NODE_PRIVATE(node);
338
339 if (msg->header.typecookie != NGM_GENERIC_COOKIE) {
340 NG_FREE_ITEM(item);
341 NG_FREE_MSG(msg);
342 return (EINVAL);
343 }
344
345 if (msg->header.cmd != NGM_TEXT_CONFIG &&
346 msg->header.cmd != NGM_TEXT_STATUS) {
347 NG_FREE_ITEM(item);
348 NG_FREE_MSG(msg);
349 return (EINVAL);
350 }
351
352 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
353 M_NOWAIT);
354 if (resp == NULL) {
355 NG_FREE_ITEM(item);
356 NG_FREE_MSG(msg);
357 return (ENOMEM);
358 }
359
360 if (msg->header.arglen)
361 s = (char *)msg->data;
362 else
363 s = NULL;
364 r = (char *)resp->data;
365 *r = '\0';
366
367 if (msg->header.cmd == NGM_TEXT_CONFIG) {
368 ngmn_config(node, s, r);
369 resp->header.arglen = strlen(r) + 1;
370 NG_RESPOND_MSG(i, node, item, resp);
371 NG_FREE_MSG(msg);
372 return (0);
373 }
374 pos = 0;
375 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20"
376 "\40LOS\37AIS\36LFA\35RRA"
377 "\34AUXP\33NMF\32LMFA\31frs0.0"
378 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
379 "\24TS16LFA\23frs1.2\22XLS\21XLO"
380 "\20RS1\17rsw.6\16RRA\15RY0"
381 "\14RY1\13RY2\12RY3\11RY4"
382 "\10SI1\7SI2\6rsp.5\5rsp.4"
383 "\4rsp.3\3RSIF\2RS13\1RS15");
384 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec);
385 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc);
386
387 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20"
388 "\40LOS\37AIS\36LFA\35RRA"
389 "\34AUXP\33NMF\32LMFA\31frs0.0"
390 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
391 "\24TS16LFA\23frs1.2\22XLS\21XLO"
392 "\20RS1\17rsw.6\16RRA\15RY0"
393 "\14RY1\13RY2\12RY3\11RY4"
394 "\10SI1\7SI2\6rsp.5\5rsp.4"
395 "\4rsp.3\3RSIF\2RS13\1RS15");
396 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20"
397 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
398 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
399 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
400 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
401 for (i = 0; i < M32_CHAN; i++) {
402 if (!sc->ch[i])
403 continue;
404 sch = sc->ch[i];
405
406 pos += sprintf(r + pos, " Chan %d <%s> ",
407 i, NG_HOOK_NAME(sch->hook));
408
409 pos += sprintf(r + pos, " Last Rx: ");
410 if (sch->last_recv)
411 pos += sprintf(r + pos, "%lu s",
412 (unsigned long)(time_second - sch->last_recv));
413 else
414 pos += sprintf(r + pos, "never");
415
416 pos += sprintf(r + pos, ", last RxErr: ");
417 if (sch->last_rxerr)
418 pos += sprintf(r + pos, "%lu s",
419 (unsigned long)(time_second - sch->last_rxerr));
420 else
421 pos += sprintf(r + pos, "never");
422
423 pos += sprintf(r + pos, ", last Tx: ");
424 if (sch->last_xmit)
425 pos += sprintf(r + pos, "%lu s\n",
426 (unsigned long)(time_second - sch->last_xmit));
427 else
428 pos += sprintf(r + pos, "never\n");
429
430 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error);
431 pos += sprintf(r + pos, " Short: %lu", sch->short_error);
432 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error);
433 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error);
434 pos += sprintf(r + pos, " Long: %lu", sch->long_error);
435 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error);
436 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error);
437
438 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n",
439 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
440 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
441 pos += sprintf(r + pos, " Xmit bytes pending %ld\n",
442 sch->tx_pending);
443 }
444 resp->header.arglen = pos + 1;
445
446 /* Take care of synchronous response, if any */
447 NG_RESPOND_MSG(i, node, item, resp);
448 NG_FREE_MSG(msg);
449 return (0);
450}
451
452static int
453ngmn_newhook(node_p node, hook_p hook, const char *name)
454{
455 u_int32_t ts, chan;
456 struct mn_softc *sc;
457 int nbit;
458
459 sc = NG_NODE_PRIVATE(node);
460
461 if (name[0] != 't' || name[1] != 's')
462 return (EINVAL);
463
464 ts = mn_parse_ts(name + 2, &nbit);
465 printf("%d bits %x\n", nbit, ts);
466 if (sc->framing == E1 && (ts & 1))
467 return (EINVAL);
468 if (sc->framing == E1U && nbit != 32)
469 return (EINVAL);
470 if (ts == 0)
471 return (EINVAL);
472 if (sc->framing == E1)
473 chan = ffs(ts) - 1;
474 else
475 chan = 1;
476 if (!sc->ch[chan])
477 mn_create_channel(sc, chan);
478 else if (sc->ch[chan]->state == UP)
479 return (EBUSY);
480 sc->ch[chan]->ts = ts;
481 sc->ch[chan]->hook = hook;
482 sc->ch[chan]->tx_limit = nbit * 8;
483 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]);
484 sc->nhooks++;
485 return(0);
486}
487
488
489static struct trxd *mn_desc_free;
490
491static struct trxd *
492mn_alloc_desc(void)
493{
494 struct trxd *dp;
495
496 dp = mn_desc_free;
497 if (dp)
498 mn_desc_free = dp->vnext;
499 else
500 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT);
501 return (dp);
502}
503
504static void
505mn_free_desc(struct trxd *dp)
506{
507 dp->vnext = mn_desc_free;
508 mn_desc_free = dp;
509}
510
511static u_int32_t
512mn_parse_ts(const char *s, int *nbit)
513{
514 unsigned r;
515 int i, j;
516 char *p;
517
518 r = 0;
519 j = -1;
520 *nbit = 0;
521 while(*s) {
522 i = strtol(s, &p, 0);
523 if (i < 0 || i > 31)
524 return (0);
525 while (j != -1 && j < i) {
526 r |= 1 << j++;
527 (*nbit)++;
528 }
529 j = -1;
530 r |= 1 << i;
531 (*nbit)++;
532 if (*p == ',') {
533 s = p + 1;
534 continue;
535 } else if (*p == '-') {
536 j = i + 1;
537 s = p + 1;
538 continue;
539 } else if (!*p) {
540 break;
541 } else {
542 return (0);
543 }
544 }
545 return (r);
546}
547
548#ifdef notyet
549static void
550mn_fmt_ts(char *p, u_int32_t ts)
551{
552 char *s;
553 int j;
554
555 s = "";
556 ts &= 0xffffffff;
557 for (j = 0; j < 32; j++) {
558 if (!(ts & (1 << j)))
559 continue;
560 sprintf(p, "%s%d", s, j);
561 p += strlen(p);
562 s = ",";
563 if (!(ts & (1 << (j+1))))
564 continue;
565 for (; j < 32; j++)
566 if (!(ts & (1 << (j+1))))
567 break;
568 sprintf(p, "-%d", j);
569 p += strlen(p);
570 s = ",";
571 }
572}
573#endif /* notyet */
574
575/*
576 * OUTPUT
577 */
578
579static int
580ngmn_rcvdata(hook_p hook, item_p item)
581{
582 struct mbuf *m2;
583 struct trxd *dp, *dp2;
584 struct schan *sch;
585 struct mn_softc *sc;
586 int chan, pitch, len;
587 struct mbuf *m;
588
589 sch = NG_HOOK_PRIVATE(hook);
590 sc = sch->sc;
591 chan = sch->chan;
592
593 if (sch->state != UP) {
594 NG_FREE_ITEM(item);
595 return (0);
596 }
597 NGI_GET_M(item, m);
598 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
599 NG_FREE_M(m);
600 NG_FREE_ITEM(item);
601 return (0);
602 }
603 NG_FREE_ITEM(item);
604 pitch = 0;
605 m2 = m;
606 dp2 = sc->ch[chan]->xl;
607 len = m->m_pkthdr.len;
608 while (len) {
609 dp = mn_alloc_desc();
610 if (!dp) {
611 pitch++;
612 m_freem(m);
613 sc->ch[chan]->xl = dp2;
614 dp = dp2->vnext;
615 while (dp) {
616 dp2 = dp->vnext;
617 mn_free_desc(dp);
618 dp = dp2;
619 }
620 sc->ch[chan]->xl->vnext = 0;
621 break;
622 }
623 dp->data = vtophys(m2->m_data);
624 dp->flags = m2->m_len << 16;
625 dp->flags += 1;
626 len -= m2->m_len;
627 dp->next = vtophys(dp);
628 dp->vnext = 0;
629 sc->ch[chan]->xl->next = vtophys(dp);
630 sc->ch[chan]->xl->vnext = dp;
631 sc->ch[chan]->xl = dp;
632 if (!len) {
633 dp->m = m;
634 dp->flags |= 0xc0000000;
635 dp2->flags &= ~0x40000000;
636 } else {
637 dp->m = 0;
638 m2 = m2->m_next;
639 }
640 }
641 if (pitch)
642 printf("%s%d: Short on mem, pitched %d packets\n",
643 sc->name, chan, pitch);
644 else {
645#if 0
646 printf("%d = %d + %d (%p)\n",
647 sch->tx_pending + m->m_pkthdr.len,
648 sch->tx_pending , m->m_pkthdr.len, m);
649#endif
650 sch->tx_pending += m->m_pkthdr.len;
651 sc->m32x->txpoll &= ~(1 << chan);
652 }
653 return (0);
654}
655
656/*
657 * OPEN
658 */
659static int
660ngmn_connect(hook_p hook)
661{
662 int i, nts, chan;
663 struct trxd *dp, *dp2;
664 struct mbuf *m;
665 struct mn_softc *sc;
666 struct schan *sch;
667 u_int32_t u;
668
669 sch = NG_HOOK_PRIVATE(hook);
670 chan = sch->chan;
671 sc = sch->sc;
672
673 if (sch->state == UP)
674 return (0);
675 sch->state = UP;
676
677 /* Count and configure the timeslots for this channel */
678 for (nts = i = 0; i < 32; i++)
679 if (sch->ts & (1 << i)) {
680 sc->m32_mem.ts[i] = 0x00ff00ff |
681 (chan << 24) | (chan << 8);
682 nts++;
683 }
684
685 /* Init the receiver & xmitter to HDLC */
686 sc->m32_mem.cs[chan].flags = 0x80e90006;
687 /* Allocate two buffers per timeslot */
688 if (nts == 32)
689 sc->m32_mem.cs[chan].itbs = 63;
690 else
691 sc->m32_mem.cs[chan].itbs = nts * 2;
692
693 /* Setup a transmit chain with one descriptor */
694 /* XXX: we actually send a 1 byte packet */
695 dp = mn_alloc_desc();
|
748 dp->m = m;
749 dp->data = vtophys(m->m_data);
750 dp->flags = 0x00000000;
751 dp->flags += 1600 << 16;
752 dp->next = vtophys(dp2);
753 dp->vnext = dp2;
754 }
755 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
756 sc->ch[chan]->r1 = dp;
757
758 /* Initialize this channel */
759 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
760 sc->m32x->cmd = 0x1;
761 DELAY(1000);
762 u = sc->m32x->stat;
763 if (!(u & 1))
764 printf("%s: init chan %d stat %08x\n", sc->name, chan, u);
765 sc->m32x->stat = 1;
766 /* probably not at splnet, force outward queueing */
767 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
768
769 return (0);
770}
771
772/*
773 * CLOSE
774 */
775static int
776ngmn_disconnect(hook_p hook)
777{
778 int chan, i;
779 struct mn_softc *sc;
780 struct schan *sch;
781 struct trxd *dp, *dp2;
782 u_int32_t u;
783
784 sch = NG_HOOK_PRIVATE(hook);
785 chan = sch->chan;
786 sc = sch->sc;
787
788 if (sch->state == DOWN)
789 return (0);
790 sch->state = DOWN;
791
792 /* Set receiver & transmitter off */
793 sc->m32_mem.cs[chan].flags = 0x80920006;
794 sc->m32_mem.cs[chan].itbs = 0;
795
796 /* free the timeslots */
797 for (i = 0; i < 32; i++)
798 if (sc->ch[chan]->ts & (1 << i))
799 sc->m32_mem.ts[i] = 0x20002000;
800
801 /* Initialize this channel */
802 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
803 sc->m32x->cmd = 0x1;
804 DELAY(30);
805 u = sc->m32x->stat;
806 if (!(u & 1))
807 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
808 sc->m32x->stat = 1;
809
810 /* Free all receive descriptors and mbufs */
811 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
812 if (dp->m)
813 m_freem(dp->m);
814 sc->ch[chan]->r1 = dp2 = dp->vnext;
815 mn_free_desc(dp);
816 }
817
818 /* Free all transmit descriptors and mbufs */
819 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
820 if (dp->m) {
821 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
822 m_freem(dp->m);
823 }
824 sc->ch[chan]->x1 = dp2 = dp->vnext;
825 mn_free_desc(dp);
826 }
827 sc->nhooks--;
828 return(0);
829}
830
831/*
832 * Create a new channel.
833 */
834static void
835mn_create_channel(struct mn_softc *sc, int chan)
836{
837 struct schan *sch;
838
839 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan],
840 M_MN, M_WAITOK | M_ZERO);
841 sch->sc = sc;
842 sch->state = DOWN;
843 sch->chan = chan;
844 sprintf(sch->name, "%s%d", sc->name, chan);
845 return;
846}
847
848#ifdef notyet
849/*
850 * Dump Munich32x state
851 */
852static void
853m32_dump(struct mn_softc *sc)
854{
855 u_int32_t *tp4;
856 int i, j;
857
858 printf("mn%d: MUNICH32X dump\n", sc->unit);
859 tp4 = (u_int32_t *)sc->m0v;
860 for(j = 0; j < 64; j += 8) {
861 printf("%02x", j * sizeof *tp4);
862 for(i = 0; i < 8; i++)
863 printf(" %08x", tp4[i+j]);
864 printf("\n");
865 }
866 for(j = 0; j < M32_CHAN; j++) {
867 if (!sc->ch[j])
868 continue;
869 printf("CH%d: state %d ts %08x",
870 j, sc->ch[j]->state, sc->ch[j]->ts);
871 printf(" %08x %08x %08x %08x %08x %08x\n",
872 sc->m32_mem.cs[j].flags,
873 sc->m32_mem.cs[j].rdesc,
874 sc->m32_mem.cs[j].tdesc,
875 sc->m32_mem.cs[j].itbs,
876 sc->m32_mem.crxd[j],
877 sc->m32_mem.ctxd[j] );
878 }
879}
880
881/*
882 * Dump Falch54 state
883 */
884static void
885f54_dump(struct mn_softc *sc)
886{
887 u_int8_t *tp1;
888 int i, j;
889
890 printf("%s: FALC54 dump\n", sc->name);
891 tp1 = (u_int8_t *)sc->m1v;
892 for(j = 0; j < 128; j += 16) {
893 printf("%s: %02x |", sc->name, j * sizeof *tp1);
894 for(i = 0; i < 16; i++)
895 printf(" %02x", tp1[i+j]);
896 printf("\n");
897 }
898}
899#endif /* notyet */
900
901/*
902 * Init Munich32x
903 */
904static void
905m32_init(struct mn_softc *sc)
906{
907
908 sc->m32x->conf = 0x00000000;
909 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
910#if 1
911 sc->m32x->mode2 = 0x00000081;
912 sc->m32x->txpoll = 0xffffffff;
913#elif 1
914 sc->m32x->mode2 = 0x00000081;
915 sc->m32x->txpoll = 0xffffffff;
916#else
917 sc->m32x->mode2 = 0x00000101;
918#endif
919 sc->m32x->lconf = 0x6060009B;
920 sc->m32x->imask = 0x00000000;
921}
922
923/*
924 * Init the Falc54
925 */
926static void
927f54_init(struct mn_softc *sc)
928{
929 sc->f54w->ipc = 0x07;
930
931 sc->f54w->xpm0 = 0xbd;
932 sc->f54w->xpm1 = 0x03;
933 sc->f54w->xpm2 = 0x00;
934
935 sc->f54w->imr0 = 0x18; /* RMB, CASC */
936 sc->f54w->imr1 = 0x08; /* XMB */
937 sc->f54w->imr2 = 0x00;
938 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
939 sc->f54w->imr4 = 0x00;
940
941 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
942 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
943 if (sc->framing == E1)
944 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
945 else if (sc->framing == E1U)
946 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */
947
948 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
949 sc->f54w->pcd = 0x0a;
950 sc->f54w->pcr = 0x15;
951 sc->f54w->xsw = 0x9f; /* fmr4 */
952 if (sc->framing == E1)
953 sc->f54w->xsp = 0x1c; /* fmr5 */
954 else if (sc->framing == E1U)
955 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */
956 sc->f54w->xc0 = 0x07;
957 sc->f54w->xc1 = 0x3d;
958 sc->f54w->rc0 = 0x05;
959 sc->f54w->rc1 = 0x00;
960 sc->f54w->cmdr = 0x51;
961}
962
963static int
964mn_reset(struct mn_softc *sc)
965{
966 u_int32_t u;
967 int i;
968
969 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
970 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
971
972 bzero(sc->tiqb, sizeof sc->tiqb);
973 sc->m32x->tiqba = vtophys(&sc->tiqb);
974 sc->m32x->tiql = NIQB / 16 - 1;
975
976 bzero(sc->riqb, sizeof sc->riqb);
977 sc->m32x->riqba = vtophys(&sc->riqb);
978 sc->m32x->riql = NIQB / 16 - 1;
979
980 bzero(sc->ltiqb, sizeof sc->ltiqb);
981 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
982 sc->m32x->ltiql = NIQB / 16 - 1;
983
984 bzero(sc->lriqb, sizeof sc->lriqb);
985 sc->m32x->lriqba = vtophys(&sc->lriqb);
986 sc->m32x->lriql = NIQB / 16 - 1;
987
988 bzero(sc->piqb, sizeof sc->piqb);
989 sc->m32x->piqba = vtophys(&sc->piqb);
990 sc->m32x->piql = NIQB / 16 - 1;
991
992 m32_init(sc);
993 f54_init(sc);
994
995 u = sc->m32x->stat;
996 sc->m32x->stat = u;
997 sc->m32_mem.ccb = 0x4;
998 sc->m32x->cmd = 0x1;
999 DELAY(1000);
1000 u = sc->m32x->stat;
1001 sc->m32x->stat = u;
1002
1003 /* set all timeslots to known state */
1004 for (i = 0; i < 32; i++)
1005 sc->m32_mem.ts[i] = 0x20002000;
1006
1007 if (!(u & 1)) {
1008 printf(
1009"mn%d: WARNING: Controller failed the PCI bus-master test.\n"
1010"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
1011 sc->unit, sc->unit);
1012 return (0);
1013 }
1014 return (1);
1015}
1016
1017/*
1018 * FALC54 interrupt handling
1019 */
1020static void
1021f54_intr(struct mn_softc *sc)
1022{
1023 unsigned g, u, s;
1024
1025 g = sc->f54r->gis;
1026 u = sc->f54r->isr0 << 24;
1027 u |= sc->f54r->isr1 << 16;
1028 u |= sc->f54r->isr2 << 8;
1029 u |= sc->f54r->isr3;
1030 sc->falc_irq = u;
1031 /* don't chat about the 1 sec heart beat */
1032 if (u & ~0x40) {
1033#if 0
1034 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
1035 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
1036 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
1037 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
1038 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
1039#endif
1040 s = sc->f54r->frs0 << 24;
1041 s |= sc->f54r->frs1 << 16;
1042 s |= sc->f54r->rsw << 8;
1043 s |= sc->f54r->rsp;
1044 sc->falc_state = s;
1045
1046 s &= ~0x01844038; /* undefined or static bits */
1047 s &= ~0x00009fc7; /* bits we don't care about */
1048 s &= ~0x00780000; /* XXX: TS16 related */
1049 s &= ~0x06000000; /* XXX: Multiframe related */
1050#if 0
1051 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
1052 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
1053 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
1054 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
1055 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
1056#endif
1057 if (s != sc->framer_state) {
1058#if 0
1059 for (i = 0; i < M32_CHAN; i++) {
1060 if (!sc->ch[i])
1061 continue;
1062 sp = &sc->ch[i]->ifsppp;
1063 if (!(SP2IFP(sp)->if_flags & IFF_UP))
1064 continue;
1065 if (s)
1066 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
1067 else
1068 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
1069 }
1070#endif
1071 sc->framer_state = s;
1072 }
1073 }
1074 /* Once per second check error counters */
1075 /* XXX: not clear if this is actually ok */
1076 if (!(u & 0x40))
1077 return;
1078 sc->cnt_fec += sc->f54r->fec;
1079 sc->cnt_cvc += sc->f54r->cvc;
1080 sc->cnt_cec1 += sc->f54r->cec1;
1081 sc->cnt_ebc += sc->f54r->ebc;
1082 sc->cnt_cec2 += sc->f54r->cec2;
1083 sc->cnt_cec3 += sc->f54r->cec3;
1084 sc->cnt_rbc += sc->f54r->rbc;
1085}
1086
1087/*
1088 * Transmit interrupt for one channel
1089 */
1090static void
1091mn_tx_intr(struct mn_softc *sc, u_int32_t vector)
1092{
1093 u_int32_t chan;
1094 struct trxd *dp;
1095 struct mbuf *m;
1096
1097 chan = vector & 0x1f;
1098 if (!sc->ch[chan])
1099 return;
1100 if (sc->ch[chan]->state != UP) {
1101 printf("%s: tx_intr when not UP\n", sc->name);
1102 return;
1103 }
1104 for (;;) {
1105 dp = sc->ch[chan]->x1;
1106 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1107 return;
1108 m = dp->m;
1109 if (m) {
1110#if 0
1111 printf("%d = %d - %d (%p)\n",
1112 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1113 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1114#endif
1115 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1116 m_freem(m);
1117 }
1118 sc->ch[chan]->last_xmit = time_second;
1119 sc->ch[chan]->x1 = dp->vnext;
1120 mn_free_desc(dp);
1121 }
1122}
1123
1124/*
1125 * Receive interrupt for one channel
1126 */
1127static void
1128mn_rx_intr(struct mn_softc *sc, u_int32_t vector)
1129{
1130 u_int32_t chan, err;
1131 struct trxd *dp;
1132 struct mbuf *m;
1133 struct schan *sch;
1134
1135 chan = vector & 0x1f;
1136 if (!sc->ch[chan])
1137 return;
1138 sch = sc->ch[chan];
1139 if (sch->state != UP) {
1140 printf("%s: rx_intr when not UP\n", sc->name);
1141 return;
1142 }
1143 vector &= ~0x1f;
1144 if (vector == 0x30000b00)
1145 sch->rx_error++;
1146 for (;;) {
1147 dp = sch->r1;
1148 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1149 return;
1150 m = dp->m;
1151 dp->m = 0;
1152 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1153 err = (dp->status >> 8) & 0xff;
1154 if (!err) {
1155 int error;
1156 NG_SEND_DATA_ONLY(error, sch->hook, m);
1157 sch->last_recv = time_second;
1158 /* we could be down by now... */
1159 if (sch->state != UP)
1160 return;
1161 } else if (err & 0x40) {
1162 sch->short_error++;
1163 } else if (err & 0x10) {
1164 sch->crc_error++;
1165 } else if (err & 0x08) {
1166 sch->dribble_error++;
1167 } else if (err & 0x04) {
1168 sch->long_error++;
1169 } else if (err & 0x02) {
1170 sch->abort_error++;
1171 } else if (err & 0x01) {
1172 sch->overflow_error++;
1173 }
1174 if (err) {
1175 sch->last_rxerr = time_second;
1176 sch->prev_error = sch->last_error;
1177 sch->last_error = err;
1178 }
1179
1180 sc->ch[chan]->r1 = dp->vnext;
1181
1182 /* Replenish desc + mbuf supplies */
1183 if (!m) {
1184 MGETHDR(m, M_DONTWAIT, MT_DATA);
1185 if (m == NULL) {
1186 mn_free_desc(dp);
1187 return; /* ENOBUFS */
1188 }
1189 MCLGET(m, M_DONTWAIT);
1190 if((m->m_flags & M_EXT) == 0) {
1191 mn_free_desc(dp);
1192 m_freem(m);
1193 return; /* ENOBUFS */
1194 }
1195 }
1196 dp->m = m;
1197 dp->data = vtophys(m->m_data);
1198 dp->flags = 0x40000000;
1199 dp->flags += 1600 << 16;
1200 dp->next = vtophys(dp);
1201 dp->vnext = 0;
1202 sc->ch[chan]->rl->next = vtophys(dp);
1203 sc->ch[chan]->rl->vnext = dp;
1204 sc->ch[chan]->rl->flags &= ~0x40000000;
1205 sc->ch[chan]->rl = dp;
1206 }
1207}
1208
1209
1210/*
1211 * Interupt handler
1212 */
1213
1214static void
1215mn_intr(void *xsc)
1216{
1217 struct mn_softc *sc;
1218 u_int32_t stat, lstat, u;
1219 int i, j;
1220
1221 sc = xsc;
1222 stat = sc->m32x->stat;
1223 lstat = sc->m32x->lstat;
1224#if 0
1225 if (!stat && !(lstat & 2))
1226 return;
1227#endif
1228
1229 if (stat & ~0xc200) {
1230 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1231 }
1232
1233 if ((stat & 0x200) || (lstat & 2))
1234 f54_intr(sc);
1235
1236 for (j = i = 0; i < 64; i ++) {
1237 u = sc->riqb[i];
1238 if (u) {
1239 sc->riqb[i] = 0;
1240 mn_rx_intr(sc, u);
1241 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1242 continue;
1243 u &= ~0x30000400; /* bits we don't care about */
1244 if ((u & ~0x1f) == 0x00000900)
1245 continue;
1246 if (!(u & ~0x1f))
1247 continue;
1248 if (!j)
1249 printf("%s*: RIQB:", sc->name);
1250 printf(" [%d]=%08x", i, u);
1251 j++;
1252 }
1253 }
1254 if (j)
1255 printf("\n");
1256
1257 for (j = i = 0; i < 64; i ++) {
1258 u = sc->tiqb[i];
1259 if (u) {
1260 sc->tiqb[i] = 0;
1261 mn_tx_intr(sc, u);
1262 if ((u & ~0x1f) == 0x20000800)
1263 continue;
1264 u &= ~0x20000000; /* bits we don't care about */
1265 if (!u)
1266 continue;
1267 if (!j)
1268 printf("%s*: TIQB:", sc->name);
1269 printf(" [%d]=%08x", i, u);
1270 j++;
1271 }
1272 }
1273 if (j)
1274 printf("\n");
1275 sc->m32x->stat = stat;
1276}
1277
1278static void
1279mn_timeout(void *xsc)
1280{
1281 static int round = 0;
1282 struct mn_softc *sc;
1283
1284 mn_intr(xsc);
1285 sc = xsc;
1286 timeout(mn_timeout, xsc, 10 * hz);
1287 round++;
1288 if (round == 2) {
1289 sc->m32_mem.ccb = 0x00008004;
1290 sc->m32x->cmd = 0x1;
1291 } else if (round > 2) {
1292 printf("%s: timeout\n", sc->name);
1293 }
1294}
1295
1296/*
1297 * PCI initialization stuff
1298 */
1299
1300static int
1301mn_probe (device_t self)
1302{
1303 u_int id = pci_get_devid(self);
1304
1305 if (sizeof (struct m32xreg) != 256) {
1306 printf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg));
1307 return (ENXIO);
1308 }
1309 if (sizeof (struct f54rreg) != 128) {
1310 printf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg));
1311 return (ENXIO);
1312 }
1313 if (sizeof (struct f54wreg) != 128) {
1314 printf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg));
1315 return (ENXIO);
1316 }
1317
1318 if (id != 0x2101110a)
1319 return (ENXIO);
1320
1321 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1322 return (BUS_PROBE_DEFAULT);
1323}
1324
1325static int
1326mn_attach (device_t self)
1327{
1328 struct mn_softc *sc;
1329 u_int32_t u;
1330 u_int32_t ver;
1331 static int once;
1332 int rid, error;
1333 struct resource *res;
1334
1335 if (!once) {
1336 if (ng_newtype(&mntypestruct))
1337 printf("ng_newtype failed\n");
1338 once++;
1339 }
1340
1341 sc = (struct mn_softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1342 device_set_softc(self, sc);
1343
1344 sc->dev = self;
1345 sc->unit = device_get_unit(self);
1346 sc->framing = E1;
1347 sprintf(sc->name, "mn%d", sc->unit);
1348
1349 rid = PCIR_BAR(0);
1350 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1351 if (res == NULL) {
1352 device_printf(self, "Could not map memory\n");
1353 free(sc, M_MN);
1354 return ENXIO;
1355 }
1356 sc->m0v = rman_get_virtual(res);
1357 sc->m0p = rman_get_start(res);
1358
1359 rid = PCIR_BAR(1);
1360 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1361 if (res == NULL) {
1362 device_printf(self, "Could not map memory\n");
1363 free(sc, M_MN);
1364 return ENXIO;
1365 }
1366 sc->m1v = rman_get_virtual(res);
1367 sc->m1p = rman_get_start(res);
1368
1369 /* Allocate interrupt */
1370 rid = 0;
1371 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
1372 RF_SHAREABLE | RF_ACTIVE);
1373
1374 if (sc->irq == NULL) {
1375 printf("couldn't map interrupt\n");
1376 free(sc, M_MN);
1377 return(ENXIO);
1378 }
1379
1380 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, NULL, mn_intr, sc, &sc->intrhand);
1381
1382 if (error) {
1383 printf("couldn't set up irq\n");
1384 free(sc, M_MN);
1385 return(ENXIO);
1386 }
1387
1388 u = pci_read_config(self, PCIR_COMMAND, 1);
1389 printf("%x\n", u);
1390 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1);
1391#if 0
1392 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1393#endif
1394 u = pci_read_config(self, PCIR_COMMAND, 1);
1395 printf("%x\n", u);
1396
1397 ver = pci_get_revid(self);
1398
1399 sc->m32x = (struct m32xreg *) sc->m0v;
1400 sc->f54w = (struct f54wreg *) sc->m1v;
1401 sc->f54r = (struct f54rreg *) sc->m1v;
1402
1403 /* We must reset before poking at FALC54 registers */
1404 u = mn_reset(sc);
1405 if (!u)
1406 return (0);
1407
1408 printf("mn%d: Munich32X", sc->unit);
1409 switch (ver) {
1410 case 0x13:
1411 printf(" Rev 2.2");
1412 break;
1413 default:
1414 printf(" Rev 0x%x\n", ver);
1415 }
1416 printf(", Falc54");
1417 switch (sc->f54r->vstr) {
1418 case 0:
1419 printf(" Rev < 1.3\n");
1420 break;
1421 case 1:
1422 printf(" Rev 1.3\n");
1423 break;
1424 case 2:
1425 printf(" Rev 1.4\n");
1426 break;
1427 case 0x10:
1428 printf("-LH Rev 1.1\n");
1429 break;
1430 case 0x13:
1431 printf("-LH Rev 1.3\n");
1432 break;
1433 default:
1434 printf(" Rev 0x%x\n", sc->f54r->vstr);
1435 }
1436
1437 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1438 printf("ng_make_node_common failed\n");
1439 return (0);
1440 }
1441 NG_NODE_SET_PRIVATE(sc->node, sc);
1442 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1443 if (ng_name_node(sc->node, sc->nodename)) {
1444 NG_NODE_UNREF(sc->node);
1445 return (0);
1446 }
1447
1448 return (0);
1449}
1450
1451
1452static device_method_t mn_methods[] = {
1453 /* Device interface */
1454 DEVMETHOD(device_probe, mn_probe),
1455 DEVMETHOD(device_attach, mn_attach),
1456 DEVMETHOD(device_suspend, bus_generic_suspend),
1457 DEVMETHOD(device_resume, bus_generic_resume),
1458 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1459
1460 {0, 0}
1461};
1462
1463static driver_t mn_driver = {
1464 "mn",
1465 mn_methods,
1466 0
1467};
1468
1469static devclass_t mn_devclass;
1470
1471DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);
| 727 dp->m = m;
728 dp->data = vtophys(m->m_data);
729 dp->flags = 0x00000000;
730 dp->flags += 1600 << 16;
731 dp->next = vtophys(dp2);
732 dp->vnext = dp2;
733 }
734 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
735 sc->ch[chan]->r1 = dp;
736
737 /* Initialize this channel */
738 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
739 sc->m32x->cmd = 0x1;
740 DELAY(1000);
741 u = sc->m32x->stat;
742 if (!(u & 1))
743 printf("%s: init chan %d stat %08x\n", sc->name, chan, u);
744 sc->m32x->stat = 1;
745 /* probably not at splnet, force outward queueing */
746 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
747
748 return (0);
749}
750
751/*
752 * CLOSE
753 */
754static int
755ngmn_disconnect(hook_p hook)
756{
757 int chan, i;
758 struct mn_softc *sc;
759 struct schan *sch;
760 struct trxd *dp, *dp2;
761 u_int32_t u;
762
763 sch = NG_HOOK_PRIVATE(hook);
764 chan = sch->chan;
765 sc = sch->sc;
766
767 if (sch->state == DOWN)
768 return (0);
769 sch->state = DOWN;
770
771 /* Set receiver & transmitter off */
772 sc->m32_mem.cs[chan].flags = 0x80920006;
773 sc->m32_mem.cs[chan].itbs = 0;
774
775 /* free the timeslots */
776 for (i = 0; i < 32; i++)
777 if (sc->ch[chan]->ts & (1 << i))
778 sc->m32_mem.ts[i] = 0x20002000;
779
780 /* Initialize this channel */
781 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
782 sc->m32x->cmd = 0x1;
783 DELAY(30);
784 u = sc->m32x->stat;
785 if (!(u & 1))
786 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
787 sc->m32x->stat = 1;
788
789 /* Free all receive descriptors and mbufs */
790 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
791 if (dp->m)
792 m_freem(dp->m);
793 sc->ch[chan]->r1 = dp2 = dp->vnext;
794 mn_free_desc(dp);
795 }
796
797 /* Free all transmit descriptors and mbufs */
798 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
799 if (dp->m) {
800 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
801 m_freem(dp->m);
802 }
803 sc->ch[chan]->x1 = dp2 = dp->vnext;
804 mn_free_desc(dp);
805 }
806 sc->nhooks--;
807 return(0);
808}
809
810/*
811 * Create a new channel.
812 */
813static void
814mn_create_channel(struct mn_softc *sc, int chan)
815{
816 struct schan *sch;
817
818 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan],
819 M_MN, M_WAITOK | M_ZERO);
820 sch->sc = sc;
821 sch->state = DOWN;
822 sch->chan = chan;
823 sprintf(sch->name, "%s%d", sc->name, chan);
824 return;
825}
826
827#ifdef notyet
828/*
829 * Dump Munich32x state
830 */
831static void
832m32_dump(struct mn_softc *sc)
833{
834 u_int32_t *tp4;
835 int i, j;
836
837 printf("mn%d: MUNICH32X dump\n", sc->unit);
838 tp4 = (u_int32_t *)sc->m0v;
839 for(j = 0; j < 64; j += 8) {
840 printf("%02x", j * sizeof *tp4);
841 for(i = 0; i < 8; i++)
842 printf(" %08x", tp4[i+j]);
843 printf("\n");
844 }
845 for(j = 0; j < M32_CHAN; j++) {
846 if (!sc->ch[j])
847 continue;
848 printf("CH%d: state %d ts %08x",
849 j, sc->ch[j]->state, sc->ch[j]->ts);
850 printf(" %08x %08x %08x %08x %08x %08x\n",
851 sc->m32_mem.cs[j].flags,
852 sc->m32_mem.cs[j].rdesc,
853 sc->m32_mem.cs[j].tdesc,
854 sc->m32_mem.cs[j].itbs,
855 sc->m32_mem.crxd[j],
856 sc->m32_mem.ctxd[j] );
857 }
858}
859
860/*
861 * Dump Falch54 state
862 */
863static void
864f54_dump(struct mn_softc *sc)
865{
866 u_int8_t *tp1;
867 int i, j;
868
869 printf("%s: FALC54 dump\n", sc->name);
870 tp1 = (u_int8_t *)sc->m1v;
871 for(j = 0; j < 128; j += 16) {
872 printf("%s: %02x |", sc->name, j * sizeof *tp1);
873 for(i = 0; i < 16; i++)
874 printf(" %02x", tp1[i+j]);
875 printf("\n");
876 }
877}
878#endif /* notyet */
879
880/*
881 * Init Munich32x
882 */
883static void
884m32_init(struct mn_softc *sc)
885{
886
887 sc->m32x->conf = 0x00000000;
888 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
889#if 1
890 sc->m32x->mode2 = 0x00000081;
891 sc->m32x->txpoll = 0xffffffff;
892#elif 1
893 sc->m32x->mode2 = 0x00000081;
894 sc->m32x->txpoll = 0xffffffff;
895#else
896 sc->m32x->mode2 = 0x00000101;
897#endif
898 sc->m32x->lconf = 0x6060009B;
899 sc->m32x->imask = 0x00000000;
900}
901
902/*
903 * Init the Falc54
904 */
905static void
906f54_init(struct mn_softc *sc)
907{
908 sc->f54w->ipc = 0x07;
909
910 sc->f54w->xpm0 = 0xbd;
911 sc->f54w->xpm1 = 0x03;
912 sc->f54w->xpm2 = 0x00;
913
914 sc->f54w->imr0 = 0x18; /* RMB, CASC */
915 sc->f54w->imr1 = 0x08; /* XMB */
916 sc->f54w->imr2 = 0x00;
917 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
918 sc->f54w->imr4 = 0x00;
919
920 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
921 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
922 if (sc->framing == E1)
923 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
924 else if (sc->framing == E1U)
925 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */
926
927 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
928 sc->f54w->pcd = 0x0a;
929 sc->f54w->pcr = 0x15;
930 sc->f54w->xsw = 0x9f; /* fmr4 */
931 if (sc->framing == E1)
932 sc->f54w->xsp = 0x1c; /* fmr5 */
933 else if (sc->framing == E1U)
934 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */
935 sc->f54w->xc0 = 0x07;
936 sc->f54w->xc1 = 0x3d;
937 sc->f54w->rc0 = 0x05;
938 sc->f54w->rc1 = 0x00;
939 sc->f54w->cmdr = 0x51;
940}
941
942static int
943mn_reset(struct mn_softc *sc)
944{
945 u_int32_t u;
946 int i;
947
948 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
949 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
950
951 bzero(sc->tiqb, sizeof sc->tiqb);
952 sc->m32x->tiqba = vtophys(&sc->tiqb);
953 sc->m32x->tiql = NIQB / 16 - 1;
954
955 bzero(sc->riqb, sizeof sc->riqb);
956 sc->m32x->riqba = vtophys(&sc->riqb);
957 sc->m32x->riql = NIQB / 16 - 1;
958
959 bzero(sc->ltiqb, sizeof sc->ltiqb);
960 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
961 sc->m32x->ltiql = NIQB / 16 - 1;
962
963 bzero(sc->lriqb, sizeof sc->lriqb);
964 sc->m32x->lriqba = vtophys(&sc->lriqb);
965 sc->m32x->lriql = NIQB / 16 - 1;
966
967 bzero(sc->piqb, sizeof sc->piqb);
968 sc->m32x->piqba = vtophys(&sc->piqb);
969 sc->m32x->piql = NIQB / 16 - 1;
970
971 m32_init(sc);
972 f54_init(sc);
973
974 u = sc->m32x->stat;
975 sc->m32x->stat = u;
976 sc->m32_mem.ccb = 0x4;
977 sc->m32x->cmd = 0x1;
978 DELAY(1000);
979 u = sc->m32x->stat;
980 sc->m32x->stat = u;
981
982 /* set all timeslots to known state */
983 for (i = 0; i < 32; i++)
984 sc->m32_mem.ts[i] = 0x20002000;
985
986 if (!(u & 1)) {
987 printf(
988"mn%d: WARNING: Controller failed the PCI bus-master test.\n"
989"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
990 sc->unit, sc->unit);
991 return (0);
992 }
993 return (1);
994}
995
996/*
997 * FALC54 interrupt handling
998 */
999static void
1000f54_intr(struct mn_softc *sc)
1001{
1002 unsigned g, u, s;
1003
1004 g = sc->f54r->gis;
1005 u = sc->f54r->isr0 << 24;
1006 u |= sc->f54r->isr1 << 16;
1007 u |= sc->f54r->isr2 << 8;
1008 u |= sc->f54r->isr3;
1009 sc->falc_irq = u;
1010 /* don't chat about the 1 sec heart beat */
1011 if (u & ~0x40) {
1012#if 0
1013 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
1014 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
1015 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
1016 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
1017 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
1018#endif
1019 s = sc->f54r->frs0 << 24;
1020 s |= sc->f54r->frs1 << 16;
1021 s |= sc->f54r->rsw << 8;
1022 s |= sc->f54r->rsp;
1023 sc->falc_state = s;
1024
1025 s &= ~0x01844038; /* undefined or static bits */
1026 s &= ~0x00009fc7; /* bits we don't care about */
1027 s &= ~0x00780000; /* XXX: TS16 related */
1028 s &= ~0x06000000; /* XXX: Multiframe related */
1029#if 0
1030 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
1031 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
1032 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
1033 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
1034 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
1035#endif
1036 if (s != sc->framer_state) {
1037#if 0
1038 for (i = 0; i < M32_CHAN; i++) {
1039 if (!sc->ch[i])
1040 continue;
1041 sp = &sc->ch[i]->ifsppp;
1042 if (!(SP2IFP(sp)->if_flags & IFF_UP))
1043 continue;
1044 if (s)
1045 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
1046 else
1047 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
1048 }
1049#endif
1050 sc->framer_state = s;
1051 }
1052 }
1053 /* Once per second check error counters */
1054 /* XXX: not clear if this is actually ok */
1055 if (!(u & 0x40))
1056 return;
1057 sc->cnt_fec += sc->f54r->fec;
1058 sc->cnt_cvc += sc->f54r->cvc;
1059 sc->cnt_cec1 += sc->f54r->cec1;
1060 sc->cnt_ebc += sc->f54r->ebc;
1061 sc->cnt_cec2 += sc->f54r->cec2;
1062 sc->cnt_cec3 += sc->f54r->cec3;
1063 sc->cnt_rbc += sc->f54r->rbc;
1064}
1065
1066/*
1067 * Transmit interrupt for one channel
1068 */
1069static void
1070mn_tx_intr(struct mn_softc *sc, u_int32_t vector)
1071{
1072 u_int32_t chan;
1073 struct trxd *dp;
1074 struct mbuf *m;
1075
1076 chan = vector & 0x1f;
1077 if (!sc->ch[chan])
1078 return;
1079 if (sc->ch[chan]->state != UP) {
1080 printf("%s: tx_intr when not UP\n", sc->name);
1081 return;
1082 }
1083 for (;;) {
1084 dp = sc->ch[chan]->x1;
1085 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1086 return;
1087 m = dp->m;
1088 if (m) {
1089#if 0
1090 printf("%d = %d - %d (%p)\n",
1091 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1092 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1093#endif
1094 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1095 m_freem(m);
1096 }
1097 sc->ch[chan]->last_xmit = time_second;
1098 sc->ch[chan]->x1 = dp->vnext;
1099 mn_free_desc(dp);
1100 }
1101}
1102
1103/*
1104 * Receive interrupt for one channel
1105 */
1106static void
1107mn_rx_intr(struct mn_softc *sc, u_int32_t vector)
1108{
1109 u_int32_t chan, err;
1110 struct trxd *dp;
1111 struct mbuf *m;
1112 struct schan *sch;
1113
1114 chan = vector & 0x1f;
1115 if (!sc->ch[chan])
1116 return;
1117 sch = sc->ch[chan];
1118 if (sch->state != UP) {
1119 printf("%s: rx_intr when not UP\n", sc->name);
1120 return;
1121 }
1122 vector &= ~0x1f;
1123 if (vector == 0x30000b00)
1124 sch->rx_error++;
1125 for (;;) {
1126 dp = sch->r1;
1127 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1128 return;
1129 m = dp->m;
1130 dp->m = 0;
1131 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1132 err = (dp->status >> 8) & 0xff;
1133 if (!err) {
1134 int error;
1135 NG_SEND_DATA_ONLY(error, sch->hook, m);
1136 sch->last_recv = time_second;
1137 /* we could be down by now... */
1138 if (sch->state != UP)
1139 return;
1140 } else if (err & 0x40) {
1141 sch->short_error++;
1142 } else if (err & 0x10) {
1143 sch->crc_error++;
1144 } else if (err & 0x08) {
1145 sch->dribble_error++;
1146 } else if (err & 0x04) {
1147 sch->long_error++;
1148 } else if (err & 0x02) {
1149 sch->abort_error++;
1150 } else if (err & 0x01) {
1151 sch->overflow_error++;
1152 }
1153 if (err) {
1154 sch->last_rxerr = time_second;
1155 sch->prev_error = sch->last_error;
1156 sch->last_error = err;
1157 }
1158
1159 sc->ch[chan]->r1 = dp->vnext;
1160
1161 /* Replenish desc + mbuf supplies */
1162 if (!m) {
1163 MGETHDR(m, M_DONTWAIT, MT_DATA);
1164 if (m == NULL) {
1165 mn_free_desc(dp);
1166 return; /* ENOBUFS */
1167 }
1168 MCLGET(m, M_DONTWAIT);
1169 if((m->m_flags & M_EXT) == 0) {
1170 mn_free_desc(dp);
1171 m_freem(m);
1172 return; /* ENOBUFS */
1173 }
1174 }
1175 dp->m = m;
1176 dp->data = vtophys(m->m_data);
1177 dp->flags = 0x40000000;
1178 dp->flags += 1600 << 16;
1179 dp->next = vtophys(dp);
1180 dp->vnext = 0;
1181 sc->ch[chan]->rl->next = vtophys(dp);
1182 sc->ch[chan]->rl->vnext = dp;
1183 sc->ch[chan]->rl->flags &= ~0x40000000;
1184 sc->ch[chan]->rl = dp;
1185 }
1186}
1187
1188
1189/*
1190 * Interupt handler
1191 */
1192
1193static void
1194mn_intr(void *xsc)
1195{
1196 struct mn_softc *sc;
1197 u_int32_t stat, lstat, u;
1198 int i, j;
1199
1200 sc = xsc;
1201 stat = sc->m32x->stat;
1202 lstat = sc->m32x->lstat;
1203#if 0
1204 if (!stat && !(lstat & 2))
1205 return;
1206#endif
1207
1208 if (stat & ~0xc200) {
1209 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1210 }
1211
1212 if ((stat & 0x200) || (lstat & 2))
1213 f54_intr(sc);
1214
1215 for (j = i = 0; i < 64; i ++) {
1216 u = sc->riqb[i];
1217 if (u) {
1218 sc->riqb[i] = 0;
1219 mn_rx_intr(sc, u);
1220 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1221 continue;
1222 u &= ~0x30000400; /* bits we don't care about */
1223 if ((u & ~0x1f) == 0x00000900)
1224 continue;
1225 if (!(u & ~0x1f))
1226 continue;
1227 if (!j)
1228 printf("%s*: RIQB:", sc->name);
1229 printf(" [%d]=%08x", i, u);
1230 j++;
1231 }
1232 }
1233 if (j)
1234 printf("\n");
1235
1236 for (j = i = 0; i < 64; i ++) {
1237 u = sc->tiqb[i];
1238 if (u) {
1239 sc->tiqb[i] = 0;
1240 mn_tx_intr(sc, u);
1241 if ((u & ~0x1f) == 0x20000800)
1242 continue;
1243 u &= ~0x20000000; /* bits we don't care about */
1244 if (!u)
1245 continue;
1246 if (!j)
1247 printf("%s*: TIQB:", sc->name);
1248 printf(" [%d]=%08x", i, u);
1249 j++;
1250 }
1251 }
1252 if (j)
1253 printf("\n");
1254 sc->m32x->stat = stat;
1255}
1256
1257static void
1258mn_timeout(void *xsc)
1259{
1260 static int round = 0;
1261 struct mn_softc *sc;
1262
1263 mn_intr(xsc);
1264 sc = xsc;
1265 timeout(mn_timeout, xsc, 10 * hz);
1266 round++;
1267 if (round == 2) {
1268 sc->m32_mem.ccb = 0x00008004;
1269 sc->m32x->cmd = 0x1;
1270 } else if (round > 2) {
1271 printf("%s: timeout\n", sc->name);
1272 }
1273}
1274
1275/*
1276 * PCI initialization stuff
1277 */
1278
1279static int
1280mn_probe (device_t self)
1281{
1282 u_int id = pci_get_devid(self);
1283
1284 if (sizeof (struct m32xreg) != 256) {
1285 printf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg));
1286 return (ENXIO);
1287 }
1288 if (sizeof (struct f54rreg) != 128) {
1289 printf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg));
1290 return (ENXIO);
1291 }
1292 if (sizeof (struct f54wreg) != 128) {
1293 printf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg));
1294 return (ENXIO);
1295 }
1296
1297 if (id != 0x2101110a)
1298 return (ENXIO);
1299
1300 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1301 return (BUS_PROBE_DEFAULT);
1302}
1303
1304static int
1305mn_attach (device_t self)
1306{
1307 struct mn_softc *sc;
1308 u_int32_t u;
1309 u_int32_t ver;
1310 static int once;
1311 int rid, error;
1312 struct resource *res;
1313
1314 if (!once) {
1315 if (ng_newtype(&mntypestruct))
1316 printf("ng_newtype failed\n");
1317 once++;
1318 }
1319
1320 sc = (struct mn_softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1321 device_set_softc(self, sc);
1322
1323 sc->dev = self;
1324 sc->unit = device_get_unit(self);
1325 sc->framing = E1;
1326 sprintf(sc->name, "mn%d", sc->unit);
1327
1328 rid = PCIR_BAR(0);
1329 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1330 if (res == NULL) {
1331 device_printf(self, "Could not map memory\n");
1332 free(sc, M_MN);
1333 return ENXIO;
1334 }
1335 sc->m0v = rman_get_virtual(res);
1336 sc->m0p = rman_get_start(res);
1337
1338 rid = PCIR_BAR(1);
1339 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1340 if (res == NULL) {
1341 device_printf(self, "Could not map memory\n");
1342 free(sc, M_MN);
1343 return ENXIO;
1344 }
1345 sc->m1v = rman_get_virtual(res);
1346 sc->m1p = rman_get_start(res);
1347
1348 /* Allocate interrupt */
1349 rid = 0;
1350 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
1351 RF_SHAREABLE | RF_ACTIVE);
1352
1353 if (sc->irq == NULL) {
1354 printf("couldn't map interrupt\n");
1355 free(sc, M_MN);
1356 return(ENXIO);
1357 }
1358
1359 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, NULL, mn_intr, sc, &sc->intrhand);
1360
1361 if (error) {
1362 printf("couldn't set up irq\n");
1363 free(sc, M_MN);
1364 return(ENXIO);
1365 }
1366
1367 u = pci_read_config(self, PCIR_COMMAND, 1);
1368 printf("%x\n", u);
1369 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1);
1370#if 0
1371 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1372#endif
1373 u = pci_read_config(self, PCIR_COMMAND, 1);
1374 printf("%x\n", u);
1375
1376 ver = pci_get_revid(self);
1377
1378 sc->m32x = (struct m32xreg *) sc->m0v;
1379 sc->f54w = (struct f54wreg *) sc->m1v;
1380 sc->f54r = (struct f54rreg *) sc->m1v;
1381
1382 /* We must reset before poking at FALC54 registers */
1383 u = mn_reset(sc);
1384 if (!u)
1385 return (0);
1386
1387 printf("mn%d: Munich32X", sc->unit);
1388 switch (ver) {
1389 case 0x13:
1390 printf(" Rev 2.2");
1391 break;
1392 default:
1393 printf(" Rev 0x%x\n", ver);
1394 }
1395 printf(", Falc54");
1396 switch (sc->f54r->vstr) {
1397 case 0:
1398 printf(" Rev < 1.3\n");
1399 break;
1400 case 1:
1401 printf(" Rev 1.3\n");
1402 break;
1403 case 2:
1404 printf(" Rev 1.4\n");
1405 break;
1406 case 0x10:
1407 printf("-LH Rev 1.1\n");
1408 break;
1409 case 0x13:
1410 printf("-LH Rev 1.3\n");
1411 break;
1412 default:
1413 printf(" Rev 0x%x\n", sc->f54r->vstr);
1414 }
1415
1416 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1417 printf("ng_make_node_common failed\n");
1418 return (0);
1419 }
1420 NG_NODE_SET_PRIVATE(sc->node, sc);
1421 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1422 if (ng_name_node(sc->node, sc->nodename)) {
1423 NG_NODE_UNREF(sc->node);
1424 return (0);
1425 }
1426
1427 return (0);
1428}
1429
1430
1431static device_method_t mn_methods[] = {
1432 /* Device interface */
1433 DEVMETHOD(device_probe, mn_probe),
1434 DEVMETHOD(device_attach, mn_attach),
1435 DEVMETHOD(device_suspend, bus_generic_suspend),
1436 DEVMETHOD(device_resume, bus_generic_resume),
1437 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1438
1439 {0, 0}
1440};
1441
1442static driver_t mn_driver = {
1443 "mn",
1444 mn_methods,
1445 0
1446};
1447
1448static devclass_t mn_devclass;
1449
1450DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);
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