44#include <sys/socket.h>
45#include <sys/bus.h>
46
47#include <machine/clock.h>
48
49#include <net/if.h>
50#include <net/if_media.h>
51
52#include <dev/mii/mii.h>
53#include <dev/mii/miivar.h>
54#include "miidevs.h"
55
56#include <dev/mii/brgphyreg.h>
57#include <net/if_arp.h>
58#include <machine/bus.h>
59#include <dev/bge/if_bgereg.h>
60
61#include <dev/pci/pcireg.h>
62#include <dev/pci/pcivar.h>
63
64#include "miibus_if.h"
65
66static int brgphy_probe(device_t);
67static int brgphy_attach(device_t);
68
69static device_method_t brgphy_methods[] = {
70 /* device interface */
71 DEVMETHOD(device_probe, brgphy_probe),
72 DEVMETHOD(device_attach, brgphy_attach),
73 DEVMETHOD(device_detach, mii_phy_detach),
74 DEVMETHOD(device_shutdown, bus_generic_shutdown),
75 { 0, 0 }
76};
77
78static devclass_t brgphy_devclass;
79
80static driver_t brgphy_driver = {
81 "brgphy",
82 brgphy_methods,
83 sizeof(struct mii_softc)
84};
85
86DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
87
88static int brgphy_service(struct mii_softc *, struct mii_data *, int);
89static void brgphy_status(struct mii_softc *);
90static int brgphy_mii_phy_auto(struct mii_softc *);
91static void brgphy_reset(struct mii_softc *);
92static void brgphy_loop(struct mii_softc *);
93static void bcm5401_load_dspcode(struct mii_softc *);
94static void bcm5411_load_dspcode(struct mii_softc *);
95static void bcm5703_load_dspcode(struct mii_softc *);
96static int brgphy_mii_model;
97
98static int
99brgphy_probe(dev)
100 device_t dev;
101{
102 struct mii_attach_args *ma;
103
104 ma = device_get_ivars(dev);
105
106 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
107 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) {
108 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400);
109 return(0);
110 }
111
112 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
113 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) {
114 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401);
115 return(0);
116 }
117
118 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
119 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) {
120 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411);
121 return(0);
122 }
123
124 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
125 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) {
126 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701);
127 return(0);
128 }
129
130 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
131 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) {
132 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703);
133 return(0);
134 }
135
136 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
137 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) {
138 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704);
139 return(0);
140 }
141
142 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
143 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) {
144 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705);
145 return(0);
146 }
147
148 return(ENXIO);
149}
150
151static int
152brgphy_attach(dev)
153 device_t dev;
154{
155 struct mii_softc *sc;
156 struct mii_attach_args *ma;
157 struct mii_data *mii;
158 const char *sep = "";
159 struct bge_softc *bge_sc;
160 int fast_ether_only = FALSE;
161
162 sc = device_get_softc(dev);
163 ma = device_get_ivars(dev);
164 sc->mii_dev = device_get_parent(dev);
165 mii = device_get_softc(sc->mii_dev);
166 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
167
168 sc->mii_inst = mii->mii_instance;
169 sc->mii_phy = ma->mii_phyno;
170 sc->mii_service = brgphy_service;
171 sc->mii_pdata = mii;
172
173 sc->mii_flags |= MIIF_NOISOLATE;
174 mii->mii_instance++;
175
176#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
177#define PRINT(s) printf("%s%s", sep, s); sep = ", "
178
179 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
180 BMCR_ISO);
181#if 0
182 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
183 BMCR_LOOP|BMCR_S100);
184#endif
185
186 brgphy_mii_model = MII_MODEL(ma->mii_id2);
187 brgphy_reset(sc);
188
189
190 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
191 sc->mii_capabilities &= ~BMSR_ANEG;
192 device_printf(dev, " ");
193 mii_add_media(sc);
194
195 /* The 590x chips are 10/100 only. */
196
197 bge_sc = mii->mii_ifp->if_softc;
198
199 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 &&
200 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
201 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
202 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2))
203 fast_ether_only = TRUE;
204
205 if (fast_ether_only == FALSE) {
206 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
207 sc->mii_inst), BRGPHY_BMCR_FDX);
208 PRINT(", 1000baseTX");
209 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
210 IFM_FDX, sc->mii_inst), 0);
211 PRINT("1000baseTX-FDX");
212 }
213
214 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
215 PRINT("auto");
216
217 printf("\n");
218#undef ADD
219#undef PRINT
220
221 MIIBUS_MEDIAINIT(sc->mii_dev);
222 return(0);
223}
224
225static int
226brgphy_service(sc, mii, cmd)
227 struct mii_softc *sc;
228 struct mii_data *mii;
229 int cmd;
230{
231 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
232 int reg, speed, gig;
233
234 switch (cmd) {
235 case MII_POLLSTAT:
236 /*
237 * If we're not polling our PHY instance, just return.
238 */
239 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
240 return (0);
241 break;
242
243 case MII_MEDIACHG:
244 /*
245 * If the media indicates a different PHY instance,
246 * isolate ourselves.
247 */
248 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
249 reg = PHY_READ(sc, MII_BMCR);
250 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
251 return (0);
252 }
253
254 /*
255 * If the interface is not up, don't do anything.
256 */
257 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
258 break;
259
260 brgphy_reset(sc); /* XXX hardware bug work-around */
261
262 switch (IFM_SUBTYPE(ife->ifm_media)) {
263 case IFM_AUTO:
264#ifdef foo
265 /*
266 * If we're already in auto mode, just return.
267 */
268 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
269 return (0);
270#endif
271 (void) brgphy_mii_phy_auto(sc);
272 break;
273 case IFM_1000_T:
274 speed = BRGPHY_S1000;
275 goto setit;
276 case IFM_100_TX:
277 speed = BRGPHY_S100;
278 goto setit;
279 case IFM_10_T:
280 speed = BRGPHY_S10;
281setit:
282 brgphy_loop(sc);
283 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
284 speed |= BRGPHY_BMCR_FDX;
285 gig = BRGPHY_1000CTL_AFD;
286 } else {
287 gig = BRGPHY_1000CTL_AHD;
288 }
289
290 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
291 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
292 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
293
294 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
295 break;
296
297 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
298 PHY_WRITE(sc, BRGPHY_MII_BMCR,
299 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
300
301 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701)
302 break;
303
304 /*
305 * When settning the link manually, one side must
306 * be the master and the other the slave. However
307 * ifmedia doesn't give us a good way to specify
308 * this, so we fake it by using one of the LINK
309 * flags. If LINK0 is set, we program the PHY to
310 * be a master, otherwise it's a slave.
311 */
312 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
313 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
314 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
315 } else {
316 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
317 gig|BRGPHY_1000CTL_MSE);
318 }
319 break;
320#ifdef foo
321 case IFM_NONE:
322 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
323 break;
324#endif
325 case IFM_100_T4:
326 default:
327 return (EINVAL);
328 }
329 break;
330
331 case MII_TICK:
332 /*
333 * If we're not currently selected, just return.
334 */
335 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
336 return (0);
337
338 /*
339 * Is the interface even up?
340 */
341 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
342 return (0);
343
344 /*
345 * Only used for autonegotiation.
346 */
347 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
348 break;
349
350 /*
351 * Check to see if we have link. If we do, we don't
352 * need to restart the autonegotiation process. Read
353 * the BMSR twice in case it's latched.
354 */
355 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
356 if (reg & BRGPHY_AUXSTS_LINK)
357 break;
358
359 /*
360 * Only retry autonegotiation every 5 seconds.
361 */
362 if (++sc->mii_ticks <= 5)
363 break;
364
365 sc->mii_ticks = 0;
366 brgphy_mii_phy_auto(sc);
367 return (0);
368 }
369
370 /* Update the media status. */
371 brgphy_status(sc);
372
373 /*
374 * Callback if something changed. Note that we need to poke
375 * the DSP on the Broadcom PHYs if the media changes.
376 *
377 */
378 if (sc->mii_media_active != mii->mii_media_active ||
379 sc->mii_media_status != mii->mii_media_status ||
380 cmd == MII_MEDIACHG) {
381 switch (brgphy_mii_model) {
382 case MII_MODEL_xxBROADCOM_BCM5401:
383 bcm5401_load_dspcode(sc);
384 break;
385 case MII_MODEL_xxBROADCOM_BCM5411:
386 bcm5411_load_dspcode(sc);
387 break;
388 }
389 }
390 mii_phy_update(sc, cmd);
391 return (0);
392}
393
394static void
395brgphy_status(sc)
396 struct mii_softc *sc;
397{
398 struct mii_data *mii = sc->mii_pdata;
399 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
400 int bmsr, bmcr;
401
402 mii->mii_media_status = IFM_AVALID;
403 mii->mii_media_active = IFM_ETHER;
404
405 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
406 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK)
407 mii->mii_media_status |= IFM_ACTIVE;
408
409 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
410
411 if (bmcr & BRGPHY_BMCR_LOOP)
412 mii->mii_media_active |= IFM_LOOP;
413
414 if (bmcr & BRGPHY_BMCR_AUTOEN) {
415 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
416 /* Erg, still trying, I guess... */
417 mii->mii_media_active |= IFM_NONE;
418 return;
419 }
420
421 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
422 BRGPHY_AUXSTS_AN_RES) {
423 case BRGPHY_RES_1000FD:
424 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
425 break;
426 case BRGPHY_RES_1000HD:
427 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
428 break;
429 case BRGPHY_RES_100FD:
430 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
431 break;
432 case BRGPHY_RES_100T4:
433 mii->mii_media_active |= IFM_100_T4;
434 break;
435 case BRGPHY_RES_100HD:
436 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
437 break;
438 case BRGPHY_RES_10FD:
439 mii->mii_media_active |= IFM_10_T | IFM_FDX;
440 break;
441 case BRGPHY_RES_10HD:
442 mii->mii_media_active |= IFM_10_T | IFM_HDX;
443 break;
444 default:
445 mii->mii_media_active |= IFM_NONE;
446 break;
447 }
448 return;
449 }
450
451 mii->mii_media_active = ife->ifm_media;
452
453 return;
454}
455
456
457static int
458brgphy_mii_phy_auto(mii)
459 struct mii_softc *mii;
460{
461 int ktcr = 0;
462
463 brgphy_loop(mii);
464 brgphy_reset(mii);
465 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
466 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701)
467 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
468 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr);
469 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL);
470 DELAY(1000);
471 PHY_WRITE(mii, BRGPHY_MII_ANAR,
472 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
473 DELAY(1000);
474 PHY_WRITE(mii, BRGPHY_MII_BMCR,
475 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
476 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00);
477 return (EJUSTRETURN);
478}
479
480static void
481brgphy_loop(struct mii_softc *sc)
482{
483 u_int32_t bmsr;
484 int i;
485
486 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
487 for (i = 0; i < 15000; i++) {
488 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
489 if (!(bmsr & BRGPHY_BMSR_LINK)) {
490#if 0
491 device_printf(sc->mii_dev, "looped %d\n", i);
492#endif
493 break;
494 }
495 DELAY(10);
496 }
497}
498
499/* Turn off tap power management on 5401. */
500static void
501bcm5401_load_dspcode(struct mii_softc *sc)
502{
503 static const struct {
504 int reg;
505 uint16_t val;
506 } dspcode[] = {
507 { BRGPHY_MII_AUXCTL, 0x0c20 },
508 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
509 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
510 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
511 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
512 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
513 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
514 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
515 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
516 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
517 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
518 { 0, 0 },
519 };
520 int i;
521
522 for (i = 0; dspcode[i].reg != 0; i++)
523 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
524 DELAY(40);
525}
526
527static void
528bcm5411_load_dspcode(struct mii_softc *sc)
529{
530 static const struct {
531 int reg;
532 uint16_t val;
533 } dspcode[] = {
534 { 0x1c, 0x8c23 },
535 { 0x1c, 0x8ca3 },
536 { 0x1c, 0x8c23 },
537 { 0, 0 },
538 };
539 int i;
540
541 for (i = 0; dspcode[i].reg != 0; i++)
542 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
543}
544
545static void
546bcm5703_load_dspcode(struct mii_softc *sc)
547{
548 static const struct {
549 int reg;
550 uint16_t val;
551 } dspcode[] = {
552 { BRGPHY_MII_AUXCTL, 0x0c00 },
553 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
554 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
555 { 0, 0 },
556 };
557 int i;
558
559 for (i = 0; dspcode[i].reg != 0; i++)
560 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
561}
562
563static void
564bcm5704_load_dspcode(struct mii_softc *sc)
565{
566 static const struct {
567 int reg;
568 u_int16_t val;
569 } dspcode[] = {
570 { 0x1c, 0x8d68 },
571 { 0x1c, 0x8d68 },
572 { 0, 0 },
573 };
574 int i;
575
576 for (i = 0; dspcode[i].reg != 0; i++)
577 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
578}
579
580static void
581brgphy_reset(struct mii_softc *sc)
582{
583 u_int32_t val;
584 struct ifnet *ifp;
585 struct bge_softc *bge_sc;
586
587 mii_phy_reset(sc);
588
589 switch (brgphy_mii_model) {
590 case MII_MODEL_xxBROADCOM_BCM5401:
591 bcm5401_load_dspcode(sc);
592 break;
593 case MII_MODEL_xxBROADCOM_BCM5411:
594 bcm5411_load_dspcode(sc);
595 break;
596 case MII_MODEL_xxBROADCOM_BCM5703:
597 bcm5703_load_dspcode(sc);
598 break;
599 case MII_MODEL_xxBROADCOM_BCM5704:
600 bcm5704_load_dspcode(sc);
601 break;
602 }
603
604 ifp = sc->mii_pdata->mii_ifp;
605 bge_sc = ifp->if_softc;
606
607 /*
608 * Don't enable Ethernet@WireSpeed for the 5700 or the
609 * 5705 A1 and A2 chips. Make sure we only do this test
610 * on "bge" NICs, since other drivers may use this same
611 * PHY subdriver.
612 */
613 if (strcmp(ifp->if_dname, "bge") == 0 &&
614 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
615 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 ||
616 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2))
617 return;
618
619 /* Enable Ethernet@WireSpeed. */
620 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
621 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
622 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
623
624 /* Enable Link LED on Dell boxes */
625 if (bge_sc->bge_no_3_led) {
626 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
627 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
628 & ~BRGPHY_PHY_EXTCTL_3_LED);
629 }
630}
| 45#include <sys/socket.h>
46#include <sys/bus.h>
47
48#include <machine/clock.h>
49
50#include <net/if.h>
51#include <net/if_media.h>
52
53#include <dev/mii/mii.h>
54#include <dev/mii/miivar.h>
55#include "miidevs.h"
56
57#include <dev/mii/brgphyreg.h>
58#include <net/if_arp.h>
59#include <machine/bus.h>
60#include <dev/bge/if_bgereg.h>
61
62#include <dev/pci/pcireg.h>
63#include <dev/pci/pcivar.h>
64
65#include "miibus_if.h"
66
67static int brgphy_probe(device_t);
68static int brgphy_attach(device_t);
69
70static device_method_t brgphy_methods[] = {
71 /* device interface */
72 DEVMETHOD(device_probe, brgphy_probe),
73 DEVMETHOD(device_attach, brgphy_attach),
74 DEVMETHOD(device_detach, mii_phy_detach),
75 DEVMETHOD(device_shutdown, bus_generic_shutdown),
76 { 0, 0 }
77};
78
79static devclass_t brgphy_devclass;
80
81static driver_t brgphy_driver = {
82 "brgphy",
83 brgphy_methods,
84 sizeof(struct mii_softc)
85};
86
87DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
88
89static int brgphy_service(struct mii_softc *, struct mii_data *, int);
90static void brgphy_status(struct mii_softc *);
91static int brgphy_mii_phy_auto(struct mii_softc *);
92static void brgphy_reset(struct mii_softc *);
93static void brgphy_loop(struct mii_softc *);
94static void bcm5401_load_dspcode(struct mii_softc *);
95static void bcm5411_load_dspcode(struct mii_softc *);
96static void bcm5703_load_dspcode(struct mii_softc *);
97static int brgphy_mii_model;
98
99static int
100brgphy_probe(dev)
101 device_t dev;
102{
103 struct mii_attach_args *ma;
104
105 ma = device_get_ivars(dev);
106
107 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
108 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) {
109 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400);
110 return(0);
111 }
112
113 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
114 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) {
115 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401);
116 return(0);
117 }
118
119 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
120 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) {
121 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411);
122 return(0);
123 }
124
125 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
126 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) {
127 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701);
128 return(0);
129 }
130
131 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
132 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) {
133 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703);
134 return(0);
135 }
136
137 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
138 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) {
139 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704);
140 return(0);
141 }
142
143 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
144 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) {
145 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705);
146 return(0);
147 }
148
149 return(ENXIO);
150}
151
152static int
153brgphy_attach(dev)
154 device_t dev;
155{
156 struct mii_softc *sc;
157 struct mii_attach_args *ma;
158 struct mii_data *mii;
159 const char *sep = "";
160 struct bge_softc *bge_sc;
161 int fast_ether_only = FALSE;
162
163 sc = device_get_softc(dev);
164 ma = device_get_ivars(dev);
165 sc->mii_dev = device_get_parent(dev);
166 mii = device_get_softc(sc->mii_dev);
167 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
168
169 sc->mii_inst = mii->mii_instance;
170 sc->mii_phy = ma->mii_phyno;
171 sc->mii_service = brgphy_service;
172 sc->mii_pdata = mii;
173
174 sc->mii_flags |= MIIF_NOISOLATE;
175 mii->mii_instance++;
176
177#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
178#define PRINT(s) printf("%s%s", sep, s); sep = ", "
179
180 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
181 BMCR_ISO);
182#if 0
183 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
184 BMCR_LOOP|BMCR_S100);
185#endif
186
187 brgphy_mii_model = MII_MODEL(ma->mii_id2);
188 brgphy_reset(sc);
189
190
191 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
192 sc->mii_capabilities &= ~BMSR_ANEG;
193 device_printf(dev, " ");
194 mii_add_media(sc);
195
196 /* The 590x chips are 10/100 only. */
197
198 bge_sc = mii->mii_ifp->if_softc;
199
200 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 &&
201 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
202 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
203 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2))
204 fast_ether_only = TRUE;
205
206 if (fast_ether_only == FALSE) {
207 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
208 sc->mii_inst), BRGPHY_BMCR_FDX);
209 PRINT(", 1000baseTX");
210 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
211 IFM_FDX, sc->mii_inst), 0);
212 PRINT("1000baseTX-FDX");
213 }
214
215 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
216 PRINT("auto");
217
218 printf("\n");
219#undef ADD
220#undef PRINT
221
222 MIIBUS_MEDIAINIT(sc->mii_dev);
223 return(0);
224}
225
226static int
227brgphy_service(sc, mii, cmd)
228 struct mii_softc *sc;
229 struct mii_data *mii;
230 int cmd;
231{
232 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
233 int reg, speed, gig;
234
235 switch (cmd) {
236 case MII_POLLSTAT:
237 /*
238 * If we're not polling our PHY instance, just return.
239 */
240 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
241 return (0);
242 break;
243
244 case MII_MEDIACHG:
245 /*
246 * If the media indicates a different PHY instance,
247 * isolate ourselves.
248 */
249 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
250 reg = PHY_READ(sc, MII_BMCR);
251 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
252 return (0);
253 }
254
255 /*
256 * If the interface is not up, don't do anything.
257 */
258 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
259 break;
260
261 brgphy_reset(sc); /* XXX hardware bug work-around */
262
263 switch (IFM_SUBTYPE(ife->ifm_media)) {
264 case IFM_AUTO:
265#ifdef foo
266 /*
267 * If we're already in auto mode, just return.
268 */
269 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
270 return (0);
271#endif
272 (void) brgphy_mii_phy_auto(sc);
273 break;
274 case IFM_1000_T:
275 speed = BRGPHY_S1000;
276 goto setit;
277 case IFM_100_TX:
278 speed = BRGPHY_S100;
279 goto setit;
280 case IFM_10_T:
281 speed = BRGPHY_S10;
282setit:
283 brgphy_loop(sc);
284 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
285 speed |= BRGPHY_BMCR_FDX;
286 gig = BRGPHY_1000CTL_AFD;
287 } else {
288 gig = BRGPHY_1000CTL_AHD;
289 }
290
291 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
292 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
293 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
294
295 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
296 break;
297
298 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
299 PHY_WRITE(sc, BRGPHY_MII_BMCR,
300 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
301
302 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701)
303 break;
304
305 /*
306 * When settning the link manually, one side must
307 * be the master and the other the slave. However
308 * ifmedia doesn't give us a good way to specify
309 * this, so we fake it by using one of the LINK
310 * flags. If LINK0 is set, we program the PHY to
311 * be a master, otherwise it's a slave.
312 */
313 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
314 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
315 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
316 } else {
317 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
318 gig|BRGPHY_1000CTL_MSE);
319 }
320 break;
321#ifdef foo
322 case IFM_NONE:
323 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
324 break;
325#endif
326 case IFM_100_T4:
327 default:
328 return (EINVAL);
329 }
330 break;
331
332 case MII_TICK:
333 /*
334 * If we're not currently selected, just return.
335 */
336 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
337 return (0);
338
339 /*
340 * Is the interface even up?
341 */
342 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
343 return (0);
344
345 /*
346 * Only used for autonegotiation.
347 */
348 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
349 break;
350
351 /*
352 * Check to see if we have link. If we do, we don't
353 * need to restart the autonegotiation process. Read
354 * the BMSR twice in case it's latched.
355 */
356 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
357 if (reg & BRGPHY_AUXSTS_LINK)
358 break;
359
360 /*
361 * Only retry autonegotiation every 5 seconds.
362 */
363 if (++sc->mii_ticks <= 5)
364 break;
365
366 sc->mii_ticks = 0;
367 brgphy_mii_phy_auto(sc);
368 return (0);
369 }
370
371 /* Update the media status. */
372 brgphy_status(sc);
373
374 /*
375 * Callback if something changed. Note that we need to poke
376 * the DSP on the Broadcom PHYs if the media changes.
377 *
378 */
379 if (sc->mii_media_active != mii->mii_media_active ||
380 sc->mii_media_status != mii->mii_media_status ||
381 cmd == MII_MEDIACHG) {
382 switch (brgphy_mii_model) {
383 case MII_MODEL_xxBROADCOM_BCM5401:
384 bcm5401_load_dspcode(sc);
385 break;
386 case MII_MODEL_xxBROADCOM_BCM5411:
387 bcm5411_load_dspcode(sc);
388 break;
389 }
390 }
391 mii_phy_update(sc, cmd);
392 return (0);
393}
394
395static void
396brgphy_status(sc)
397 struct mii_softc *sc;
398{
399 struct mii_data *mii = sc->mii_pdata;
400 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
401 int bmsr, bmcr;
402
403 mii->mii_media_status = IFM_AVALID;
404 mii->mii_media_active = IFM_ETHER;
405
406 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
407 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK)
408 mii->mii_media_status |= IFM_ACTIVE;
409
410 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
411
412 if (bmcr & BRGPHY_BMCR_LOOP)
413 mii->mii_media_active |= IFM_LOOP;
414
415 if (bmcr & BRGPHY_BMCR_AUTOEN) {
416 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
417 /* Erg, still trying, I guess... */
418 mii->mii_media_active |= IFM_NONE;
419 return;
420 }
421
422 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
423 BRGPHY_AUXSTS_AN_RES) {
424 case BRGPHY_RES_1000FD:
425 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
426 break;
427 case BRGPHY_RES_1000HD:
428 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
429 break;
430 case BRGPHY_RES_100FD:
431 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
432 break;
433 case BRGPHY_RES_100T4:
434 mii->mii_media_active |= IFM_100_T4;
435 break;
436 case BRGPHY_RES_100HD:
437 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
438 break;
439 case BRGPHY_RES_10FD:
440 mii->mii_media_active |= IFM_10_T | IFM_FDX;
441 break;
442 case BRGPHY_RES_10HD:
443 mii->mii_media_active |= IFM_10_T | IFM_HDX;
444 break;
445 default:
446 mii->mii_media_active |= IFM_NONE;
447 break;
448 }
449 return;
450 }
451
452 mii->mii_media_active = ife->ifm_media;
453
454 return;
455}
456
457
458static int
459brgphy_mii_phy_auto(mii)
460 struct mii_softc *mii;
461{
462 int ktcr = 0;
463
464 brgphy_loop(mii);
465 brgphy_reset(mii);
466 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
467 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701)
468 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
469 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr);
470 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL);
471 DELAY(1000);
472 PHY_WRITE(mii, BRGPHY_MII_ANAR,
473 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
474 DELAY(1000);
475 PHY_WRITE(mii, BRGPHY_MII_BMCR,
476 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
477 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00);
478 return (EJUSTRETURN);
479}
480
481static void
482brgphy_loop(struct mii_softc *sc)
483{
484 u_int32_t bmsr;
485 int i;
486
487 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
488 for (i = 0; i < 15000; i++) {
489 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
490 if (!(bmsr & BRGPHY_BMSR_LINK)) {
491#if 0
492 device_printf(sc->mii_dev, "looped %d\n", i);
493#endif
494 break;
495 }
496 DELAY(10);
497 }
498}
499
500/* Turn off tap power management on 5401. */
501static void
502bcm5401_load_dspcode(struct mii_softc *sc)
503{
504 static const struct {
505 int reg;
506 uint16_t val;
507 } dspcode[] = {
508 { BRGPHY_MII_AUXCTL, 0x0c20 },
509 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
510 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
511 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
512 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
513 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
514 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
515 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
516 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
517 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
518 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
519 { 0, 0 },
520 };
521 int i;
522
523 for (i = 0; dspcode[i].reg != 0; i++)
524 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
525 DELAY(40);
526}
527
528static void
529bcm5411_load_dspcode(struct mii_softc *sc)
530{
531 static const struct {
532 int reg;
533 uint16_t val;
534 } dspcode[] = {
535 { 0x1c, 0x8c23 },
536 { 0x1c, 0x8ca3 },
537 { 0x1c, 0x8c23 },
538 { 0, 0 },
539 };
540 int i;
541
542 for (i = 0; dspcode[i].reg != 0; i++)
543 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
544}
545
546static void
547bcm5703_load_dspcode(struct mii_softc *sc)
548{
549 static const struct {
550 int reg;
551 uint16_t val;
552 } dspcode[] = {
553 { BRGPHY_MII_AUXCTL, 0x0c00 },
554 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
555 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
556 { 0, 0 },
557 };
558 int i;
559
560 for (i = 0; dspcode[i].reg != 0; i++)
561 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
562}
563
564static void
565bcm5704_load_dspcode(struct mii_softc *sc)
566{
567 static const struct {
568 int reg;
569 u_int16_t val;
570 } dspcode[] = {
571 { 0x1c, 0x8d68 },
572 { 0x1c, 0x8d68 },
573 { 0, 0 },
574 };
575 int i;
576
577 for (i = 0; dspcode[i].reg != 0; i++)
578 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
579}
580
581static void
582brgphy_reset(struct mii_softc *sc)
583{
584 u_int32_t val;
585 struct ifnet *ifp;
586 struct bge_softc *bge_sc;
587
588 mii_phy_reset(sc);
589
590 switch (brgphy_mii_model) {
591 case MII_MODEL_xxBROADCOM_BCM5401:
592 bcm5401_load_dspcode(sc);
593 break;
594 case MII_MODEL_xxBROADCOM_BCM5411:
595 bcm5411_load_dspcode(sc);
596 break;
597 case MII_MODEL_xxBROADCOM_BCM5703:
598 bcm5703_load_dspcode(sc);
599 break;
600 case MII_MODEL_xxBROADCOM_BCM5704:
601 bcm5704_load_dspcode(sc);
602 break;
603 }
604
605 ifp = sc->mii_pdata->mii_ifp;
606 bge_sc = ifp->if_softc;
607
608 /*
609 * Don't enable Ethernet@WireSpeed for the 5700 or the
610 * 5705 A1 and A2 chips. Make sure we only do this test
611 * on "bge" NICs, since other drivers may use this same
612 * PHY subdriver.
613 */
614 if (strcmp(ifp->if_dname, "bge") == 0 &&
615 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
616 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 ||
617 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2))
618 return;
619
620 /* Enable Ethernet@WireSpeed. */
621 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
622 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
623 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
624
625 /* Enable Link LED on Dell boxes */
626 if (bge_sc->bge_no_3_led) {
627 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
628 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
629 & ~BRGPHY_PHY_EXTCTL_3_LED);
630 }
631}
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