1/*-
2 * Copyright (c) 2000
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 166680 2007-02-13 00:34:32Z jkim $");
35
36/*
37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/bus.h>
46
47#include <net/if.h>
48#include <net/ethernet.h>
49#include <net/if_media.h>
50
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53#include "miidevs.h"
54
55#include <dev/mii/brgphyreg.h>
56#include <net/if_arp.h>
57#include <machine/bus.h>
58#include <dev/bge/if_bgereg.h>
59#include <dev/bce/if_bcereg.h>
60
61#include <dev/pci/pcireg.h>
62#include <dev/pci/pcivar.h>
63
64#include "miibus_if.h"
65
66static int brgphy_probe(device_t);
67static int brgphy_attach(device_t);
68
69struct brgphy_softc {
70 struct mii_softc mii_sc;
71 int mii_model;
72 int mii_rev;
73};
74
75static device_method_t brgphy_methods[] = {
76 /* device interface */
77 DEVMETHOD(device_probe, brgphy_probe),
78 DEVMETHOD(device_attach, brgphy_attach),
79 DEVMETHOD(device_detach, mii_phy_detach),
80 DEVMETHOD(device_shutdown, bus_generic_shutdown),
81 { 0, 0 }
82};
83
84static devclass_t brgphy_devclass;
85
86static driver_t brgphy_driver = {
87 "brgphy",
88 brgphy_methods,
89 sizeof(struct brgphy_softc)
90};
91
92DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
93
94static int brgphy_service(struct mii_softc *, struct mii_data *, int);
95static void brgphy_setmedia(struct mii_softc *, int, int);
96static void brgphy_status(struct mii_softc *);
97static int brgphy_mii_phy_auto(struct mii_softc *);
98static void brgphy_reset(struct mii_softc *);
99static void brgphy_loop(struct mii_softc *);
100static void bcm5401_load_dspcode(struct mii_softc *);
101static void bcm5411_load_dspcode(struct mii_softc *);
102static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
103static void brgphy_fixup_adc_bug(struct mii_softc *);
104static void brgphy_fixup_adjust_trim(struct mii_softc *);
105static void brgphy_fixup_ber_bug(struct mii_softc *);
106static void brgphy_fixup_crc_bug(struct mii_softc *);
107static void brgphy_fixup_jitter_bug(struct mii_softc *);
108static void brgphy_ethernet_wirespeed(struct mii_softc *);
109static void brgphy_jumbo_settings(struct mii_softc *, u_long);
110
111static const struct mii_phydesc brgphys[] = {
112 MII_PHY_DESC(xxBROADCOM, BCM5400),
113 MII_PHY_DESC(xxBROADCOM, BCM5401),
114 MII_PHY_DESC(xxBROADCOM, BCM5411),
115 MII_PHY_DESC(xxBROADCOM, BCM5701),
116 MII_PHY_DESC(xxBROADCOM, BCM5703),
117 MII_PHY_DESC(xxBROADCOM, BCM5704),
118 MII_PHY_DESC(xxBROADCOM, BCM5705),
119 MII_PHY_DESC(xxBROADCOM, BCM5706C),
120 MII_PHY_DESC(xxBROADCOM, BCM5714),
121 MII_PHY_DESC(xxBROADCOM, BCM5750),
122 MII_PHY_DESC(xxBROADCOM, BCM5752),
123 MII_PHY_DESC(xxBROADCOM, BCM5754),
124 MII_PHY_DESC(xxBROADCOM, BCM5780),
125 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
126 MII_PHY_END
127};
128
129static int
130brgphy_probe(device_t dev)
131{
132
133 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
134}
135
136static int
137brgphy_attach(device_t dev)
138{
139 struct brgphy_softc *bsc;
140 struct mii_softc *sc;
141 struct mii_attach_args *ma;
142 struct mii_data *mii;
143 const char *sep = "";
144 struct bge_softc *bge_sc = NULL;
145 struct bce_softc *bce_sc = NULL;
146 int fast_ether_only = FALSE;
147
148 bsc = device_get_softc(dev);
149 sc = &bsc->mii_sc;
150 ma = device_get_ivars(dev);
151 sc->mii_dev = device_get_parent(dev);
152 mii = device_get_softc(sc->mii_dev);
153 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
154
155 sc->mii_inst = mii->mii_instance;
156 sc->mii_phy = ma->mii_phyno;
157 sc->mii_service = brgphy_service;
158 sc->mii_pdata = mii;
159
160 sc->mii_flags |= MIIF_NOISOLATE;
161 mii->mii_instance++;
162
163#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
164#define PRINT(s) printf("%s%s", sep, s); sep = ", "
165
166 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
167 BMCR_ISO);
168#if 0
169 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
170 BMCR_LOOP | BMCR_S100);
171#endif
172
173 bsc->mii_model = MII_MODEL(ma->mii_id2);
174 bsc->mii_rev = MII_REV(ma->mii_id2);
175 brgphy_reset(sc);
176
177 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
178 sc->mii_capabilities &= ~BMSR_ANEG;
179 device_printf(dev, " ");
180 mii_add_media(sc);
181
182 /* Find the driver associated with this PHY. */
183 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) {
184 bge_sc = mii->mii_ifp->if_softc;
185 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) {
186 bce_sc = mii->mii_ifp->if_softc;
187 }
188
189 /* The 590x chips are 10/100 only. */
190 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 &&
191 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
192 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
193 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2))
194 fast_ether_only = TRUE;
195
196 if (fast_ether_only == FALSE) {
197 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
198 sc->mii_inst), BRGPHY_BMCR_FDX);
199 PRINT(", 1000baseTX");
200 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
201 IFM_FDX, sc->mii_inst), 0);
202 PRINT("1000baseTX-FDX");
203 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
204 } else
205 sc->mii_anegticks = MII_ANEGTICKS;
206
207 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
208 PRINT("auto");
209
210 printf("\n");
211#undef ADD
212#undef PRINT
213
214 MIIBUS_MEDIAINIT(sc->mii_dev);
215 return (0);
216}
217
218static int
219brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
220{
221 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
222 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
223
224 switch (cmd) {
225 case MII_POLLSTAT:
226 /* If we're not polling our PHY instance, just return. */
227 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
228 return (0);
229 break;
230 case MII_MEDIACHG:
231 /*
232 * If the media indicates a different PHY instance,
233 * isolate ourselves.
234 */
235 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
236 PHY_WRITE(sc, MII_BMCR,
237 PHY_READ(sc, MII_BMCR) | BMCR_ISO);
238 return (0);
239 }
240
241 /* If the interface is not up, don't do anything. */
242 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
243 break;
244
245 brgphy_reset(sc); /* XXX hardware bug work-around */
246
247 switch (IFM_SUBTYPE(ife->ifm_media)) {
248 case IFM_AUTO:
249#ifdef foo
250 /* If we're already in auto mode, just return. */
251 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
252 return (0);
253#endif
254 (void)brgphy_mii_phy_auto(sc);
255 break;
256 case IFM_1000_T:
257 case IFM_100_TX:
258 case IFM_10_T:
259 brgphy_setmedia(sc, ife->ifm_media,
260 mii->mii_ifp->if_flags & IFF_LINK0);
261 break;
262#ifdef foo
263 case IFM_NONE:
264 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
265 break;
266#endif
267 case IFM_100_T4:
268 default:
269 return (EINVAL);
270 }
271 break;
272 case MII_TICK:
273 /* If we're not currently selected, just return. */
274 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
275 return (0);
276
277 /* Is the interface even up? */
278 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
279 return (0);
280
281 /* Only used for autonegotiation. */
282 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
283 sc->mii_ticks = 0; /* Reset autoneg timer. */
284 break;
285 }
286
287 /*
288 * Check to see if we have link. If we do, we don't
289 * need to restart the autonegotiation process.
290 */
291 if (PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK) {
292 sc->mii_ticks = 0; /* Reset autoneg timer. */
293 break;
294 }
295
296 /* Announce link loss right after it happens. */
297 if (sc->mii_ticks++ == 0)
298 break;
299
300 /* Only retry autonegotiation every mii_anegticks seconds. */
301 if (sc->mii_ticks <= sc->mii_anegticks)
302 return (0);
303
304 sc->mii_ticks = 0;
305 (void)brgphy_mii_phy_auto(sc);
306 break;
307 }
308
309 /* Update the media status. */
310 brgphy_status(sc);
311
312 /*
313 * Callback if something changed. Note that we need to poke
314 * the DSP on the Broadcom PHYs if the media changes.
315 */
316 if (sc->mii_media_active != mii->mii_media_active ||
317 sc->mii_media_status != mii->mii_media_status ||
318 cmd == MII_MEDIACHG) {
319 switch (bsc->mii_model) {
320 case MII_MODEL_xxBROADCOM_BCM5400:
321 bcm5401_load_dspcode(sc);
322 break;
323 case MII_MODEL_xxBROADCOM_BCM5401:
324 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
325 bcm5401_load_dspcode(sc);
326 break;
327 case MII_MODEL_xxBROADCOM_BCM5411:
328 bcm5411_load_dspcode(sc);
329 break;
330 }
331 }
332 mii_phy_update(sc, cmd);
333 return (0);
334}
335
336static void
337brgphy_setmedia(struct mii_softc *sc, int media, int master)
338{
339 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
340 int bmcr, gig;
341
342 switch (IFM_SUBTYPE(media)) {
343 case IFM_1000_T:
344 bmcr = BRGPHY_S1000;
345 break;
346 case IFM_100_TX:
347 bmcr = BRGPHY_S100;
348 break;
349 case IFM_10_T:
350 default:
351 bmcr = BRGPHY_S10;
352 break;
353 }
354 if ((media & IFM_GMASK) == IFM_FDX) {
355 bmcr |= BRGPHY_BMCR_FDX;
356 gig = BRGPHY_1000CTL_AFD;
357 } else {
358 gig = BRGPHY_1000CTL_AHD;
359 }
360
361 brgphy_loop(sc);
362 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
363 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
364 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
365
366 if (IFM_SUBTYPE(media) != IFM_1000_T)
367 return;
368
369 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
370 PHY_WRITE(sc, BRGPHY_MII_BMCR,
371 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
372
373 if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
374 return;
375
376 /*
377 * When setting the link manually, one side must be the master and
378 * the other the slave. However ifmedia doesn't give us a good way
379 * to specify this, so we fake it by using one of the LINK flags.
380 * If LINK0 is set, we program the PHY to be a master, otherwise
381 * it's a slave.
382 */
383 if (master) {
384 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
385 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC);
386 } else {
387 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
388 gig | BRGPHY_1000CTL_MSE);
389 }
390}
391
392static void
393brgphy_status(struct mii_softc *sc)
394{
395 struct mii_data *mii = sc->mii_pdata;
396 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
397 int bmcr, bmsr;
398
399 mii->mii_media_status = IFM_AVALID;
400 mii->mii_media_active = IFM_ETHER;
401
402 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
403 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
404
405 if (bmsr & BRGPHY_BMSR_LINK)
406 mii->mii_media_status |= IFM_ACTIVE;
407
408 if (bmcr & BRGPHY_BMCR_LOOP)
409 mii->mii_media_active |= IFM_LOOP;
410
411 if (bmcr & BRGPHY_BMCR_AUTOEN) {
412 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
413 /* Erg, still trying, I guess... */
414 mii->mii_media_active |= IFM_NONE;
415 return;
416 }
417 }
418
419 if (bmsr & BRGPHY_BMSR_LINK) {
420 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
421 BRGPHY_AUXSTS_AN_RES) {
422 case BRGPHY_RES_1000FD:
423 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
424 break;
425 case BRGPHY_RES_1000HD:
426 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
427 break;
428 case BRGPHY_RES_100FD:
429 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
430 break;
431 case BRGPHY_RES_100T4:
432 mii->mii_media_active |= IFM_100_T4;
433 break;
434 case BRGPHY_RES_100HD:
435 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
436 break;
437 case BRGPHY_RES_10FD:
438 mii->mii_media_active |= IFM_10_T | IFM_FDX;
439 break;
440 case BRGPHY_RES_10HD:
441 mii->mii_media_active |= IFM_10_T | IFM_HDX;
442 break;
443 default:
444 mii->mii_media_active |= IFM_NONE;
445 break;
446 }
447 } else
448 mii->mii_media_active = ife->ifm_media;
449}
450
451static int
452brgphy_mii_phy_auto(struct mii_softc *sc)
453{
454 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
455 int ktcr = 0;
456
457 brgphy_loop(sc);
458 brgphy_reset(sc);
459 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
460 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
461 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
462 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
463 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
464 DELAY(1000);
465 PHY_WRITE(sc, BRGPHY_MII_ANAR,
466 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
467 DELAY(1000);
468 PHY_WRITE(sc, BRGPHY_MII_BMCR,
469 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
470 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
471 return (EJUSTRETURN);
472}
473
474static void
475brgphy_loop(struct mii_softc *sc)
476{
477 int i;
478
479 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
480 for (i = 0; i < 15000; i++) {
481 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) {
482#if 0
483 device_printf(sc->mii_dev, "looped %d\n", i);
484#endif
485 break;
486 }
487 DELAY(10);
488 }
489}
490
491/* Turn off tap power management on 5401. */
492static void
493bcm5401_load_dspcode(struct mii_softc *sc)
494{
495 static const struct {
496 int reg;
497 uint16_t val;
498 } dspcode[] = {
499 { BRGPHY_MII_AUXCTL, 0x0c20 },
500 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
501 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
502 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
503 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
504 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
505 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
506 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
507 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
508 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
509 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
510 { 0, 0 },
511 };
512 int i;
513
514 for (i = 0; dspcode[i].reg != 0; i++)
515 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
516 DELAY(40);
517}
518
519static void
520bcm5411_load_dspcode(struct mii_softc *sc)
521{
522 static const struct {
523 int reg;
524 uint16_t val;
525 } dspcode[] = {
526 { 0x1c, 0x8c23 },
527 { 0x1c, 0x8ca3 },
528 { 0x1c, 0x8c23 },
529 { 0, 0 },
530 };
531 int i;
532
533 for (i = 0; dspcode[i].reg != 0; i++)
534 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
535}
536
537static void
538brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
539{
540 static const struct {
541 int reg;
542 uint16_t val;
543 } dspcode[] = {
544 { 0x1c, 0x8d68 },
545 { 0x1c, 0x8d68 },
546 { 0, 0 },
547 };
548 int i;
549
550 for (i = 0; dspcode[i].reg != 0; i++)
551 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
552}
553
554static void
555brgphy_fixup_adc_bug(struct mii_softc *sc)
556{
557 static const struct {
558 int reg;
559 uint16_t val;
560 } dspcode[] = {
561 { BRGPHY_MII_AUXCTL, 0x0c00 },
562 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
563 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
564 { 0, 0 },
565 };
566 int i;
567
568 for (i = 0; dspcode[i].reg != 0; i++)
569 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
570}
571
572static void
573brgphy_fixup_adjust_trim(struct mii_softc *sc)
574{
575 static const struct {
576 int reg;
577 uint16_t val;
578 } dspcode[] = {
579 { BRGPHY_MII_AUXCTL, 0x0c00 },
580 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
581 { BRGPHY_MII_DSP_RW_PORT, 0x110b },
582 { BRGPHY_MII_TEST1, 0x0014 },
583 { BRGPHY_MII_AUXCTL, 0x0400 },
584 { 0, 0 },
585 };
586 int i;
587
588 for (i = 0; dspcode[i].reg != 0; i++)
589 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
590}
591
592static void
593brgphy_fixup_ber_bug(struct mii_softc *sc)
594{
595 static const struct {
596 int reg;
597 uint16_t val;
598 } dspcode[] = {
599 { BRGPHY_MII_AUXCTL, 0x0c00 },
600 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
601 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
602 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
603 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
604 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
605 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
606 { BRGPHY_MII_AUXCTL, 0x0400 },
607 { 0, 0 },
608 };
609 int i;
610
611 for (i = 0; dspcode[i].reg != 0; i++)
612 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
613}
614
615static void
616brgphy_fixup_crc_bug(struct mii_softc *sc)
617{
618 static const struct {
619 int reg;
620 uint16_t val;
621 } dspcode[] = {
622 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 },
623 { 0x1c, 0x8c68 },
624 { 0x1c, 0x8d68 },
625 { 0x1c, 0x8c68 },
626 { 0, 0 },
627 };
628 int i;
629
630 for (i = 0; dspcode[i].reg != 0; i++)
631 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
632}
633
634static void
635brgphy_fixup_jitter_bug(struct mii_softc *sc)
636{
637 static const struct {
638 int reg;
639 uint16_t val;
640 } dspcode[] = {
641 { BRGPHY_MII_AUXCTL, 0x0c00 },
642 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
643 { BRGPHY_MII_DSP_RW_PORT, 0x010b },
644 { BRGPHY_MII_AUXCTL, 0x0400 },
645 { 0, 0 },
646 };
647 int i;
648
649 for (i = 0; dspcode[i].reg != 0; i++)
650 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
651}
652
653static void
654brgphy_ethernet_wirespeed(struct mii_softc *sc)
655{
656 uint32_t val;
657
658 /* Enable Ethernet@WireSpeed. */
659 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
660 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
661 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
662}
663
664static void
665brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
666{
667 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
668 uint32_t val;
669
670 /* Set or clear jumbo frame settings in the PHY. */
671 if (mtu > ETHER_MAX_LEN) {
672 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
673 /* BCM5401 PHY cannot read-modify-write. */
674 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
675 } else {
676 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
677 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
678 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
679 val | BRGPHY_AUXCTL_LONG_PKT);
680 }
681
682 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
683 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
684 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
685 } else {
686 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
687 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
688 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
689 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
690
691 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
692 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
693 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
694 }
695}
696
697static void
698brgphy_reset(struct mii_softc *sc)
699{
700 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
701 struct bge_softc *bge_sc = NULL;
702 struct bce_softc *bce_sc = NULL;
703 struct ifnet *ifp;
704
705 mii_phy_reset(sc);
706
707 switch (bsc->mii_model) {
708 case MII_MODEL_xxBROADCOM_BCM5400:
709 bcm5401_load_dspcode(sc);
710 break;
711 case MII_MODEL_xxBROADCOM_BCM5401:
712 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
713 bcm5401_load_dspcode(sc);
714 break;
715 case MII_MODEL_xxBROADCOM_BCM5411:
716 bcm5411_load_dspcode(sc);
717 break;
718 }
719
720 ifp = sc->mii_pdata->mii_ifp;
721
722 /* Find the driver associated with this PHY. */
723 if (strcmp(ifp->if_dname, "bge") == 0) {
724 bge_sc = ifp->if_softc;
725 } else if (strcmp(ifp->if_dname, "bce") == 0) {
726 bce_sc = ifp->if_softc;
727 }
728
729 /* Handle any NetXtreme/bge workarounds. */
730 if (bge_sc) {
731 /* Fix up various bugs */
732 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
733 brgphy_fixup_5704_a0_bug(sc);
734 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
735 brgphy_fixup_adc_bug(sc);
736 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
737 brgphy_fixup_adjust_trim(sc);
738 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
739 brgphy_fixup_ber_bug(sc);
740 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
741 brgphy_fixup_crc_bug(sc);
742 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
743 brgphy_fixup_jitter_bug(sc);
744
745 brgphy_jumbo_settings(sc, ifp->if_mtu);
746
747 /*
748 * Don't enable Ethernet@WireSpeed for the 5700 or the
749 * 5705 A1 and A2 chips.
750 */
751 if (bge_sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
752 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A1 &&
753 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A2)
754 brgphy_ethernet_wirespeed(sc);
755
756 /* Enable Link LED on Dell boxes */
757 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
758 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
759 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
760 ~BRGPHY_PHY_EXTCTL_3_LED);
761 }
762 } else if (bce_sc) {
763 brgphy_fixup_ber_bug(sc);
764 brgphy_jumbo_settings(sc, ifp->if_mtu);
765 brgphy_ethernet_wirespeed(sc);
766 }
767}
2 * Copyright (c) 2000
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 166680 2007-02-13 00:34:32Z jkim $");
35
36/*
37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/bus.h>
46
47#include <net/if.h>
48#include <net/ethernet.h>
49#include <net/if_media.h>
50
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53#include "miidevs.h"
54
55#include <dev/mii/brgphyreg.h>
56#include <net/if_arp.h>
57#include <machine/bus.h>
58#include <dev/bge/if_bgereg.h>
59#include <dev/bce/if_bcereg.h>
60
61#include <dev/pci/pcireg.h>
62#include <dev/pci/pcivar.h>
63
64#include "miibus_if.h"
65
66static int brgphy_probe(device_t);
67static int brgphy_attach(device_t);
68
69struct brgphy_softc {
70 struct mii_softc mii_sc;
71 int mii_model;
72 int mii_rev;
73};
74
75static device_method_t brgphy_methods[] = {
76 /* device interface */
77 DEVMETHOD(device_probe, brgphy_probe),
78 DEVMETHOD(device_attach, brgphy_attach),
79 DEVMETHOD(device_detach, mii_phy_detach),
80 DEVMETHOD(device_shutdown, bus_generic_shutdown),
81 { 0, 0 }
82};
83
84static devclass_t brgphy_devclass;
85
86static driver_t brgphy_driver = {
87 "brgphy",
88 brgphy_methods,
89 sizeof(struct brgphy_softc)
90};
91
92DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
93
94static int brgphy_service(struct mii_softc *, struct mii_data *, int);
95static void brgphy_setmedia(struct mii_softc *, int, int);
96static void brgphy_status(struct mii_softc *);
97static int brgphy_mii_phy_auto(struct mii_softc *);
98static void brgphy_reset(struct mii_softc *);
99static void brgphy_loop(struct mii_softc *);
100static void bcm5401_load_dspcode(struct mii_softc *);
101static void bcm5411_load_dspcode(struct mii_softc *);
102static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
103static void brgphy_fixup_adc_bug(struct mii_softc *);
104static void brgphy_fixup_adjust_trim(struct mii_softc *);
105static void brgphy_fixup_ber_bug(struct mii_softc *);
106static void brgphy_fixup_crc_bug(struct mii_softc *);
107static void brgphy_fixup_jitter_bug(struct mii_softc *);
108static void brgphy_ethernet_wirespeed(struct mii_softc *);
109static void brgphy_jumbo_settings(struct mii_softc *, u_long);
110
111static const struct mii_phydesc brgphys[] = {
112 MII_PHY_DESC(xxBROADCOM, BCM5400),
113 MII_PHY_DESC(xxBROADCOM, BCM5401),
114 MII_PHY_DESC(xxBROADCOM, BCM5411),
115 MII_PHY_DESC(xxBROADCOM, BCM5701),
116 MII_PHY_DESC(xxBROADCOM, BCM5703),
117 MII_PHY_DESC(xxBROADCOM, BCM5704),
118 MII_PHY_DESC(xxBROADCOM, BCM5705),
119 MII_PHY_DESC(xxBROADCOM, BCM5706C),
120 MII_PHY_DESC(xxBROADCOM, BCM5714),
121 MII_PHY_DESC(xxBROADCOM, BCM5750),
122 MII_PHY_DESC(xxBROADCOM, BCM5752),
123 MII_PHY_DESC(xxBROADCOM, BCM5754),
124 MII_PHY_DESC(xxBROADCOM, BCM5780),
125 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
126 MII_PHY_END
127};
128
129static int
130brgphy_probe(device_t dev)
131{
132
133 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
134}
135
136static int
137brgphy_attach(device_t dev)
138{
139 struct brgphy_softc *bsc;
140 struct mii_softc *sc;
141 struct mii_attach_args *ma;
142 struct mii_data *mii;
143 const char *sep = "";
144 struct bge_softc *bge_sc = NULL;
145 struct bce_softc *bce_sc = NULL;
146 int fast_ether_only = FALSE;
147
148 bsc = device_get_softc(dev);
149 sc = &bsc->mii_sc;
150 ma = device_get_ivars(dev);
151 sc->mii_dev = device_get_parent(dev);
152 mii = device_get_softc(sc->mii_dev);
153 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
154
155 sc->mii_inst = mii->mii_instance;
156 sc->mii_phy = ma->mii_phyno;
157 sc->mii_service = brgphy_service;
158 sc->mii_pdata = mii;
159
160 sc->mii_flags |= MIIF_NOISOLATE;
161 mii->mii_instance++;
162
163#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
164#define PRINT(s) printf("%s%s", sep, s); sep = ", "
165
166 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
167 BMCR_ISO);
168#if 0
169 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
170 BMCR_LOOP | BMCR_S100);
171#endif
172
173 bsc->mii_model = MII_MODEL(ma->mii_id2);
174 bsc->mii_rev = MII_REV(ma->mii_id2);
175 brgphy_reset(sc);
176
177 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
178 sc->mii_capabilities &= ~BMSR_ANEG;
179 device_printf(dev, " ");
180 mii_add_media(sc);
181
182 /* Find the driver associated with this PHY. */
183 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) {
184 bge_sc = mii->mii_ifp->if_softc;
185 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) {
186 bce_sc = mii->mii_ifp->if_softc;
187 }
188
189 /* The 590x chips are 10/100 only. */
190 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 &&
191 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
192 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
193 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2))
194 fast_ether_only = TRUE;
195
196 if (fast_ether_only == FALSE) {
197 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
198 sc->mii_inst), BRGPHY_BMCR_FDX);
199 PRINT(", 1000baseTX");
200 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
201 IFM_FDX, sc->mii_inst), 0);
202 PRINT("1000baseTX-FDX");
203 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
204 } else
205 sc->mii_anegticks = MII_ANEGTICKS;
206
207 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
208 PRINT("auto");
209
210 printf("\n");
211#undef ADD
212#undef PRINT
213
214 MIIBUS_MEDIAINIT(sc->mii_dev);
215 return (0);
216}
217
218static int
219brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
220{
221 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
222 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
223
224 switch (cmd) {
225 case MII_POLLSTAT:
226 /* If we're not polling our PHY instance, just return. */
227 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
228 return (0);
229 break;
230 case MII_MEDIACHG:
231 /*
232 * If the media indicates a different PHY instance,
233 * isolate ourselves.
234 */
235 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
236 PHY_WRITE(sc, MII_BMCR,
237 PHY_READ(sc, MII_BMCR) | BMCR_ISO);
238 return (0);
239 }
240
241 /* If the interface is not up, don't do anything. */
242 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
243 break;
244
245 brgphy_reset(sc); /* XXX hardware bug work-around */
246
247 switch (IFM_SUBTYPE(ife->ifm_media)) {
248 case IFM_AUTO:
249#ifdef foo
250 /* If we're already in auto mode, just return. */
251 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
252 return (0);
253#endif
254 (void)brgphy_mii_phy_auto(sc);
255 break;
256 case IFM_1000_T:
257 case IFM_100_TX:
258 case IFM_10_T:
259 brgphy_setmedia(sc, ife->ifm_media,
260 mii->mii_ifp->if_flags & IFF_LINK0);
261 break;
262#ifdef foo
263 case IFM_NONE:
264 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
265 break;
266#endif
267 case IFM_100_T4:
268 default:
269 return (EINVAL);
270 }
271 break;
272 case MII_TICK:
273 /* If we're not currently selected, just return. */
274 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
275 return (0);
276
277 /* Is the interface even up? */
278 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
279 return (0);
280
281 /* Only used for autonegotiation. */
282 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
283 sc->mii_ticks = 0; /* Reset autoneg timer. */
284 break;
285 }
286
287 /*
288 * Check to see if we have link. If we do, we don't
289 * need to restart the autonegotiation process.
290 */
291 if (PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK) {
292 sc->mii_ticks = 0; /* Reset autoneg timer. */
293 break;
294 }
295
296 /* Announce link loss right after it happens. */
297 if (sc->mii_ticks++ == 0)
298 break;
299
300 /* Only retry autonegotiation every mii_anegticks seconds. */
301 if (sc->mii_ticks <= sc->mii_anegticks)
302 return (0);
303
304 sc->mii_ticks = 0;
305 (void)brgphy_mii_phy_auto(sc);
306 break;
307 }
308
309 /* Update the media status. */
310 brgphy_status(sc);
311
312 /*
313 * Callback if something changed. Note that we need to poke
314 * the DSP on the Broadcom PHYs if the media changes.
315 */
316 if (sc->mii_media_active != mii->mii_media_active ||
317 sc->mii_media_status != mii->mii_media_status ||
318 cmd == MII_MEDIACHG) {
319 switch (bsc->mii_model) {
320 case MII_MODEL_xxBROADCOM_BCM5400:
321 bcm5401_load_dspcode(sc);
322 break;
323 case MII_MODEL_xxBROADCOM_BCM5401:
324 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
325 bcm5401_load_dspcode(sc);
326 break;
327 case MII_MODEL_xxBROADCOM_BCM5411:
328 bcm5411_load_dspcode(sc);
329 break;
330 }
331 }
332 mii_phy_update(sc, cmd);
333 return (0);
334}
335
336static void
337brgphy_setmedia(struct mii_softc *sc, int media, int master)
338{
339 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
340 int bmcr, gig;
341
342 switch (IFM_SUBTYPE(media)) {
343 case IFM_1000_T:
344 bmcr = BRGPHY_S1000;
345 break;
346 case IFM_100_TX:
347 bmcr = BRGPHY_S100;
348 break;
349 case IFM_10_T:
350 default:
351 bmcr = BRGPHY_S10;
352 break;
353 }
354 if ((media & IFM_GMASK) == IFM_FDX) {
355 bmcr |= BRGPHY_BMCR_FDX;
356 gig = BRGPHY_1000CTL_AFD;
357 } else {
358 gig = BRGPHY_1000CTL_AHD;
359 }
360
361 brgphy_loop(sc);
362 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
363 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
364 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
365
366 if (IFM_SUBTYPE(media) != IFM_1000_T)
367 return;
368
369 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
370 PHY_WRITE(sc, BRGPHY_MII_BMCR,
371 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
372
373 if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
374 return;
375
376 /*
377 * When setting the link manually, one side must be the master and
378 * the other the slave. However ifmedia doesn't give us a good way
379 * to specify this, so we fake it by using one of the LINK flags.
380 * If LINK0 is set, we program the PHY to be a master, otherwise
381 * it's a slave.
382 */
383 if (master) {
384 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
385 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC);
386 } else {
387 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
388 gig | BRGPHY_1000CTL_MSE);
389 }
390}
391
392static void
393brgphy_status(struct mii_softc *sc)
394{
395 struct mii_data *mii = sc->mii_pdata;
396 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
397 int bmcr, bmsr;
398
399 mii->mii_media_status = IFM_AVALID;
400 mii->mii_media_active = IFM_ETHER;
401
402 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
403 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
404
405 if (bmsr & BRGPHY_BMSR_LINK)
406 mii->mii_media_status |= IFM_ACTIVE;
407
408 if (bmcr & BRGPHY_BMCR_LOOP)
409 mii->mii_media_active |= IFM_LOOP;
410
411 if (bmcr & BRGPHY_BMCR_AUTOEN) {
412 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
413 /* Erg, still trying, I guess... */
414 mii->mii_media_active |= IFM_NONE;
415 return;
416 }
417 }
418
419 if (bmsr & BRGPHY_BMSR_LINK) {
420 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
421 BRGPHY_AUXSTS_AN_RES) {
422 case BRGPHY_RES_1000FD:
423 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
424 break;
425 case BRGPHY_RES_1000HD:
426 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
427 break;
428 case BRGPHY_RES_100FD:
429 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
430 break;
431 case BRGPHY_RES_100T4:
432 mii->mii_media_active |= IFM_100_T4;
433 break;
434 case BRGPHY_RES_100HD:
435 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
436 break;
437 case BRGPHY_RES_10FD:
438 mii->mii_media_active |= IFM_10_T | IFM_FDX;
439 break;
440 case BRGPHY_RES_10HD:
441 mii->mii_media_active |= IFM_10_T | IFM_HDX;
442 break;
443 default:
444 mii->mii_media_active |= IFM_NONE;
445 break;
446 }
447 } else
448 mii->mii_media_active = ife->ifm_media;
449}
450
451static int
452brgphy_mii_phy_auto(struct mii_softc *sc)
453{
454 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
455 int ktcr = 0;
456
457 brgphy_loop(sc);
458 brgphy_reset(sc);
459 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
460 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
461 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
462 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
463 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
464 DELAY(1000);
465 PHY_WRITE(sc, BRGPHY_MII_ANAR,
466 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
467 DELAY(1000);
468 PHY_WRITE(sc, BRGPHY_MII_BMCR,
469 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
470 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
471 return (EJUSTRETURN);
472}
473
474static void
475brgphy_loop(struct mii_softc *sc)
476{
477 int i;
478
479 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
480 for (i = 0; i < 15000; i++) {
481 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) {
482#if 0
483 device_printf(sc->mii_dev, "looped %d\n", i);
484#endif
485 break;
486 }
487 DELAY(10);
488 }
489}
490
491/* Turn off tap power management on 5401. */
492static void
493bcm5401_load_dspcode(struct mii_softc *sc)
494{
495 static const struct {
496 int reg;
497 uint16_t val;
498 } dspcode[] = {
499 { BRGPHY_MII_AUXCTL, 0x0c20 },
500 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
501 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
502 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
503 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
504 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
505 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
506 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
507 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
508 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
509 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
510 { 0, 0 },
511 };
512 int i;
513
514 for (i = 0; dspcode[i].reg != 0; i++)
515 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
516 DELAY(40);
517}
518
519static void
520bcm5411_load_dspcode(struct mii_softc *sc)
521{
522 static const struct {
523 int reg;
524 uint16_t val;
525 } dspcode[] = {
526 { 0x1c, 0x8c23 },
527 { 0x1c, 0x8ca3 },
528 { 0x1c, 0x8c23 },
529 { 0, 0 },
530 };
531 int i;
532
533 for (i = 0; dspcode[i].reg != 0; i++)
534 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
535}
536
537static void
538brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
539{
540 static const struct {
541 int reg;
542 uint16_t val;
543 } dspcode[] = {
544 { 0x1c, 0x8d68 },
545 { 0x1c, 0x8d68 },
546 { 0, 0 },
547 };
548 int i;
549
550 for (i = 0; dspcode[i].reg != 0; i++)
551 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
552}
553
554static void
555brgphy_fixup_adc_bug(struct mii_softc *sc)
556{
557 static const struct {
558 int reg;
559 uint16_t val;
560 } dspcode[] = {
561 { BRGPHY_MII_AUXCTL, 0x0c00 },
562 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
563 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
564 { 0, 0 },
565 };
566 int i;
567
568 for (i = 0; dspcode[i].reg != 0; i++)
569 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
570}
571
572static void
573brgphy_fixup_adjust_trim(struct mii_softc *sc)
574{
575 static const struct {
576 int reg;
577 uint16_t val;
578 } dspcode[] = {
579 { BRGPHY_MII_AUXCTL, 0x0c00 },
580 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
581 { BRGPHY_MII_DSP_RW_PORT, 0x110b },
582 { BRGPHY_MII_TEST1, 0x0014 },
583 { BRGPHY_MII_AUXCTL, 0x0400 },
584 { 0, 0 },
585 };
586 int i;
587
588 for (i = 0; dspcode[i].reg != 0; i++)
589 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
590}
591
592static void
593brgphy_fixup_ber_bug(struct mii_softc *sc)
594{
595 static const struct {
596 int reg;
597 uint16_t val;
598 } dspcode[] = {
599 { BRGPHY_MII_AUXCTL, 0x0c00 },
600 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
601 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
602 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
603 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
604 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
605 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
606 { BRGPHY_MII_AUXCTL, 0x0400 },
607 { 0, 0 },
608 };
609 int i;
610
611 for (i = 0; dspcode[i].reg != 0; i++)
612 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
613}
614
615static void
616brgphy_fixup_crc_bug(struct mii_softc *sc)
617{
618 static const struct {
619 int reg;
620 uint16_t val;
621 } dspcode[] = {
622 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 },
623 { 0x1c, 0x8c68 },
624 { 0x1c, 0x8d68 },
625 { 0x1c, 0x8c68 },
626 { 0, 0 },
627 };
628 int i;
629
630 for (i = 0; dspcode[i].reg != 0; i++)
631 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
632}
633
634static void
635brgphy_fixup_jitter_bug(struct mii_softc *sc)
636{
637 static const struct {
638 int reg;
639 uint16_t val;
640 } dspcode[] = {
641 { BRGPHY_MII_AUXCTL, 0x0c00 },
642 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
643 { BRGPHY_MII_DSP_RW_PORT, 0x010b },
644 { BRGPHY_MII_AUXCTL, 0x0400 },
645 { 0, 0 },
646 };
647 int i;
648
649 for (i = 0; dspcode[i].reg != 0; i++)
650 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
651}
652
653static void
654brgphy_ethernet_wirespeed(struct mii_softc *sc)
655{
656 uint32_t val;
657
658 /* Enable Ethernet@WireSpeed. */
659 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
660 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
661 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
662}
663
664static void
665brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
666{
667 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
668 uint32_t val;
669
670 /* Set or clear jumbo frame settings in the PHY. */
671 if (mtu > ETHER_MAX_LEN) {
672 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
673 /* BCM5401 PHY cannot read-modify-write. */
674 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
675 } else {
676 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
677 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
678 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
679 val | BRGPHY_AUXCTL_LONG_PKT);
680 }
681
682 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
683 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
684 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
685 } else {
686 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
687 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
688 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
689 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
690
691 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
692 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
693 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
694 }
695}
696
697static void
698brgphy_reset(struct mii_softc *sc)
699{
700 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
701 struct bge_softc *bge_sc = NULL;
702 struct bce_softc *bce_sc = NULL;
703 struct ifnet *ifp;
704
705 mii_phy_reset(sc);
706
707 switch (bsc->mii_model) {
708 case MII_MODEL_xxBROADCOM_BCM5400:
709 bcm5401_load_dspcode(sc);
710 break;
711 case MII_MODEL_xxBROADCOM_BCM5401:
712 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
713 bcm5401_load_dspcode(sc);
714 break;
715 case MII_MODEL_xxBROADCOM_BCM5411:
716 bcm5411_load_dspcode(sc);
717 break;
718 }
719
720 ifp = sc->mii_pdata->mii_ifp;
721
722 /* Find the driver associated with this PHY. */
723 if (strcmp(ifp->if_dname, "bge") == 0) {
724 bge_sc = ifp->if_softc;
725 } else if (strcmp(ifp->if_dname, "bce") == 0) {
726 bce_sc = ifp->if_softc;
727 }
728
729 /* Handle any NetXtreme/bge workarounds. */
730 if (bge_sc) {
731 /* Fix up various bugs */
732 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
733 brgphy_fixup_5704_a0_bug(sc);
734 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
735 brgphy_fixup_adc_bug(sc);
736 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
737 brgphy_fixup_adjust_trim(sc);
738 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
739 brgphy_fixup_ber_bug(sc);
740 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
741 brgphy_fixup_crc_bug(sc);
742 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
743 brgphy_fixup_jitter_bug(sc);
744
745 brgphy_jumbo_settings(sc, ifp->if_mtu);
746
747 /*
748 * Don't enable Ethernet@WireSpeed for the 5700 or the
749 * 5705 A1 and A2 chips.
750 */
751 if (bge_sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
752 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A1 &&
753 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A2)
754 brgphy_ethernet_wirespeed(sc);
755
756 /* Enable Link LED on Dell boxes */
757 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
758 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
759 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
760 ~BRGPHY_PHY_EXTCTL_3_LED);
761 }
762 } else if (bce_sc) {
763 brgphy_fixup_ber_bug(sc);
764 brgphy_jumbo_settings(sc, ifp->if_mtu);
765 brgphy_ethernet_wirespeed(sc);
766 }
767}