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ixgbe_type.h (181003) ixgbe_type.h (185352)
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 181003 2008-07-30 18:15:18Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 185352 2008-11-26 23:41:18Z jfv $*/
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40/* Vendor ID */
41#define IXGBE_INTEL_VENDOR_ID 0x8086
42
43/* Device IDs */
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40/* Vendor ID */
41#define IXGBE_INTEL_VENDOR_ID 0x8086
42
43/* Device IDs */
44#define IXGBE_DEV_ID_82598 0x10B6
44#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
45#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
46#define IXGBE_DEV_ID_82598AT 0x10C8
45#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
46#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
47#define IXGBE_DEV_ID_82598AT 0x10C8
47#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10D7
48#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
48#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
49#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
49#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
50#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
51#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
52#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
50#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
51
52/* General Registers */
53#define IXGBE_CTRL 0x00000
54#define IXGBE_STATUS 0x00008
55#define IXGBE_CTRL_EXT 0x00018
56#define IXGBE_ESDP 0x00020
57#define IXGBE_EODSDP 0x00028

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73
74/* Interrupt Registers */
75#define IXGBE_EICR 0x00800
76#define IXGBE_EICS 0x00808
77#define IXGBE_EIMS 0x00880
78#define IXGBE_EIMC 0x00888
79#define IXGBE_EIAC 0x00810
80#define IXGBE_EIAM 0x00890
53#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
54
55/* General Registers */
56#define IXGBE_CTRL 0x00000
57#define IXGBE_STATUS 0x00008
58#define IXGBE_CTRL_EXT 0x00018
59#define IXGBE_ESDP 0x00020
60#define IXGBE_EODSDP 0x00028

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76
77/* Interrupt Registers */
78#define IXGBE_EICR 0x00800
79#define IXGBE_EICS 0x00808
80#define IXGBE_EIMS 0x00880
81#define IXGBE_EIMC 0x00888
82#define IXGBE_EIAC 0x00810
83#define IXGBE_EIAM 0x00890
81#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4)))
84#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
85 (0x012300 + ((_i) * 4)))
86#define IXGBE_EITR_ITR_INT_MASK 0x00000FFF
82#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
83#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
84#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
85#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
86#define IXGBE_GPIE 0x00898
87
88/* Flow Control Registers */
89#define IXGBE_PFCTOP 0x03008
90#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
91#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
92#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
93#define IXGBE_FCRTV 0x032A0
94#define IXGBE_TFCS 0x0CE00
95
96/* Receive DMA Registers */
87#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
88#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
89#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
90#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
91#define IXGBE_GPIE 0x00898
92
93/* Flow Control Registers */
94#define IXGBE_PFCTOP 0x03008
95#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
96#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
97#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
98#define IXGBE_FCRTV 0x032A0
99#define IXGBE_TFCS 0x0CE00
100
101/* Receive DMA Registers */
97#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40)))
98#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40)))
99#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40)))
100#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40)))
101#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40)))
102#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40)))
102#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
103 (0x0D000 + ((_i - 64) * 0x40)))
104#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
105 (0x0D004 + ((_i - 64) * 0x40)))
106#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
107 (0x0D008 + ((_i - 64) * 0x40)))
108#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
109 (0x0D010 + ((_i - 64) * 0x40)))
110#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
111 (0x0D018 + ((_i - 64) * 0x40)))
112#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
113 (0x0D028 + ((_i - 64) * 0x40)))
103/*
104 * Split and Replication Receive Control Registers
105 * 00-15 : 0x02100 + n*4
106 * 16-64 : 0x01014 + n*0x40
107 * 64-127: 0x0D014 + (n-64)*0x40
108 */
109#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
110 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
111 (0x0D014 + ((_i - 64) * 0x40))))
112/*
113 * Rx DCA Control Register:
114 * 00-15 : 0x02200 + n*4
115 * 16-64 : 0x0100C + n*0x40
116 * 64-127: 0x0D00C + (n-64)*0x40
117 */
118#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
119 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
120 (0x0D00C + ((_i - 64) * 0x40))))
114/*
115 * Split and Replication Receive Control Registers
116 * 00-15 : 0x02100 + n*4
117 * 16-64 : 0x01014 + n*0x40
118 * 64-127: 0x0D014 + (n-64)*0x40
119 */
120#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
121 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
122 (0x0D014 + ((_i - 64) * 0x40))))
123/*
124 * Rx DCA Control Register:
125 * 00-15 : 0x02200 + n*4
126 * 16-64 : 0x0100C + n*0x40
127 * 64-127: 0x0D00C + (n-64)*0x40
128 */
129#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
130 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
131 (0x0D00C + ((_i - 64) * 0x40))))
121#define IXGBE_RDRXCTL 0x02F00
122#define IXGBE_RDRXCTRL_RSC_PUSH 0x80
132#define IXGBE_RDRXCTL 0x02F00
123#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
124 /* 8 of these 0x03C00 - 0x03C1C */
125#define IXGBE_RXCTRL 0x03000
126#define IXGBE_DROPEN 0x03D04
127#define IXGBE_RXPBSIZE_SHIFT 10
128
129/* Receive Registers */
130#define IXGBE_RXCSUM 0x05000
131#define IXGBE_RFCTL 0x05008
133#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
134 /* 8 of these 0x03C00 - 0x03C1C */
135#define IXGBE_RXCTRL 0x03000
136#define IXGBE_DROPEN 0x03D04
137#define IXGBE_RXPBSIZE_SHIFT 10
138
139/* Receive Registers */
140#define IXGBE_RXCSUM 0x05000
141#define IXGBE_RFCTL 0x05008
142#define IXGBE_DRECCCTL 0x02F08
143#define IXGBE_DRECCCTL_DISABLE 0
132/* Multicast Table Array - 128 entries */
133#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
144/* Multicast Table Array - 128 entries */
145#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
134#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8)))
135#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8)))
146#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
147 (0x0A200 + ((_i) * 8)))
148#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
149 (0x0A204 + ((_i) * 8)))
136/* Packet split receive type */
150/* Packet split receive type */
137#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4)))
151#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
152 (0x0EA00 + ((_i) * 4)))
138/* array of 4096 1-bit vlan filters */
139#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
140/*array of 4096 4-bit vlan vmdq indices */
141#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
142#define IXGBE_FCTRL 0x05080
143#define IXGBE_VLNCTRL 0x05088
144#define IXGBE_MCSTCTRL 0x05090
145#define IXGBE_MRQC 0x05818

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159#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
160#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
161#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
162#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
163#define IXGBE_DTXCTL 0x07E00
164
165#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
166#define IXGBE_TIPG 0x0CB00
153/* array of 4096 1-bit vlan filters */
154#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
155/*array of 4096 4-bit vlan vmdq indices */
156#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
157#define IXGBE_FCTRL 0x05080
158#define IXGBE_VLNCTRL 0x05088
159#define IXGBE_MCSTCTRL 0x05090
160#define IXGBE_MRQC 0x05818

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174#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
175#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
176#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
177#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
178#define IXGBE_DTXCTL 0x07E00
179
180#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
181#define IXGBE_TIPG 0x0CB00
167#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) /* 8 of these */
182#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
168#define IXGBE_MNGTXMAP 0x0CD10
169#define IXGBE_TIPG_FIBER_DEFAULT 3
170#define IXGBE_TXPBSIZE_SHIFT 10
171
172/* Wake up registers */
173#define IXGBE_WUC 0x05800
174#define IXGBE_WUFC 0x05808
175#define IXGBE_WUS 0x05810
176#define IXGBE_IPAV 0x05838
177#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
178#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
183#define IXGBE_MNGTXMAP 0x0CD10
184#define IXGBE_TIPG_FIBER_DEFAULT 3
185#define IXGBE_TXPBSIZE_SHIFT 10
186
187/* Wake up registers */
188#define IXGBE_WUC 0x05800
189#define IXGBE_WUFC 0x05808
190#define IXGBE_WUS 0x05810
191#define IXGBE_IPAV 0x05838
192#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
193#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
194
179#define IXGBE_WUPL 0x05900
180#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
195#define IXGBE_WUPL 0x05900
196#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
181#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */
197#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
198#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
199 * Filter Table */
182
200
183/* Music registers */
201#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
202#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
203
204/* Each Flexible Filter is at most 128 (0x80) bytes in length */
205#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
206#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
207#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
208
209/* Definitions for power management and wakeup registers */
210/* Wake Up Control */
211#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
212#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
213#define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/
214
215/* Wake Up Filter Control */
216#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
217#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
218#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
219#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
220#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
221#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
222#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
223#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
224#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
225
226#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
227#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
228#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
229#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
230#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
231#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
232#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
233#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
234#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
235#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
236#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
237
238/* Wake Up Status */
239#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
240#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
241#define IXGBE_WUS_EX IXGBE_WUFC_EX
242#define IXGBE_WUS_MC IXGBE_WUFC_MC
243#define IXGBE_WUS_BC IXGBE_WUFC_BC
244#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
245#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
246#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
247#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
248#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
249#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
250#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
251#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
252#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
253#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
254#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
255
256/* Wake Up Packet Length */
257#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
258
259/* DCB registers */
184#define IXGBE_RMCS 0x03D00
185#define IXGBE_DPMCS 0x07F40
186#define IXGBE_PDPMCS 0x0CD00
187#define IXGBE_RUPPBMR 0x050A0
188#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
189#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
190#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
191#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
192#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
193#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
194
260#define IXGBE_RMCS 0x03D00
261#define IXGBE_DPMCS 0x07F40
262#define IXGBE_PDPMCS 0x0CD00
263#define IXGBE_RUPPBMR 0x050A0
264#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
265#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
266#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
267#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
268#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
269#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
270
195/* LinkSec (MacSec) Registers */
196#define IXGBE_LSECTXCTRL 0x08A04
197#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
198#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
199#define IXGBE_LSECTXSA 0x08A10
200#define IXGBE_LSECTXPN0 0x08A14
201#define IXGBE_LSECTXPN1 0x08A18
202#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
203#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
204#define IXGBE_LSECRXCTRL 0x08F04
205#define IXGBE_LSECRXSCL 0x08F08
206#define IXGBE_LSECRXSCH 0x08F0C
207#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
208#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
209#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
210
271
211/* IpSec Registers */
212#define IXGBE_IPSTXIDX 0x08900
213#define IXGBE_IPSTXSALT 0x08904
214#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
215#define IXGBE_IPSRXIDX 0x08E00
216#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
217#define IXGBE_IPSRXSPI 0x08E14
218#define IXGBE_IPSRXIPIDX 0x08E18
219#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
220#define IXGBE_IPSRXSALT 0x08E2C
221#define IXGBE_IPSRXMOD 0x08E30
222
272
223
224/* Stats registers */
225#define IXGBE_CRCERRS 0x04000
226#define IXGBE_ILLERRC 0x04004
227#define IXGBE_ERRBC 0x04008
228#define IXGBE_MSPDC 0x04010
229#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
230#define IXGBE_MLFC 0x04034
231#define IXGBE_MRFC 0x04038

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269#define IXGBE_PTC255 0x040E0
270#define IXGBE_PTC511 0x040E4
271#define IXGBE_PTC1023 0x040E8
272#define IXGBE_PTC1522 0x040EC
273#define IXGBE_MPTC 0x040F0
274#define IXGBE_BPTC 0x040F4
275#define IXGBE_XEC 0x04120
276
273/* Stats registers */
274#define IXGBE_CRCERRS 0x04000
275#define IXGBE_ILLERRC 0x04004
276#define IXGBE_ERRBC 0x04008
277#define IXGBE_MSPDC 0x04010
278#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
279#define IXGBE_MLFC 0x04034
280#define IXGBE_MRFC 0x04038

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318#define IXGBE_PTC255 0x040E0
319#define IXGBE_PTC511 0x040E4
320#define IXGBE_PTC1023 0x040E8
321#define IXGBE_PTC1522 0x040EC
322#define IXGBE_MPTC 0x040F0
323#define IXGBE_BPTC 0x040F4
324#define IXGBE_XEC 0x04120
325
277#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
278#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4)))
326#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
327#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
328 (0x08600 + ((_i) * 4)))
279
280#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
281#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
282#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
283#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
284
285/* Management */
286#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */

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414/* FACTPS */
415#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
416
417/* MHADD Bit Masks */
418#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
419#define IXGBE_MHADD_MFS_SHIFT 16
420
421/* Extended Device Control */
329
330#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
331#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
332#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
333#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
334
335/* Management */
336#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */

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464/* FACTPS */
465#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
466
467/* MHADD Bit Masks */
468#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
469#define IXGBE_MHADD_MFS_SHIFT 16
470
471/* Extended Device Control */
472#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
422#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
423#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
424#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
425
426/* Direct Cache Access (DCA) definitions */
427#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
428#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
429

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474
475/* Atlas bit masks */
476#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
477#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
478#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
479#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
480#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
481
473#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
474#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
475#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
476
477/* Direct Cache Access (DCA) definitions */
478#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
479#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
480

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525
526/* Atlas bit masks */
527#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
528#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
529#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
530#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
531#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
532
533
482/* Device Type definitions for new protocol MDIO commands */
483#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
484#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
485#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
486#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
487#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
534/* Device Type definitions for new protocol MDIO commands */
535#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
536#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
537#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
538#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
539#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
540#define IXGBE_TWINAX_DEV 1
488
489#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
490
491#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
492#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
493#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
494#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
495#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018

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500#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
501#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
502#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
503#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
504#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
505#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
506#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
507
541
542#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
543
544#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
545#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
546#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
547#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
548#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018

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553#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
554#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
555#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
556#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
557#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
558#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
559#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
560
561#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
562#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
563#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
564
508/* MII clause 22/28 definitions */
509#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
510
511#define IXGBE_MII_SPEED_SELECTION_REG 0x10
512#define IXGBE_MII_RESTART 0x200
513#define IXGBE_MII_AUTONEG_COMPLETE 0x20
514#define IXGBE_MII_AUTONEG_REG 0x0
515
516#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
517#define IXGBE_MAX_PHY_ADDR 32
518
519/* PHY IDs*/
520#define TN1010_PHY_ID 0x00A19410
521#define TNX_FW_REV 0xB
522#define QT2022_PHY_ID 0x0043A400
565/* MII clause 22/28 definitions */
566#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
567
568#define IXGBE_MII_SPEED_SELECTION_REG 0x10
569#define IXGBE_MII_RESTART 0x200
570#define IXGBE_MII_AUTONEG_COMPLETE 0x20
571#define IXGBE_MII_AUTONEG_REG 0x0
572
573#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
574#define IXGBE_MAX_PHY_ADDR 32
575
576/* PHY IDs*/
577#define TN1010_PHY_ID 0x00A19410
578#define TNX_FW_REV 0xB
579#define QT2022_PHY_ID 0x0043A400
580#define ATH_PHY_ID 0x03429050
523
524/* PHY Types */
525#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
526
581
582/* PHY Types */
583#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
584
585/* Special PHY Init Routine */
586#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
587#define IXGBE_PHY_INIT_END_NL 0xFFFF
588#define IXGBE_CONTROL_MASK_NL 0xF000
589#define IXGBE_DATA_MASK_NL 0x0FFF
590#define IXGBE_CONTROL_SHIFT_NL 12
591#define IXGBE_DELAY_NL 0
592#define IXGBE_DATA_NL 1
593#define IXGBE_CONTROL_NL 0x000F
594#define IXGBE_CONTROL_EOL_NL 0x0FFF
595#define IXGBE_CONTROL_SOL_NL 0x0000
596
527/* General purpose Interrupt Enable */
528#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
529#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
530#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
531#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
532#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
533#define IXGBE_GPIE_EIAME 0x40000000
534#define IXGBE_GPIE_PBA_SUPPORT 0x80000000

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580#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
581#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
582
583/* Receive Checksum Control */
584#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
585#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
586
587/* FCRTL Bit Masks */
597/* General purpose Interrupt Enable */
598#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
599#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
600#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
601#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
602#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
603#define IXGBE_GPIE_EIAME 0x40000000
604#define IXGBE_GPIE_PBA_SUPPORT 0x80000000

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650#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
651#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
652
653/* Receive Checksum Control */
654#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
655#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
656
657/* FCRTL Bit Masks */
588#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
589#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
658#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
659#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
590
591/* PAP bit masks*/
592#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
593
594/* RMCS Bit Masks */
595#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
596/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
597#define IXGBE_RMCS_RAC 0x00000004
598#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
660
661/* PAP bit masks*/
662#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
663
664/* RMCS Bit Masks */
665#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
666/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
667#define IXGBE_RMCS_RAC 0x00000004
668#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
599#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
600#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
669#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
670#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
601#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
602
603
604/* Interrupt register bitmasks */
605
606/* Extended Interrupt Cause Read */
607#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
608#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */

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689#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
690#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
691#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
692
693
694#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
695
696/* STATUS Bit Masks */
671#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
672
673
674/* Interrupt register bitmasks */
675
676/* Extended Interrupt Cause Read */
677#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
678#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */

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759#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
760#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
761#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
762
763
764#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
765
766/* STATUS Bit Masks */
697#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
698#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
767#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
768#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
769#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
699
700#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
701#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
702
703/* ESDP Bit Masks */
770
771#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
772#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
773
774/* ESDP Bit Masks */
704#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */
705#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */
775#define IXGBE_ESDP_SDP1 0x00000001
776#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
777#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
778#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
706#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
779#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
707#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */
780#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
708
709/* LEDCTL Bit Masks */
710#define IXGBE_LED_IVRT_BASE 0x00000040
711#define IXGBE_LED_BLINK_BASE 0x00000080
712#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
713#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
714#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
715#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)

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722#define IXGBE_LED_MAC 0x2
723#define IXGBE_LED_FILTER 0x3
724#define IXGBE_LED_LINK_ACTIVE 0x4
725#define IXGBE_LED_LINK_1G 0x5
726#define IXGBE_LED_ON 0xE
727#define IXGBE_LED_OFF 0xF
728
729/* AUTOC Bit Masks */
781
782/* LEDCTL Bit Masks */
783#define IXGBE_LED_IVRT_BASE 0x00000040
784#define IXGBE_LED_BLINK_BASE 0x00000080
785#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
786#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
787#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
788#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)

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795#define IXGBE_LED_MAC 0x2
796#define IXGBE_LED_FILTER 0x3
797#define IXGBE_LED_LINK_ACTIVE 0x4
798#define IXGBE_LED_LINK_1G 0x5
799#define IXGBE_LED_ON 0xE
800#define IXGBE_LED_OFF 0xF
801
802/* AUTOC Bit Masks */
803#define IXGBE_AUTOC_KX4_KX_SUPP 0xC0000000
730#define IXGBE_AUTOC_KX4_SUPP 0x80000000
731#define IXGBE_AUTOC_KX_SUPP 0x40000000
732#define IXGBE_AUTOC_PAUSE 0x30000000
733#define IXGBE_AUTOC_RF 0x08000000
734#define IXGBE_AUTOC_PD_TMR 0x06000000
735#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
736#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
737#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
738#define IXGBE_AUTOC_AN_RESTART 0x00001000
739#define IXGBE_AUTOC_FLU 0x00000001
740#define IXGBE_AUTOC_LMS_SHIFT 13
804#define IXGBE_AUTOC_KX4_SUPP 0x80000000
805#define IXGBE_AUTOC_KX_SUPP 0x40000000
806#define IXGBE_AUTOC_PAUSE 0x30000000
807#define IXGBE_AUTOC_RF 0x08000000
808#define IXGBE_AUTOC_PD_TMR 0x06000000
809#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
810#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
811#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
812#define IXGBE_AUTOC_AN_RESTART 0x00001000
813#define IXGBE_AUTOC_FLU 0x00000001
814#define IXGBE_AUTOC_LMS_SHIFT 13
741#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
742#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
743#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
744#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
745#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
746#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
747#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
815#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
816#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
817#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
818#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
819#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
820#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
821#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
748
822
749#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
750#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
823#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
824#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
751#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
752#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
753#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
754#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
755#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
756#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
757#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
758

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1014#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
1015#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
1016#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
1017#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
1018#define IXGBE_RXD_PRI_SHIFT 13
1019#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
1020#define IXGBE_RXD_CFI_SHIFT 12
1021
825#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
826#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
827#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
828#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
829#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
830#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
831#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
832

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1088#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
1089#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
1090#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
1091#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
1092#define IXGBE_RXD_PRI_SHIFT 13
1093#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
1094#define IXGBE_RXD_CFI_SHIFT 12
1095
1096
1022/* SRRCTL bit definitions */
1023#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
1024#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1025#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1026#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
1027#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
1028#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
1029#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000

--- 27 unchanged lines hidden (view full) ---

1057#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
1058#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
1059#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
1060#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1061#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1062#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1063#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1064#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
1097/* SRRCTL bit definitions */
1098#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
1099#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1100#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1101#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
1102#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
1103#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
1104#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000

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1132#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
1133#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
1134#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
1135#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1136#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1137#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1138#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1139#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
1065
1066/* Masks to determine if packets should be dropped due to frame errors */
1067#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1068 IXGBE_RXD_ERR_CE | \
1069 IXGBE_RXD_ERR_LE | \
1070 IXGBE_RXD_ERR_PE | \
1071 IXGBE_RXD_ERR_OSE | \
1072 IXGBE_RXD_ERR_USE)
1073

--- 15 unchanged lines hidden (view full) ---

1089/* Vlan-specific macros */
1090#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1091#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1092#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1093#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1094
1095#ifndef __le16
1096/* Little Endian defines */
1140/* Masks to determine if packets should be dropped due to frame errors */
1141#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1142 IXGBE_RXD_ERR_CE | \
1143 IXGBE_RXD_ERR_LE | \
1144 IXGBE_RXD_ERR_PE | \
1145 IXGBE_RXD_ERR_OSE | \
1146 IXGBE_RXD_ERR_USE)
1147

--- 15 unchanged lines hidden (view full) ---

1163/* Vlan-specific macros */
1164#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1165#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1166#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1167#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1168
1169#ifndef __le16
1170/* Little Endian defines */
1097#define __le8 u8
1098#define __le16 u16
1099#define __le32 u32
1100#define __le64 u64
1101
1102#endif
1171#define __le16 u16
1172#define __le32 u32
1173#define __le64 u64
1174
1175#endif
1176#ifndef __be16
1177/* Big Endian defines */
1178#define __be16 u16
1179#define __be32 u32
1180#define __be64 u64
1103
1181
1182#endif
1104
1105/* Transmit Descriptor - Legacy */
1106struct ixgbe_legacy_tx_desc {
1107 u64 buffer_addr; /* Address of the descriptor's data buffer */
1108 union {
1109 __le32 data;
1110 struct {
1111 __le16 length; /* Data buffer length */
1183
1184/* Transmit Descriptor - Legacy */
1185struct ixgbe_legacy_tx_desc {
1186 u64 buffer_addr; /* Address of the descriptor's data buffer */
1187 union {
1188 __le32 data;
1189 struct {
1190 __le16 length; /* Data buffer length */
1112 __le8 cso; /* Checksum offset */
1113 __le8 cmd; /* Descriptor control */
1191 u8 cso; /* Checksum offset */
1192 u8 cmd; /* Descriptor control */
1114 } flags;
1115 } lower;
1116 union {
1117 __le32 data;
1118 struct {
1193 } flags;
1194 } lower;
1195 union {
1196 __le32 data;
1197 struct {
1119 __le8 status; /* Descriptor status */
1120 __le8 css; /* Checksum start */
1198 u8 status; /* Descriptor status */
1199 u8 css; /* Checksum start */
1121 __le16 vlan;
1122 } fields;
1123 } upper;
1124};
1125
1126/* Transmit Descriptor - Advanced */
1127union ixgbe_adv_tx_desc {
1128 struct {

--- 8 unchanged lines hidden (view full) ---

1137 } wb;
1138};
1139
1140/* Receive Descriptor - Legacy */
1141struct ixgbe_legacy_rx_desc {
1142 __le64 buffer_addr; /* Address of the descriptor's data buffer */
1143 __le16 length; /* Length of data DMAed into data buffer */
1144 __le16 csum; /* Packet checksum */
1200 __le16 vlan;
1201 } fields;
1202 } upper;
1203};
1204
1205/* Transmit Descriptor - Advanced */
1206union ixgbe_adv_tx_desc {
1207 struct {

--- 8 unchanged lines hidden (view full) ---

1216 } wb;
1217};
1218
1219/* Receive Descriptor - Legacy */
1220struct ixgbe_legacy_rx_desc {
1221 __le64 buffer_addr; /* Address of the descriptor's data buffer */
1222 __le16 length; /* Length of data DMAed into data buffer */
1223 __le16 csum; /* Packet checksum */
1145 __le8 status; /* Descriptor status */
1146 __le8 errors; /* Descriptor Errors */
1224 u8 status; /* Descriptor status */
1225 u8 errors; /* Descriptor Errors */
1147 __le16 vlan;
1148};
1149
1150/* Receive Descriptor - Advanced */
1151union ixgbe_adv_rx_desc {
1152 struct {
1153 __le64 pkt_addr; /* Packet buffer address */
1154 __le64 hdr_addr; /* Header buffer address */

--- 61 unchanged lines hidden (view full) ---

1216#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1217#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1218#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1219#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1220#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1221#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1222#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1223#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
1226 __le16 vlan;
1227};
1228
1229/* Receive Descriptor - Advanced */
1230union ixgbe_adv_rx_desc {
1231 struct {
1232 __le64 pkt_addr; /* Packet buffer address */
1233 __le64 hdr_addr; /* Header buffer address */

--- 61 unchanged lines hidden (view full) ---

1295#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1296#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1297#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1298#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1299#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1300#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1301#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1302#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
1224#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
1303#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
1225#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1226#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1227
1228/* Autonegotiation advertised speeds */
1229typedef u32 ixgbe_autoneg_advertised;
1230/* Link speed */
1231typedef u32 ixgbe_link_speed;
1232#define IXGBE_LINK_SPEED_UNKNOWN 0
1233#define IXGBE_LINK_SPEED_100_FULL 0x0008
1234#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1235#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1236#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
1237 IXGBE_LINK_SPEED_10GB_FULL)
1238
1304#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1305#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1306
1307/* Autonegotiation advertised speeds */
1308typedef u32 ixgbe_autoneg_advertised;
1309/* Link speed */
1310typedef u32 ixgbe_link_speed;
1311#define IXGBE_LINK_SPEED_UNKNOWN 0
1312#define IXGBE_LINK_SPEED_100_FULL 0x0008
1313#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1314#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1315#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
1316 IXGBE_LINK_SPEED_10GB_FULL)
1317
1318/* Physical layer type */
1319typedef u32 ixgbe_physical_layer;
1320#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
1321#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
1322#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
1323#define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004
1324#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
1325#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
1326#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
1327#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
1328#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
1329#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
1330#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
1331#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
1332
1333
1239enum ixgbe_eeprom_type {
1240 ixgbe_eeprom_uninitialized = 0,
1241 ixgbe_eeprom_spi,
1242 ixgbe_eeprom_none /* No NVM support */
1243};
1244
1245enum ixgbe_mac_type {
1246 ixgbe_mac_unknown = 0,
1247 ixgbe_mac_82598EB,
1248 ixgbe_num_macs
1249};
1250
1251enum ixgbe_phy_type {
1252 ixgbe_phy_unknown = 0,
1253 ixgbe_phy_tn,
1254 ixgbe_phy_qt,
1255 ixgbe_phy_xaui,
1334enum ixgbe_eeprom_type {
1335 ixgbe_eeprom_uninitialized = 0,
1336 ixgbe_eeprom_spi,
1337 ixgbe_eeprom_none /* No NVM support */
1338};
1339
1340enum ixgbe_mac_type {
1341 ixgbe_mac_unknown = 0,
1342 ixgbe_mac_82598EB,
1343 ixgbe_num_macs
1344};
1345
1346enum ixgbe_phy_type {
1347 ixgbe_phy_unknown = 0,
1348 ixgbe_phy_tn,
1349 ixgbe_phy_qt,
1350 ixgbe_phy_xaui,
1351 ixgbe_phy_nl,
1352 ixgbe_phy_tw_tyco,
1353 ixgbe_phy_tw_unknown,
1354 ixgbe_phy_sfp_avago,
1355 ixgbe_phy_sfp_ftl,
1356 ixgbe_phy_sfp_unknown,
1256 ixgbe_phy_generic
1257};
1258
1357 ixgbe_phy_generic
1358};
1359
1360/*
1361 * SFP+ module type IDs:
1362 *
1363 * ID Module Type
1364 * =============
1365 * 0 SFP_DA_CU
1366 * 1 SFP_SR
1367 * 2 SFP_LR
1368 */
1369enum ixgbe_sfp_type {
1370 ixgbe_sfp_type_da_cu = 0,
1371 ixgbe_sfp_type_sr = 1,
1372 ixgbe_sfp_type_lr = 2,
1373 ixgbe_sfp_type_not_present = 0xFFFE,
1374 ixgbe_sfp_type_unknown = 0xFFFF
1375};
1376
1259enum ixgbe_media_type {
1260 ixgbe_media_type_unknown = 0,
1261 ixgbe_media_type_fiber,
1262 ixgbe_media_type_copper,
1263 ixgbe_media_type_backplane,
1264 ixgbe_media_type_virtual
1265};
1266
1267/* Flow Control Settings */
1377enum ixgbe_media_type {
1378 ixgbe_media_type_unknown = 0,
1379 ixgbe_media_type_fiber,
1380 ixgbe_media_type_copper,
1381 ixgbe_media_type_backplane,
1382 ixgbe_media_type_virtual
1383};
1384
1385/* Flow Control Settings */
1268enum ixgbe_fc_type {
1386enum ixgbe_fc_mode {
1269 ixgbe_fc_none = 0,
1270 ixgbe_fc_rx_pause,
1271 ixgbe_fc_tx_pause,
1272 ixgbe_fc_full,
1273 ixgbe_fc_default
1274};
1275
1276/* PCI bus types */

--- 39 unchanged lines hidden (view full) ---

1316 bool user_set_promisc;
1317};
1318
1319/* Bus parameters */
1320struct ixgbe_bus_info {
1321 enum ixgbe_bus_speed speed;
1322 enum ixgbe_bus_width width;
1323 enum ixgbe_bus_type type;
1387 ixgbe_fc_none = 0,
1388 ixgbe_fc_rx_pause,
1389 ixgbe_fc_tx_pause,
1390 ixgbe_fc_full,
1391 ixgbe_fc_default
1392};
1393
1394/* PCI bus types */

--- 39 unchanged lines hidden (view full) ---

1434 bool user_set_promisc;
1435};
1436
1437/* Bus parameters */
1438struct ixgbe_bus_info {
1439 enum ixgbe_bus_speed speed;
1440 enum ixgbe_bus_width width;
1441 enum ixgbe_bus_type type;
1442
1443 u16 func;
1324};
1325
1326/* Flow control parameters */
1327struct ixgbe_fc_info {
1328 u32 high_water; /* Flow Control High-water */
1329 u32 low_water; /* Flow Control Low-water */
1330 u16 pause_time; /* Flow Control Pause timer */
1331 bool send_xon; /* Flow control send XON */
1332 bool strict_ieee; /* Strict IEEE mode */
1444};
1445
1446/* Flow control parameters */
1447struct ixgbe_fc_info {
1448 u32 high_water; /* Flow Control High-water */
1449 u32 low_water; /* Flow Control Low-water */
1450 u16 pause_time; /* Flow Control Pause timer */
1451 bool send_xon; /* Flow control send XON */
1452 bool strict_ieee; /* Strict IEEE mode */
1333 enum ixgbe_fc_type type; /* Type of flow control */
1334 enum ixgbe_fc_type original_type;
1453 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
1454 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
1335};
1336
1337/* Statistics counters collected by the MAC */
1338struct ixgbe_hw_stats {
1339 u64 crcerrs;
1340 u64 illerrc;
1341 u64 errbc;
1342 u64 mspdc;

--- 67 unchanged lines hidden (view full) ---

1410};
1411
1412struct ixgbe_mac_operations {
1413 s32 (*init_hw)(struct ixgbe_hw *);
1414 s32 (*reset_hw)(struct ixgbe_hw *);
1415 s32 (*start_hw)(struct ixgbe_hw *);
1416 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
1417 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
1455};
1456
1457/* Statistics counters collected by the MAC */
1458struct ixgbe_hw_stats {
1459 u64 crcerrs;
1460 u64 illerrc;
1461 u64 errbc;
1462 u64 mspdc;

--- 67 unchanged lines hidden (view full) ---

1530};
1531
1532struct ixgbe_mac_operations {
1533 s32 (*init_hw)(struct ixgbe_hw *);
1534 s32 (*reset_hw)(struct ixgbe_hw *);
1535 s32 (*start_hw)(struct ixgbe_hw *);
1536 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
1537 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
1538 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
1418 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
1419 s32 (*stop_adapter)(struct ixgbe_hw *);
1420 s32 (*get_bus_info)(struct ixgbe_hw *);
1539 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
1540 s32 (*stop_adapter)(struct ixgbe_hw *);
1541 s32 (*get_bus_info)(struct ixgbe_hw *);
1542 void (*set_lan_id)(struct ixgbe_hw *);
1421 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
1422 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
1423
1424 /* Link */
1425 s32 (*setup_link)(struct ixgbe_hw *);
1426 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1427 bool);
1428 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);

--- 23 unchanged lines hidden (view full) ---

1452 s32 (*init_uta_tables)(struct ixgbe_hw *);
1453
1454 /* Flow Control */
1455 s32 (*setup_fc)(struct ixgbe_hw *, s32);
1456};
1457
1458struct ixgbe_phy_operations {
1459 s32 (*identify)(struct ixgbe_hw *);
1543 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
1544 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
1545
1546 /* Link */
1547 s32 (*setup_link)(struct ixgbe_hw *);
1548 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1549 bool);
1550 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);

--- 23 unchanged lines hidden (view full) ---

1574 s32 (*init_uta_tables)(struct ixgbe_hw *);
1575
1576 /* Flow Control */
1577 s32 (*setup_fc)(struct ixgbe_hw *, s32);
1578};
1579
1580struct ixgbe_phy_operations {
1581 s32 (*identify)(struct ixgbe_hw *);
1582 s32 (*identify_sfp)(struct ixgbe_hw *);
1460 s32 (*reset)(struct ixgbe_hw *);
1461 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
1462 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
1463 s32 (*setup_link)(struct ixgbe_hw *);
1464 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1465 bool);
1466 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
1467 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
1583 s32 (*reset)(struct ixgbe_hw *);
1584 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
1585 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
1586 s32 (*setup_link)(struct ixgbe_hw *);
1587 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1588 bool);
1589 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
1590 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
1591 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
1592 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
1593 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
1594 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
1468};
1469
1470struct ixgbe_eeprom_info {
1471 struct ixgbe_eeprom_operations ops;
1472 enum ixgbe_eeprom_type type;
1473 u32 semaphore_delay;
1474 u16 word_size;
1475 u16 address_bits;

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1483 s32 mc_filter_type;
1484 u32 mcft_size;
1485 u32 vft_size;
1486 u32 num_rar_entries;
1487 u32 max_tx_queues;
1488 u32 max_rx_queues;
1489 u32 link_attach_type;
1490 u32 link_mode_select;
1595};
1596
1597struct ixgbe_eeprom_info {
1598 struct ixgbe_eeprom_operations ops;
1599 enum ixgbe_eeprom_type type;
1600 u32 semaphore_delay;
1601 u16 word_size;
1602 u16 address_bits;

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1610 s32 mc_filter_type;
1611 u32 mcft_size;
1612 u32 vft_size;
1613 u32 num_rar_entries;
1614 u32 max_tx_queues;
1615 u32 max_rx_queues;
1616 u32 link_attach_type;
1617 u32 link_mode_select;
1618 u32 link_kx4_kx_supp;
1491 bool link_settings_loaded;
1492 bool autoneg;
1619 bool link_settings_loaded;
1620 bool autoneg;
1493 bool autoneg_failed;
1621 bool autoneg_succeeded;
1494};
1495
1496struct ixgbe_phy_info {
1497 struct ixgbe_phy_operations ops;
1498 enum ixgbe_phy_type type;
1499 u32 addr;
1500 u32 id;
1622};
1623
1624struct ixgbe_phy_info {
1625 struct ixgbe_phy_operations ops;
1626 enum ixgbe_phy_type type;
1627 u32 addr;
1628 u32 id;
1629 enum ixgbe_sfp_type sfp_type;
1501 u32 revision;
1502 enum ixgbe_media_type media_type;
1503 bool reset_disable;
1504 ixgbe_autoneg_advertised autoneg_advertised;
1505 bool autoneg_wait_to_complete;
1630 u32 revision;
1631 enum ixgbe_media_type media_type;
1632 bool reset_disable;
1633 ixgbe_autoneg_advertised autoneg_advertised;
1634 bool autoneg_wait_to_complete;
1635 bool multispeed_fiber;
1506};
1507
1508struct ixgbe_hw {
1509 u8 *hw_addr;
1510 void *back;
1511 struct ixgbe_mac_info mac;
1512 struct ixgbe_addr_filter_info addr_ctrl;
1513 struct ixgbe_fc_info fc;

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1518 u16 vendor_id;
1519 u16 subsystem_device_id;
1520 u16 subsystem_vendor_id;
1521 u8 revision_id;
1522 bool adapter_stopped;
1523};
1524
1525#define ixgbe_call_func(hw, func, params, error) \
1636};
1637
1638struct ixgbe_hw {
1639 u8 *hw_addr;
1640 void *back;
1641 struct ixgbe_mac_info mac;
1642 struct ixgbe_addr_filter_info addr_ctrl;
1643 struct ixgbe_fc_info fc;

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1648 u16 vendor_id;
1649 u16 subsystem_device_id;
1650 u16 subsystem_vendor_id;
1651 u8 revision_id;
1652 bool adapter_stopped;
1653};
1654
1655#define ixgbe_call_func(hw, func, params, error) \
1526 (func != NULL) ? func params: error
1656 (func != NULL) ? func params : error
1527
1528/* Error Codes */
1529#define IXGBE_SUCCESS 0
1530#define IXGBE_ERR_EEPROM -1
1531#define IXGBE_ERR_EEPROM_CHECKSUM -2
1532#define IXGBE_ERR_PHY -3
1533#define IXGBE_ERR_CONFIG -4
1534#define IXGBE_ERR_PARAM -5

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1539#define IXGBE_ERR_INVALID_MAC_ADDR -10
1540#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
1541#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
1542#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
1543#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
1544#define IXGBE_ERR_RESET_FAILED -15
1545#define IXGBE_ERR_SWFW_SYNC -16
1546#define IXGBE_ERR_PHY_ADDR_INVALID -17
1657
1658/* Error Codes */
1659#define IXGBE_SUCCESS 0
1660#define IXGBE_ERR_EEPROM -1
1661#define IXGBE_ERR_EEPROM_CHECKSUM -2
1662#define IXGBE_ERR_PHY -3
1663#define IXGBE_ERR_CONFIG -4
1664#define IXGBE_ERR_PARAM -5

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1669#define IXGBE_ERR_INVALID_MAC_ADDR -10
1670#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
1671#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
1672#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
1673#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
1674#define IXGBE_ERR_RESET_FAILED -15
1675#define IXGBE_ERR_SWFW_SYNC -16
1676#define IXGBE_ERR_PHY_ADDR_INVALID -17
1677#define IXGBE_ERR_I2C -18
1678#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
1679#define IXGBE_ERR_SFP_NOT_PRESENT -20
1547#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1548
1549#define UNREFERENCED_PARAMETER(_p)
1550
1551#endif /* _IXGBE_TYPE_H_ */
1680#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1681
1682#define UNREFERENCED_PARAMETER(_p)
1683
1684#endif /* _IXGBE_TYPE_H_ */