33c33
< /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 181003 2008-07-30 18:15:18Z jfv $*/
---
> /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 185352 2008-11-26 23:41:18Z jfv $*/
43a44
> #define IXGBE_DEV_ID_82598 0x10B6
47c48
< #define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10D7
---
> #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
49a51,52
> #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
> #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
81c84,86
< #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4)))
---
> #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
> (0x012300 + ((_i) * 4)))
> #define IXGBE_EITR_ITR_INT_MASK 0x00000FFF
97,102c102,113
< #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40)))
< #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40)))
< #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40)))
< #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40)))
< #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40)))
< #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40)))
---
> #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
> (0x0D000 + ((_i - 64) * 0x40)))
> #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
> (0x0D004 + ((_i - 64) * 0x40)))
> #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
> (0x0D008 + ((_i - 64) * 0x40)))
> #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
> (0x0D010 + ((_i - 64) * 0x40)))
> #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
> (0x0D018 + ((_i - 64) * 0x40)))
> #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
> (0x0D028 + ((_i - 64) * 0x40)))
121,122c132
< #define IXGBE_RDRXCTL 0x02F00
< #define IXGBE_RDRXCTRL_RSC_PUSH 0x80
---
> #define IXGBE_RDRXCTL 0x02F00
131a142,143
> #define IXGBE_DRECCCTL 0x02F08
> #define IXGBE_DRECCCTL_DISABLE 0
134,135c146,149
< #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8)))
< #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8)))
---
> #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
> (0x0A200 + ((_i) * 8)))
> #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
> (0x0A204 + ((_i) * 8)))
137c151,152
< #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4)))
---
> #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
> (0x0EA00 + ((_i) * 4)))
167c182
< #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) /* 8 of these */
---
> #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
178a194
>
181c197,199
< #define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */
---
> #define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
> #define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
> * Filter Table */
183c201,259
< /* Music registers */
---
> #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
> #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
>
> /* Each Flexible Filter is at most 128 (0x80) bytes in length */
> #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
> #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
> #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
>
> /* Definitions for power management and wakeup registers */
> /* Wake Up Control */
> #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
> #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
> #define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/
>
> /* Wake Up Filter Control */
> #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
> #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
> #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
> #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
> #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
> #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
> #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
> #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
> #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
>
> #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
> #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
> #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
> #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
> #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
> #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
> #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
> #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
> #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
> #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
> #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
>
> /* Wake Up Status */
> #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
> #define IXGBE_WUS_MAG IXGBE_WUFC_MAG
> #define IXGBE_WUS_EX IXGBE_WUFC_EX
> #define IXGBE_WUS_MC IXGBE_WUFC_MC
> #define IXGBE_WUS_BC IXGBE_WUFC_BC
> #define IXGBE_WUS_ARP IXGBE_WUFC_ARP
> #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
> #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
> #define IXGBE_WUS_MNG IXGBE_WUFC_MNG
> #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
> #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
> #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
> #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
> #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
> #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
> #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
>
> /* Wake Up Packet Length */
> #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
>
> /* DCB registers */
195,209d270
< /* LinkSec (MacSec) Registers */
< #define IXGBE_LSECTXCTRL 0x08A04
< #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
< #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
< #define IXGBE_LSECTXSA 0x08A10
< #define IXGBE_LSECTXPN0 0x08A14
< #define IXGBE_LSECTXPN1 0x08A18
< #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
< #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
< #define IXGBE_LSECRXCTRL 0x08F04
< #define IXGBE_LSECRXSCL 0x08F08
< #define IXGBE_LSECRXSCH 0x08F0C
< #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
< #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
< #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
211,221d271
< /* IpSec Registers */
< #define IXGBE_IPSTXIDX 0x08900
< #define IXGBE_IPSTXSALT 0x08904
< #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
< #define IXGBE_IPSRXIDX 0x08E00
< #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
< #define IXGBE_IPSRXSPI 0x08E14
< #define IXGBE_IPSRXIPIDX 0x08E18
< #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
< #define IXGBE_IPSRXSALT 0x08E2C
< #define IXGBE_IPSRXMOD 0x08E30
223d272
<
277,278c326,328
< #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
< #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4)))
---
> #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
> #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
> (0x08600 + ((_i) * 4)))
421a472
> #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
481a533
>
487a540
> #define IXGBE_TWINAX_DEV 1
507a561,564
> #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
> #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
> #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
>
522a580
> #define ATH_PHY_ID 0x03429050
526a585,596
> /* Special PHY Init Routine */
> #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
> #define IXGBE_PHY_INIT_END_NL 0xFFFF
> #define IXGBE_CONTROL_MASK_NL 0xF000
> #define IXGBE_DATA_MASK_NL 0x0FFF
> #define IXGBE_CONTROL_SHIFT_NL 12
> #define IXGBE_DELAY_NL 0
> #define IXGBE_DATA_NL 1
> #define IXGBE_CONTROL_NL 0x000F
> #define IXGBE_CONTROL_EOL_NL 0x0FFF
> #define IXGBE_CONTROL_SOL_NL 0x0000
>
588,589c658,659
< #define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
< #define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
---
> #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
> #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
599,600c669,670
< #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
< #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
---
> #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
> #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
697,698c767,769
< #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
< #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
---
> #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
> #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
> #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
704,705c775,778
< #define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */
< #define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */
---
> #define IXGBE_ESDP_SDP1 0x00000001
> #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
> #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
> #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
707c780
< #define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */
---
> #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
729a803
> #define IXGBE_AUTOC_KX4_KX_SUPP 0xC0000000
741,747c815,821
< #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
---
> #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
749,750c823,824
< #define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
< #define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
---
> #define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
> #define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
1021a1096
>
1065d1139
<
1097d1170
< #define __le8 u8
1102a1176,1180
> #ifndef __be16
> /* Big Endian defines */
> #define __be16 u16
> #define __be32 u32
> #define __be64 u64
1103a1182
> #endif
1112,1113c1191,1192
< __le8 cso; /* Checksum offset */
< __le8 cmd; /* Descriptor control */
---
> u8 cso; /* Checksum offset */
> u8 cmd; /* Descriptor control */
1119,1120c1198,1199
< __le8 status; /* Descriptor status */
< __le8 css; /* Checksum start */
---
> u8 status; /* Descriptor status */
> u8 css; /* Checksum start */
1145,1146c1224,1225
< __le8 status; /* Descriptor status */
< __le8 errors; /* Descriptor Errors */
---
> u8 status; /* Descriptor status */
> u8 errors; /* Descriptor Errors */
1224c1303
< #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
---
> #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
1238a1318,1333
> /* Physical layer type */
> typedef u32 ixgbe_physical_layer;
> #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
> #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
> #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
> #define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004
> #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
> #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
> #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
> #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
> #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
> #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
> #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
> #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
>
>
1255a1351,1356
> ixgbe_phy_nl,
> ixgbe_phy_tw_tyco,
> ixgbe_phy_tw_unknown,
> ixgbe_phy_sfp_avago,
> ixgbe_phy_sfp_ftl,
> ixgbe_phy_sfp_unknown,
1258a1360,1376
> /*
> * SFP+ module type IDs:
> *
> * ID Module Type
> * =============
> * 0 SFP_DA_CU
> * 1 SFP_SR
> * 2 SFP_LR
> */
> enum ixgbe_sfp_type {
> ixgbe_sfp_type_da_cu = 0,
> ixgbe_sfp_type_sr = 1,
> ixgbe_sfp_type_lr = 2,
> ixgbe_sfp_type_not_present = 0xFFFE,
> ixgbe_sfp_type_unknown = 0xFFFF
> };
>
1268c1386
< enum ixgbe_fc_type {
---
> enum ixgbe_fc_mode {
1323a1442,1443
>
> u16 func;
1333,1334c1453,1454
< enum ixgbe_fc_type type; /* Type of flow control */
< enum ixgbe_fc_type original_type;
---
> enum ixgbe_fc_mode current_mode; /* FC mode in effect */
> enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
1417a1538
> u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
1420a1542
> void (*set_lan_id)(struct ixgbe_hw *);
1459a1582
> s32 (*identify_sfp)(struct ixgbe_hw *);
1467a1591,1594
> s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
> s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
> s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
> s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
1490a1618
> u32 link_kx4_kx_supp;
1493c1621
< bool autoneg_failed;
---
> bool autoneg_succeeded;
1500a1629
> enum ixgbe_sfp_type sfp_type;
1505a1635
> bool multispeed_fiber;
1526c1656
< (func != NULL) ? func params: error
---
> (func != NULL) ? func params : error
1546a1677,1679
> #define IXGBE_ERR_I2C -18
> #define IXGBE_ERR_SFP_NOT_SUPPORTED -19
> #define IXGBE_ERR_SFP_NOT_PRESENT -20
< /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 181003 2008-07-30 18:15:18Z jfv $*/
---
> /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 185352 2008-11-26 23:41:18Z jfv $*/
43a44
> #define IXGBE_DEV_ID_82598 0x10B6
47c48
< #define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10D7
---
> #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
49a51,52
> #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
> #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
81c84,86
< #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4)))
---
> #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
> (0x012300 + ((_i) * 4)))
> #define IXGBE_EITR_ITR_INT_MASK 0x00000FFF
97,102c102,113
< #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40)))
< #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40)))
< #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40)))
< #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40)))
< #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40)))
< #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40)))
---
> #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
> (0x0D000 + ((_i - 64) * 0x40)))
> #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
> (0x0D004 + ((_i - 64) * 0x40)))
> #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
> (0x0D008 + ((_i - 64) * 0x40)))
> #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
> (0x0D010 + ((_i - 64) * 0x40)))
> #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
> (0x0D018 + ((_i - 64) * 0x40)))
> #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
> (0x0D028 + ((_i - 64) * 0x40)))
121,122c132
< #define IXGBE_RDRXCTL 0x02F00
< #define IXGBE_RDRXCTRL_RSC_PUSH 0x80
---
> #define IXGBE_RDRXCTL 0x02F00
131a142,143
> #define IXGBE_DRECCCTL 0x02F08
> #define IXGBE_DRECCCTL_DISABLE 0
134,135c146,149
< #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8)))
< #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8)))
---
> #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
> (0x0A200 + ((_i) * 8)))
> #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
> (0x0A204 + ((_i) * 8)))
137c151,152
< #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4)))
---
> #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
> (0x0EA00 + ((_i) * 4)))
167c182
< #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) /* 8 of these */
---
> #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
178a194
>
181c197,199
< #define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */
---
> #define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
> #define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
> * Filter Table */
183c201,259
< /* Music registers */
---
> #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
> #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
>
> /* Each Flexible Filter is at most 128 (0x80) bytes in length */
> #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
> #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
> #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
>
> /* Definitions for power management and wakeup registers */
> /* Wake Up Control */
> #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
> #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
> #define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/
>
> /* Wake Up Filter Control */
> #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
> #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
> #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
> #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
> #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
> #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
> #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
> #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
> #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
>
> #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
> #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
> #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
> #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
> #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
> #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
> #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
> #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
> #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
> #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
> #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
>
> /* Wake Up Status */
> #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
> #define IXGBE_WUS_MAG IXGBE_WUFC_MAG
> #define IXGBE_WUS_EX IXGBE_WUFC_EX
> #define IXGBE_WUS_MC IXGBE_WUFC_MC
> #define IXGBE_WUS_BC IXGBE_WUFC_BC
> #define IXGBE_WUS_ARP IXGBE_WUFC_ARP
> #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
> #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
> #define IXGBE_WUS_MNG IXGBE_WUFC_MNG
> #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
> #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
> #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
> #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
> #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
> #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
> #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
>
> /* Wake Up Packet Length */
> #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
>
> /* DCB registers */
195,209d270
< /* LinkSec (MacSec) Registers */
< #define IXGBE_LSECTXCTRL 0x08A04
< #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
< #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
< #define IXGBE_LSECTXSA 0x08A10
< #define IXGBE_LSECTXPN0 0x08A14
< #define IXGBE_LSECTXPN1 0x08A18
< #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
< #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
< #define IXGBE_LSECRXCTRL 0x08F04
< #define IXGBE_LSECRXSCL 0x08F08
< #define IXGBE_LSECRXSCH 0x08F0C
< #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
< #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
< #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
211,221d271
< /* IpSec Registers */
< #define IXGBE_IPSTXIDX 0x08900
< #define IXGBE_IPSTXSALT 0x08904
< #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
< #define IXGBE_IPSRXIDX 0x08E00
< #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
< #define IXGBE_IPSRXSPI 0x08E14
< #define IXGBE_IPSRXIPIDX 0x08E18
< #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
< #define IXGBE_IPSRXSALT 0x08E2C
< #define IXGBE_IPSRXMOD 0x08E30
223d272
<
277,278c326,328
< #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
< #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4)))
---
> #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
> #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
> (0x08600 + ((_i) * 4)))
421a472
> #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
481a533
>
487a540
> #define IXGBE_TWINAX_DEV 1
507a561,564
> #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
> #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
> #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
>
522a580
> #define ATH_PHY_ID 0x03429050
526a585,596
> /* Special PHY Init Routine */
> #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
> #define IXGBE_PHY_INIT_END_NL 0xFFFF
> #define IXGBE_CONTROL_MASK_NL 0xF000
> #define IXGBE_DATA_MASK_NL 0x0FFF
> #define IXGBE_CONTROL_SHIFT_NL 12
> #define IXGBE_DELAY_NL 0
> #define IXGBE_DATA_NL 1
> #define IXGBE_CONTROL_NL 0x000F
> #define IXGBE_CONTROL_EOL_NL 0x0FFF
> #define IXGBE_CONTROL_SOL_NL 0x0000
>
588,589c658,659
< #define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
< #define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
---
> #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
> #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
599,600c669,670
< #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
< #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
---
> #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
> #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
697,698c767,769
< #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
< #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
---
> #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
> #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
> #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
704,705c775,778
< #define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */
< #define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */
---
> #define IXGBE_ESDP_SDP1 0x00000001
> #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
> #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
> #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
707c780
< #define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */
---
> #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
729a803
> #define IXGBE_AUTOC_KX4_KX_SUPP 0xC0000000
741,747c815,821
< #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
< #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
---
> #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
> #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
749,750c823,824
< #define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
< #define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
---
> #define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
> #define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
1021a1096
>
1065d1139
<
1097d1170
< #define __le8 u8
1102a1176,1180
> #ifndef __be16
> /* Big Endian defines */
> #define __be16 u16
> #define __be32 u32
> #define __be64 u64
1103a1182
> #endif
1112,1113c1191,1192
< __le8 cso; /* Checksum offset */
< __le8 cmd; /* Descriptor control */
---
> u8 cso; /* Checksum offset */
> u8 cmd; /* Descriptor control */
1119,1120c1198,1199
< __le8 status; /* Descriptor status */
< __le8 css; /* Checksum start */
---
> u8 status; /* Descriptor status */
> u8 css; /* Checksum start */
1145,1146c1224,1225
< __le8 status; /* Descriptor status */
< __le8 errors; /* Descriptor Errors */
---
> u8 status; /* Descriptor status */
> u8 errors; /* Descriptor Errors */
1224c1303
< #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
---
> #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
1238a1318,1333
> /* Physical layer type */
> typedef u32 ixgbe_physical_layer;
> #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
> #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
> #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
> #define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004
> #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
> #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
> #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
> #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
> #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
> #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
> #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
> #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
>
>
1255a1351,1356
> ixgbe_phy_nl,
> ixgbe_phy_tw_tyco,
> ixgbe_phy_tw_unknown,
> ixgbe_phy_sfp_avago,
> ixgbe_phy_sfp_ftl,
> ixgbe_phy_sfp_unknown,
1258a1360,1376
> /*
> * SFP+ module type IDs:
> *
> * ID Module Type
> * =============
> * 0 SFP_DA_CU
> * 1 SFP_SR
> * 2 SFP_LR
> */
> enum ixgbe_sfp_type {
> ixgbe_sfp_type_da_cu = 0,
> ixgbe_sfp_type_sr = 1,
> ixgbe_sfp_type_lr = 2,
> ixgbe_sfp_type_not_present = 0xFFFE,
> ixgbe_sfp_type_unknown = 0xFFFF
> };
>
1268c1386
< enum ixgbe_fc_type {
---
> enum ixgbe_fc_mode {
1323a1442,1443
>
> u16 func;
1333,1334c1453,1454
< enum ixgbe_fc_type type; /* Type of flow control */
< enum ixgbe_fc_type original_type;
---
> enum ixgbe_fc_mode current_mode; /* FC mode in effect */
> enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
1417a1538
> u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
1420a1542
> void (*set_lan_id)(struct ixgbe_hw *);
1459a1582
> s32 (*identify_sfp)(struct ixgbe_hw *);
1467a1591,1594
> s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
> s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
> s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
> s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
1490a1618
> u32 link_kx4_kx_supp;
1493c1621
< bool autoneg_failed;
---
> bool autoneg_succeeded;
1500a1629
> enum ixgbe_sfp_type sfp_type;
1505a1635
> bool multispeed_fiber;
1526c1656
< (func != NULL) ? func params: error
---
> (func != NULL) ? func params : error
1546a1677,1679
> #define IXGBE_ERR_I2C -18
> #define IXGBE_ERR_SFP_NOT_SUPPORTED -19
> #define IXGBE_ERR_SFP_NOT_PRESENT -20