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< __FBSDID("$FreeBSD: head/sys/dev/ieee488/upd7210.c 202898 2010-01-23 21:33:33Z joerg $");
---
> __FBSDID("$FreeBSD: head/sys/dev/ieee488/upd7210.c 203360 2010-02-01 21:21:10Z joerg $");
56a57
> #include <dev/ieee488/tnt4882.h>
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< u_int isr1, isr2;
---
> u_int isr_1, isr_2, isr_3;
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< isr1 = upd7210_rd(u, ISR1);
< isr2 = upd7210_rd(u, ISR2);
< if (isr1 != 0 || isr2 != 0) {
< if (u->busy == 0 || u->irq == NULL || !u->irq(u, 1)) {
---
> isr_1 = upd7210_rd(u, ISR1);
> isr_2 = upd7210_rd(u, ISR2);
> if (u->use_fifo) {
> isr_3 = bus_read_1(u->reg_res[0], isr3);
> } else {
> isr_3 = 0;
> }
> if (isr_1 != 0 || isr_2 != 0 || isr_3 != 0) {
> if (u->busy == 0 || u->irq == NULL || !u->irq(u, isr_3)) {
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< gpib_l_irq(struct upd7210 *u, int intr __unused)
---
> gpib_l_irq(struct upd7210 *u, int isr_3)
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> int have_data = 0;
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< if (u->rreg[ISR1] & 1) {
---
> if (u->use_fifo) {
> /* TNT5004 or TNT4882 in FIFO mode */
> if (isr_3 & 0x04) {
> /* FIFO not empty */
> i = bus_read_1(u->reg_res[0], fifob);
> have_data = 1;
> bus_write_1(u->reg_res[0], cnt0, -1);
> bus_write_1(u->reg_res[0], cnt1, (-1) >> 8);
> bus_write_1(u->reg_res[0], cnt2, (-1) >> 16);
> bus_write_1(u->reg_res[0], cnt3, (-1) >> 24);
> bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
> }
> } else if (u->rreg[ISR1] & 1) {
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> have_data = 1;
> }
>
> if (have_data) {
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< if (i < 8)
< upd7210_wr(u, IMR1, 0);
---
> if (i < 8) {
> if (u->use_fifo)
> bus_write_1(u->reg_res[0], imr3, 0x00);
> else
> upd7210_wr(u, IMR1, 0);
> }
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< upd7210_wr(u, AUXMR, AUXMR_CRST);
---
> upd7210_wr(u, AUXMR, AUXMR_CRST); /* chip reset */
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< upd7210_wr(u, AUXMR, C_ICR | 8);
---
> upd7210_wr(u, AUXMR, C_ICR | 8); /* 8 MHz clock */
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< upd7210_wr(u, ADR, 0x60);
< upd7210_wr(u, ADR, 0xe0);
< upd7210_wr(u, ADMR, 0x70);
< upd7210_wr(u, AUXMR, AUXMR_PON);
< upd7210_wr(u, IMR1, 0x01);
---
> upd7210_wr(u, ADR, 0x60); /* ADR0: disable listener and talker 0 */
> upd7210_wr(u, ADR, 0xe0); /* ADR1: disable listener and talker 1 */
> upd7210_wr(u, ADMR, 0x70); /* listen-only (lon) */
> upd7210_wr(u, AUXMR, AUXMR_PON); /* immediate execute power-on (pon) */
> if (u->use_fifo) {
> /* TNT5004 or TNT4882 in FIFO mode */
> bus_write_1(u->reg_res[0], cmdr, 0x10); /* reset FIFO */
> bus_write_1(u->reg_res[0], cfg, 0x20); /* xfer IN, 8-bit FIFO */
> bus_write_1(u->reg_res[0], cnt0, -1);
> bus_write_1(u->reg_res[0], cnt1, (-1) >> 8);
> bus_write_1(u->reg_res[0], cnt2, (-1) >> 16);
> bus_write_1(u->reg_res[0], cnt3, (-1) >> 24);
> bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
> bus_write_1(u->reg_res[0], imr3, 0x04); /* NEF IE */
> } else {
> /* �PD7210/NAT7210, or TNT4882 in non-FIFO mode */
> upd7210_wr(u, IMR1, 0x01); /* data in interrupt enable */
> }
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> if (u->use_fifo) {
> /* TNT5004 or TNT4882 in FIFO mode */
> bus_write_1(u->reg_res[0], cmdr, 0x22); /* soft RESET */
> bus_write_1(u->reg_res[0], imr3, 0x00);
> }
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< if (u->wreg[IMR1] == 0)
< upd7210_wr(u, IMR1, 0x01);
---
> if (u->use_fifo) {
> bus_write_1(u->reg_res[0], imr3, 0x04); /* NFF IE */
> } else {
> if (u->wreg[IMR1] == 0)
> upd7210_wr(u, IMR1, 0x01);
> }