2a3
> * Copyright (c) 2010 Joerg Wunsch <joerg@FreeBSD.org>
35a37,38
> * "National Instruments GPIB-PCII/PCIIA" (in PCIIa mode)
> * "Axiom AX5488"
40c43
< __FBSDID("$FreeBSD: head/sys/dev/ieee488/pcii.c 166914 2007-02-23 19:34:52Z imp $");
---
> __FBSDID("$FreeBSD: head/sys/dev/ieee488/pcii.c 202870 2010-01-23 07:54:06Z joerg $");
59c62
< struct resource *res[3];
---
> struct resource *res[11];
81a85,92
> { SYS_RES_IOPORT, 1, RF_ACTIVE},
> { SYS_RES_IOPORT, 2, RF_ACTIVE},
> { SYS_RES_IOPORT, 3, RF_ACTIVE},
> { SYS_RES_IOPORT, 4, RF_ACTIVE},
> { SYS_RES_IOPORT, 5, RF_ACTIVE},
> { SYS_RES_IOPORT, 6, RF_ACTIVE},
> { SYS_RES_IOPORT, 7, RF_ACTIVE},
> { SYS_RES_IOPORT, 8, RF_ACTIVE | RF_SHAREABLE},
95c106
< u_long start, count;
---
> u_long start, count, addr;
105c116,143
< if ((start & 0x3ff) != 0x2e1)
---
> /*
> * The PCIIA decodes a fixed pattern of 0x2e1 for the lower 10
> * address bits A0 ... A9. Bits A10 through A12 are used by
> * the �PD7210 register select lines. This makes the
> * individual 7210 register being 0x400 bytes apart in the ISA
> * bus address space. Address bits A13 and A14 are compared
> * to a DIP switch setting on the card, allowing for up to 4
> * different cards being installed (at base addresses 0x2e1,
> * 0x22e1, 0x42e1, and 0x62e1, respectively). A15 has been
> * used to select an optional on-board time-of-day clock chip
> * (MM58167A) on the original PCIIA rather than the �PD7210
> * (which is not implemented on later boards). The
> * documentation states the respective addresses for that chip
> * should be handled as reserved addresses, which we don't do
> * (right now). Finally, the IO addresses 0x2f0 ... 0x2f7 for
> * a "special interrupt handling feature" (re-enable
> * interrupts so the IRQ can be shared).
> *
> * Usually, the user will only set the base address in the
> * device hints, so we handle the rest here.
> *
> * (Source: GPIB-PCIIA Technical Reference Manual, September
> * 1989 Edition, National Instruments.)
> */
> if ((start & 0x3ff) != 0x2e1) {
> printf("pcii_probe: PCIIA base address 0x%lx not "
> "0x2e1/0x22e1/0x42e1/0x62e1\n",
> start);
107,108c145,155
< count = 1;
< if (bus_set_resource(dev, SYS_RES_IOPORT, rid, start, count) != 0)
---
> }
>
> for (rid = 0, addr = start; rid < 8; rid++, addr += 0x400) {
> if (bus_set_resource(dev, SYS_RES_IOPORT, rid, addr, 1) != 0) {
> printf("pcii_probe: could not set IO port 0x%lx\n",
> addr);
> return (ENXIO);
> }
> }
> if (bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &count) != 0) {
> printf("pcii_probe: cannot obtain IRQ level\n");
109a157,168
> }
> if (start > 7) {
> printf("pcii_probe: IRQ level %lu too high\n", start);
> return ENXIO;
> }
>
> if (bus_set_resource(dev, SYS_RES_IOPORT, 8, 0x2f0 + start, 1) != 0) {
> printf("pcii_probe: could not set IO port 0x%3lx\n",
> 0x2f0 + start);
> return (ENXIO);
> }
>
111c170,171
< if (error)
---
> if (error) {
> printf("pcii_probe: Could not allocate resources\n");
112a173
> }
113a175,179
> /*
> * Perform some basic tests on the �PD7210 registers. At
> * least *some* register must read different from 0x00 or
> * 0xff.
> */
115c181
< j = bus_read_1(sc->res[2], i * 0x400);
---
> j = bus_read_1(sc->res[2 + i], 0);
118a185
> /* SPSR/SPMR read/write test */
120,121c187,188
< bus_write_1(sc->res[2], 3 * 0x400, 0x55);
< if (bus_read_1(sc->res[2], 3 * 0x400) != 0x55)
---
> bus_write_1(sc->res[2 + 3], 0, 0x55);
> if (bus_read_1(sc->res[2 + 3], 0) != 0x55)
125,126c192,193
< bus_write_1(sc->res[2], 3 * 0x400, 0xaa);
< if (bus_read_1(sc->res[2], 3 * 0x400) != 0xaa)
---
> bus_write_1(sc->res[2 + 3], 0, 0xaa);
> if (bus_read_1(sc->res[2 + 3], 0) != 0xaa)
128a196,198
> if (error)
> printf("pcii_probe: probe failure\n");
>
136a207
> u_long start, count;
146a218,222
> if (bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &count) != 0) {
> printf("pcii_attach: cannot obtain IRQ number\n");
> return ENXIO;
> }
>
160,161c236
< sc->upd7210.reg_res[rid] = sc->res[2];
< sc->upd7210.reg_offset[rid] = 0x400 * rid;
---
> sc->upd7210.reg_res[rid] = sc->res[2 + rid];
162a238
> sc->upd7210.irq_clear_res = sc->res[10];