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hwpmc_core.c (254476) hwpmc_core.c (254824)
1/*-
2 * Copyright (c) 2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * Intel Core PMCs.
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * Intel Core PMCs.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_core.c 254476 2013-08-18 06:08:52Z adrian $");
32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_core.c 254824 2013-08-25 02:07:28Z adrian $");
33
34#include <sys/param.h>
35#include <sys/bus.h>
36#include <sys/pmc.h>
37#include <sys/pmckern.h>
38#include <sys/systm.h>
39
40#include <machine/intr_machdep.h>
41#include <machine/apicvar.h>
42#include <machine/cpu.h>
43#include <machine/cpufunc.h>
44#include <machine/md_var.h>
45#include <machine/specialreg.h>
46
47#define CORE_CPUID_REQUEST 0xA
48#define CORE_CPUID_REQUEST_SIZE 0x4
49#define CORE_CPUID_EAX 0x0
50#define CORE_CPUID_EBX 0x1
51#define CORE_CPUID_ECX 0x2
52#define CORE_CPUID_EDX 0x3
53
54#define IAF_PMC_CAPS \
55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \
56 PMC_CAP_USER | PMC_CAP_SYSTEM)
57#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
58
59#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
62
63#define EV_IS_NOTARCH 0
64#define EV_IS_ARCH_SUPP 1
65#define EV_IS_ARCH_NOTSUPP -1
66
67/*
68 * "Architectural" events defined by Intel. The values of these
69 * symbols correspond to positions in the bitmask returned by
70 * the CPUID.0AH instruction.
71 */
72enum core_arch_events {
73 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
74 CORE_AE_BRANCH_MISSES_RETIRED = 6,
75 CORE_AE_INSTRUCTION_RETIRED = 1,
76 CORE_AE_LLC_MISSES = 4,
77 CORE_AE_LLC_REFERENCE = 3,
78 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
79 CORE_AE_UNHALTED_CORE_CYCLES = 0
80};
81
82static enum pmc_cputype core_cputype;
83
84struct core_cpu {
85 volatile uint32_t pc_resync;
86 volatile uint32_t pc_iafctrl; /* Fixed function control. */
87 volatile uint64_t pc_globalctrl; /* Global control register. */
88 struct pmc_hw pc_corepmcs[];
89};
90
91static struct core_cpu **core_pcpu;
92
93static uint32_t core_architectural_events;
94static uint64_t core_pmcmask;
95
96static int core_iaf_ri; /* relative index of fixed counters */
97static int core_iaf_width;
98static int core_iaf_npmc;
99
100static int core_iap_width;
101static int core_iap_npmc;
102
103static int
104core_pcpu_noop(struct pmc_mdep *md, int cpu)
105{
106 (void) md;
107 (void) cpu;
108 return (0);
109}
110
111static int
112core_pcpu_init(struct pmc_mdep *md, int cpu)
113{
114 struct pmc_cpu *pc;
115 struct core_cpu *cc;
116 struct pmc_hw *phw;
117 int core_ri, n, npmc;
118
119 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
120 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
121
122 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu);
123
124 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
125 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
126
127 if (core_cputype != PMC_CPU_INTEL_CORE)
128 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
129
130 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
131 M_PMC, M_WAITOK | M_ZERO);
132
133 core_pcpu[cpu] = cc;
134 pc = pmc_pcpu[cpu];
135
136 KASSERT(pc != NULL && cc != NULL,
137 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
138
139 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
140 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
141 PMC_PHW_CPU_TO_STATE(cpu) |
142 PMC_PHW_INDEX_TO_STATE(n + core_ri);
143 phw->phw_pmc = NULL;
144 pc->pc_hwpmcs[n + core_ri] = phw;
145 }
146
147 return (0);
148}
149
150static int
151core_pcpu_fini(struct pmc_mdep *md, int cpu)
152{
153 int core_ri, n, npmc;
154 struct pmc_cpu *pc;
155 struct core_cpu *cc;
156 uint64_t msr = 0;
157
158 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
159 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
160
161 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
162
163 if ((cc = core_pcpu[cpu]) == NULL)
164 return (0);
165
166 core_pcpu[cpu] = NULL;
167
168 pc = pmc_pcpu[cpu];
169
170 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
171 cpu));
172
173 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
174 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
175
176 for (n = 0; n < npmc; n++) {
177 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
178 wrmsr(IAP_EVSEL0 + n, msr);
179 }
180
181 if (core_cputype != PMC_CPU_INTEL_CORE) {
182 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
183 wrmsr(IAF_CTRL, msr);
184 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
185 }
186
187 for (n = 0; n < npmc; n++)
188 pc->pc_hwpmcs[n + core_ri] = NULL;
189
190 free(cc, M_PMC);
191
192 return (0);
193}
194
195/*
196 * Fixed function counters.
197 */
198
199static pmc_value_t
200iaf_perfctr_value_to_reload_count(pmc_value_t v)
201{
202 v &= (1ULL << core_iaf_width) - 1;
203 return (1ULL << core_iaf_width) - v;
204}
205
206static pmc_value_t
207iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
208{
209 return (1ULL << core_iaf_width) - rlc;
210}
211
212static int
213iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
214 const struct pmc_op_pmcallocate *a)
215{
216 enum pmc_event ev;
217 uint32_t caps, flags, validflags;
218
219 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
220 ("[core,%d] illegal CPU %d", __LINE__, cpu));
221
222 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
223
224 if (ri < 0 || ri > core_iaf_npmc)
225 return (EINVAL);
226
227 caps = a->pm_caps;
228
229 if (a->pm_class != PMC_CLASS_IAF ||
230 (caps & IAF_PMC_CAPS) != caps)
231 return (EINVAL);
232
233 ev = pm->pm_event;
234 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST)
235 return (EINVAL);
236
237 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
238 return (EINVAL);
239 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
240 return (EINVAL);
241 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
242 return (EINVAL);
243
244 flags = a->pm_md.pm_iaf.pm_iaf_flags;
245
246 validflags = IAF_MASK;
247
248 if (core_cputype != PMC_CPU_INTEL_ATOM)
249 validflags &= ~IAF_ANY;
250
251 if ((flags & ~validflags) != 0)
252 return (EINVAL);
253
254 if (caps & PMC_CAP_INTERRUPT)
255 flags |= IAF_PMI;
256 if (caps & PMC_CAP_SYSTEM)
257 flags |= IAF_OS;
258 if (caps & PMC_CAP_USER)
259 flags |= IAF_USR;
260 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
261 flags |= (IAF_OS | IAF_USR);
262
263 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
264
265 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx",
266 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
267
268 return (0);
269}
270
271static int
272iaf_config_pmc(int cpu, int ri, struct pmc *pm)
273{
274 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
275 ("[core,%d] illegal CPU %d", __LINE__, cpu));
276
277 KASSERT(ri >= 0 && ri < core_iaf_npmc,
278 ("[core,%d] illegal row-index %d", __LINE__, ri));
279
280 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
281
282 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
283 cpu));
284
285 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
286
287 return (0);
288}
289
290static int
291iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
292{
293 int error;
294 struct pmc_hw *phw;
295 char iaf_name[PMC_NAME_MAX];
296
297 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
298
299 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
300 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
301 NULL)) != 0)
302 return (error);
303
304 pi->pm_class = PMC_CLASS_IAF;
305
306 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
307 pi->pm_enabled = TRUE;
308 *ppmc = phw->phw_pmc;
309 } else {
310 pi->pm_enabled = FALSE;
311 *ppmc = NULL;
312 }
313
314 return (0);
315}
316
317static int
318iaf_get_config(int cpu, int ri, struct pmc **ppm)
319{
320 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
321
322 return (0);
323}
324
325static int
326iaf_get_msr(int ri, uint32_t *msr)
327{
328 KASSERT(ri >= 0 && ri < core_iaf_npmc,
329 ("[iaf,%d] ri %d out of range", __LINE__, ri));
330
331 *msr = IAF_RI_TO_MSR(ri);
332
333 return (0);
334}
335
336static int
337iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
338{
339 struct pmc *pm;
340 pmc_value_t tmp;
341
342 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
343 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
344 KASSERT(ri >= 0 && ri < core_iaf_npmc,
345 ("[core,%d] illegal row-index %d", __LINE__, ri));
346
347 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
348
349 KASSERT(pm,
350 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
351 ri, ri + core_iaf_ri));
352
353 tmp = rdpmc(IAF_RI_TO_MSR(ri));
354
355 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
356 *v = iaf_perfctr_value_to_reload_count(tmp);
357 else
358 *v = tmp;
359
360 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
361 IAF_RI_TO_MSR(ri), *v);
362
363 return (0);
364}
365
366static int
367iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
368{
369 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
370
371 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
372 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
373 KASSERT(ri >= 0 && ri < core_iaf_npmc,
374 ("[core,%d] illegal row-index %d", __LINE__, ri));
375
376 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
377 ("[core,%d] PHW pmc non-NULL", __LINE__));
378
379 return (0);
380}
381
382static int
383iaf_start_pmc(int cpu, int ri)
384{
385 struct pmc *pm;
386 struct core_cpu *iafc;
387 uint64_t msr = 0;
388
389 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
390 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
391 KASSERT(ri >= 0 && ri < core_iaf_npmc,
392 ("[core,%d] illegal row-index %d", __LINE__, ri));
393
394 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
395
396 iafc = core_pcpu[cpu];
397 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
398
399 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
400
401 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
402 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
403
404 do {
405 iafc->pc_resync = 0;
406 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
407 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
408 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
409 IAF_GLOBAL_CTRL_MASK));
410 } while (iafc->pc_resync != 0);
411
412 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
413 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
414 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
415
416 return (0);
417}
418
419static int
420iaf_stop_pmc(int cpu, int ri)
421{
422 uint32_t fc;
423 struct core_cpu *iafc;
424 uint64_t msr = 0;
425
426 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
427
428 iafc = core_pcpu[cpu];
429
430 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
431 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
432 KASSERT(ri >= 0 && ri < core_iaf_npmc,
433 ("[core,%d] illegal row-index %d", __LINE__, ri));
434
435 fc = (IAF_MASK << (ri * 4));
436
437 if (core_cputype != PMC_CPU_INTEL_ATOM)
438 fc &= ~IAF_ANY;
439
440 iafc->pc_iafctrl &= ~fc;
441
442 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
443 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
444 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
445
446 do {
447 iafc->pc_resync = 0;
448 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
449 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
450 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
451 IAF_GLOBAL_CTRL_MASK));
452 } while (iafc->pc_resync != 0);
453
454 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
455 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
456 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
457
458 return (0);
459}
460
461static int
462iaf_write_pmc(int cpu, int ri, pmc_value_t v)
463{
464 struct core_cpu *cc;
465 struct pmc *pm;
466 uint64_t msr;
467
468 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
469 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
470 KASSERT(ri >= 0 && ri < core_iaf_npmc,
471 ("[core,%d] illegal row-index %d", __LINE__, ri));
472
473 cc = core_pcpu[cpu];
474 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
475
476 KASSERT(pm,
477 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
478
479 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
480 v = iaf_reload_count_to_perfctr_value(v);
481
482 /* Turn off fixed counters */
483 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
484 wrmsr(IAF_CTRL, msr);
485
486 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
487
488 /* Turn on fixed counters */
489 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
490 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
491
492 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
493 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
494 (uintmax_t) rdmsr(IAF_CTRL),
495 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
496
497 return (0);
498}
499
500
501static void
502iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
503{
504 struct pmc_classdep *pcd;
505
506 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
507
508 PMCDBG(MDP,INI,1, "%s", "iaf-initialize");
509
510 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
511
512 pcd->pcd_caps = IAF_PMC_CAPS;
513 pcd->pcd_class = PMC_CLASS_IAF;
514 pcd->pcd_num = npmc;
515 pcd->pcd_ri = md->pmd_npmc;
516 pcd->pcd_width = pmcwidth;
517
518 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
519 pcd->pcd_config_pmc = iaf_config_pmc;
520 pcd->pcd_describe = iaf_describe;
521 pcd->pcd_get_config = iaf_get_config;
522 pcd->pcd_get_msr = iaf_get_msr;
523 pcd->pcd_pcpu_fini = core_pcpu_noop;
524 pcd->pcd_pcpu_init = core_pcpu_noop;
525 pcd->pcd_read_pmc = iaf_read_pmc;
526 pcd->pcd_release_pmc = iaf_release_pmc;
527 pcd->pcd_start_pmc = iaf_start_pmc;
528 pcd->pcd_stop_pmc = iaf_stop_pmc;
529 pcd->pcd_write_pmc = iaf_write_pmc;
530
531 md->pmd_npmc += npmc;
532}
533
534/*
535 * Intel programmable PMCs.
536 */
537
538/*
539 * Event descriptor tables.
540 *
541 * For each event id, we track:
542 *
543 * 1. The CPUs that the event is valid for.
544 *
545 * 2. If the event uses a fixed UMASK, the value of the umask field.
546 * If the event doesn't use a fixed UMASK, a mask of legal bits
547 * to check against.
548 */
549
550struct iap_event_descr {
551 enum pmc_event iap_ev;
552 unsigned char iap_evcode;
553 unsigned char iap_umask;
554 unsigned int iap_flags;
555};
556
557#define IAP_F_CC (1 << 0) /* CPU: Core */
558#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */
559#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */
560#define IAP_F_CA (1 << 3) /* CPU: Atom */
561#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */
562#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */
563#define IAP_F_WM (1 << 5) /* CPU: Westmere */
564#define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */
565#define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */
566#define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */
567#define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */
568#define IAP_F_HW (1 << 10) /* CPU: Haswell */
569#define IAP_F_FM (1 << 11) /* Fixed mask */
570
571#define IAP_F_ALLCPUSCORE2 \
572 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
573
574/* Sub fields of UMASK that this event supports. */
575#define IAP_M_CORE (1 << 0) /* Core specificity */
576#define IAP_M_AGENT (1 << 1) /* Agent specificity */
577#define IAP_M_PREFETCH (1 << 2) /* Prefetch */
578#define IAP_M_MESI (1 << 3) /* MESI */
579#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
580#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
581#define IAP_M_TRANSITION (1 << 6) /* Transition */
582
583#define IAP_F_CORE (0x3 << 14) /* Core specificity */
584#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
585#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
586#define IAP_F_MESI (0xF << 8) /* MESI */
587#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
588#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
589#define IAP_F_TRANSITION (0x1 << 12) /* Transition */
590
591#define IAP_PREFETCH_RESERVED (0x2 << 12)
592#define IAP_CORE_THIS (0x1 << 14)
593#define IAP_CORE_ALL (0x3 << 14)
594#define IAP_F_CMASK 0xFF000000
595
596static struct iap_event_descr iap_events[] = {
597#undef IAPDESCR
598#define IAPDESCR(N,EV,UM,FLAGS) { \
599 .iap_ev = PMC_EV_IAP_EVENT_##N, \
600 .iap_evcode = (EV), \
601 .iap_umask = (UM), \
602 .iap_flags = (FLAGS) \
603 }
604
605 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O),
606 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
607
608 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
609 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
610 IAP_F_SBX),
611 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
612 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
613 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
614 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
615 IAP_F_SBX),
616 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
617 IAP_F_SBX),
618 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
619
620 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
621 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
622 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
623 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
624 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
625
626 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
627 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
628 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
629 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB |
630 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
631 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
632
633 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
634 IAP_F_CC2E | IAP_F_CA),
635 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O),
636 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O),
637 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
638 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
639 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
640
641 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
642 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
643 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
644 IAP_F_HW),
645 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
646 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
647 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
648 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB |
649 IAP_F_SBX),
650
651 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
652 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
653 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
654 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
655 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
656 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
657 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
658 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
659 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
660 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
661 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
662 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW),
663 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
664 IAP_F_SBX | IAP_F_HW),
665 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW),
666 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
667 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW),
668 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW),
669 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
670 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
671 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
672
673 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
674 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
675 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O),
676 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O),
677
678 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
679 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
680 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
681
682 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
683 IAP_F_WM),
684 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
685 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
686
687 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
688 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
689
690 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
691 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
692 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
693 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
694 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
695 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
696
697 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
698 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
699 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
700 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
701 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
702 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
703
704 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
705 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
706 IAP_F_WM | IAP_F_SB | IAP_F_SBX),
707 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
708 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
709 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
710 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
711 IAP_F_SBX),
712 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
713 IAP_F_SBX),
714 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
715 IAP_F_SBX),
716 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
717 IAP_F_SBX),
718 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
719
720 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
721 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB |
722 IAP_F_SBX),
723 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
724 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
725
726 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
727 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
728 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
729 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
730 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
731 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
732 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
733 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
734 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA),
735
736 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
737 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
738 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
739 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
740 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
741 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
742
743 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
744 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
745 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
746 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
747
748 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
749 IAP_F_SBX),
750
751 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
752 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
753
754 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
755 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
756 IAP_F_I7 | IAP_F_WM),
757 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
758
759 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O),
760 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O),
761 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O),
762
763 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
764
765 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
766 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
767 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2),
768 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
769
770 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
771 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
772 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
773 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
774 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
775 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
776 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
777 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
778 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
779 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
780 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
781 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
782 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
783 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
784 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
785 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
786 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW),
787 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW),
788 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW),
789 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW),
790 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
791 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
792 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
793 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
794 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW),
795 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW),
796 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW),
797 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW),
798 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
799 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
800 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
801 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
802 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW),
803 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW),
804 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW),
805 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW),
806 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
807 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW),
808 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW),
809 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW),
810
811 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
812
813 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
814 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
815 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
816 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
817 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
818 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
819 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
820 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
821 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
822 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
823 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
824 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
825
826 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
827 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
828 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
829 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
830 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
831 IAP_F_SBX),
832 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
833 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
834 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
835 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
836 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
837 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
838 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
839 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
840 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW),
841 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
842 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
843 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
844
845 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
846 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
847 IAP_F_SBX | IAP_F_IBX),
848 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX),
849 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
850 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
851 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
852 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
853 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
854 IAP_F_SBX | IAP_F_IBX),
855
856 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
857 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
858 IAP_F_CA | IAP_F_CC2),
859 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
860 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2),
861
862 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
863 IAP_F_ALLCPUSCORE2),
864 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
865 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
866 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
867 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
868 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
869 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
870
871 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
872 IAP_F_ALLCPUSCORE2),
873 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC),
874 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
875
876 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC),
877 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
878
879 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
880
881 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
882 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
883 IAP_F_HW),
884 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
885 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
886 IAP_F_HW),
887 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
888
889 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
890
891 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
892 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7),
893 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7),
894 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7),
895 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7),
896 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7),
897 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA),
898
899 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
900 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O),
901 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7),
902 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7),
903 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7),
904 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O),
905 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA),
906
907 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2),
908 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7),
909 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7),
910 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7),
911 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7),
912 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
913
914 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
915 IAP_F_I7),
916 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA |
917 IAP_F_CC2 | IAP_F_I7),
918
919 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC),
920
921 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2),
922
923 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
924 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
925
926 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
927 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
928 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
929 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O),
930
931 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
932 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
933 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
934 IAP_F_HW),
935 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
936 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
937 IAP_F_HW),
938 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB |
939 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
940 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW),
941 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
942 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
943 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW),
944 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
945 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW),
946 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW),
947
948 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
949 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O),
950 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
951 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC),
952 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
953
954 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
955 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
956 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
957 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
958 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
959
960 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
961
962 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
963 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
964 IAP_F_SB | IAP_F_SBX),
965 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
966 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
967
968 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC),
969 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O),
970 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O),
971 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
972 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
973
974 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
975 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
976 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
977 IAP_F_SB | IAP_F_SBX),
978 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
979 IAP_F_SB | IAP_F_SBX),
980 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
981 IAP_F_SB | IAP_F_SBX),
982
983 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
984
985 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
986
987 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
988 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
989 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
990 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
991
992 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
993 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
994 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
995
996 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
997 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
998 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
999 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1000
1001 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1002 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1003 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1004 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1005
1006 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1007 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1008
1009 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB),
1010 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX),
1011
1012 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1013 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1014 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1015 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1016 IAP_F_IBX | IAP_F_HW),
1017 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1018 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1019 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1020 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1021
1022 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1023 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
1024
1025 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2),
1026 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC),
1027
1028 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
1029 IAP_F_CA | IAP_F_CC2),
1030 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
1031 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1032 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1033 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1034 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1035
1036 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1037 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
1038
1039 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE,
1040 IAP_F_CA | IAP_F_CC2),
1041 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC),
1042
1043 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1044
1045 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1046 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC),
1047
1048 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1049 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1050 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1051 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1052
1053 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1054 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1055
1056 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1057 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC),
1058
1059 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1060 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC),
1061
1062 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1063 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC),
1064
1065 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1066 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC),
1067
1068 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE,
1069 IAP_F_CA | IAP_F_CC2),
1070 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC),
1071
1072 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
1073 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
1074
1075 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1076 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1077 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1078 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1079 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1080 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1081 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1082 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1083 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1084 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1085 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1086 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1087 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1088 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1089 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1090
1091 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1092
1093 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1094
1095 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1096
1097 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1098 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC),
1099
1100 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1101
1102 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1103 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1104 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1105 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1106 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1107 IAP_F_WM),
1108 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1109
1110 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1111 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O),
1112 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O),
1113
1114 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1115 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1116 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA),
1117 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1118 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2),
1119 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2),
1120
1121 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O),
1122 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1123
1124 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
1125 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1126 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1127 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1128 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1129 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1130 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1131 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW),
1132 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
1133 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1134 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
1135 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
1136 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW),
1137 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1138
1139 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1140
1141 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1142 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1143 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1144 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1145 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1146 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1147 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1148 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1149
1150 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1151 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1152 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1153 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1154 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1155 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1156 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1157 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1158 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1159 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1160 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1161 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1162 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1163 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1164 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1165 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1166 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1167 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1168 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1169 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1170 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1171 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1172
1173 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1174 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1175 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1176 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1177 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1178 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1179 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1180 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1181 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1182 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1183 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1184 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1185 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1186 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1187 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1188 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1189 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1190 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1191 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1192 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1193 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1194
1195 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1196 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1197 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1198 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1199 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1200 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1201
1202 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1203 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1204 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1205 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1206 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1207
1208 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1209 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1210
1211 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1212 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1213 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1214
1215 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1216 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1217 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1218 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1219 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1220 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1221 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1222 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1223 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1224 IAP_F_SBX | IAP_F_IBX),
1225 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1226 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1227 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1228 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1229 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1230 IAP_F_SBX | IAP_F_IBX),
1231 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1232 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1233 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1234 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1235
1236 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
1237 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1238 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1239 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1240 IAP_F_SB | IAP_F_SBX),
1241 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1242 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1243 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1244 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1245 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1246 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1247 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1248 IAP_F_SB | IAP_F_SBX),
1249 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1250 IAP_F_SB | IAP_F_SBX),
1251 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1252 IAP_F_SB | IAP_F_SBX),
1253
1254 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1255 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1256 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1257 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW),
1258 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW),
1259
1260 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1261 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1262 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1263
1264 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2),
1265 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA),
1266 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
1267 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
1268
1269 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1270 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1271 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1272 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1273
1274 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1275 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1276 IAP_F_SBX | IAP_F_IBX),
1277 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1278
1279 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1280 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1281
1282 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1283 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1284 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1285 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1286 IAP_F_IBX | IAP_F_HW),
1287 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1288 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1289 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1290 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1291 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1292 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
1293 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1294 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
1295
1296 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1297 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1298 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1299 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1300 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1301 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1302 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1303 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1304 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1305 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1306 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1307 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1308 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1309 IAP_F_WM),
1310
1311 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1312 IAP_F_SB | IAP_F_SBX),
1313
1314 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1315 IAP_F_WM | IAP_F_I7O),
1316 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1317 IAP_F_WM | IAP_F_I7O),
1318 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1319 IAP_F_WM | IAP_F_I7O),
1320 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1321 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1322 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1323 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA),
1324 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA),
1325 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA),
1326 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA),
1327 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA),
1328 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA),
1329
1330 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM),
1331 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
1332 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
1333
1334 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1335
1336 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1337 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1338
1339 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1340 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1341 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1342
1343 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
1344 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
1345
1346 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1347 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1348
1349 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW),
1350 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW),
1351 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW),
1352 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW),
1353 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW),
1354 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW),
1355 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW),
1356 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW),
1357
1358 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1359 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1360 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1361 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1362
1363 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1364
1365 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1366 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1367 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1368 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1369 IAP_F_IBX | IAP_F_HW),
1370 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1371 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1372 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1373 IAP_F_I7 | IAP_F_WM),
1374 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
1375
1376 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
1377 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1378 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1379 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1380 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1381 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1382 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1383 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1384 IAP_F_SBX | IAP_F_IBX),
1385 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW),
1386 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1387
1388 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
1389 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1390 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1391 IAP_F_IBX | IAP_F_HW),
1392 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1393 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1394 IAP_F_IBX | IAP_F_HW),
1395 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1396 IAP_F_I7 | IAP_F_WM),
1397 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1398 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1399 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2),
1400 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA),
1401
1402 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
1403 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1404 IAP_F_I7 | IAP_F_WM),
1405 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1406 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1407 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1408 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1409 IAP_F_IBX | IAP_F_HW),
1410 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
1411 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1412 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1413
1414 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1415 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1416 IAP_F_IBX | IAP_F_HW),
1417 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1418 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1419 IAP_F_IBX | IAP_F_HW),
1420 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1421 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1422 IAP_F_IBX | IAP_F_HW),
1423 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1424 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1425 IAP_F_IBX | IAP_F_HW),
1426 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1427 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1428 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1429 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
1430 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1431 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1432 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1433 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1434 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1435 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1436
1437 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1438 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1439 IAP_F_IBX | IAP_F_HW),
1440 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1441 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1442 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1443 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1444 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1445 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1446 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1447 IAP_F_SBX | IAP_F_IBX),
1448 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1449 IAP_F_SBX | IAP_F_IBX),
1450
1451 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
1452 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1453 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1454
1455 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC),
1456 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1457 IAP_F_I7 | IAP_F_WM),
1458 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1459 IAP_F_I7 | IAP_F_WM),
1460 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1461 IAP_F_I7 | IAP_F_WM),
1462 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1463 IAP_F_I7 | IAP_F_WM),
1464 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1465 IAP_F_I7 | IAP_F_WM),
1466 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1467
1468 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1469 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1470
1471 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1472
1473 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
1474 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1475 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1476 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1477 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1478 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1479 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1480 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1481 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1482 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1483 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1484 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1485
1486 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1487 IAP_F_I7 | IAP_F_WM),
1488 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1489 IAP_F_I7 | IAP_F_WM),
1490 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1491 IAP_F_I7 | IAP_F_WM),
1492 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1493 IAP_F_I7 | IAP_F_WM),
1494 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
1495 IAP_F_WM),
1496 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1497 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1498
1499 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC),
1500 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1501 IAP_F_I7 | IAP_F_WM),
1502 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1503 IAP_F_I7 | IAP_F_WM),
1504 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1505 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1506 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1507
1508 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1509 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1510 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1511 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1512 IAP_F_SBX | IAP_F_IBX),
1513
1514 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1515 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1516
33
34#include <sys/param.h>
35#include <sys/bus.h>
36#include <sys/pmc.h>
37#include <sys/pmckern.h>
38#include <sys/systm.h>
39
40#include <machine/intr_machdep.h>
41#include <machine/apicvar.h>
42#include <machine/cpu.h>
43#include <machine/cpufunc.h>
44#include <machine/md_var.h>
45#include <machine/specialreg.h>
46
47#define CORE_CPUID_REQUEST 0xA
48#define CORE_CPUID_REQUEST_SIZE 0x4
49#define CORE_CPUID_EAX 0x0
50#define CORE_CPUID_EBX 0x1
51#define CORE_CPUID_ECX 0x2
52#define CORE_CPUID_EDX 0x3
53
54#define IAF_PMC_CAPS \
55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \
56 PMC_CAP_USER | PMC_CAP_SYSTEM)
57#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
58
59#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
62
63#define EV_IS_NOTARCH 0
64#define EV_IS_ARCH_SUPP 1
65#define EV_IS_ARCH_NOTSUPP -1
66
67/*
68 * "Architectural" events defined by Intel. The values of these
69 * symbols correspond to positions in the bitmask returned by
70 * the CPUID.0AH instruction.
71 */
72enum core_arch_events {
73 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
74 CORE_AE_BRANCH_MISSES_RETIRED = 6,
75 CORE_AE_INSTRUCTION_RETIRED = 1,
76 CORE_AE_LLC_MISSES = 4,
77 CORE_AE_LLC_REFERENCE = 3,
78 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
79 CORE_AE_UNHALTED_CORE_CYCLES = 0
80};
81
82static enum pmc_cputype core_cputype;
83
84struct core_cpu {
85 volatile uint32_t pc_resync;
86 volatile uint32_t pc_iafctrl; /* Fixed function control. */
87 volatile uint64_t pc_globalctrl; /* Global control register. */
88 struct pmc_hw pc_corepmcs[];
89};
90
91static struct core_cpu **core_pcpu;
92
93static uint32_t core_architectural_events;
94static uint64_t core_pmcmask;
95
96static int core_iaf_ri; /* relative index of fixed counters */
97static int core_iaf_width;
98static int core_iaf_npmc;
99
100static int core_iap_width;
101static int core_iap_npmc;
102
103static int
104core_pcpu_noop(struct pmc_mdep *md, int cpu)
105{
106 (void) md;
107 (void) cpu;
108 return (0);
109}
110
111static int
112core_pcpu_init(struct pmc_mdep *md, int cpu)
113{
114 struct pmc_cpu *pc;
115 struct core_cpu *cc;
116 struct pmc_hw *phw;
117 int core_ri, n, npmc;
118
119 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
120 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
121
122 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu);
123
124 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
125 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
126
127 if (core_cputype != PMC_CPU_INTEL_CORE)
128 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
129
130 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
131 M_PMC, M_WAITOK | M_ZERO);
132
133 core_pcpu[cpu] = cc;
134 pc = pmc_pcpu[cpu];
135
136 KASSERT(pc != NULL && cc != NULL,
137 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
138
139 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
140 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
141 PMC_PHW_CPU_TO_STATE(cpu) |
142 PMC_PHW_INDEX_TO_STATE(n + core_ri);
143 phw->phw_pmc = NULL;
144 pc->pc_hwpmcs[n + core_ri] = phw;
145 }
146
147 return (0);
148}
149
150static int
151core_pcpu_fini(struct pmc_mdep *md, int cpu)
152{
153 int core_ri, n, npmc;
154 struct pmc_cpu *pc;
155 struct core_cpu *cc;
156 uint64_t msr = 0;
157
158 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
159 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
160
161 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
162
163 if ((cc = core_pcpu[cpu]) == NULL)
164 return (0);
165
166 core_pcpu[cpu] = NULL;
167
168 pc = pmc_pcpu[cpu];
169
170 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
171 cpu));
172
173 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
174 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
175
176 for (n = 0; n < npmc; n++) {
177 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
178 wrmsr(IAP_EVSEL0 + n, msr);
179 }
180
181 if (core_cputype != PMC_CPU_INTEL_CORE) {
182 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
183 wrmsr(IAF_CTRL, msr);
184 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
185 }
186
187 for (n = 0; n < npmc; n++)
188 pc->pc_hwpmcs[n + core_ri] = NULL;
189
190 free(cc, M_PMC);
191
192 return (0);
193}
194
195/*
196 * Fixed function counters.
197 */
198
199static pmc_value_t
200iaf_perfctr_value_to_reload_count(pmc_value_t v)
201{
202 v &= (1ULL << core_iaf_width) - 1;
203 return (1ULL << core_iaf_width) - v;
204}
205
206static pmc_value_t
207iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
208{
209 return (1ULL << core_iaf_width) - rlc;
210}
211
212static int
213iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
214 const struct pmc_op_pmcallocate *a)
215{
216 enum pmc_event ev;
217 uint32_t caps, flags, validflags;
218
219 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
220 ("[core,%d] illegal CPU %d", __LINE__, cpu));
221
222 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
223
224 if (ri < 0 || ri > core_iaf_npmc)
225 return (EINVAL);
226
227 caps = a->pm_caps;
228
229 if (a->pm_class != PMC_CLASS_IAF ||
230 (caps & IAF_PMC_CAPS) != caps)
231 return (EINVAL);
232
233 ev = pm->pm_event;
234 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST)
235 return (EINVAL);
236
237 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
238 return (EINVAL);
239 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
240 return (EINVAL);
241 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
242 return (EINVAL);
243
244 flags = a->pm_md.pm_iaf.pm_iaf_flags;
245
246 validflags = IAF_MASK;
247
248 if (core_cputype != PMC_CPU_INTEL_ATOM)
249 validflags &= ~IAF_ANY;
250
251 if ((flags & ~validflags) != 0)
252 return (EINVAL);
253
254 if (caps & PMC_CAP_INTERRUPT)
255 flags |= IAF_PMI;
256 if (caps & PMC_CAP_SYSTEM)
257 flags |= IAF_OS;
258 if (caps & PMC_CAP_USER)
259 flags |= IAF_USR;
260 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
261 flags |= (IAF_OS | IAF_USR);
262
263 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
264
265 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx",
266 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
267
268 return (0);
269}
270
271static int
272iaf_config_pmc(int cpu, int ri, struct pmc *pm)
273{
274 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
275 ("[core,%d] illegal CPU %d", __LINE__, cpu));
276
277 KASSERT(ri >= 0 && ri < core_iaf_npmc,
278 ("[core,%d] illegal row-index %d", __LINE__, ri));
279
280 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
281
282 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
283 cpu));
284
285 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
286
287 return (0);
288}
289
290static int
291iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
292{
293 int error;
294 struct pmc_hw *phw;
295 char iaf_name[PMC_NAME_MAX];
296
297 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
298
299 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
300 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
301 NULL)) != 0)
302 return (error);
303
304 pi->pm_class = PMC_CLASS_IAF;
305
306 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
307 pi->pm_enabled = TRUE;
308 *ppmc = phw->phw_pmc;
309 } else {
310 pi->pm_enabled = FALSE;
311 *ppmc = NULL;
312 }
313
314 return (0);
315}
316
317static int
318iaf_get_config(int cpu, int ri, struct pmc **ppm)
319{
320 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
321
322 return (0);
323}
324
325static int
326iaf_get_msr(int ri, uint32_t *msr)
327{
328 KASSERT(ri >= 0 && ri < core_iaf_npmc,
329 ("[iaf,%d] ri %d out of range", __LINE__, ri));
330
331 *msr = IAF_RI_TO_MSR(ri);
332
333 return (0);
334}
335
336static int
337iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
338{
339 struct pmc *pm;
340 pmc_value_t tmp;
341
342 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
343 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
344 KASSERT(ri >= 0 && ri < core_iaf_npmc,
345 ("[core,%d] illegal row-index %d", __LINE__, ri));
346
347 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
348
349 KASSERT(pm,
350 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
351 ri, ri + core_iaf_ri));
352
353 tmp = rdpmc(IAF_RI_TO_MSR(ri));
354
355 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
356 *v = iaf_perfctr_value_to_reload_count(tmp);
357 else
358 *v = tmp;
359
360 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
361 IAF_RI_TO_MSR(ri), *v);
362
363 return (0);
364}
365
366static int
367iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
368{
369 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
370
371 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
372 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
373 KASSERT(ri >= 0 && ri < core_iaf_npmc,
374 ("[core,%d] illegal row-index %d", __LINE__, ri));
375
376 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
377 ("[core,%d] PHW pmc non-NULL", __LINE__));
378
379 return (0);
380}
381
382static int
383iaf_start_pmc(int cpu, int ri)
384{
385 struct pmc *pm;
386 struct core_cpu *iafc;
387 uint64_t msr = 0;
388
389 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
390 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
391 KASSERT(ri >= 0 && ri < core_iaf_npmc,
392 ("[core,%d] illegal row-index %d", __LINE__, ri));
393
394 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
395
396 iafc = core_pcpu[cpu];
397 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
398
399 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
400
401 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
402 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
403
404 do {
405 iafc->pc_resync = 0;
406 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
407 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
408 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
409 IAF_GLOBAL_CTRL_MASK));
410 } while (iafc->pc_resync != 0);
411
412 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
413 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
414 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
415
416 return (0);
417}
418
419static int
420iaf_stop_pmc(int cpu, int ri)
421{
422 uint32_t fc;
423 struct core_cpu *iafc;
424 uint64_t msr = 0;
425
426 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
427
428 iafc = core_pcpu[cpu];
429
430 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
431 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
432 KASSERT(ri >= 0 && ri < core_iaf_npmc,
433 ("[core,%d] illegal row-index %d", __LINE__, ri));
434
435 fc = (IAF_MASK << (ri * 4));
436
437 if (core_cputype != PMC_CPU_INTEL_ATOM)
438 fc &= ~IAF_ANY;
439
440 iafc->pc_iafctrl &= ~fc;
441
442 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
443 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
444 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
445
446 do {
447 iafc->pc_resync = 0;
448 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
449 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
450 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
451 IAF_GLOBAL_CTRL_MASK));
452 } while (iafc->pc_resync != 0);
453
454 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
455 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
456 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
457
458 return (0);
459}
460
461static int
462iaf_write_pmc(int cpu, int ri, pmc_value_t v)
463{
464 struct core_cpu *cc;
465 struct pmc *pm;
466 uint64_t msr;
467
468 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
469 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
470 KASSERT(ri >= 0 && ri < core_iaf_npmc,
471 ("[core,%d] illegal row-index %d", __LINE__, ri));
472
473 cc = core_pcpu[cpu];
474 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
475
476 KASSERT(pm,
477 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
478
479 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
480 v = iaf_reload_count_to_perfctr_value(v);
481
482 /* Turn off fixed counters */
483 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
484 wrmsr(IAF_CTRL, msr);
485
486 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
487
488 /* Turn on fixed counters */
489 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
490 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
491
492 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
493 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
494 (uintmax_t) rdmsr(IAF_CTRL),
495 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
496
497 return (0);
498}
499
500
501static void
502iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
503{
504 struct pmc_classdep *pcd;
505
506 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
507
508 PMCDBG(MDP,INI,1, "%s", "iaf-initialize");
509
510 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
511
512 pcd->pcd_caps = IAF_PMC_CAPS;
513 pcd->pcd_class = PMC_CLASS_IAF;
514 pcd->pcd_num = npmc;
515 pcd->pcd_ri = md->pmd_npmc;
516 pcd->pcd_width = pmcwidth;
517
518 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
519 pcd->pcd_config_pmc = iaf_config_pmc;
520 pcd->pcd_describe = iaf_describe;
521 pcd->pcd_get_config = iaf_get_config;
522 pcd->pcd_get_msr = iaf_get_msr;
523 pcd->pcd_pcpu_fini = core_pcpu_noop;
524 pcd->pcd_pcpu_init = core_pcpu_noop;
525 pcd->pcd_read_pmc = iaf_read_pmc;
526 pcd->pcd_release_pmc = iaf_release_pmc;
527 pcd->pcd_start_pmc = iaf_start_pmc;
528 pcd->pcd_stop_pmc = iaf_stop_pmc;
529 pcd->pcd_write_pmc = iaf_write_pmc;
530
531 md->pmd_npmc += npmc;
532}
533
534/*
535 * Intel programmable PMCs.
536 */
537
538/*
539 * Event descriptor tables.
540 *
541 * For each event id, we track:
542 *
543 * 1. The CPUs that the event is valid for.
544 *
545 * 2. If the event uses a fixed UMASK, the value of the umask field.
546 * If the event doesn't use a fixed UMASK, a mask of legal bits
547 * to check against.
548 */
549
550struct iap_event_descr {
551 enum pmc_event iap_ev;
552 unsigned char iap_evcode;
553 unsigned char iap_umask;
554 unsigned int iap_flags;
555};
556
557#define IAP_F_CC (1 << 0) /* CPU: Core */
558#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */
559#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */
560#define IAP_F_CA (1 << 3) /* CPU: Atom */
561#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */
562#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */
563#define IAP_F_WM (1 << 5) /* CPU: Westmere */
564#define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */
565#define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */
566#define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */
567#define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */
568#define IAP_F_HW (1 << 10) /* CPU: Haswell */
569#define IAP_F_FM (1 << 11) /* Fixed mask */
570
571#define IAP_F_ALLCPUSCORE2 \
572 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
573
574/* Sub fields of UMASK that this event supports. */
575#define IAP_M_CORE (1 << 0) /* Core specificity */
576#define IAP_M_AGENT (1 << 1) /* Agent specificity */
577#define IAP_M_PREFETCH (1 << 2) /* Prefetch */
578#define IAP_M_MESI (1 << 3) /* MESI */
579#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
580#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
581#define IAP_M_TRANSITION (1 << 6) /* Transition */
582
583#define IAP_F_CORE (0x3 << 14) /* Core specificity */
584#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
585#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
586#define IAP_F_MESI (0xF << 8) /* MESI */
587#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
588#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
589#define IAP_F_TRANSITION (0x1 << 12) /* Transition */
590
591#define IAP_PREFETCH_RESERVED (0x2 << 12)
592#define IAP_CORE_THIS (0x1 << 14)
593#define IAP_CORE_ALL (0x3 << 14)
594#define IAP_F_CMASK 0xFF000000
595
596static struct iap_event_descr iap_events[] = {
597#undef IAPDESCR
598#define IAPDESCR(N,EV,UM,FLAGS) { \
599 .iap_ev = PMC_EV_IAP_EVENT_##N, \
600 .iap_evcode = (EV), \
601 .iap_umask = (UM), \
602 .iap_flags = (FLAGS) \
603 }
604
605 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O),
606 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
607
608 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
609 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
610 IAP_F_SBX),
611 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
612 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
613 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
614 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
615 IAP_F_SBX),
616 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
617 IAP_F_SBX),
618 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
619
620 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
621 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
622 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
623 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
624 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
625
626 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
627 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
628 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
629 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB |
630 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
631 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
632
633 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
634 IAP_F_CC2E | IAP_F_CA),
635 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O),
636 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O),
637 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
638 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
639 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
640
641 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
642 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
643 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
644 IAP_F_HW),
645 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
646 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
647 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
648 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB |
649 IAP_F_SBX),
650
651 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
652 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
653 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
654 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
655 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
656 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
657 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
658 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
659 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
660 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
661 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
662 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW),
663 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
664 IAP_F_SBX | IAP_F_HW),
665 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW),
666 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
667 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW),
668 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW),
669 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
670 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
671 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
672
673 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
674 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
675 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O),
676 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O),
677
678 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
679 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
680 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
681
682 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
683 IAP_F_WM),
684 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
685 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
686
687 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
688 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
689
690 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
691 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
692 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
693 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
694 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
695 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
696
697 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
698 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
699 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
700 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
701 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
702 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
703
704 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
705 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
706 IAP_F_WM | IAP_F_SB | IAP_F_SBX),
707 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
708 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
709 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
710 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
711 IAP_F_SBX),
712 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
713 IAP_F_SBX),
714 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
715 IAP_F_SBX),
716 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
717 IAP_F_SBX),
718 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
719
720 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
721 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB |
722 IAP_F_SBX),
723 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
724 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
725
726 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
727 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
728 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
729 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
730 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
731 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
732 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
733 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
734 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA),
735
736 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
737 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
738 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
739 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
740 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
741 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
742
743 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
744 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
745 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
746 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
747
748 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
749 IAP_F_SBX),
750
751 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
752 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
753
754 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
755 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
756 IAP_F_I7 | IAP_F_WM),
757 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
758
759 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O),
760 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O),
761 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O),
762
763 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
764
765 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
766 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
767 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2),
768 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
769
770 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
771 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
772 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
773 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
774 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
775 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
776 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
777 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
778 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
779 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
780 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
781 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
782 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
783 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
784 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
785 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
786 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW),
787 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW),
788 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW),
789 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW),
790 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
791 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
792 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
793 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
794 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW),
795 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW),
796 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW),
797 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW),
798 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
799 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
800 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
801 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
802 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW),
803 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW),
804 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW),
805 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW),
806 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
807 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW),
808 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW),
809 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW),
810
811 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
812
813 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
814 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
815 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
816 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
817 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
818 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
819 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
820 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
821 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
822 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
823 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
824 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
825
826 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
827 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
828 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
829 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
830 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
831 IAP_F_SBX),
832 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
833 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
834 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
835 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
836 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
837 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
838 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
839 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
840 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW),
841 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
842 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
843 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
844
845 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
846 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
847 IAP_F_SBX | IAP_F_IBX),
848 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX),
849 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
850 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
851 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
852 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
853 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
854 IAP_F_SBX | IAP_F_IBX),
855
856 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
857 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
858 IAP_F_CA | IAP_F_CC2),
859 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
860 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2),
861
862 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
863 IAP_F_ALLCPUSCORE2),
864 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
865 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
866 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
867 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
868 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
869 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
870
871 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
872 IAP_F_ALLCPUSCORE2),
873 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC),
874 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
875
876 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC),
877 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
878
879 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
880
881 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
882 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
883 IAP_F_HW),
884 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
885 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
886 IAP_F_HW),
887 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
888
889 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
890
891 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
892 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7),
893 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7),
894 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7),
895 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7),
896 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7),
897 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA),
898
899 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
900 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O),
901 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7),
902 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7),
903 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7),
904 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O),
905 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA),
906
907 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2),
908 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7),
909 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7),
910 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7),
911 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7),
912 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
913
914 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
915 IAP_F_I7),
916 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA |
917 IAP_F_CC2 | IAP_F_I7),
918
919 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC),
920
921 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2),
922
923 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
924 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
925
926 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
927 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
928 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
929 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O),
930
931 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
932 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
933 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
934 IAP_F_HW),
935 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
936 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
937 IAP_F_HW),
938 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB |
939 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
940 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW),
941 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
942 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
943 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW),
944 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
945 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW),
946 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW),
947
948 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
949 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O),
950 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
951 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC),
952 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
953
954 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
955 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
956 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
957 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
958 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
959
960 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
961
962 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
963 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
964 IAP_F_SB | IAP_F_SBX),
965 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
966 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
967
968 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC),
969 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O),
970 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O),
971 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
972 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
973
974 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
975 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
976 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
977 IAP_F_SB | IAP_F_SBX),
978 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
979 IAP_F_SB | IAP_F_SBX),
980 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
981 IAP_F_SB | IAP_F_SBX),
982
983 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
984
985 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
986
987 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
988 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
989 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
990 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
991
992 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
993 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
994 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
995
996 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
997 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
998 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
999 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1000
1001 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1002 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1003 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1004 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1005
1006 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1007 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1008
1009 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB),
1010 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX),
1011
1012 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1013 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1014 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1015 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1016 IAP_F_IBX | IAP_F_HW),
1017 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1018 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1019 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1020 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1021
1022 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1023 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
1024
1025 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2),
1026 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC),
1027
1028 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
1029 IAP_F_CA | IAP_F_CC2),
1030 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
1031 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1032 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1033 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1034 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1035
1036 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1037 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
1038
1039 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE,
1040 IAP_F_CA | IAP_F_CC2),
1041 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC),
1042
1043 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1044
1045 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1046 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC),
1047
1048 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1049 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1050 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1051 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1052
1053 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1054 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1055
1056 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1057 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC),
1058
1059 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1060 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC),
1061
1062 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1063 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC),
1064
1065 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1066 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC),
1067
1068 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE,
1069 IAP_F_CA | IAP_F_CC2),
1070 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC),
1071
1072 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
1073 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
1074
1075 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1076 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1077 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1078 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1079 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1080 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1081 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1082 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1083 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1084 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1085 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1086 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1087 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1088 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1089 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1090
1091 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1092
1093 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1094
1095 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1096
1097 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1098 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC),
1099
1100 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1101
1102 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1103 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1104 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1105 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1106 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1107 IAP_F_WM),
1108 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1109
1110 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1111 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O),
1112 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O),
1113
1114 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1115 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1116 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA),
1117 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1118 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2),
1119 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2),
1120
1121 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O),
1122 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1123
1124 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
1125 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1126 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1127 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1128 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1129 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1130 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1131 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW),
1132 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
1133 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1134 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
1135 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
1136 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW),
1137 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1138
1139 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1140
1141 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1142 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1143 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1144 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1145 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1146 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1147 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1148 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1149
1150 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1151 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1152 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1153 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1154 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1155 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1156 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1157 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1158 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1159 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1160 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1161 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1162 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1163 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1164 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1165 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1166 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1167 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1168 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1169 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1170 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1171 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1172
1173 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1174 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1175 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1176 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1177 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1178 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1179 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1180 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1181 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1182 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1183 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1184 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1185 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1186 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1187 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1188 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1189 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1190 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1191 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1192 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1193 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1194
1195 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1196 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1197 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1198 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1199 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1200 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1201
1202 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1203 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1204 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1205 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1206 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1207
1208 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1209 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1210
1211 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1212 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1213 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1214
1215 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1216 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1217 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1218 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1219 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1220 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1221 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1222 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1223 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1224 IAP_F_SBX | IAP_F_IBX),
1225 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1226 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1227 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1228 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1229 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1230 IAP_F_SBX | IAP_F_IBX),
1231 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1232 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1233 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1234 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1235
1236 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
1237 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1238 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1239 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1240 IAP_F_SB | IAP_F_SBX),
1241 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1242 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1243 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1244 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1245 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1246 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1247 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1248 IAP_F_SB | IAP_F_SBX),
1249 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1250 IAP_F_SB | IAP_F_SBX),
1251 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1252 IAP_F_SB | IAP_F_SBX),
1253
1254 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1255 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1256 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1257 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW),
1258 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW),
1259
1260 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1261 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1262 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1263
1264 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2),
1265 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA),
1266 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
1267 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
1268
1269 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1270 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1271 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1272 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1273
1274 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1275 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1276 IAP_F_SBX | IAP_F_IBX),
1277 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1278
1279 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1280 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1281
1282 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1283 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1284 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1285 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1286 IAP_F_IBX | IAP_F_HW),
1287 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1288 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1289 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1290 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1291 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1292 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
1293 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1294 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
1295
1296 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1297 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1298 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1299 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1300 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1301 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1302 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1303 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1304 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1305 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1306 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1307 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1308 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1309 IAP_F_WM),
1310
1311 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1312 IAP_F_SB | IAP_F_SBX),
1313
1314 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1315 IAP_F_WM | IAP_F_I7O),
1316 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1317 IAP_F_WM | IAP_F_I7O),
1318 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1319 IAP_F_WM | IAP_F_I7O),
1320 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1321 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1322 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1323 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA),
1324 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA),
1325 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA),
1326 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA),
1327 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA),
1328 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA),
1329
1330 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM),
1331 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
1332 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
1333
1334 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1335
1336 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1337 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1338
1339 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1340 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1341 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1342
1343 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
1344 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
1345
1346 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1347 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1348
1349 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW),
1350 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW),
1351 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW),
1352 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW),
1353 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW),
1354 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW),
1355 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW),
1356 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW),
1357
1358 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1359 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1360 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1361 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1362
1363 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1364
1365 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1366 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1367 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1368 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1369 IAP_F_IBX | IAP_F_HW),
1370 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1371 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1372 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1373 IAP_F_I7 | IAP_F_WM),
1374 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
1375
1376 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
1377 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1378 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1379 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1380 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1381 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1382 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1383 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1384 IAP_F_SBX | IAP_F_IBX),
1385 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW),
1386 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1387
1388 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
1389 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1390 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1391 IAP_F_IBX | IAP_F_HW),
1392 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1393 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1394 IAP_F_IBX | IAP_F_HW),
1395 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1396 IAP_F_I7 | IAP_F_WM),
1397 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1398 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1399 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2),
1400 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA),
1401
1402 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
1403 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1404 IAP_F_I7 | IAP_F_WM),
1405 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1406 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1407 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1408 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1409 IAP_F_IBX | IAP_F_HW),
1410 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
1411 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1412 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1413
1414 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1415 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1416 IAP_F_IBX | IAP_F_HW),
1417 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1418 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1419 IAP_F_IBX | IAP_F_HW),
1420 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1421 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1422 IAP_F_IBX | IAP_F_HW),
1423 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1424 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1425 IAP_F_IBX | IAP_F_HW),
1426 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1427 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1428 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1429 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
1430 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1431 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1432 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1433 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1434 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1435 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1436
1437 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1438 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1439 IAP_F_IBX | IAP_F_HW),
1440 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1441 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1442 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1443 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1444 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1445 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1446 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1447 IAP_F_SBX | IAP_F_IBX),
1448 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1449 IAP_F_SBX | IAP_F_IBX),
1450
1451 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
1452 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1453 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1454
1455 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC),
1456 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1457 IAP_F_I7 | IAP_F_WM),
1458 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1459 IAP_F_I7 | IAP_F_WM),
1460 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1461 IAP_F_I7 | IAP_F_WM),
1462 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1463 IAP_F_I7 | IAP_F_WM),
1464 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1465 IAP_F_I7 | IAP_F_WM),
1466 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1467
1468 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1469 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1470
1471 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1472
1473 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
1474 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1475 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1476 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1477 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1478 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1479 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1480 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1481 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1482 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1483 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1484 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1485
1486 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1487 IAP_F_I7 | IAP_F_WM),
1488 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1489 IAP_F_I7 | IAP_F_WM),
1490 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1491 IAP_F_I7 | IAP_F_WM),
1492 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1493 IAP_F_I7 | IAP_F_WM),
1494 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
1495 IAP_F_WM),
1496 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1497 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1498
1499 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC),
1500 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1501 IAP_F_I7 | IAP_F_WM),
1502 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1503 IAP_F_I7 | IAP_F_WM),
1504 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1505 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1506 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1507
1508 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1509 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1510 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1511 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1512 IAP_F_SBX | IAP_F_IBX),
1513
1514 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1515 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1516
1517 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */
1517 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
1518 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
1518 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1519 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1520 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1521 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1522 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1523 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1524 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1525 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1526 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1527 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1528 IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1529 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1519 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1520 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1521 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1522 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1523 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1524 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1525 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1526 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1527 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1528 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1529 IAPDESCR(D0H_80H, 0xD0, 0x80, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1530 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1531 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1530
1531 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1532 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1533 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1534 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1535 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1536 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1537 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1538 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW),
1539 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1540 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1541 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1542
1543 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1544 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1545 IAP_F_IBX | IAP_F_HW),
1546 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1547 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1548 IAP_F_IBX | IAP_F_HW),
1549 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1550 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1551 IAP_F_IBX | IAP_F_HW),
1552 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1553 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1554 IAP_F_IBX | IAP_F_HW),
1555 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1556 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1557 IAP_F_IBX | IAP_F_HW),
1558
1559 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
1560
1561 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX |
1562 IAP_F_IBX | IAP_F_HW),
1563 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1564 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX),
1565 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX),
1566
1567 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1568 IAP_F_I7 | IAP_F_WM),
1569 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1570 IAP_F_SB | IAP_F_SBX),
1571 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1572 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1573 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1574
1575 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1576 IAP_F_I7 | IAP_F_WM),
1577 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1578 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1579 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1580 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1581
1582 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC),
1583
1584 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC),
1585 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC),
1586 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC),
1587 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC),
1588 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC),
1589
1590 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC),
1591 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC),
1592 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC),
1593 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC),
1594
1595 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC),
1596 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC),
1597 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC),
1598
1599 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC),
1600 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1601
1602 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1603 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1604 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1605 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1606 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1607 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1608
1609 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1610 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1611 IAP_F_WM),
1612
1613 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC),
1614
1615 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1616 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O),
1617
1618 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1619
1620 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1621 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1622 IAP_F_WM | IAP_F_SBX),
1623 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1624 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IBX | IAP_F_HW),
1625
1626 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1627 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1628 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O),
1629
1630 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
1631
1632 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1633 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1634 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1635 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1636 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1637 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1638 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1639 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1640 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1641 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1642 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1643 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1644 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1645 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1646 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1647 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1648 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1649
1650 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1651 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1652 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1653 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1654 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1655 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1656 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1657 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1658
1659 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1660 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1661 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1662 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1663 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1664 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1665 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW),
1666 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW),
1667 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1668 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1669 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
1670 IAP_F_IBX),
1671 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1672
1673 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
1674 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O),
1675 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O),
1676 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O),
1677 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O),
1678 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O),
1679
1680 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O),
1681 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
1682 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1683 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
1684 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1685 IAP_F_SB | IAP_F_SBX),
1686
1687 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1688
1689 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1690 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1691 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1692
1693 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1694 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O),
1695
1696 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1697 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1698 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1699 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1700 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1701 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1702 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1703};
1704
1705static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]);
1706
1707static pmc_value_t
1708iap_perfctr_value_to_reload_count(pmc_value_t v)
1709{
1710 v &= (1ULL << core_iap_width) - 1;
1711 return (1ULL << core_iap_width) - v;
1712}
1713
1714static pmc_value_t
1715iap_reload_count_to_perfctr_value(pmc_value_t rlc)
1716{
1717 return (1ULL << core_iap_width) - rlc;
1718}
1719
1720static int
1721iap_pmc_has_overflowed(int ri)
1722{
1723 uint64_t v;
1724
1725 /*
1726 * We treat a Core (i.e., Intel architecture v1) PMC as has
1727 * having overflowed if its MSB is zero.
1728 */
1729 v = rdpmc(ri);
1730 return ((v & (1ULL << (core_iap_width - 1))) == 0);
1731}
1732
1733/*
1734 * Check an event against the set of supported architectural events.
1735 *
1736 * If the event is not architectural EV_IS_NOTARCH is returned.
1737 * If the event is architectural and supported on this CPU, the correct
1738 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned.
1739 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP.
1740 */
1741
1742static int
1743iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map)
1744{
1745 enum core_arch_events ae;
1746
1747 switch (pe) {
1748 case PMC_EV_IAP_ARCH_UNH_COR_CYC:
1749 ae = CORE_AE_UNHALTED_CORE_CYCLES;
1750 *map = PMC_EV_IAP_EVENT_C4H_00H;
1751 break;
1752 case PMC_EV_IAP_ARCH_INS_RET:
1753 ae = CORE_AE_INSTRUCTION_RETIRED;
1754 *map = PMC_EV_IAP_EVENT_C0H_00H;
1755 break;
1756 case PMC_EV_IAP_ARCH_UNH_REF_CYC:
1757 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES;
1758 *map = PMC_EV_IAP_EVENT_3CH_01H;
1759 break;
1760 case PMC_EV_IAP_ARCH_LLC_REF:
1761 ae = CORE_AE_LLC_REFERENCE;
1762 *map = PMC_EV_IAP_EVENT_2EH_4FH;
1763 break;
1764 case PMC_EV_IAP_ARCH_LLC_MIS:
1765 ae = CORE_AE_LLC_MISSES;
1766 *map = PMC_EV_IAP_EVENT_2EH_41H;
1767 break;
1768 case PMC_EV_IAP_ARCH_BR_INS_RET:
1769 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED;
1770 *map = PMC_EV_IAP_EVENT_C4H_00H;
1771 break;
1772 case PMC_EV_IAP_ARCH_BR_MIS_RET:
1773 ae = CORE_AE_BRANCH_MISSES_RETIRED;
1774 *map = PMC_EV_IAP_EVENT_C5H_00H;
1775 break;
1776
1777 default: /* Non architectural event. */
1778 return (EV_IS_NOTARCH);
1779 }
1780
1781 return (((core_architectural_events & (1 << ae)) == 0) ?
1782 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP);
1783}
1784
1785static int
1786iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri)
1787{
1788 uint32_t mask;
1789
1790 switch (pe) {
1791 /*
1792 * Events valid only on counter 0, 1.
1793 */
1794 case PMC_EV_IAP_EVENT_40H_01H:
1795 case PMC_EV_IAP_EVENT_40H_02H:
1796 case PMC_EV_IAP_EVENT_40H_04H:
1797 case PMC_EV_IAP_EVENT_40H_08H:
1798 case PMC_EV_IAP_EVENT_40H_0FH:
1799 case PMC_EV_IAP_EVENT_41H_02H:
1800 case PMC_EV_IAP_EVENT_41H_04H:
1801 case PMC_EV_IAP_EVENT_41H_08H:
1802 case PMC_EV_IAP_EVENT_42H_01H:
1803 case PMC_EV_IAP_EVENT_42H_02H:
1804 case PMC_EV_IAP_EVENT_42H_04H:
1805 case PMC_EV_IAP_EVENT_42H_08H:
1806 case PMC_EV_IAP_EVENT_43H_01H:
1807 case PMC_EV_IAP_EVENT_43H_02H:
1808 case PMC_EV_IAP_EVENT_51H_01H:
1809 case PMC_EV_IAP_EVENT_51H_02H:
1810 case PMC_EV_IAP_EVENT_51H_04H:
1811 case PMC_EV_IAP_EVENT_51H_08H:
1812 case PMC_EV_IAP_EVENT_63H_01H:
1813 case PMC_EV_IAP_EVENT_63H_02H:
1814 mask = 0x3;
1815 break;
1816
1817 default:
1818 mask = ~0; /* Any row index is ok. */
1819 }
1820
1821 return (mask & (1 << ri));
1822}
1823
1824static int
1825iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
1826{
1827 uint32_t mask;
1828
1829 switch (pe) {
1830 /*
1831 * Events valid only on counter 0.
1832 */
1833 case PMC_EV_IAP_EVENT_60H_01H:
1834 case PMC_EV_IAP_EVENT_60H_02H:
1835 case PMC_EV_IAP_EVENT_60H_04H:
1836 case PMC_EV_IAP_EVENT_60H_08H:
1837 case PMC_EV_IAP_EVENT_B3H_01H:
1838 case PMC_EV_IAP_EVENT_B3H_02H:
1839 case PMC_EV_IAP_EVENT_B3H_04H:
1840 mask = 0x1;
1841 break;
1842
1843 /*
1844 * Events valid only on counter 0, 1.
1845 */
1846 case PMC_EV_IAP_EVENT_4CH_01H:
1847 case PMC_EV_IAP_EVENT_4EH_01H:
1848 case PMC_EV_IAP_EVENT_4EH_02H:
1849 case PMC_EV_IAP_EVENT_4EH_04H:
1850 case PMC_EV_IAP_EVENT_51H_01H:
1851 case PMC_EV_IAP_EVENT_51H_02H:
1852 case PMC_EV_IAP_EVENT_51H_04H:
1853 case PMC_EV_IAP_EVENT_51H_08H:
1854 case PMC_EV_IAP_EVENT_63H_01H:
1855 case PMC_EV_IAP_EVENT_63H_02H:
1856 mask = 0x3;
1857 break;
1858
1859 default:
1860 mask = ~0; /* Any row index is ok. */
1861 }
1862
1863 return (mask & (1 << ri));
1864}
1865
1866static int
1867iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri)
1868{
1869 uint32_t mask;
1870
1871 switch (pe) {
1872 /* Events valid only on counter 0. */
1873 case PMC_EV_IAP_EVENT_B7H_01H:
1874 mask = 0x1;
1875 break;
1876 /* Events valid only on counter 1. */
1877 case PMC_EV_IAP_EVENT_C0H_01H:
1878 mask = 0x1;
1879 break;
1880 /* Events valid only on counter 2. */
1881 case PMC_EV_IAP_EVENT_48H_01H:
1882 case PMC_EV_IAP_EVENT_A2H_02H:
1883 mask = 0x4;
1884 break;
1885 /* Events valid only on counter 3. */
1886 case PMC_EV_IAP_EVENT_A3H_08H:
1887 case PMC_EV_IAP_EVENT_BBH_01H:
1888 case PMC_EV_IAP_EVENT_CDH_01H:
1889 case PMC_EV_IAP_EVENT_CDH_02H:
1890 mask = 0x8;
1891 break;
1892 default:
1893 mask = ~0; /* Any row index is ok. */
1894 }
1895
1896 return (mask & (1 << ri));
1897}
1898
1899static int
1900iap_event_ok_on_counter(enum pmc_event pe, int ri)
1901{
1902 uint32_t mask;
1903
1904 switch (pe) {
1905 /*
1906 * Events valid only on counter 0.
1907 */
1908 case PMC_EV_IAP_EVENT_10H_00H:
1909 case PMC_EV_IAP_EVENT_14H_00H:
1910 case PMC_EV_IAP_EVENT_18H_00H:
1911 case PMC_EV_IAP_EVENT_B3H_01H:
1912 case PMC_EV_IAP_EVENT_B3H_02H:
1913 case PMC_EV_IAP_EVENT_B3H_04H:
1914 case PMC_EV_IAP_EVENT_C1H_00H:
1915 case PMC_EV_IAP_EVENT_CBH_01H:
1916 case PMC_EV_IAP_EVENT_CBH_02H:
1917 mask = (1 << 0);
1918 break;
1919
1920 /*
1921 * Events valid only on counter 1.
1922 */
1923 case PMC_EV_IAP_EVENT_11H_00H:
1924 case PMC_EV_IAP_EVENT_12H_00H:
1925 case PMC_EV_IAP_EVENT_13H_00H:
1926 mask = (1 << 1);
1927 break;
1928
1929 default:
1930 mask = ~0; /* Any row index is ok. */
1931 }
1932
1933 return (mask & (1 << ri));
1934}
1935
1936static int
1937iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
1938 const struct pmc_op_pmcallocate *a)
1939{
1940 int arch, n, model;
1941 enum pmc_event ev, map;
1942 struct iap_event_descr *ie;
1943 uint32_t c, caps, config, cpuflag, evsel, mask;
1944
1945 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1946 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1947 KASSERT(ri >= 0 && ri < core_iap_npmc,
1948 ("[core,%d] illegal row-index value %d", __LINE__, ri));
1949
1950 /* check requested capabilities */
1951 caps = a->pm_caps;
1952 if ((IAP_PMC_CAPS & caps) != caps)
1953 return (EPERM);
1954 map = 0; /* XXX: silent GCC warning */
1955 arch = iap_is_event_architectural(pm->pm_event, &map);
1956 if (arch == EV_IS_ARCH_NOTSUPP)
1957 return (EOPNOTSUPP);
1958 else if (arch == EV_IS_ARCH_SUPP)
1959 ev = map;
1960 else
1961 ev = pm->pm_event;
1962
1963 /*
1964 * A small number of events are not supported in all the
1965 * processors based on a given microarchitecture.
1966 */
1967 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) {
1968 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
1969 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E)
1970 return (EINVAL);
1971 }
1972
1973 switch (core_cputype) {
1974 case PMC_CPU_INTEL_COREI7:
1975 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
1976 return (EINVAL);
1977 break;
1978 case PMC_CPU_INTEL_SANDYBRIDGE:
1979 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
1980 case PMC_CPU_INTEL_IVYBRIDGE:
1981 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
1982 case PMC_CPU_INTEL_HASWELL:
1983 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0)
1984 return (EINVAL);
1985 break;
1986 case PMC_CPU_INTEL_WESTMERE:
1987 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
1988 return (EINVAL);
1989 break;
1990 default:
1991 if (iap_event_ok_on_counter(ev, ri) == 0)
1992 return (EINVAL);
1993 }
1994
1995 /*
1996 * Look for an event descriptor with matching CPU and event id
1997 * fields.
1998 */
1999
2000 switch (core_cputype) {
2001 default:
2002 case PMC_CPU_INTEL_ATOM:
2003 cpuflag = IAP_F_CA;
2004 break;
2005 case PMC_CPU_INTEL_CORE:
2006 cpuflag = IAP_F_CC;
2007 break;
2008 case PMC_CPU_INTEL_CORE2:
2009 cpuflag = IAP_F_CC2;
2010 break;
2011 case PMC_CPU_INTEL_CORE2EXTREME:
2012 cpuflag = IAP_F_CC2 | IAP_F_CC2E;
2013 break;
2014 case PMC_CPU_INTEL_COREI7:
2015 cpuflag = IAP_F_I7;
2016 break;
2017 case PMC_CPU_INTEL_HASWELL:
2018 cpuflag = IAP_F_HW;
2019 break;
2020 case PMC_CPU_INTEL_IVYBRIDGE:
2021 cpuflag = IAP_F_IB;
2022 break;
2023 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2024 cpuflag = IAP_F_IBX;
2025 break;
2026 case PMC_CPU_INTEL_SANDYBRIDGE:
2027 cpuflag = IAP_F_SB;
2028 break;
2029 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2030 cpuflag = IAP_F_SBX;
2031 break;
2032 case PMC_CPU_INTEL_WESTMERE:
2033 cpuflag = IAP_F_WM;
2034 break;
2035 }
2036
2037 for (n = 0, ie = iap_events; n < niap_events; n++, ie++)
2038 if (ie->iap_ev == ev && ie->iap_flags & cpuflag)
2039 break;
2040
2041 if (n == niap_events)
2042 return (EINVAL);
2043
2044 /*
2045 * A matching event descriptor has been found, so start
2046 * assembling the contents of the event select register.
2047 */
2048 evsel = ie->iap_evcode;
2049
2050 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK;
2051
2052 /*
2053 * If the event uses a fixed umask value, reject any umask
2054 * bits set by the user.
2055 */
2056 if (ie->iap_flags & IAP_F_FM) {
2057
2058 if (IAP_UMASK(config) != 0)
2059 return (EINVAL);
2060
2061 evsel |= (ie->iap_umask << 8);
2062
2063 } else {
2064
2065 /*
2066 * Otherwise, the UMASK value needs to be taken from
2067 * the MD fields of the allocation request. Reject
2068 * requests that specify reserved bits.
2069 */
2070
2071 mask = 0;
2072
2073 if (ie->iap_umask & IAP_M_CORE) {
2074 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL &&
2075 c != IAP_CORE_THIS)
2076 return (EINVAL);
2077 mask |= IAP_F_CORE;
2078 }
2079
2080 if (ie->iap_umask & IAP_M_AGENT)
2081 mask |= IAP_F_AGENT;
2082
2083 if (ie->iap_umask & IAP_M_PREFETCH) {
2084
2085 if ((c = (config & IAP_F_PREFETCH)) ==
2086 IAP_PREFETCH_RESERVED)
2087 return (EINVAL);
2088
2089 mask |= IAP_F_PREFETCH;
2090 }
2091
2092 if (ie->iap_umask & IAP_M_MESI)
2093 mask |= IAP_F_MESI;
2094
2095 if (ie->iap_umask & IAP_M_SNOOPRESPONSE)
2096 mask |= IAP_F_SNOOPRESPONSE;
2097
2098 if (ie->iap_umask & IAP_M_SNOOPTYPE)
2099 mask |= IAP_F_SNOOPTYPE;
2100
2101 if (ie->iap_umask & IAP_M_TRANSITION)
2102 mask |= IAP_F_TRANSITION;
2103
2104 /*
2105 * If bits outside of the allowed set of umask bits
2106 * are set, reject the request.
2107 */
2108 if (config & ~mask)
2109 return (EINVAL);
2110
2111 evsel |= (config & mask);
2112
2113 }
2114
2115 /*
2116 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier.
2117 */
2118 if (core_cputype == PMC_CPU_INTEL_ATOM ||
2119 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2120 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON)
2121 evsel |= (config & IAP_ANY);
2122 else if (config & IAP_ANY)
2123 return (EINVAL);
2124
2125 /*
2126 * Check offcore response configuration.
2127 */
2128 if (a->pm_md.pm_iap.pm_iap_rsp != 0) {
2129 if (ev != PMC_EV_IAP_EVENT_B7H_01H &&
2130 ev != PMC_EV_IAP_EVENT_BBH_01H)
2131 return (EINVAL);
2132 if (core_cputype == PMC_CPU_INTEL_COREI7 &&
2133 ev == PMC_EV_IAP_EVENT_BBH_01H)
2134 return (EINVAL);
2135 if ((core_cputype == PMC_CPU_INTEL_COREI7 ||
2136 core_cputype == PMC_CPU_INTEL_WESTMERE) &&
2137 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM)
2138 return (EINVAL);
2139 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2140 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
2141 core_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
2142 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) &&
2143 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB)
2144 return (EINVAL);
2145 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp;
2146 }
2147
2148 if (caps & PMC_CAP_THRESHOLD)
2149 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK);
2150 if (caps & PMC_CAP_USER)
2151 evsel |= IAP_USR;
2152 if (caps & PMC_CAP_SYSTEM)
2153 evsel |= IAP_OS;
2154 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
2155 evsel |= (IAP_OS | IAP_USR);
2156 if (caps & PMC_CAP_EDGE)
2157 evsel |= IAP_EDGE;
2158 if (caps & PMC_CAP_INVERT)
2159 evsel |= IAP_INV;
2160 if (caps & PMC_CAP_INTERRUPT)
2161 evsel |= IAP_INT;
2162
2163 pm->pm_md.pm_iap.pm_iap_evsel = evsel;
2164
2165 return (0);
2166}
2167
2168static int
2169iap_config_pmc(int cpu, int ri, struct pmc *pm)
2170{
2171 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2172 ("[core,%d] illegal CPU %d", __LINE__, cpu));
2173
2174 KASSERT(ri >= 0 && ri < core_iap_npmc,
2175 ("[core,%d] illegal row-index %d", __LINE__, ri));
2176
2177 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
2178
2179 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
2180 cpu));
2181
2182 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
2183
2184 return (0);
2185}
2186
2187static int
2188iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
2189{
2190 int error;
2191 struct pmc_hw *phw;
2192 char iap_name[PMC_NAME_MAX];
2193
2194 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
2195
2196 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
2197 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
2198 NULL)) != 0)
2199 return (error);
2200
2201 pi->pm_class = PMC_CLASS_IAP;
2202
2203 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
2204 pi->pm_enabled = TRUE;
2205 *ppmc = phw->phw_pmc;
2206 } else {
2207 pi->pm_enabled = FALSE;
2208 *ppmc = NULL;
2209 }
2210
2211 return (0);
2212}
2213
2214static int
2215iap_get_config(int cpu, int ri, struct pmc **ppm)
2216{
2217 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2218
2219 return (0);
2220}
2221
2222static int
2223iap_get_msr(int ri, uint32_t *msr)
2224{
2225 KASSERT(ri >= 0 && ri < core_iap_npmc,
2226 ("[iap,%d] ri %d out of range", __LINE__, ri));
2227
2228 *msr = ri;
2229
2230 return (0);
2231}
2232
2233static int
2234iap_read_pmc(int cpu, int ri, pmc_value_t *v)
2235{
2236 struct pmc *pm;
2237 pmc_value_t tmp;
2238
2239 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2240 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2241 KASSERT(ri >= 0 && ri < core_iap_npmc,
2242 ("[core,%d] illegal row-index %d", __LINE__, ri));
2243
2244 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2245
2246 KASSERT(pm,
2247 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
2248 ri));
2249
2250 tmp = rdpmc(ri);
2251 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2252 *v = iap_perfctr_value_to_reload_count(tmp);
2253 else
2254 *v = tmp & ((1ULL << core_iap_width) - 1);
2255
2256 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
2257 ri, *v);
2258
2259 return (0);
2260}
2261
2262static int
2263iap_release_pmc(int cpu, int ri, struct pmc *pm)
2264{
2265 (void) pm;
2266
2267 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
2268 pm);
2269
2270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2271 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2272 KASSERT(ri >= 0 && ri < core_iap_npmc,
2273 ("[core,%d] illegal row-index %d", __LINE__, ri));
2274
2275 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
2276 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
2277
2278 return (0);
2279}
2280
2281static int
2282iap_start_pmc(int cpu, int ri)
2283{
2284 struct pmc *pm;
2285 uint32_t evsel;
2286 struct core_cpu *cc;
2287
2288 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2289 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2290 KASSERT(ri >= 0 && ri < core_iap_npmc,
2291 ("[core,%d] illegal row-index %d", __LINE__, ri));
2292
2293 cc = core_pcpu[cpu];
2294 pm = cc->pc_corepmcs[ri].phw_pmc;
2295
2296 KASSERT(pm,
2297 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
2298 __LINE__, cpu, ri));
2299
2300 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
2301
2302 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
2303
2304 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
2305 cpu, ri, IAP_EVSEL0 + ri, evsel);
2306
2307 /* Event specific configuration. */
2308 switch (pm->pm_event) {
2309 case PMC_EV_IAP_EVENT_B7H_01H:
2310 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
2311 break;
2312 case PMC_EV_IAP_EVENT_BBH_01H:
2313 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
2314 break;
2315 default:
2316 break;
2317 }
2318
2319 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
2320
2321 if (core_cputype == PMC_CPU_INTEL_CORE)
2322 return (0);
2323
2324 do {
2325 cc->pc_resync = 0;
2326 cc->pc_globalctrl |= (1ULL << ri);
2327 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2328 } while (cc->pc_resync != 0);
2329
2330 return (0);
2331}
2332
2333static int
2334iap_stop_pmc(int cpu, int ri)
2335{
2336 struct pmc *pm;
2337 struct core_cpu *cc;
2338 uint64_t msr;
2339
2340 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2341 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2342 KASSERT(ri >= 0 && ri < core_iap_npmc,
2343 ("[core,%d] illegal row index %d", __LINE__, ri));
2344
2345 cc = core_pcpu[cpu];
2346 pm = cc->pc_corepmcs[ri].phw_pmc;
2347
2348 KASSERT(pm,
2349 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2350 cpu, ri));
2351
2352 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
2353
2354 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2355 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */
2356
2357 if (core_cputype == PMC_CPU_INTEL_CORE)
2358 return (0);
2359
2360 msr = 0;
2361 do {
2362 cc->pc_resync = 0;
2363 cc->pc_globalctrl &= ~(1ULL << ri);
2364 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2365 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2366 } while (cc->pc_resync != 0);
2367
2368 return (0);
2369}
2370
2371static int
2372iap_write_pmc(int cpu, int ri, pmc_value_t v)
2373{
2374 struct pmc *pm;
2375 struct core_cpu *cc;
2376
2377 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2378 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2379 KASSERT(ri >= 0 && ri < core_iap_npmc,
2380 ("[core,%d] illegal row index %d", __LINE__, ri));
2381
2382 cc = core_pcpu[cpu];
2383 pm = cc->pc_corepmcs[ri].phw_pmc;
2384
2385 KASSERT(pm,
2386 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2387 cpu, ri));
2388
2389 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
2390 IAP_PMC0 + ri, v);
2391
2392 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2393 v = iap_reload_count_to_perfctr_value(v);
2394
2395 /*
2396 * Write the new value to the counter. The counter will be in
2397 * a stopped state when the pcd_write() entry point is called.
2398 */
2399
2400 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1));
2401
2402 return (0);
2403}
2404
2405
2406static void
2407iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
2408 int flags)
2409{
2410 struct pmc_classdep *pcd;
2411
2412 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
2413
2414 PMCDBG(MDP,INI,1, "%s", "iap-initialize");
2415
2416 /* Remember the set of architectural events supported. */
2417 core_architectural_events = ~flags;
2418
2419 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
2420
2421 pcd->pcd_caps = IAP_PMC_CAPS;
2422 pcd->pcd_class = PMC_CLASS_IAP;
2423 pcd->pcd_num = npmc;
2424 pcd->pcd_ri = md->pmd_npmc;
2425 pcd->pcd_width = pmcwidth;
2426
2427 pcd->pcd_allocate_pmc = iap_allocate_pmc;
2428 pcd->pcd_config_pmc = iap_config_pmc;
2429 pcd->pcd_describe = iap_describe;
2430 pcd->pcd_get_config = iap_get_config;
2431 pcd->pcd_get_msr = iap_get_msr;
2432 pcd->pcd_pcpu_fini = core_pcpu_fini;
2433 pcd->pcd_pcpu_init = core_pcpu_init;
2434 pcd->pcd_read_pmc = iap_read_pmc;
2435 pcd->pcd_release_pmc = iap_release_pmc;
2436 pcd->pcd_start_pmc = iap_start_pmc;
2437 pcd->pcd_stop_pmc = iap_stop_pmc;
2438 pcd->pcd_write_pmc = iap_write_pmc;
2439
2440 md->pmd_npmc += npmc;
2441}
2442
2443static int
2444core_intr(int cpu, struct trapframe *tf)
2445{
2446 pmc_value_t v;
2447 struct pmc *pm;
2448 struct core_cpu *cc;
2449 int error, found_interrupt, ri;
2450 uint64_t msr;
2451
2452 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2453 TRAPF_USERMODE(tf));
2454
2455 found_interrupt = 0;
2456 cc = core_pcpu[cpu];
2457
2458 for (ri = 0; ri < core_iap_npmc; ri++) {
2459
2460 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
2461 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2462 continue;
2463
2464 if (!iap_pmc_has_overflowed(ri))
2465 continue;
2466
2467 found_interrupt = 1;
2468
2469 if (pm->pm_state != PMC_STATE_RUNNING)
2470 continue;
2471
2472 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2473 TRAPF_USERMODE(tf));
2474
2475 v = pm->pm_sc.pm_reloadcount;
2476 v = iaf_reload_count_to_perfctr_value(v);
2477
2478 /*
2479 * Stop the counter, reload it but only restart it if
2480 * the PMC is not stalled.
2481 */
2482 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2483 wrmsr(IAP_EVSEL0 + ri, msr);
2484 wrmsr(IAP_PMC0 + ri, v);
2485
2486 if (error)
2487 continue;
2488
2489 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
2490 IAP_EN));
2491 }
2492
2493 if (found_interrupt)
2494 lapic_reenable_pmc();
2495
2496 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2497 &pmc_stats.pm_intr_ignored, 1);
2498
2499 return (found_interrupt);
2500}
2501
2502static int
2503core2_intr(int cpu, struct trapframe *tf)
2504{
2505 int error, found_interrupt, n;
2506 uint64_t flag, intrstatus, intrenable, msr;
2507 struct pmc *pm;
2508 struct core_cpu *cc;
2509 pmc_value_t v;
2510
2511 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2512 TRAPF_USERMODE(tf));
2513
2514 /*
2515 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
2516 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
2517 * the current set of interrupting PMCs and process these
2518 * after stopping them.
2519 */
2520 intrstatus = rdmsr(IA_GLOBAL_STATUS);
2521 intrenable = intrstatus & core_pmcmask;
2522
2523 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
2524 (uintmax_t) intrstatus);
2525
2526 found_interrupt = 0;
2527 cc = core_pcpu[cpu];
2528
2529 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
2530
2531 cc->pc_globalctrl &= ~intrenable;
2532 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
2533
2534 /*
2535 * Stop PMCs and clear overflow status bits.
2536 */
2537 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2538 wrmsr(IA_GLOBAL_CTRL, msr);
2539 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
2540 IA_GLOBAL_STATUS_FLAG_OVFBUF |
2541 IA_GLOBAL_STATUS_FLAG_CONDCHG);
2542
2543 /*
2544 * Look for interrupts from fixed function PMCs.
2545 */
2546 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
2547 n++, flag <<= 1) {
2548
2549 if ((intrstatus & flag) == 0)
2550 continue;
2551
2552 found_interrupt = 1;
2553
2554 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
2555 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2556 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2557 continue;
2558
2559 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2560 TRAPF_USERMODE(tf));
2561 if (error)
2562 intrenable &= ~flag;
2563
2564 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2565
2566 /* Reload sampling count. */
2567 wrmsr(IAF_CTR0 + n, v);
2568
2569 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu,
2570 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
2571 }
2572
2573 /*
2574 * Process interrupts from the programmable counters.
2575 */
2576 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
2577 if ((intrstatus & flag) == 0)
2578 continue;
2579
2580 found_interrupt = 1;
2581
2582 pm = cc->pc_corepmcs[n].phw_pmc;
2583 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2584 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2585 continue;
2586
2587 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2588 TRAPF_USERMODE(tf));
2589 if (error)
2590 intrenable &= ~flag;
2591
2592 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2593
2594 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
2595 (uintmax_t) v);
2596
2597 /* Reload sampling count. */
2598 wrmsr(IAP_PMC0 + n, v);
2599 }
2600
2601 /*
2602 * Reenable all non-stalled PMCs.
2603 */
2604 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
2605 (uintmax_t) intrenable);
2606
2607 cc->pc_globalctrl |= intrenable;
2608
2609 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
2610
2611 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
2612 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
2613 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
2614 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
2615 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
2616
2617 if (found_interrupt)
2618 lapic_reenable_pmc();
2619
2620 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2621 &pmc_stats.pm_intr_ignored, 1);
2622
2623 return (found_interrupt);
2624}
2625
2626int
2627pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
2628{
2629 int cpuid[CORE_CPUID_REQUEST_SIZE];
2630 int ipa_version, flags, nflags;
2631
2632 do_cpuid(CORE_CPUID_REQUEST, cpuid);
2633
2634 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
2635
2636 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
2637 md->pmd_cputype, maxcpu, ipa_version);
2638
2639 if (ipa_version < 1 || ipa_version > 3) {
2640 /* Unknown PMC architecture. */
2641 printf("hwpc_core: unknown PMC architecture: %d\n",
2642 ipa_version);
2643 return (EPROGMISMATCH);
2644 }
2645
2646 core_cputype = md->pmd_cputype;
2647
2648 core_pmcmask = 0;
2649
2650 /*
2651 * Initialize programmable counters.
2652 */
2653 KASSERT(ipa_version >= 1,
2654 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
2655
2656 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
2657 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
2658
2659 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
2660
2661 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
2662 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
2663
2664 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
2665
2666 /*
2667 * Initialize fixed function counters, if present.
2668 */
2669 if (core_cputype != PMC_CPU_INTEL_CORE) {
2670 KASSERT(ipa_version >= 2,
2671 ("[core,%d] ipa_version %d too small", __LINE__,
2672 ipa_version));
2673
2674 core_iaf_ri = core_iap_npmc;
2675 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
2676 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
2677
2678 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
2679 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
2680 }
2681
2682 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
2683 core_iaf_ri);
2684
2685 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC,
2686 M_ZERO | M_WAITOK);
2687
2688 /*
2689 * Choose the appropriate interrupt handler.
2690 */
2691 if (ipa_version == 1)
2692 md->pmd_intr = core_intr;
2693 else
2694 md->pmd_intr = core2_intr;
2695
2696 md->pmd_pcpu_fini = NULL;
2697 md->pmd_pcpu_init = NULL;
2698
2699 return (0);
2700}
2701
2702void
2703pmc_core_finalize(struct pmc_mdep *md)
2704{
2705 PMCDBG(MDP,INI,1, "%s", "core-finalize");
2706
2707 free(core_pcpu, M_PMC);
2708 core_pcpu = NULL;
2709}
1532
1533 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1534 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1535 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1536 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1537 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1538 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1539 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1540 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW),
1541 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1542 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1543 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1544
1545 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1546 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1547 IAP_F_IBX | IAP_F_HW),
1548 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1549 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1550 IAP_F_IBX | IAP_F_HW),
1551 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1552 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1553 IAP_F_IBX | IAP_F_HW),
1554 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1555 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1556 IAP_F_IBX | IAP_F_HW),
1557 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1558 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1559 IAP_F_IBX | IAP_F_HW),
1560
1561 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
1562
1563 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX |
1564 IAP_F_IBX | IAP_F_HW),
1565 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1566 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX),
1567 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX),
1568
1569 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1570 IAP_F_I7 | IAP_F_WM),
1571 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1572 IAP_F_SB | IAP_F_SBX),
1573 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1574 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1575 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1576
1577 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1578 IAP_F_I7 | IAP_F_WM),
1579 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1580 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1581 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1582 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1583
1584 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC),
1585
1586 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC),
1587 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC),
1588 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC),
1589 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC),
1590 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC),
1591
1592 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC),
1593 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC),
1594 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC),
1595 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC),
1596
1597 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC),
1598 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC),
1599 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC),
1600
1601 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC),
1602 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1603
1604 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1605 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1606 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1607 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1608 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1609 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1610
1611 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1612 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1613 IAP_F_WM),
1614
1615 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC),
1616
1617 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1618 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O),
1619
1620 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1621
1622 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1623 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1624 IAP_F_WM | IAP_F_SBX),
1625 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1626 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IBX | IAP_F_HW),
1627
1628 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1629 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1630 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O),
1631
1632 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
1633
1634 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1635 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1636 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1637 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1638 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1639 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1640 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1641 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1642 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1643 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1644 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1645 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1646 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1647 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1648 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1649 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1650 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1651
1652 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1653 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1654 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1655 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1656 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1657 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1658 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1659 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1660
1661 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1662 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1663 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1664 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1665 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1666 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1667 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW),
1668 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW),
1669 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1670 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1671 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
1672 IAP_F_IBX),
1673 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1674
1675 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
1676 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O),
1677 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O),
1678 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O),
1679 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O),
1680 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O),
1681
1682 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O),
1683 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
1684 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1685 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
1686 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1687 IAP_F_SB | IAP_F_SBX),
1688
1689 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1690
1691 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1692 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1693 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1694
1695 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1696 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O),
1697
1698 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1699 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1700 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1701 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1702 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1703 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1704 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1705};
1706
1707static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]);
1708
1709static pmc_value_t
1710iap_perfctr_value_to_reload_count(pmc_value_t v)
1711{
1712 v &= (1ULL << core_iap_width) - 1;
1713 return (1ULL << core_iap_width) - v;
1714}
1715
1716static pmc_value_t
1717iap_reload_count_to_perfctr_value(pmc_value_t rlc)
1718{
1719 return (1ULL << core_iap_width) - rlc;
1720}
1721
1722static int
1723iap_pmc_has_overflowed(int ri)
1724{
1725 uint64_t v;
1726
1727 /*
1728 * We treat a Core (i.e., Intel architecture v1) PMC as has
1729 * having overflowed if its MSB is zero.
1730 */
1731 v = rdpmc(ri);
1732 return ((v & (1ULL << (core_iap_width - 1))) == 0);
1733}
1734
1735/*
1736 * Check an event against the set of supported architectural events.
1737 *
1738 * If the event is not architectural EV_IS_NOTARCH is returned.
1739 * If the event is architectural and supported on this CPU, the correct
1740 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned.
1741 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP.
1742 */
1743
1744static int
1745iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map)
1746{
1747 enum core_arch_events ae;
1748
1749 switch (pe) {
1750 case PMC_EV_IAP_ARCH_UNH_COR_CYC:
1751 ae = CORE_AE_UNHALTED_CORE_CYCLES;
1752 *map = PMC_EV_IAP_EVENT_C4H_00H;
1753 break;
1754 case PMC_EV_IAP_ARCH_INS_RET:
1755 ae = CORE_AE_INSTRUCTION_RETIRED;
1756 *map = PMC_EV_IAP_EVENT_C0H_00H;
1757 break;
1758 case PMC_EV_IAP_ARCH_UNH_REF_CYC:
1759 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES;
1760 *map = PMC_EV_IAP_EVENT_3CH_01H;
1761 break;
1762 case PMC_EV_IAP_ARCH_LLC_REF:
1763 ae = CORE_AE_LLC_REFERENCE;
1764 *map = PMC_EV_IAP_EVENT_2EH_4FH;
1765 break;
1766 case PMC_EV_IAP_ARCH_LLC_MIS:
1767 ae = CORE_AE_LLC_MISSES;
1768 *map = PMC_EV_IAP_EVENT_2EH_41H;
1769 break;
1770 case PMC_EV_IAP_ARCH_BR_INS_RET:
1771 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED;
1772 *map = PMC_EV_IAP_EVENT_C4H_00H;
1773 break;
1774 case PMC_EV_IAP_ARCH_BR_MIS_RET:
1775 ae = CORE_AE_BRANCH_MISSES_RETIRED;
1776 *map = PMC_EV_IAP_EVENT_C5H_00H;
1777 break;
1778
1779 default: /* Non architectural event. */
1780 return (EV_IS_NOTARCH);
1781 }
1782
1783 return (((core_architectural_events & (1 << ae)) == 0) ?
1784 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP);
1785}
1786
1787static int
1788iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri)
1789{
1790 uint32_t mask;
1791
1792 switch (pe) {
1793 /*
1794 * Events valid only on counter 0, 1.
1795 */
1796 case PMC_EV_IAP_EVENT_40H_01H:
1797 case PMC_EV_IAP_EVENT_40H_02H:
1798 case PMC_EV_IAP_EVENT_40H_04H:
1799 case PMC_EV_IAP_EVENT_40H_08H:
1800 case PMC_EV_IAP_EVENT_40H_0FH:
1801 case PMC_EV_IAP_EVENT_41H_02H:
1802 case PMC_EV_IAP_EVENT_41H_04H:
1803 case PMC_EV_IAP_EVENT_41H_08H:
1804 case PMC_EV_IAP_EVENT_42H_01H:
1805 case PMC_EV_IAP_EVENT_42H_02H:
1806 case PMC_EV_IAP_EVENT_42H_04H:
1807 case PMC_EV_IAP_EVENT_42H_08H:
1808 case PMC_EV_IAP_EVENT_43H_01H:
1809 case PMC_EV_IAP_EVENT_43H_02H:
1810 case PMC_EV_IAP_EVENT_51H_01H:
1811 case PMC_EV_IAP_EVENT_51H_02H:
1812 case PMC_EV_IAP_EVENT_51H_04H:
1813 case PMC_EV_IAP_EVENT_51H_08H:
1814 case PMC_EV_IAP_EVENT_63H_01H:
1815 case PMC_EV_IAP_EVENT_63H_02H:
1816 mask = 0x3;
1817 break;
1818
1819 default:
1820 mask = ~0; /* Any row index is ok. */
1821 }
1822
1823 return (mask & (1 << ri));
1824}
1825
1826static int
1827iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
1828{
1829 uint32_t mask;
1830
1831 switch (pe) {
1832 /*
1833 * Events valid only on counter 0.
1834 */
1835 case PMC_EV_IAP_EVENT_60H_01H:
1836 case PMC_EV_IAP_EVENT_60H_02H:
1837 case PMC_EV_IAP_EVENT_60H_04H:
1838 case PMC_EV_IAP_EVENT_60H_08H:
1839 case PMC_EV_IAP_EVENT_B3H_01H:
1840 case PMC_EV_IAP_EVENT_B3H_02H:
1841 case PMC_EV_IAP_EVENT_B3H_04H:
1842 mask = 0x1;
1843 break;
1844
1845 /*
1846 * Events valid only on counter 0, 1.
1847 */
1848 case PMC_EV_IAP_EVENT_4CH_01H:
1849 case PMC_EV_IAP_EVENT_4EH_01H:
1850 case PMC_EV_IAP_EVENT_4EH_02H:
1851 case PMC_EV_IAP_EVENT_4EH_04H:
1852 case PMC_EV_IAP_EVENT_51H_01H:
1853 case PMC_EV_IAP_EVENT_51H_02H:
1854 case PMC_EV_IAP_EVENT_51H_04H:
1855 case PMC_EV_IAP_EVENT_51H_08H:
1856 case PMC_EV_IAP_EVENT_63H_01H:
1857 case PMC_EV_IAP_EVENT_63H_02H:
1858 mask = 0x3;
1859 break;
1860
1861 default:
1862 mask = ~0; /* Any row index is ok. */
1863 }
1864
1865 return (mask & (1 << ri));
1866}
1867
1868static int
1869iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri)
1870{
1871 uint32_t mask;
1872
1873 switch (pe) {
1874 /* Events valid only on counter 0. */
1875 case PMC_EV_IAP_EVENT_B7H_01H:
1876 mask = 0x1;
1877 break;
1878 /* Events valid only on counter 1. */
1879 case PMC_EV_IAP_EVENT_C0H_01H:
1880 mask = 0x1;
1881 break;
1882 /* Events valid only on counter 2. */
1883 case PMC_EV_IAP_EVENT_48H_01H:
1884 case PMC_EV_IAP_EVENT_A2H_02H:
1885 mask = 0x4;
1886 break;
1887 /* Events valid only on counter 3. */
1888 case PMC_EV_IAP_EVENT_A3H_08H:
1889 case PMC_EV_IAP_EVENT_BBH_01H:
1890 case PMC_EV_IAP_EVENT_CDH_01H:
1891 case PMC_EV_IAP_EVENT_CDH_02H:
1892 mask = 0x8;
1893 break;
1894 default:
1895 mask = ~0; /* Any row index is ok. */
1896 }
1897
1898 return (mask & (1 << ri));
1899}
1900
1901static int
1902iap_event_ok_on_counter(enum pmc_event pe, int ri)
1903{
1904 uint32_t mask;
1905
1906 switch (pe) {
1907 /*
1908 * Events valid only on counter 0.
1909 */
1910 case PMC_EV_IAP_EVENT_10H_00H:
1911 case PMC_EV_IAP_EVENT_14H_00H:
1912 case PMC_EV_IAP_EVENT_18H_00H:
1913 case PMC_EV_IAP_EVENT_B3H_01H:
1914 case PMC_EV_IAP_EVENT_B3H_02H:
1915 case PMC_EV_IAP_EVENT_B3H_04H:
1916 case PMC_EV_IAP_EVENT_C1H_00H:
1917 case PMC_EV_IAP_EVENT_CBH_01H:
1918 case PMC_EV_IAP_EVENT_CBH_02H:
1919 mask = (1 << 0);
1920 break;
1921
1922 /*
1923 * Events valid only on counter 1.
1924 */
1925 case PMC_EV_IAP_EVENT_11H_00H:
1926 case PMC_EV_IAP_EVENT_12H_00H:
1927 case PMC_EV_IAP_EVENT_13H_00H:
1928 mask = (1 << 1);
1929 break;
1930
1931 default:
1932 mask = ~0; /* Any row index is ok. */
1933 }
1934
1935 return (mask & (1 << ri));
1936}
1937
1938static int
1939iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
1940 const struct pmc_op_pmcallocate *a)
1941{
1942 int arch, n, model;
1943 enum pmc_event ev, map;
1944 struct iap_event_descr *ie;
1945 uint32_t c, caps, config, cpuflag, evsel, mask;
1946
1947 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1948 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1949 KASSERT(ri >= 0 && ri < core_iap_npmc,
1950 ("[core,%d] illegal row-index value %d", __LINE__, ri));
1951
1952 /* check requested capabilities */
1953 caps = a->pm_caps;
1954 if ((IAP_PMC_CAPS & caps) != caps)
1955 return (EPERM);
1956 map = 0; /* XXX: silent GCC warning */
1957 arch = iap_is_event_architectural(pm->pm_event, &map);
1958 if (arch == EV_IS_ARCH_NOTSUPP)
1959 return (EOPNOTSUPP);
1960 else if (arch == EV_IS_ARCH_SUPP)
1961 ev = map;
1962 else
1963 ev = pm->pm_event;
1964
1965 /*
1966 * A small number of events are not supported in all the
1967 * processors based on a given microarchitecture.
1968 */
1969 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) {
1970 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
1971 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E)
1972 return (EINVAL);
1973 }
1974
1975 switch (core_cputype) {
1976 case PMC_CPU_INTEL_COREI7:
1977 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
1978 return (EINVAL);
1979 break;
1980 case PMC_CPU_INTEL_SANDYBRIDGE:
1981 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
1982 case PMC_CPU_INTEL_IVYBRIDGE:
1983 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
1984 case PMC_CPU_INTEL_HASWELL:
1985 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0)
1986 return (EINVAL);
1987 break;
1988 case PMC_CPU_INTEL_WESTMERE:
1989 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
1990 return (EINVAL);
1991 break;
1992 default:
1993 if (iap_event_ok_on_counter(ev, ri) == 0)
1994 return (EINVAL);
1995 }
1996
1997 /*
1998 * Look for an event descriptor with matching CPU and event id
1999 * fields.
2000 */
2001
2002 switch (core_cputype) {
2003 default:
2004 case PMC_CPU_INTEL_ATOM:
2005 cpuflag = IAP_F_CA;
2006 break;
2007 case PMC_CPU_INTEL_CORE:
2008 cpuflag = IAP_F_CC;
2009 break;
2010 case PMC_CPU_INTEL_CORE2:
2011 cpuflag = IAP_F_CC2;
2012 break;
2013 case PMC_CPU_INTEL_CORE2EXTREME:
2014 cpuflag = IAP_F_CC2 | IAP_F_CC2E;
2015 break;
2016 case PMC_CPU_INTEL_COREI7:
2017 cpuflag = IAP_F_I7;
2018 break;
2019 case PMC_CPU_INTEL_HASWELL:
2020 cpuflag = IAP_F_HW;
2021 break;
2022 case PMC_CPU_INTEL_IVYBRIDGE:
2023 cpuflag = IAP_F_IB;
2024 break;
2025 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2026 cpuflag = IAP_F_IBX;
2027 break;
2028 case PMC_CPU_INTEL_SANDYBRIDGE:
2029 cpuflag = IAP_F_SB;
2030 break;
2031 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2032 cpuflag = IAP_F_SBX;
2033 break;
2034 case PMC_CPU_INTEL_WESTMERE:
2035 cpuflag = IAP_F_WM;
2036 break;
2037 }
2038
2039 for (n = 0, ie = iap_events; n < niap_events; n++, ie++)
2040 if (ie->iap_ev == ev && ie->iap_flags & cpuflag)
2041 break;
2042
2043 if (n == niap_events)
2044 return (EINVAL);
2045
2046 /*
2047 * A matching event descriptor has been found, so start
2048 * assembling the contents of the event select register.
2049 */
2050 evsel = ie->iap_evcode;
2051
2052 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK;
2053
2054 /*
2055 * If the event uses a fixed umask value, reject any umask
2056 * bits set by the user.
2057 */
2058 if (ie->iap_flags & IAP_F_FM) {
2059
2060 if (IAP_UMASK(config) != 0)
2061 return (EINVAL);
2062
2063 evsel |= (ie->iap_umask << 8);
2064
2065 } else {
2066
2067 /*
2068 * Otherwise, the UMASK value needs to be taken from
2069 * the MD fields of the allocation request. Reject
2070 * requests that specify reserved bits.
2071 */
2072
2073 mask = 0;
2074
2075 if (ie->iap_umask & IAP_M_CORE) {
2076 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL &&
2077 c != IAP_CORE_THIS)
2078 return (EINVAL);
2079 mask |= IAP_F_CORE;
2080 }
2081
2082 if (ie->iap_umask & IAP_M_AGENT)
2083 mask |= IAP_F_AGENT;
2084
2085 if (ie->iap_umask & IAP_M_PREFETCH) {
2086
2087 if ((c = (config & IAP_F_PREFETCH)) ==
2088 IAP_PREFETCH_RESERVED)
2089 return (EINVAL);
2090
2091 mask |= IAP_F_PREFETCH;
2092 }
2093
2094 if (ie->iap_umask & IAP_M_MESI)
2095 mask |= IAP_F_MESI;
2096
2097 if (ie->iap_umask & IAP_M_SNOOPRESPONSE)
2098 mask |= IAP_F_SNOOPRESPONSE;
2099
2100 if (ie->iap_umask & IAP_M_SNOOPTYPE)
2101 mask |= IAP_F_SNOOPTYPE;
2102
2103 if (ie->iap_umask & IAP_M_TRANSITION)
2104 mask |= IAP_F_TRANSITION;
2105
2106 /*
2107 * If bits outside of the allowed set of umask bits
2108 * are set, reject the request.
2109 */
2110 if (config & ~mask)
2111 return (EINVAL);
2112
2113 evsel |= (config & mask);
2114
2115 }
2116
2117 /*
2118 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier.
2119 */
2120 if (core_cputype == PMC_CPU_INTEL_ATOM ||
2121 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2122 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON)
2123 evsel |= (config & IAP_ANY);
2124 else if (config & IAP_ANY)
2125 return (EINVAL);
2126
2127 /*
2128 * Check offcore response configuration.
2129 */
2130 if (a->pm_md.pm_iap.pm_iap_rsp != 0) {
2131 if (ev != PMC_EV_IAP_EVENT_B7H_01H &&
2132 ev != PMC_EV_IAP_EVENT_BBH_01H)
2133 return (EINVAL);
2134 if (core_cputype == PMC_CPU_INTEL_COREI7 &&
2135 ev == PMC_EV_IAP_EVENT_BBH_01H)
2136 return (EINVAL);
2137 if ((core_cputype == PMC_CPU_INTEL_COREI7 ||
2138 core_cputype == PMC_CPU_INTEL_WESTMERE) &&
2139 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM)
2140 return (EINVAL);
2141 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2142 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
2143 core_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
2144 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) &&
2145 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB)
2146 return (EINVAL);
2147 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp;
2148 }
2149
2150 if (caps & PMC_CAP_THRESHOLD)
2151 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK);
2152 if (caps & PMC_CAP_USER)
2153 evsel |= IAP_USR;
2154 if (caps & PMC_CAP_SYSTEM)
2155 evsel |= IAP_OS;
2156 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
2157 evsel |= (IAP_OS | IAP_USR);
2158 if (caps & PMC_CAP_EDGE)
2159 evsel |= IAP_EDGE;
2160 if (caps & PMC_CAP_INVERT)
2161 evsel |= IAP_INV;
2162 if (caps & PMC_CAP_INTERRUPT)
2163 evsel |= IAP_INT;
2164
2165 pm->pm_md.pm_iap.pm_iap_evsel = evsel;
2166
2167 return (0);
2168}
2169
2170static int
2171iap_config_pmc(int cpu, int ri, struct pmc *pm)
2172{
2173 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2174 ("[core,%d] illegal CPU %d", __LINE__, cpu));
2175
2176 KASSERT(ri >= 0 && ri < core_iap_npmc,
2177 ("[core,%d] illegal row-index %d", __LINE__, ri));
2178
2179 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
2180
2181 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
2182 cpu));
2183
2184 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
2185
2186 return (0);
2187}
2188
2189static int
2190iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
2191{
2192 int error;
2193 struct pmc_hw *phw;
2194 char iap_name[PMC_NAME_MAX];
2195
2196 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
2197
2198 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
2199 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
2200 NULL)) != 0)
2201 return (error);
2202
2203 pi->pm_class = PMC_CLASS_IAP;
2204
2205 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
2206 pi->pm_enabled = TRUE;
2207 *ppmc = phw->phw_pmc;
2208 } else {
2209 pi->pm_enabled = FALSE;
2210 *ppmc = NULL;
2211 }
2212
2213 return (0);
2214}
2215
2216static int
2217iap_get_config(int cpu, int ri, struct pmc **ppm)
2218{
2219 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2220
2221 return (0);
2222}
2223
2224static int
2225iap_get_msr(int ri, uint32_t *msr)
2226{
2227 KASSERT(ri >= 0 && ri < core_iap_npmc,
2228 ("[iap,%d] ri %d out of range", __LINE__, ri));
2229
2230 *msr = ri;
2231
2232 return (0);
2233}
2234
2235static int
2236iap_read_pmc(int cpu, int ri, pmc_value_t *v)
2237{
2238 struct pmc *pm;
2239 pmc_value_t tmp;
2240
2241 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2242 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2243 KASSERT(ri >= 0 && ri < core_iap_npmc,
2244 ("[core,%d] illegal row-index %d", __LINE__, ri));
2245
2246 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2247
2248 KASSERT(pm,
2249 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
2250 ri));
2251
2252 tmp = rdpmc(ri);
2253 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2254 *v = iap_perfctr_value_to_reload_count(tmp);
2255 else
2256 *v = tmp & ((1ULL << core_iap_width) - 1);
2257
2258 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
2259 ri, *v);
2260
2261 return (0);
2262}
2263
2264static int
2265iap_release_pmc(int cpu, int ri, struct pmc *pm)
2266{
2267 (void) pm;
2268
2269 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
2270 pm);
2271
2272 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2273 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2274 KASSERT(ri >= 0 && ri < core_iap_npmc,
2275 ("[core,%d] illegal row-index %d", __LINE__, ri));
2276
2277 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
2278 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
2279
2280 return (0);
2281}
2282
2283static int
2284iap_start_pmc(int cpu, int ri)
2285{
2286 struct pmc *pm;
2287 uint32_t evsel;
2288 struct core_cpu *cc;
2289
2290 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2291 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2292 KASSERT(ri >= 0 && ri < core_iap_npmc,
2293 ("[core,%d] illegal row-index %d", __LINE__, ri));
2294
2295 cc = core_pcpu[cpu];
2296 pm = cc->pc_corepmcs[ri].phw_pmc;
2297
2298 KASSERT(pm,
2299 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
2300 __LINE__, cpu, ri));
2301
2302 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
2303
2304 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
2305
2306 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
2307 cpu, ri, IAP_EVSEL0 + ri, evsel);
2308
2309 /* Event specific configuration. */
2310 switch (pm->pm_event) {
2311 case PMC_EV_IAP_EVENT_B7H_01H:
2312 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
2313 break;
2314 case PMC_EV_IAP_EVENT_BBH_01H:
2315 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
2316 break;
2317 default:
2318 break;
2319 }
2320
2321 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
2322
2323 if (core_cputype == PMC_CPU_INTEL_CORE)
2324 return (0);
2325
2326 do {
2327 cc->pc_resync = 0;
2328 cc->pc_globalctrl |= (1ULL << ri);
2329 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2330 } while (cc->pc_resync != 0);
2331
2332 return (0);
2333}
2334
2335static int
2336iap_stop_pmc(int cpu, int ri)
2337{
2338 struct pmc *pm;
2339 struct core_cpu *cc;
2340 uint64_t msr;
2341
2342 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2343 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2344 KASSERT(ri >= 0 && ri < core_iap_npmc,
2345 ("[core,%d] illegal row index %d", __LINE__, ri));
2346
2347 cc = core_pcpu[cpu];
2348 pm = cc->pc_corepmcs[ri].phw_pmc;
2349
2350 KASSERT(pm,
2351 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2352 cpu, ri));
2353
2354 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
2355
2356 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2357 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */
2358
2359 if (core_cputype == PMC_CPU_INTEL_CORE)
2360 return (0);
2361
2362 msr = 0;
2363 do {
2364 cc->pc_resync = 0;
2365 cc->pc_globalctrl &= ~(1ULL << ri);
2366 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2367 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2368 } while (cc->pc_resync != 0);
2369
2370 return (0);
2371}
2372
2373static int
2374iap_write_pmc(int cpu, int ri, pmc_value_t v)
2375{
2376 struct pmc *pm;
2377 struct core_cpu *cc;
2378
2379 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2380 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2381 KASSERT(ri >= 0 && ri < core_iap_npmc,
2382 ("[core,%d] illegal row index %d", __LINE__, ri));
2383
2384 cc = core_pcpu[cpu];
2385 pm = cc->pc_corepmcs[ri].phw_pmc;
2386
2387 KASSERT(pm,
2388 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2389 cpu, ri));
2390
2391 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
2392 IAP_PMC0 + ri, v);
2393
2394 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2395 v = iap_reload_count_to_perfctr_value(v);
2396
2397 /*
2398 * Write the new value to the counter. The counter will be in
2399 * a stopped state when the pcd_write() entry point is called.
2400 */
2401
2402 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1));
2403
2404 return (0);
2405}
2406
2407
2408static void
2409iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
2410 int flags)
2411{
2412 struct pmc_classdep *pcd;
2413
2414 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
2415
2416 PMCDBG(MDP,INI,1, "%s", "iap-initialize");
2417
2418 /* Remember the set of architectural events supported. */
2419 core_architectural_events = ~flags;
2420
2421 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
2422
2423 pcd->pcd_caps = IAP_PMC_CAPS;
2424 pcd->pcd_class = PMC_CLASS_IAP;
2425 pcd->pcd_num = npmc;
2426 pcd->pcd_ri = md->pmd_npmc;
2427 pcd->pcd_width = pmcwidth;
2428
2429 pcd->pcd_allocate_pmc = iap_allocate_pmc;
2430 pcd->pcd_config_pmc = iap_config_pmc;
2431 pcd->pcd_describe = iap_describe;
2432 pcd->pcd_get_config = iap_get_config;
2433 pcd->pcd_get_msr = iap_get_msr;
2434 pcd->pcd_pcpu_fini = core_pcpu_fini;
2435 pcd->pcd_pcpu_init = core_pcpu_init;
2436 pcd->pcd_read_pmc = iap_read_pmc;
2437 pcd->pcd_release_pmc = iap_release_pmc;
2438 pcd->pcd_start_pmc = iap_start_pmc;
2439 pcd->pcd_stop_pmc = iap_stop_pmc;
2440 pcd->pcd_write_pmc = iap_write_pmc;
2441
2442 md->pmd_npmc += npmc;
2443}
2444
2445static int
2446core_intr(int cpu, struct trapframe *tf)
2447{
2448 pmc_value_t v;
2449 struct pmc *pm;
2450 struct core_cpu *cc;
2451 int error, found_interrupt, ri;
2452 uint64_t msr;
2453
2454 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2455 TRAPF_USERMODE(tf));
2456
2457 found_interrupt = 0;
2458 cc = core_pcpu[cpu];
2459
2460 for (ri = 0; ri < core_iap_npmc; ri++) {
2461
2462 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
2463 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2464 continue;
2465
2466 if (!iap_pmc_has_overflowed(ri))
2467 continue;
2468
2469 found_interrupt = 1;
2470
2471 if (pm->pm_state != PMC_STATE_RUNNING)
2472 continue;
2473
2474 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2475 TRAPF_USERMODE(tf));
2476
2477 v = pm->pm_sc.pm_reloadcount;
2478 v = iaf_reload_count_to_perfctr_value(v);
2479
2480 /*
2481 * Stop the counter, reload it but only restart it if
2482 * the PMC is not stalled.
2483 */
2484 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2485 wrmsr(IAP_EVSEL0 + ri, msr);
2486 wrmsr(IAP_PMC0 + ri, v);
2487
2488 if (error)
2489 continue;
2490
2491 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
2492 IAP_EN));
2493 }
2494
2495 if (found_interrupt)
2496 lapic_reenable_pmc();
2497
2498 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2499 &pmc_stats.pm_intr_ignored, 1);
2500
2501 return (found_interrupt);
2502}
2503
2504static int
2505core2_intr(int cpu, struct trapframe *tf)
2506{
2507 int error, found_interrupt, n;
2508 uint64_t flag, intrstatus, intrenable, msr;
2509 struct pmc *pm;
2510 struct core_cpu *cc;
2511 pmc_value_t v;
2512
2513 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2514 TRAPF_USERMODE(tf));
2515
2516 /*
2517 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
2518 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
2519 * the current set of interrupting PMCs and process these
2520 * after stopping them.
2521 */
2522 intrstatus = rdmsr(IA_GLOBAL_STATUS);
2523 intrenable = intrstatus & core_pmcmask;
2524
2525 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
2526 (uintmax_t) intrstatus);
2527
2528 found_interrupt = 0;
2529 cc = core_pcpu[cpu];
2530
2531 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
2532
2533 cc->pc_globalctrl &= ~intrenable;
2534 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
2535
2536 /*
2537 * Stop PMCs and clear overflow status bits.
2538 */
2539 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2540 wrmsr(IA_GLOBAL_CTRL, msr);
2541 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
2542 IA_GLOBAL_STATUS_FLAG_OVFBUF |
2543 IA_GLOBAL_STATUS_FLAG_CONDCHG);
2544
2545 /*
2546 * Look for interrupts from fixed function PMCs.
2547 */
2548 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
2549 n++, flag <<= 1) {
2550
2551 if ((intrstatus & flag) == 0)
2552 continue;
2553
2554 found_interrupt = 1;
2555
2556 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
2557 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2558 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2559 continue;
2560
2561 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2562 TRAPF_USERMODE(tf));
2563 if (error)
2564 intrenable &= ~flag;
2565
2566 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2567
2568 /* Reload sampling count. */
2569 wrmsr(IAF_CTR0 + n, v);
2570
2571 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu,
2572 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
2573 }
2574
2575 /*
2576 * Process interrupts from the programmable counters.
2577 */
2578 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
2579 if ((intrstatus & flag) == 0)
2580 continue;
2581
2582 found_interrupt = 1;
2583
2584 pm = cc->pc_corepmcs[n].phw_pmc;
2585 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2586 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2587 continue;
2588
2589 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2590 TRAPF_USERMODE(tf));
2591 if (error)
2592 intrenable &= ~flag;
2593
2594 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2595
2596 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
2597 (uintmax_t) v);
2598
2599 /* Reload sampling count. */
2600 wrmsr(IAP_PMC0 + n, v);
2601 }
2602
2603 /*
2604 * Reenable all non-stalled PMCs.
2605 */
2606 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
2607 (uintmax_t) intrenable);
2608
2609 cc->pc_globalctrl |= intrenable;
2610
2611 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
2612
2613 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
2614 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
2615 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
2616 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
2617 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
2618
2619 if (found_interrupt)
2620 lapic_reenable_pmc();
2621
2622 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2623 &pmc_stats.pm_intr_ignored, 1);
2624
2625 return (found_interrupt);
2626}
2627
2628int
2629pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
2630{
2631 int cpuid[CORE_CPUID_REQUEST_SIZE];
2632 int ipa_version, flags, nflags;
2633
2634 do_cpuid(CORE_CPUID_REQUEST, cpuid);
2635
2636 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
2637
2638 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
2639 md->pmd_cputype, maxcpu, ipa_version);
2640
2641 if (ipa_version < 1 || ipa_version > 3) {
2642 /* Unknown PMC architecture. */
2643 printf("hwpc_core: unknown PMC architecture: %d\n",
2644 ipa_version);
2645 return (EPROGMISMATCH);
2646 }
2647
2648 core_cputype = md->pmd_cputype;
2649
2650 core_pmcmask = 0;
2651
2652 /*
2653 * Initialize programmable counters.
2654 */
2655 KASSERT(ipa_version >= 1,
2656 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
2657
2658 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
2659 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
2660
2661 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
2662
2663 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
2664 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
2665
2666 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
2667
2668 /*
2669 * Initialize fixed function counters, if present.
2670 */
2671 if (core_cputype != PMC_CPU_INTEL_CORE) {
2672 KASSERT(ipa_version >= 2,
2673 ("[core,%d] ipa_version %d too small", __LINE__,
2674 ipa_version));
2675
2676 core_iaf_ri = core_iap_npmc;
2677 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
2678 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
2679
2680 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
2681 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
2682 }
2683
2684 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
2685 core_iaf_ri);
2686
2687 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC,
2688 M_ZERO | M_WAITOK);
2689
2690 /*
2691 * Choose the appropriate interrupt handler.
2692 */
2693 if (ipa_version == 1)
2694 md->pmd_intr = core_intr;
2695 else
2696 md->pmd_intr = core2_intr;
2697
2698 md->pmd_pcpu_fini = NULL;
2699 md->pmd_pcpu_init = NULL;
2700
2701 return (0);
2702}
2703
2704void
2705pmc_core_finalize(struct pmc_mdep *md)
2706{
2707 PMCDBG(MDP,INI,1, "%s", "core-finalize");
2708
2709 free(core_pcpu, M_PMC);
2710 core_pcpu = NULL;
2711}