1/*-
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
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19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 150610 2005-09-27 09:01:11Z mux $
28 */
29
30/*
31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
32 * Ethernet driver
33 */
34
35/*
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137};
138
139/*
140 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
141 * for functional grouping.
142 */
143struct fxp_softc {
144 struct ifnet *ifp; /* per-interface network data */
145 struct resource *fxp_res[2]; /* I/O and IRQ resources */
146 struct resource_spec *fxp_spec; /* the resource spec we used */
147 void *ih; /* interrupt handler cookie */
148 struct mtx sc_mtx;
149 bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */
150 bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */
151 bus_dmamap_t fxp_smap; /* bus DMA map for stats */
152 bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */
153 bus_dmamap_t cbl_map; /* DMA map for the TxCB list */
154 bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */
155 bus_dmamap_t mcs_map; /* DMA map for the multicast setup */
156 bus_dmamap_t spare_map; /* spare DMA map */
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189#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */
190#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */
191#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */
192#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */
193#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */
194#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */
195
196/* Macros to ease CSR access. */
197#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg)
198#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)
199#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)
200#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)
201#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val)
202#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val)
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 10 unchanged lines hidden (view full) ---
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 150610 2005-09-27 09:01:11Z mux $
28 */
29
30/*
31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
32 * Ethernet driver
33 */
34
35/*
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137};
138
139/*
140 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
141 * for functional grouping.
142 */
143struct fxp_softc {
144 struct ifnet *ifp; /* per-interface network data */
145 struct resource *fxp_res[2]; /* I/O and IRQ resources */
146 struct resource_spec *fxp_spec; /* the resource spec we used */
147 void *ih; /* interrupt handler cookie */
148 struct mtx sc_mtx;
149 bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */
150 bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */
151 bus_dmamap_t fxp_smap; /* bus DMA map for stats */
152 bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */
153 bus_dmamap_t cbl_map; /* DMA map for the TxCB list */
154 bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */
155 bus_dmamap_t mcs_map; /* DMA map for the multicast setup */
156 bus_dmamap_t spare_map; /* spare DMA map */
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189#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */
190#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */
191#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */
192#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */
193#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */
194#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */
195
196/* Macros to ease CSR access. */
197#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg)
198#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)
199#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)
200#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)
201#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val)
202#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val)