1/*-
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/ed/if_edvar.h 154895 2006-01-27 08:25:47Z imp $
28 */
29
30#ifndef SYS_DEV_ED_IF_EDVAR_H
31#define SYS_DEV_ED_IF_EDVAR_H
32/*
33 * ed_softc: per line info and status
34 */
35struct ed_softc {
36 struct ifnet *ifp;
37 struct ifmedia ifmedia; /* Media info */
38 device_t dev;
39 struct mtx sc_mtx;
40
41 char *type_str; /* pointer to type string */
42 u_char vendor; /* interface vendor */
43 u_char type; /* interface type code */
44 u_char chip_type; /* the type of chip (one of ED_CHIP_TYPE_*) */
45 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
46 u_char mem_shared; /* NIC memory is shared with host */
47 u_char xmit_busy; /* transmitter is busy */
48 u_char enaddr[6];
49
50 int port_rid; /* resource id for port range */
51 int port_used; /* nonzero if ports used */
52 struct resource* port_res; /* resource for port range */
53 bus_space_tag_t port_bst;
54 bus_space_handle_t port_bsh;
55 int mem_rid; /* resource id for memory range */
56 int mem_used; /* nonzero if memory used */
57 struct resource* mem_res; /* resource for memory range */
58 bus_space_tag_t mem_bst;
59 bus_space_handle_t mem_bsh;
60 int irq_rid; /* resource id for irq */
61 struct resource* irq_res; /* resource for irq */
62 void* irq_handle; /* handle for irq handler */
63 int modem_rid; /* resource ID for modem part of device */
64 int (*sc_media_ioctl)(struct ed_softc *sc, struct ifreq *ifr,
65 u_long command);
66 void (*sc_mediachg)(struct ed_softc *);
67 device_t miibus; /* MII bus for cards with MII. */
68 void (*mii_writebits)(struct ed_softc *, u_int, int);
69 u_int (*mii_readbits)(struct ed_softc *, int);
70 struct callout tick_ch;
71 void (*sc_tick)(void *);
72 void (*readmem)(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
73 uint16_t amount);
74
75 int nic_offset; /* NIC (DS8390) I/O bus address offset */
76 int asic_offset; /* ASIC I/O bus address offset */
77
78/*
79 * The following 'proto' variable is part of a work-around for 8013EBT asics
80 * being write-only. It's sort of a prototype/shadow of the real thing.
81 */
82 u_char wd_laar_proto;
83 u_char cr_proto;
84
85/*
86 * HP PC LAN PLUS card support.
87 */
88
89 u_short hpp_options; /* flags controlling behaviour of the HP card */
90 u_short hpp_id; /* software revision and other fields */
91 caddr_t hpp_mem_start; /* Memory-mapped IO register address */
92
93 bus_size_t mem_start; /* NIC memory start address */
94 bus_size_t mem_end; /* NIC memory end address */
95 uint32_t mem_size; /* total NIC memory size */
96 bus_size_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
97
98 u_char txb_cnt; /* number of transmit buffers */
99 u_char txb_inuse; /* number of TX buffers currently in-use */
100
101 u_char txb_new; /* pointer to where new buffer will be added */
102 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
103 u_short txb_len[8]; /* buffered xmit buffer lengths */
104 u_char tx_page_start; /* first page of TX buffer area */
105 u_char rec_page_start; /* first page of RX ring-buffer */
106 u_char rec_page_stop; /* last page of RX ring-buffer */
107 u_char next_packet; /* pointer to next unread RX packet */
108 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
109};
110
111#define ed_nic_inb(sc, port) \
112 bus_space_read_1(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
113
114#define ed_nic_outb(sc, port, value) \
115 bus_space_write_1(sc->port_bst, sc->port_bsh, \
116 (sc)->nic_offset + (port), (value))
117
118#define ed_nic_inw(sc, port) \
119 bus_space_read_2(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
120
121#define ed_nic_outw(sc, port, value) \
122 bus_space_write_2(sc->port_bst, sc->port_bsh, \
123 (sc)->nic_offset + (port), (value))
124
125#define ed_nic_insb(sc, port, addr, count) \
126 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \
127 (sc)->nic_offset + (port), (addr), (count))
128
129#define ed_nic_outsb(sc, port, addr, count) \
130 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
131 (sc)->nic_offset + (port), (addr), (count))
132
133#define ed_nic_insw(sc, port, addr, count) \
134 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
135 (sc)->nic_offset + (port), (uint16_t *)(addr), (count))
136
137#define ed_nic_outsw(sc, port, addr, count) \
138 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
139 (sc)->nic_offset + (port), (uint16_t *)(addr), (count))
140
141#define ed_nic_insl(sc, port, addr, count) \
142 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
143 (sc)->nic_offset + (port), (uint32_t *)(addr), (count))
144
145#define ed_nic_outsl(sc, port, addr, count) \
146 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
147 (sc)->nic_offset + (port), (uint32_t *)(addr), (count))
148
149#define ed_asic_inb(sc, port) \
150 bus_space_read_1(sc->port_bst, sc->port_bsh, \
151 (sc)->asic_offset + (port))
152
153#define ed_asic_outb(sc, port, value) \
154 bus_space_write_1(sc->port_bst, sc->port_bsh, \
155 (sc)->asic_offset + (port), (value))
156
157#define ed_asic_inw(sc, port) \
158 bus_space_read_2(sc->port_bst, sc->port_bsh, \
159 (sc)->asic_offset + (port))
160
161#define ed_asic_outw(sc, port, value) \
162 bus_space_write_2(sc->port_bst, sc->port_bsh, \
163 (sc)->asic_offset + (port), (value))
164
165#define ed_asic_insb(sc, port, addr, count) \
166 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \
167 (sc)->asic_offset + (port), (addr), (count))
168
169#define ed_asic_outsb(sc, port, addr, count) \
170 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
171 (sc)->asic_offset + (port), (addr), (count))
172
173#define ed_asic_insw(sc, port, addr, count) \
174 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
175 (sc)->asic_offset + (port), (uint16_t *)(addr), (count))
176
177#define ed_asic_outsw(sc, port, addr, count) \
178 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
179 (sc)->asic_offset + (port), (uint16_t *)(addr), (count))
180
181#define ed_asic_insl(sc, port, addr, count) \
182 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
183 (sc)->asic_offset + (port), (uint32_t *)(addr), (count))
184
185#define ed_asic_outsl(sc, port, addr, count) \
186 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
187 (sc)->asic_offset + (port), (uint32_t *)(addr), (count))
188
189void ed_release_resources(device_t);
190int ed_alloc_port(device_t, int, int);
191int ed_alloc_memory(device_t, int, int);
192int ed_alloc_irq(device_t, int, int);
193
194int ed_probe_generic8390(struct ed_softc *);
195int ed_probe_WD80x3(device_t, int, int);
196int ed_probe_WD80x3_generic(device_t, int, uint16_t *[]);
197int ed_probe_RTL80x9(device_t, int, int);
198#ifdef ED_3C503
199int ed_probe_3Com(device_t, int, int);
200#endif
201#ifdef ED_SIC
202int ed_probe_SIC(device_t, int, int);
203#endif
204int ed_probe_Novell_generic(device_t, int);
205int ed_probe_Novell(device_t, int, int);
206void ed_Novell_read_mac(struct ed_softc *);
207#ifdef ED_HPP
208int ed_probe_HP_pclanp(device_t, int, int);
209#endif
210
211int ed_attach(device_t);
212int ed_detach(device_t);
213int ed_clear_memory(device_t);
214int ed_isa_mem_ok(device_t, u_long, u_int); /* XXX isa specific */
215void ed_stop(struct ed_softc *);
216void ed_shmem_readmem16(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
217void ed_shmem_readmem8(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
218void ed_pio_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
219void ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t);
220
221/* The following is unsatisfying XXX */
222#ifdef ED_HPP
223void ed_hpp_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
224u_short ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int);
225#endif
226
227void ed_disable_16bit_access(struct ed_softc *);
228void ed_enable_16bit_access(struct ed_softc *);
229
230driver_intr_t edintr;
231
232extern devclass_t ed_devclass;
233
234
235/*
236 * Vendor types
237 */
238#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
239#define ED_VENDOR_3COM 0x01 /* 3Com */
240#define ED_VENDOR_NOVELL 0x02 /* Novell */
241#define ED_VENDOR_HP 0x03 /* Hewlett Packard */
242#define ED_VENDOR_SIC 0x04 /* Allied-Telesis SIC */
243
244/*
245 * Configure time flags
246 */
247/*
248 * this sets the default for enabling/disabling the transceiver
249 */
250#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
251
252/*
253 * This forces the board to be used in 8/16bit mode even if it
254 * autoconfigs differently
255 */
256#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
257#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
258
259/*
260 * This disables the use of double transmit buffers.
261 */
262#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
263
264/*
265 * This forces all operations with the NIC memory to use Programmed
266 * I/O (i.e. not via shared memory)
267 */
268#define ED_FLAGS_FORCE_PIO 0x0010
269
270/*
271 * These are flags describing the chip type.
272 */
273#define ED_FLAGS_TOSH_ETHER 0x10000
274#define ED_FLAGS_GWETHER 0x20000
275#define ED_FLAGS_AX88190 0x30000
276#define ED_FLAGS_LINKSYS 0x80000
277
278#define ED_FLAGS_GETTYPE(flg) ((flg) & 0xff0000)
279
280#define ED_MUTEX(_sc) (&(_sc)->sc_mtx)
281#define ED_LOCK(_sc) mtx_lock(ED_MUTEX(_sc))
282#define ED_UNLOCK(_sc) mtx_unlock(ED_MUTEX(_sc))
283#define ED_LOCK_INIT(_sc) \
284 mtx_init(ED_MUTEX(_sc), device_get_nameunit(_sc->dev), \
285 MTX_NETWORK_LOCK, MTX_DEF)
286#define ED_LOCK_DESTROY(_sc) mtx_destroy(ED_MUTEX(_sc));
287#define ED_ASSERT_LOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_OWNED);
288#define ED_ASSERT_UNLOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_NOTOWNED);
289
290#endif /* SYS_DEV_ED_IF_EDVAR_H */
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/ed/if_edvar.h 154895 2006-01-27 08:25:47Z imp $
28 */
29
30#ifndef SYS_DEV_ED_IF_EDVAR_H
31#define SYS_DEV_ED_IF_EDVAR_H
32/*
33 * ed_softc: per line info and status
34 */
35struct ed_softc {
36 struct ifnet *ifp;
37 struct ifmedia ifmedia; /* Media info */
38 device_t dev;
39 struct mtx sc_mtx;
40
41 char *type_str; /* pointer to type string */
42 u_char vendor; /* interface vendor */
43 u_char type; /* interface type code */
44 u_char chip_type; /* the type of chip (one of ED_CHIP_TYPE_*) */
45 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
46 u_char mem_shared; /* NIC memory is shared with host */
47 u_char xmit_busy; /* transmitter is busy */
48 u_char enaddr[6];
49
50 int port_rid; /* resource id for port range */
51 int port_used; /* nonzero if ports used */
52 struct resource* port_res; /* resource for port range */
53 bus_space_tag_t port_bst;
54 bus_space_handle_t port_bsh;
55 int mem_rid; /* resource id for memory range */
56 int mem_used; /* nonzero if memory used */
57 struct resource* mem_res; /* resource for memory range */
58 bus_space_tag_t mem_bst;
59 bus_space_handle_t mem_bsh;
60 int irq_rid; /* resource id for irq */
61 struct resource* irq_res; /* resource for irq */
62 void* irq_handle; /* handle for irq handler */
63 int modem_rid; /* resource ID for modem part of device */
64 int (*sc_media_ioctl)(struct ed_softc *sc, struct ifreq *ifr,
65 u_long command);
66 void (*sc_mediachg)(struct ed_softc *);
67 device_t miibus; /* MII bus for cards with MII. */
68 void (*mii_writebits)(struct ed_softc *, u_int, int);
69 u_int (*mii_readbits)(struct ed_softc *, int);
70 struct callout tick_ch;
71 void (*sc_tick)(void *);
72 void (*readmem)(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
73 uint16_t amount);
74
75 int nic_offset; /* NIC (DS8390) I/O bus address offset */
76 int asic_offset; /* ASIC I/O bus address offset */
77
78/*
79 * The following 'proto' variable is part of a work-around for 8013EBT asics
80 * being write-only. It's sort of a prototype/shadow of the real thing.
81 */
82 u_char wd_laar_proto;
83 u_char cr_proto;
84
85/*
86 * HP PC LAN PLUS card support.
87 */
88
89 u_short hpp_options; /* flags controlling behaviour of the HP card */
90 u_short hpp_id; /* software revision and other fields */
91 caddr_t hpp_mem_start; /* Memory-mapped IO register address */
92
93 bus_size_t mem_start; /* NIC memory start address */
94 bus_size_t mem_end; /* NIC memory end address */
95 uint32_t mem_size; /* total NIC memory size */
96 bus_size_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
97
98 u_char txb_cnt; /* number of transmit buffers */
99 u_char txb_inuse; /* number of TX buffers currently in-use */
100
101 u_char txb_new; /* pointer to where new buffer will be added */
102 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
103 u_short txb_len[8]; /* buffered xmit buffer lengths */
104 u_char tx_page_start; /* first page of TX buffer area */
105 u_char rec_page_start; /* first page of RX ring-buffer */
106 u_char rec_page_stop; /* last page of RX ring-buffer */
107 u_char next_packet; /* pointer to next unread RX packet */
108 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
109};
110
111#define ed_nic_inb(sc, port) \
112 bus_space_read_1(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
113
114#define ed_nic_outb(sc, port, value) \
115 bus_space_write_1(sc->port_bst, sc->port_bsh, \
116 (sc)->nic_offset + (port), (value))
117
118#define ed_nic_inw(sc, port) \
119 bus_space_read_2(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
120
121#define ed_nic_outw(sc, port, value) \
122 bus_space_write_2(sc->port_bst, sc->port_bsh, \
123 (sc)->nic_offset + (port), (value))
124
125#define ed_nic_insb(sc, port, addr, count) \
126 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \
127 (sc)->nic_offset + (port), (addr), (count))
128
129#define ed_nic_outsb(sc, port, addr, count) \
130 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
131 (sc)->nic_offset + (port), (addr), (count))
132
133#define ed_nic_insw(sc, port, addr, count) \
134 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
135 (sc)->nic_offset + (port), (uint16_t *)(addr), (count))
136
137#define ed_nic_outsw(sc, port, addr, count) \
138 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
139 (sc)->nic_offset + (port), (uint16_t *)(addr), (count))
140
141#define ed_nic_insl(sc, port, addr, count) \
142 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
143 (sc)->nic_offset + (port), (uint32_t *)(addr), (count))
144
145#define ed_nic_outsl(sc, port, addr, count) \
146 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
147 (sc)->nic_offset + (port), (uint32_t *)(addr), (count))
148
149#define ed_asic_inb(sc, port) \
150 bus_space_read_1(sc->port_bst, sc->port_bsh, \
151 (sc)->asic_offset + (port))
152
153#define ed_asic_outb(sc, port, value) \
154 bus_space_write_1(sc->port_bst, sc->port_bsh, \
155 (sc)->asic_offset + (port), (value))
156
157#define ed_asic_inw(sc, port) \
158 bus_space_read_2(sc->port_bst, sc->port_bsh, \
159 (sc)->asic_offset + (port))
160
161#define ed_asic_outw(sc, port, value) \
162 bus_space_write_2(sc->port_bst, sc->port_bsh, \
163 (sc)->asic_offset + (port), (value))
164
165#define ed_asic_insb(sc, port, addr, count) \
166 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \
167 (sc)->asic_offset + (port), (addr), (count))
168
169#define ed_asic_outsb(sc, port, addr, count) \
170 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
171 (sc)->asic_offset + (port), (addr), (count))
172
173#define ed_asic_insw(sc, port, addr, count) \
174 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
175 (sc)->asic_offset + (port), (uint16_t *)(addr), (count))
176
177#define ed_asic_outsw(sc, port, addr, count) \
178 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
179 (sc)->asic_offset + (port), (uint16_t *)(addr), (count))
180
181#define ed_asic_insl(sc, port, addr, count) \
182 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
183 (sc)->asic_offset + (port), (uint32_t *)(addr), (count))
184
185#define ed_asic_outsl(sc, port, addr, count) \
186 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
187 (sc)->asic_offset + (port), (uint32_t *)(addr), (count))
188
189void ed_release_resources(device_t);
190int ed_alloc_port(device_t, int, int);
191int ed_alloc_memory(device_t, int, int);
192int ed_alloc_irq(device_t, int, int);
193
194int ed_probe_generic8390(struct ed_softc *);
195int ed_probe_WD80x3(device_t, int, int);
196int ed_probe_WD80x3_generic(device_t, int, uint16_t *[]);
197int ed_probe_RTL80x9(device_t, int, int);
198#ifdef ED_3C503
199int ed_probe_3Com(device_t, int, int);
200#endif
201#ifdef ED_SIC
202int ed_probe_SIC(device_t, int, int);
203#endif
204int ed_probe_Novell_generic(device_t, int);
205int ed_probe_Novell(device_t, int, int);
206void ed_Novell_read_mac(struct ed_softc *);
207#ifdef ED_HPP
208int ed_probe_HP_pclanp(device_t, int, int);
209#endif
210
211int ed_attach(device_t);
212int ed_detach(device_t);
213int ed_clear_memory(device_t);
214int ed_isa_mem_ok(device_t, u_long, u_int); /* XXX isa specific */
215void ed_stop(struct ed_softc *);
216void ed_shmem_readmem16(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
217void ed_shmem_readmem8(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
218void ed_pio_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
219void ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t);
220
221/* The following is unsatisfying XXX */
222#ifdef ED_HPP
223void ed_hpp_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
224u_short ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int);
225#endif
226
227void ed_disable_16bit_access(struct ed_softc *);
228void ed_enable_16bit_access(struct ed_softc *);
229
230driver_intr_t edintr;
231
232extern devclass_t ed_devclass;
233
234
235/*
236 * Vendor types
237 */
238#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
239#define ED_VENDOR_3COM 0x01 /* 3Com */
240#define ED_VENDOR_NOVELL 0x02 /* Novell */
241#define ED_VENDOR_HP 0x03 /* Hewlett Packard */
242#define ED_VENDOR_SIC 0x04 /* Allied-Telesis SIC */
243
244/*
245 * Configure time flags
246 */
247/*
248 * this sets the default for enabling/disabling the transceiver
249 */
250#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
251
252/*
253 * This forces the board to be used in 8/16bit mode even if it
254 * autoconfigs differently
255 */
256#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
257#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
258
259/*
260 * This disables the use of double transmit buffers.
261 */
262#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
263
264/*
265 * This forces all operations with the NIC memory to use Programmed
266 * I/O (i.e. not via shared memory)
267 */
268#define ED_FLAGS_FORCE_PIO 0x0010
269
270/*
271 * These are flags describing the chip type.
272 */
273#define ED_FLAGS_TOSH_ETHER 0x10000
274#define ED_FLAGS_GWETHER 0x20000
275#define ED_FLAGS_AX88190 0x30000
276#define ED_FLAGS_LINKSYS 0x80000
277
278#define ED_FLAGS_GETTYPE(flg) ((flg) & 0xff0000)
279
280#define ED_MUTEX(_sc) (&(_sc)->sc_mtx)
281#define ED_LOCK(_sc) mtx_lock(ED_MUTEX(_sc))
282#define ED_UNLOCK(_sc) mtx_unlock(ED_MUTEX(_sc))
283#define ED_LOCK_INIT(_sc) \
284 mtx_init(ED_MUTEX(_sc), device_get_nameunit(_sc->dev), \
285 MTX_NETWORK_LOCK, MTX_DEF)
286#define ED_LOCK_DESTROY(_sc) mtx_destroy(ED_MUTEX(_sc));
287#define ED_ASSERT_LOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_OWNED);
288#define ED_ASSERT_UNLOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_NOTOWNED);
289
290#endif /* SYS_DEV_ED_IF_EDVAR_H */