31 * Revision 1.1 93/06/23 03:01:07 davidg
32 * Initial revision
33 *
34 */
35
36/*
37 * Page 0 register offsets
38 */
39#define ED_P0_CR 0x00 /* Command Register */
40
41#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
42#define ED_P0_PSTART 0x01 /* Page Start register (write) */
43
44#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
45#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
46
47#define ED_P0_BNRY 0x03 /* Boundary Pointer */
48
49#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
50#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
51
52#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
53#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
54
55#define ED_P0_FIFO 0x06 /* FIFO register (read) */
56#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
57
58#define ED_P0_ISR 0x07 /* Interrupt Status Register */
59
60#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
61#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
62
63#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
64#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
65
66#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
67
68#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
69
70#define ED_P0_RSR 0x0c /* Receive Status (read) */
71#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
72
73#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
74#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
75
76#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
77#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
78
79#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
80#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
81
82/*
83 * Page 1 register offsets
84 */
85#define ED_P1_CR 0x00 /* Command Register */
86#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
87#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
88#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
89#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
90#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
91#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
92#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
93#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
94#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
95#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
96#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
97#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
98#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
99#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
100#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
101
102/*
103 * Page 2 register offsets
104 */
105#define ED_P2_CR 0x00 /* Command Register */
106#define ED_P2_PSTART 0x01 /* Page Start (read) */
107#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
108#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
109#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
110#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
111#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
112#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
113#define ED_P2_ACU 0x06 /* Address Counter Upper */
114#define ED_P2_ACL 0x07 /* Address Counter Lower */
115#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
116#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
117#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
118#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
119
120/*
121 * Command Register (CR) definitions
122 */
123
124/*
125 * STP: SToP. Software reset command. Takes the controller offline. No
126 * packets will be received or transmitted. Any reception or
127 * transmission in progress will continue to completion before
128 * entering reset state. To exit this state, the STP bit must
129 * reset and the STA bit must be set. The software reset has
130 * executed only when indicated by the RST bit in the ISR being
131 * set.
132 */
133#define ED_CR_STP 0x01
134
135/*
136 * STA: STArt. This bit is used to activate the NIC after either power-up,
137 * or when the NIC has been put in reset mode by software command
138 * or error.
139 */
140#define ED_CR_STA 0x02
141
142/*
143 * TXP: Transmit Packet. This bit must be set to indicate transmission of
144 * a packet. TXP is internally reset either after the transmission is
145 * completed or aborted. This bit should be set only after the Transmit
146 * Byte Count and Transmit Page Start register have been programmed.
147 */
148#define ED_CR_TXP 0x04
149
150/*
151 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
152 * of the remote DMA channel. RD2 can be set to abort any remote DMA
153 * command in progress. The Remote Byte Count registers should be cleared
154 * when a remote DMA has been aborted. The Remote Start Addresses are not
155 * restored to the starting address if the remote DMA is aborted.
156 *
157 * RD2 RD1 RD0 function
158 * 0 0 0 not allowed
159 * 0 0 1 remote read
160 * 0 1 0 remote write
161 * 0 1 1 send packet
162 * 1 X X abort
163 */
164#define ED_CR_RD0 0x08
165#define ED_CR_RD1 0x10
166#define ED_CR_RD2 0x20
167
168/*
169 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
170 * access.
171 *
172 * PS1 PS0 page
173 * 0 0 0
174 * 0 1 1
175 * 1 0 2
176 * 1 1 reserved
177 */
178#define ED_CR_PS0 0x40
179#define ED_CR_PS1 0x80
180/* bit encoded aliases */
181#define ED_CR_PAGE_0 0x00 /* (for consistency) */
182#define ED_CR_PAGE_1 0x40
183#define ED_CR_PAGE_2 0x80
184
185/*
186 * Interrupt Status Register (ISR) definitions
187 */
188
189/*
190 * PRX: Packet Received. Indicates packet received with no errors.
191 */
192#define ED_ISR_PRX 0x01
193
194/*
195 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
196 */
197#define ED_ISR_PTX 0x02
198
199/*
200 * RXE: Receive Error. Indicates that a packet was received with one or more
201 * the following errors: CRC error, frame alignment error, FIFO overrun,
202 * missed packet.
203 */
204#define ED_ISR_RXE 0x04
205
206/*
207 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
208 * resulted in one or more of the following errors: excessive
209 * collisions, FIFO underrun.
210 */
211#define ED_ISR_TXE 0x08
212
213/*
214 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
215 * would exceed (has exceeded?) the boundry pointer, resulting in data
216 * that was previously received and not yet read from the buffer to be
217 * overwritten.
218 */
219#define ED_ISR_OVW 0x10
220
221/*
222 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
223 * Counters has been set.
224 */
225#define ED_ISR_CNT 0x20
226
227/*
228 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
229 */
230#define ED_ISR_RDC 0x40
231
232/*
233 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
234 * Start Command is issued to the CR. This bit is also set when a receive
235 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
236 * packets have been removed from the ring. This is a read-only bit.
237 */
238#define ED_ISR_RST 0x80
239
240/*
241 * Interrupt Mask Register (IMR) definitions
242 */
243
244/*
245 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
246 * an interrupt.
247 */
248#define ED_IMR_PRXE 0x01
249
250/*
251 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
252 * a packet transmission completes.
253 */
254#define ED_IMR_PTXE 0x02
255
256/*
257 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
258 * packet is received with an error.
259 */
260#define ED_IMR_RXEE 0x04
261
262/*
263 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
264 * a transmission results in an error.
265 */
266#define ED_IMR_TXEE 0x08
267
268/*
269 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
270 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
271 */
272#define ED_IMR_OVWE 0x10
273
274/*
275 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
276 * the MSB of one or more of the Network Statistics counters has been set.
277 */
278#define ED_IMR_CNTE 0x20
279
280/*
281 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
282 * when a remote DMA transfer has completed.
283 */
284#define ED_IMR_RDCE 0x40
285
286/*
287 * bit 7 is unused/reserved
288 */
289
290/*
291 * Data Configuration Register (DCR) definitions
292 */
293
294/*
295 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
296 * both remote and local DMA transfers
297 */
298#define ED_DCR_WTS 0x01
299
300/*
301 * BOS: Byte Order Select. BOS sets the byte order for the host.
302 * Should be 0 for 80x86, and 1 for 68000 series processors
303 */
304#define ED_DCR_BOS 0x02
305
306/*
307 * LAS: Long Address Select. When LAS is 1, the contents of the remote
308 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
309 */
310#define ED_DCR_LAS 0x04
311
312/*
313 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
314 * of the TCR must also be programmed for loopback operation.
315 * When 1, normal operation is selected.
316 */
317#define ED_DCR_LS 0x08
318
319/*
320 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
321 * under program control. When 1, remote DMA is automatically initiated
322 * and the boundry pointer is automatically updated
323 */
324#define ED_DCR_AR 0x10
325
326/*
327 * FT0, FT1: Fifo Threshold select.
328 * FT1 FT0 Word-width Byte-width
329 * 0 0 1 word 2 bytes
330 * 0 1 2 words 4 bytes
331 * 1 0 4 words 8 bytes
332 * 1 1 8 words 12 bytes
333 *
334 * During transmission, the FIFO threshold indicates the number of bytes
335 * or words that the FIFO has filled from the local DMA before BREQ is
336 * asserted. The transmission threshold is 16 bytes minus the receiver
337 * threshold.
338 */
339#define ED_DCR_FT0 0x20
340#define ED_DCR_FT1 0x40
341
342/*
343 * bit 7 (0x80) is unused/reserved
344 */
345
346/*
347 * Transmit Configuration Register (TCR) definitions
348 */
349
350/*
351 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
352 * is not appended by the transmitter.
353 */
354#define ED_TCR_CRC 0x01
355
356/*
357 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
358 * to be performed.
359 *
360 * LB1 LB0 mode
361 * 0 0 0 - normal operation (DCR_LS = 0)
362 * 0 1 1 - internal loopback (DCR_LS = 0)
363 * 1 0 2 - external loopback (DCR_LS = 1)
364 * 1 1 3 - external loopback (DCR_LS = 0)
365 */
366#define ED_TCR_LB0 0x02
367#define ED_TCR_LB1 0x04
368
369/*
370 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
371 * another station to disable the NIC's transmitter by transmitting to
372 * a multicast address hashing to bit 62. Reception of a multicast address
373 * hashing to bit 63 enables the transmitter.
374 */
375#define ED_TCR_ATD 0x08
376
377/*
378 * OFST: Collision Offset enable. This bit when set modifies the backoff
379 * algorithm to allow prioritization of nodes.
380 */
381#define ED_TCR_OFST 0x10
382
383/*
384 * bits 5, 6, and 7 are unused/reserved
385 */
386
387/*
388 * Transmit Status Register (TSR) definitions
389 */
390
391/*
392 * PTX: Packet Transmitted. Indicates successful transmission of packet.
393 */
394#define ED_TSR_PTX 0x01
395
396/*
397 * bit 1 (0x02) is unused/reserved
398 */
399
400/*
401 * COL: Transmit Collided. Indicates that the transmission collided at least
402 * once with another station on the network.
403 */
404#define ED_TSR_COL 0x04
405
406/*
407 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
408 * excessive collisions.
409 */
410#define ED_TSR_ABT 0x08
411
412/*
413 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
414 * transmission of the packet. (Transmission is not aborted because
415 * of a loss of carrier)
416 */
417#define ED_TSR_CRS 0x10
418
419/*
420 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
421 * transmission memory before the FIFO emptied. Transmission of the
422 * packet was aborted.
423 */
424#define ED_TSR_FU 0x20
425
426/*
427 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
428 * isn't working correctly during a collision heartbeat test.
429 */
430#define ED_TSR_CDH 0x40
431
432/*
433 * OWC: Out of Window Collision: Indicates that a collision occurred after
434 * a slot time (51.2us). The transmission is rescheduled just as in
435 * normal collisions.
436 */
437#define ED_TSR_OWC 0x80
438
439/*
440 * Receiver Configuration Register (RCR) definitions
441 */
442
443/*
444 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
445 * packets with CRC and frame errors are not discarded.
446 */
447#define ED_RCR_SEP 0x01
448
449/*
450 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
451 * If set to 1, packets with less than 64 byte are not discarded.
452 */
453#define ED_RCR_AR 0x02
454
455/*
456 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
457 * accepted.
458 */
459#define ED_RCR_AB 0x04
460
461/*
462 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
463 * for a match in the hashing array. If clear, multicast packets are ignored.
464 */
465#define ED_RCR_AM 0x08
466
467/*
468 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
469 * accepted. If clear, a physical destination address must match this
470 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
471 * must also be set. In addition, the multicast hashing array must be set
472 * to all 1's so that all multicast addresses are accepted.
473 */
474#define ED_RCR_PRO 0x10
475
476/*
477 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
478 * but are not stored in the ring-buffer. If clear, packets are stored (normal
479 * operation).
480 */
481#define ED_RCR_MON 0x20
482
483/*
484 * bits 6 and 7 are unused/reserved.
485 */
486
487/*
488 * Receiver Status Register (RSR) definitions
489 */
490
491/*
492 * PRX: Packet Received without error.
493 */
494#define ED_RSR_PRX 0x01
495
496/*
497 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
498 * alignment errors.
499 */
500#define ED_RSR_CRC 0x02
501
502/*
503 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
504 * a byte boundry and the CRC did not match at the last byte boundry.
505 */
506#define ED_RSR_FAE 0x04
507
508/*
509 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
510 * causing it to overrun. Reception of the packet is aborted.
511 */
512#define ED_RSR_FO 0x08
513
514/*
515 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
516 * the ring-buffer because of insufficient buffer space (exceeding the
517 * boundry pointer), or because the transfer to the ring-buffer was inhibited
518 * by RCR_MON - monitor mode.
519 */
520#define ED_RSR_MPA 0x10
521
522/*
523 * PHY: Physical address. If 0, the packet received was sent to a physical address.
524 * If 1, the packet was accepted because of a multicast/broadcast address
525 * match.
526 */
527#define ED_RSR_PHY 0x20
528
529/*
530 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
531 * mode. Cleared when the receiver exits monitor mode.
532 */
533#define ED_RSR_DIS 0x40
534
535/*
536 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
537 * are active, and the transceiver has set the CD line as a result of the
538 * jabber.
539 */
540#define ED_RSR_DFR 0x80
541
542/*
543 * receive ring discriptor
544 *
545 * The National Semiconductor DS8390 Network interface controller uses
546 * the following receive ring headers. The way this works is that the
547 * memory on the interface card is chopped up into 256 bytes blocks.
548 * A contiguous portion of those blocks are marked for receive packets
549 * by setting start and end block #'s in the NIC. For each packet that
550 * is put into the receive ring, one of these headers (4 bytes each) is
551 * tacked onto the front.
552 */
553struct ed_ring {
554 struct edr_status { /* received packet status */
555 u_char rs_prx:1, /* packet received intack */
556 rs_crc:1, /* crc error */
557 rs_fae:1, /* frame alignment error */
558 rs_fo:1, /* fifo overrun */
559 rs_mpa:1, /* packet received intack */
560 rs_phy:1, /* packet received intack */
561 rs_dis:1, /* packet received intack */
562 rs_dfr:1; /* packet received intack */
563 } ed_rcv_status; /* received packet status */
564 u_char next_packet; /* pointer to next packet */
565 u_short count; /* bytes in packet (length + 4) */
566};
567
568/*
569 * Common constants
570 */
571#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
572#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
573
574/*
575 * Vendor types
576 */
577#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
578#define ED_VENDOR_3COM 0x01 /* 3Com */
579#define ED_VENDOR_NOVELL 0x02 /* Novell */
580
581/*
582 * Compile-time config flags
583 */
584/*
585 * this sets the default for enabling/disablng the tranceiver
586 */
587#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
588
589/*
590 * This forces the board to be used in 8/16bit mode even if it
591 * autoconfigs differently
592 */
593#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
594#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
595
596/*
597 * This disables the use of double transmit buffers.
598 */
599#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
600
601/*
602 * This forces all operations with the NIC memory to use Programmed
603 * I/O (i.e. not via shared memory)
604 */
605#define ED_FLAGS_FORCE_PIO 0x0010
606
607/*
608 * Definitions for Western digital/SMC WD80x3 series ASIC
609 */
610/*
611 * Memory Select Register (MSR)
612 */
613#define ED_WD_MSR 0
614
615#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
616#define ED_WD_MSR_MENB 0x40 /* Memory enable */
617#define ED_WD_MSR_RST 0x80 /* Reset board */
618
619/*
620 * Interface Configuration Register (ICR)
621 */
622#define ED_WD_ICR 1
623
624#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
625#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
626#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
627#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
628#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
629#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
630#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
631#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
632
633/*
634 * IO Address Register (IAR)
635 */
636#define ED_WD_IAR 2
637
638/*
639 * EEROM Address Register
640 */
641#define ED_WD_EAR 3
642
643/*
644 * Interrupt Request Register (IRR)
645 */
646#define ED_WD_IRR 4
647
648#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
649#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
650#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
651#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
652#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
653
654/*
655 * The three bit of the encoded IRQ are decoded as follows:
656 *
657 * IR2 IR1 IR0 IRQ
658 * 0 0 0 2/9
659 * 0 0 1 3
660 * 0 1 0 5
661 * 0 1 1 7
662 * 1 0 0 10
663 * 1 0 1 11
664 * 1 1 0 15
665 * 1 1 1 4
666 */
667#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
668#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
669#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
670
671/*
672 * LA Address Register (LAAR)
673 */
674#define ED_WD_LAAR 5
675
676#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
677#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
678#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
679#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
680
681/* i/o base offset to station address/card-ID PROM */
682#define ED_WD_PROM 8
683
684/* i/o base offset to CARD ID */
685#define ED_WD_CARD_ID ED_WD_PROM+6
686
687/* Board type codes in card ID */
688#define ED_TYPE_WD8003S 0x02
689#define ED_TYPE_WD8003E 0x03
690#define ED_TYPE_WD8013EBT 0x05
691#define ED_TYPE_WD8013EP 0x27
692#define ED_TYPE_WD8013WC 0x28
693#define ED_TYPE_WD8013EBP 0x2c
694#define ED_TYPE_WD8013EPC 0x29
| 17 * Revision 1.1 93/06/23 03:01:07 davidg
18 * Initial revision
19 *
20 */
21
22/*
23 * Page 0 register offsets
24 */
25#define ED_P0_CR 0x00 /* Command Register */
26
27#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
28#define ED_P0_PSTART 0x01 /* Page Start register (write) */
29
30#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
31#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
32
33#define ED_P0_BNRY 0x03 /* Boundary Pointer */
34
35#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
36#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
37
38#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
39#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
40
41#define ED_P0_FIFO 0x06 /* FIFO register (read) */
42#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
43
44#define ED_P0_ISR 0x07 /* Interrupt Status Register */
45
46#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
47#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
48
49#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
50#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
51
52#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
53
54#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
55
56#define ED_P0_RSR 0x0c /* Receive Status (read) */
57#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
58
59#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
60#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
61
62#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
63#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
64
65#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
66#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
67
68/*
69 * Page 1 register offsets
70 */
71#define ED_P1_CR 0x00 /* Command Register */
72#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
73#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
74#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
75#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
76#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
77#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
78#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
79#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
80#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
81#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
82#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
83#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
84#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
85#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
86#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
87
88/*
89 * Page 2 register offsets
90 */
91#define ED_P2_CR 0x00 /* Command Register */
92#define ED_P2_PSTART 0x01 /* Page Start (read) */
93#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
94#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
95#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
96#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
97#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
98#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
99#define ED_P2_ACU 0x06 /* Address Counter Upper */
100#define ED_P2_ACL 0x07 /* Address Counter Lower */
101#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
102#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
103#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
104#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
105
106/*
107 * Command Register (CR) definitions
108 */
109
110/*
111 * STP: SToP. Software reset command. Takes the controller offline. No
112 * packets will be received or transmitted. Any reception or
113 * transmission in progress will continue to completion before
114 * entering reset state. To exit this state, the STP bit must
115 * reset and the STA bit must be set. The software reset has
116 * executed only when indicated by the RST bit in the ISR being
117 * set.
118 */
119#define ED_CR_STP 0x01
120
121/*
122 * STA: STArt. This bit is used to activate the NIC after either power-up,
123 * or when the NIC has been put in reset mode by software command
124 * or error.
125 */
126#define ED_CR_STA 0x02
127
128/*
129 * TXP: Transmit Packet. This bit must be set to indicate transmission of
130 * a packet. TXP is internally reset either after the transmission is
131 * completed or aborted. This bit should be set only after the Transmit
132 * Byte Count and Transmit Page Start register have been programmed.
133 */
134#define ED_CR_TXP 0x04
135
136/*
137 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
138 * of the remote DMA channel. RD2 can be set to abort any remote DMA
139 * command in progress. The Remote Byte Count registers should be cleared
140 * when a remote DMA has been aborted. The Remote Start Addresses are not
141 * restored to the starting address if the remote DMA is aborted.
142 *
143 * RD2 RD1 RD0 function
144 * 0 0 0 not allowed
145 * 0 0 1 remote read
146 * 0 1 0 remote write
147 * 0 1 1 send packet
148 * 1 X X abort
149 */
150#define ED_CR_RD0 0x08
151#define ED_CR_RD1 0x10
152#define ED_CR_RD2 0x20
153
154/*
155 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
156 * access.
157 *
158 * PS1 PS0 page
159 * 0 0 0
160 * 0 1 1
161 * 1 0 2
162 * 1 1 reserved
163 */
164#define ED_CR_PS0 0x40
165#define ED_CR_PS1 0x80
166/* bit encoded aliases */
167#define ED_CR_PAGE_0 0x00 /* (for consistency) */
168#define ED_CR_PAGE_1 0x40
169#define ED_CR_PAGE_2 0x80
170
171/*
172 * Interrupt Status Register (ISR) definitions
173 */
174
175/*
176 * PRX: Packet Received. Indicates packet received with no errors.
177 */
178#define ED_ISR_PRX 0x01
179
180/*
181 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
182 */
183#define ED_ISR_PTX 0x02
184
185/*
186 * RXE: Receive Error. Indicates that a packet was received with one or more
187 * the following errors: CRC error, frame alignment error, FIFO overrun,
188 * missed packet.
189 */
190#define ED_ISR_RXE 0x04
191
192/*
193 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
194 * resulted in one or more of the following errors: excessive
195 * collisions, FIFO underrun.
196 */
197#define ED_ISR_TXE 0x08
198
199/*
200 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
201 * would exceed (has exceeded?) the boundry pointer, resulting in data
202 * that was previously received and not yet read from the buffer to be
203 * overwritten.
204 */
205#define ED_ISR_OVW 0x10
206
207/*
208 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
209 * Counters has been set.
210 */
211#define ED_ISR_CNT 0x20
212
213/*
214 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
215 */
216#define ED_ISR_RDC 0x40
217
218/*
219 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
220 * Start Command is issued to the CR. This bit is also set when a receive
221 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
222 * packets have been removed from the ring. This is a read-only bit.
223 */
224#define ED_ISR_RST 0x80
225
226/*
227 * Interrupt Mask Register (IMR) definitions
228 */
229
230/*
231 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
232 * an interrupt.
233 */
234#define ED_IMR_PRXE 0x01
235
236/*
237 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
238 * a packet transmission completes.
239 */
240#define ED_IMR_PTXE 0x02
241
242/*
243 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
244 * packet is received with an error.
245 */
246#define ED_IMR_RXEE 0x04
247
248/*
249 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
250 * a transmission results in an error.
251 */
252#define ED_IMR_TXEE 0x08
253
254/*
255 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
256 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
257 */
258#define ED_IMR_OVWE 0x10
259
260/*
261 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
262 * the MSB of one or more of the Network Statistics counters has been set.
263 */
264#define ED_IMR_CNTE 0x20
265
266/*
267 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
268 * when a remote DMA transfer has completed.
269 */
270#define ED_IMR_RDCE 0x40
271
272/*
273 * bit 7 is unused/reserved
274 */
275
276/*
277 * Data Configuration Register (DCR) definitions
278 */
279
280/*
281 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
282 * both remote and local DMA transfers
283 */
284#define ED_DCR_WTS 0x01
285
286/*
287 * BOS: Byte Order Select. BOS sets the byte order for the host.
288 * Should be 0 for 80x86, and 1 for 68000 series processors
289 */
290#define ED_DCR_BOS 0x02
291
292/*
293 * LAS: Long Address Select. When LAS is 1, the contents of the remote
294 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
295 */
296#define ED_DCR_LAS 0x04
297
298/*
299 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
300 * of the TCR must also be programmed for loopback operation.
301 * When 1, normal operation is selected.
302 */
303#define ED_DCR_LS 0x08
304
305/*
306 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
307 * under program control. When 1, remote DMA is automatically initiated
308 * and the boundry pointer is automatically updated
309 */
310#define ED_DCR_AR 0x10
311
312/*
313 * FT0, FT1: Fifo Threshold select.
314 * FT1 FT0 Word-width Byte-width
315 * 0 0 1 word 2 bytes
316 * 0 1 2 words 4 bytes
317 * 1 0 4 words 8 bytes
318 * 1 1 8 words 12 bytes
319 *
320 * During transmission, the FIFO threshold indicates the number of bytes
321 * or words that the FIFO has filled from the local DMA before BREQ is
322 * asserted. The transmission threshold is 16 bytes minus the receiver
323 * threshold.
324 */
325#define ED_DCR_FT0 0x20
326#define ED_DCR_FT1 0x40
327
328/*
329 * bit 7 (0x80) is unused/reserved
330 */
331
332/*
333 * Transmit Configuration Register (TCR) definitions
334 */
335
336/*
337 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
338 * is not appended by the transmitter.
339 */
340#define ED_TCR_CRC 0x01
341
342/*
343 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
344 * to be performed.
345 *
346 * LB1 LB0 mode
347 * 0 0 0 - normal operation (DCR_LS = 0)
348 * 0 1 1 - internal loopback (DCR_LS = 0)
349 * 1 0 2 - external loopback (DCR_LS = 1)
350 * 1 1 3 - external loopback (DCR_LS = 0)
351 */
352#define ED_TCR_LB0 0x02
353#define ED_TCR_LB1 0x04
354
355/*
356 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
357 * another station to disable the NIC's transmitter by transmitting to
358 * a multicast address hashing to bit 62. Reception of a multicast address
359 * hashing to bit 63 enables the transmitter.
360 */
361#define ED_TCR_ATD 0x08
362
363/*
364 * OFST: Collision Offset enable. This bit when set modifies the backoff
365 * algorithm to allow prioritization of nodes.
366 */
367#define ED_TCR_OFST 0x10
368
369/*
370 * bits 5, 6, and 7 are unused/reserved
371 */
372
373/*
374 * Transmit Status Register (TSR) definitions
375 */
376
377/*
378 * PTX: Packet Transmitted. Indicates successful transmission of packet.
379 */
380#define ED_TSR_PTX 0x01
381
382/*
383 * bit 1 (0x02) is unused/reserved
384 */
385
386/*
387 * COL: Transmit Collided. Indicates that the transmission collided at least
388 * once with another station on the network.
389 */
390#define ED_TSR_COL 0x04
391
392/*
393 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
394 * excessive collisions.
395 */
396#define ED_TSR_ABT 0x08
397
398/*
399 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
400 * transmission of the packet. (Transmission is not aborted because
401 * of a loss of carrier)
402 */
403#define ED_TSR_CRS 0x10
404
405/*
406 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
407 * transmission memory before the FIFO emptied. Transmission of the
408 * packet was aborted.
409 */
410#define ED_TSR_FU 0x20
411
412/*
413 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
414 * isn't working correctly during a collision heartbeat test.
415 */
416#define ED_TSR_CDH 0x40
417
418/*
419 * OWC: Out of Window Collision: Indicates that a collision occurred after
420 * a slot time (51.2us). The transmission is rescheduled just as in
421 * normal collisions.
422 */
423#define ED_TSR_OWC 0x80
424
425/*
426 * Receiver Configuration Register (RCR) definitions
427 */
428
429/*
430 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
431 * packets with CRC and frame errors are not discarded.
432 */
433#define ED_RCR_SEP 0x01
434
435/*
436 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
437 * If set to 1, packets with less than 64 byte are not discarded.
438 */
439#define ED_RCR_AR 0x02
440
441/*
442 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
443 * accepted.
444 */
445#define ED_RCR_AB 0x04
446
447/*
448 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
449 * for a match in the hashing array. If clear, multicast packets are ignored.
450 */
451#define ED_RCR_AM 0x08
452
453/*
454 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
455 * accepted. If clear, a physical destination address must match this
456 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
457 * must also be set. In addition, the multicast hashing array must be set
458 * to all 1's so that all multicast addresses are accepted.
459 */
460#define ED_RCR_PRO 0x10
461
462/*
463 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
464 * but are not stored in the ring-buffer. If clear, packets are stored (normal
465 * operation).
466 */
467#define ED_RCR_MON 0x20
468
469/*
470 * bits 6 and 7 are unused/reserved.
471 */
472
473/*
474 * Receiver Status Register (RSR) definitions
475 */
476
477/*
478 * PRX: Packet Received without error.
479 */
480#define ED_RSR_PRX 0x01
481
482/*
483 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
484 * alignment errors.
485 */
486#define ED_RSR_CRC 0x02
487
488/*
489 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
490 * a byte boundry and the CRC did not match at the last byte boundry.
491 */
492#define ED_RSR_FAE 0x04
493
494/*
495 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
496 * causing it to overrun. Reception of the packet is aborted.
497 */
498#define ED_RSR_FO 0x08
499
500/*
501 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
502 * the ring-buffer because of insufficient buffer space (exceeding the
503 * boundry pointer), or because the transfer to the ring-buffer was inhibited
504 * by RCR_MON - monitor mode.
505 */
506#define ED_RSR_MPA 0x10
507
508/*
509 * PHY: Physical address. If 0, the packet received was sent to a physical address.
510 * If 1, the packet was accepted because of a multicast/broadcast address
511 * match.
512 */
513#define ED_RSR_PHY 0x20
514
515/*
516 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
517 * mode. Cleared when the receiver exits monitor mode.
518 */
519#define ED_RSR_DIS 0x40
520
521/*
522 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
523 * are active, and the transceiver has set the CD line as a result of the
524 * jabber.
525 */
526#define ED_RSR_DFR 0x80
527
528/*
529 * receive ring discriptor
530 *
531 * The National Semiconductor DS8390 Network interface controller uses
532 * the following receive ring headers. The way this works is that the
533 * memory on the interface card is chopped up into 256 bytes blocks.
534 * A contiguous portion of those blocks are marked for receive packets
535 * by setting start and end block #'s in the NIC. For each packet that
536 * is put into the receive ring, one of these headers (4 bytes each) is
537 * tacked onto the front.
538 */
539struct ed_ring {
540 struct edr_status { /* received packet status */
541 u_char rs_prx:1, /* packet received intack */
542 rs_crc:1, /* crc error */
543 rs_fae:1, /* frame alignment error */
544 rs_fo:1, /* fifo overrun */
545 rs_mpa:1, /* packet received intack */
546 rs_phy:1, /* packet received intack */
547 rs_dis:1, /* packet received intack */
548 rs_dfr:1; /* packet received intack */
549 } ed_rcv_status; /* received packet status */
550 u_char next_packet; /* pointer to next packet */
551 u_short count; /* bytes in packet (length + 4) */
552};
553
554/*
555 * Common constants
556 */
557#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
558#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
559
560/*
561 * Vendor types
562 */
563#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
564#define ED_VENDOR_3COM 0x01 /* 3Com */
565#define ED_VENDOR_NOVELL 0x02 /* Novell */
566
567/*
568 * Compile-time config flags
569 */
570/*
571 * this sets the default for enabling/disablng the tranceiver
572 */
573#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
574
575/*
576 * This forces the board to be used in 8/16bit mode even if it
577 * autoconfigs differently
578 */
579#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
580#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
581
582/*
583 * This disables the use of double transmit buffers.
584 */
585#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
586
587/*
588 * This forces all operations with the NIC memory to use Programmed
589 * I/O (i.e. not via shared memory)
590 */
591#define ED_FLAGS_FORCE_PIO 0x0010
592
593/*
594 * Definitions for Western digital/SMC WD80x3 series ASIC
595 */
596/*
597 * Memory Select Register (MSR)
598 */
599#define ED_WD_MSR 0
600
601#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
602#define ED_WD_MSR_MENB 0x40 /* Memory enable */
603#define ED_WD_MSR_RST 0x80 /* Reset board */
604
605/*
606 * Interface Configuration Register (ICR)
607 */
608#define ED_WD_ICR 1
609
610#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
611#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
612#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
613#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
614#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
615#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
616#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
617#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
618
619/*
620 * IO Address Register (IAR)
621 */
622#define ED_WD_IAR 2
623
624/*
625 * EEROM Address Register
626 */
627#define ED_WD_EAR 3
628
629/*
630 * Interrupt Request Register (IRR)
631 */
632#define ED_WD_IRR 4
633
634#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
635#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
636#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
637#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
638#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
639
640/*
641 * The three bit of the encoded IRQ are decoded as follows:
642 *
643 * IR2 IR1 IR0 IRQ
644 * 0 0 0 2/9
645 * 0 0 1 3
646 * 0 1 0 5
647 * 0 1 1 7
648 * 1 0 0 10
649 * 1 0 1 11
650 * 1 1 0 15
651 * 1 1 1 4
652 */
653#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
654#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
655#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
656
657/*
658 * LA Address Register (LAAR)
659 */
660#define ED_WD_LAAR 5
661
662#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
663#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
664#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
665#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
666
667/* i/o base offset to station address/card-ID PROM */
668#define ED_WD_PROM 8
669
670/* i/o base offset to CARD ID */
671#define ED_WD_CARD_ID ED_WD_PROM+6
672
673/* Board type codes in card ID */
674#define ED_TYPE_WD8003S 0x02
675#define ED_TYPE_WD8003E 0x03
676#define ED_TYPE_WD8013EBT 0x05
677#define ED_TYPE_WD8013EP 0x27
678#define ED_TYPE_WD8013WC 0x28
679#define ED_TYPE_WD8013EBP 0x2c
680#define ED_TYPE_WD8013EPC 0x29
|