1/*
2 * National Semiconductor DS8390 NIC register definitions
3 *
4 * $Id: if_edreg.h,v 2.1 1993/11/22 10:52:33 davidg Exp davidg $
5 *
6 * Modification history
7 *
8 * Revision 2.1 1993/11/22 10:52:33 davidg
9 * patch to add support for SMC8216 (Elite-Ultra) boards
10 * from Glen H. Lowe
11 *
12 * Revision 2.0 93/09/29 00:37:15 davidg
13 * changed double buffering flag to multi buffering
14 * made changes/additions for 3c503 multi-buffering
15 * ...companion to Rev. 2.0 of 'ed' driver.
16 *
17 * Revision 1.1 93/06/23 03:01:07 davidg
18 * Initial revision
19 *
20 */
21
22/*
23 * Page 0 register offsets
24 */
25#define ED_P0_CR 0x00 /* Command Register */
26
27#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
28#define ED_P0_PSTART 0x01 /* Page Start register (write) */
29
30#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
31#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
32
33#define ED_P0_BNRY 0x03 /* Boundary Pointer */
34
35#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
36#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
37
38#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
39#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
40
41#define ED_P0_FIFO 0x06 /* FIFO register (read) */
42#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
43
44#define ED_P0_ISR 0x07 /* Interrupt Status Register */
45
46#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
47#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
48
49#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
50#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
51
52#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
53
54#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
55
56#define ED_P0_RSR 0x0c /* Receive Status (read) */
57#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
58
59#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
60#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
61
62#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
63#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
64
65#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
66#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
67
68/*
69 * Page 1 register offsets
70 */
71#define ED_P1_CR 0x00 /* Command Register */
72#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
73#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
74#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
75#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
76#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
77#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
78#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
79#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
80#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
81#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
82#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
83#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
84#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
85#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
86#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
87
88/*
89 * Page 2 register offsets
90 */
91#define ED_P2_CR 0x00 /* Command Register */
92#define ED_P2_PSTART 0x01 /* Page Start (read) */
93#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
94#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
95#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
96#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
97#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
98#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
99#define ED_P2_ACU 0x06 /* Address Counter Upper */
100#define ED_P2_ACL 0x07 /* Address Counter Lower */
101#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
102#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
103#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
104#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
105
106/*
107 * Command Register (CR) definitions
108 */
109
110/*
111 * STP: SToP. Software reset command. Takes the controller offline. No
112 * packets will be received or transmitted. Any reception or
113 * transmission in progress will continue to completion before
114 * entering reset state. To exit this state, the STP bit must
115 * reset and the STA bit must be set. The software reset has
116 * executed only when indicated by the RST bit in the ISR being
117 * set.
118 */
119#define ED_CR_STP 0x01
120
121/*
122 * STA: STArt. This bit is used to activate the NIC after either power-up,
123 * or when the NIC has been put in reset mode by software command
124 * or error.
125 */
126#define ED_CR_STA 0x02
127
128/*
129 * TXP: Transmit Packet. This bit must be set to indicate transmission of
130 * a packet. TXP is internally reset either after the transmission is
131 * completed or aborted. This bit should be set only after the Transmit
132 * Byte Count and Transmit Page Start register have been programmed.
133 */
134#define ED_CR_TXP 0x04
135
136/*
137 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
138 * of the remote DMA channel. RD2 can be set to abort any remote DMA
139 * command in progress. The Remote Byte Count registers should be cleared
140 * when a remote DMA has been aborted. The Remote Start Addresses are not
141 * restored to the starting address if the remote DMA is aborted.
142 *
143 * RD2 RD1 RD0 function
144 * 0 0 0 not allowed
145 * 0 0 1 remote read
146 * 0 1 0 remote write
147 * 0 1 1 send packet
148 * 1 X X abort
149 */
150#define ED_CR_RD0 0x08
151#define ED_CR_RD1 0x10
152#define ED_CR_RD2 0x20
153
154/*
155 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
156 * access.
157 *
158 * PS1 PS0 page
159 * 0 0 0
160 * 0 1 1
161 * 1 0 2
162 * 1 1 reserved
163 */
164#define ED_CR_PS0 0x40
165#define ED_CR_PS1 0x80
166/* bit encoded aliases */
167#define ED_CR_PAGE_0 0x00 /* (for consistency) */
168#define ED_CR_PAGE_1 0x40
169#define ED_CR_PAGE_2 0x80
170
171/*
172 * Interrupt Status Register (ISR) definitions
173 */
174
175/*
176 * PRX: Packet Received. Indicates packet received with no errors.
177 */
178#define ED_ISR_PRX 0x01
179
180/*
181 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
182 */
183#define ED_ISR_PTX 0x02
184
185/*
186 * RXE: Receive Error. Indicates that a packet was received with one or more
187 * the following errors: CRC error, frame alignment error, FIFO overrun,
188 * missed packet.
189 */
190#define ED_ISR_RXE 0x04
191
192/*
193 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
194 * resulted in one or more of the following errors: excessive
195 * collisions, FIFO underrun.
196 */
197#define ED_ISR_TXE 0x08
198
199/*
200 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
201 * would exceed (has exceeded?) the boundry pointer, resulting in data
202 * that was previously received and not yet read from the buffer to be
203 * overwritten.
204 */
205#define ED_ISR_OVW 0x10
206
207/*
208 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
209 * Counters has been set.
210 */
211#define ED_ISR_CNT 0x20
212
213/*
214 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
215 */
216#define ED_ISR_RDC 0x40
217
218/*
219 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
220 * Start Command is issued to the CR. This bit is also set when a receive
221 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
222 * packets have been removed from the ring. This is a read-only bit.
223 */
224#define ED_ISR_RST 0x80
225
226/*
227 * Interrupt Mask Register (IMR) definitions
228 */
229
230/*
231 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
232 * an interrupt.
233 */
234#define ED_IMR_PRXE 0x01
235
236/*
237 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
238 * a packet transmission completes.
239 */
240#define ED_IMR_PTXE 0x02
241
242/*
243 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
244 * packet is received with an error.
245 */
246#define ED_IMR_RXEE 0x04
247
248/*
249 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
250 * a transmission results in an error.
251 */
252#define ED_IMR_TXEE 0x08
253
254/*
255 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
256 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
257 */
258#define ED_IMR_OVWE 0x10
259
260/*
261 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
262 * the MSB of one or more of the Network Statistics counters has been set.
263 */
264#define ED_IMR_CNTE 0x20
265
266/*
267 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
268 * when a remote DMA transfer has completed.
269 */
270#define ED_IMR_RDCE 0x40
271
272/*
273 * bit 7 is unused/reserved
274 */
275
276/*
277 * Data Configuration Register (DCR) definitions
278 */
279
280/*
281 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
282 * both remote and local DMA transfers
283 */
284#define ED_DCR_WTS 0x01
285
286/*
287 * BOS: Byte Order Select. BOS sets the byte order for the host.
288 * Should be 0 for 80x86, and 1 for 68000 series processors
289 */
290#define ED_DCR_BOS 0x02
291
292/*
293 * LAS: Long Address Select. When LAS is 1, the contents of the remote
294 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
295 */
296#define ED_DCR_LAS 0x04
297
298/*
299 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
300 * of the TCR must also be programmed for loopback operation.
301 * When 1, normal operation is selected.
302 */
303#define ED_DCR_LS 0x08
304
305/*
306 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
307 * under program control. When 1, remote DMA is automatically initiated
308 * and the boundry pointer is automatically updated
309 */
310#define ED_DCR_AR 0x10
311
312/*
313 * FT0, FT1: Fifo Threshold select.
314 * FT1 FT0 Word-width Byte-width
315 * 0 0 1 word 2 bytes
316 * 0 1 2 words 4 bytes
317 * 1 0 4 words 8 bytes
318 * 1 1 8 words 12 bytes
319 *
320 * During transmission, the FIFO threshold indicates the number of bytes
321 * or words that the FIFO has filled from the local DMA before BREQ is
322 * asserted. The transmission threshold is 16 bytes minus the receiver
323 * threshold.
324 */
325#define ED_DCR_FT0 0x20
326#define ED_DCR_FT1 0x40
327
328/*
329 * bit 7 (0x80) is unused/reserved
330 */
331
332/*
333 * Transmit Configuration Register (TCR) definitions
334 */
335
336/*
337 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
338 * is not appended by the transmitter.
339 */
340#define ED_TCR_CRC 0x01
341
342/*
343 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
344 * to be performed.
345 *
346 * LB1 LB0 mode
347 * 0 0 0 - normal operation (DCR_LS = 0)
348 * 0 1 1 - internal loopback (DCR_LS = 0)
349 * 1 0 2 - external loopback (DCR_LS = 1)
350 * 1 1 3 - external loopback (DCR_LS = 0)
351 */
352#define ED_TCR_LB0 0x02
353#define ED_TCR_LB1 0x04
354
355/*
356 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
357 * another station to disable the NIC's transmitter by transmitting to
358 * a multicast address hashing to bit 62. Reception of a multicast address
359 * hashing to bit 63 enables the transmitter.
360 */
361#define ED_TCR_ATD 0x08
362
363/*
364 * OFST: Collision Offset enable. This bit when set modifies the backoff
365 * algorithm to allow prioritization of nodes.
366 */
367#define ED_TCR_OFST 0x10
368
369/*
370 * bits 5, 6, and 7 are unused/reserved
371 */
372
373/*
374 * Transmit Status Register (TSR) definitions
375 */
376
377/*
378 * PTX: Packet Transmitted. Indicates successful transmission of packet.
379 */
380#define ED_TSR_PTX 0x01
381
382/*
383 * bit 1 (0x02) is unused/reserved
384 */
385
386/*
387 * COL: Transmit Collided. Indicates that the transmission collided at least
388 * once with another station on the network.
389 */
390#define ED_TSR_COL 0x04
391
392/*
393 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
394 * excessive collisions.
395 */
396#define ED_TSR_ABT 0x08
397
398/*
399 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
400 * transmission of the packet. (Transmission is not aborted because
401 * of a loss of carrier)
402 */
403#define ED_TSR_CRS 0x10
404
405/*
406 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
407 * transmission memory before the FIFO emptied. Transmission of the
408 * packet was aborted.
409 */
410#define ED_TSR_FU 0x20
411
412/*
413 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
414 * isn't working correctly during a collision heartbeat test.
415 */
416#define ED_TSR_CDH 0x40
417
418/*
419 * OWC: Out of Window Collision: Indicates that a collision occurred after
420 * a slot time (51.2us). The transmission is rescheduled just as in
421 * normal collisions.
422 */
423#define ED_TSR_OWC 0x80
424
425/*
426 * Receiver Configuration Register (RCR) definitions
427 */
428
429/*
430 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
431 * packets with CRC and frame errors are not discarded.
432 */
433#define ED_RCR_SEP 0x01
434
435/*
436 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
437 * If set to 1, packets with less than 64 byte are not discarded.
438 */
439#define ED_RCR_AR 0x02
440
441/*
442 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
443 * accepted.
444 */
445#define ED_RCR_AB 0x04
446
447/*
448 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
449 * for a match in the hashing array. If clear, multicast packets are ignored.
450 */
451#define ED_RCR_AM 0x08
452
453/*
454 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
455 * accepted. If clear, a physical destination address must match this
456 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
457 * must also be set. In addition, the multicast hashing array must be set
458 * to all 1's so that all multicast addresses are accepted.
459 */
460#define ED_RCR_PRO 0x10
461
462/*
463 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
464 * but are not stored in the ring-buffer. If clear, packets are stored (normal
465 * operation).
466 */
467#define ED_RCR_MON 0x20
468
469/*
470 * bits 6 and 7 are unused/reserved.
471 */
472
473/*
474 * Receiver Status Register (RSR) definitions
475 */
476
477/*
478 * PRX: Packet Received without error.
479 */
480#define ED_RSR_PRX 0x01
481
482/*
483 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
484 * alignment errors.
485 */
486#define ED_RSR_CRC 0x02
487
488/*
489 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
490 * a byte boundry and the CRC did not match at the last byte boundry.
491 */
492#define ED_RSR_FAE 0x04
493
494/*
495 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
496 * causing it to overrun. Reception of the packet is aborted.
497 */
498#define ED_RSR_FO 0x08
499
500/*
501 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
502 * the ring-buffer because of insufficient buffer space (exceeding the
503 * boundry pointer), or because the transfer to the ring-buffer was inhibited
504 * by RCR_MON - monitor mode.
505 */
506#define ED_RSR_MPA 0x10
507
508/*
509 * PHY: Physical address. If 0, the packet received was sent to a physical address.
510 * If 1, the packet was accepted because of a multicast/broadcast address
511 * match.
512 */
513#define ED_RSR_PHY 0x20
514
515/*
516 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
517 * mode. Cleared when the receiver exits monitor mode.
518 */
519#define ED_RSR_DIS 0x40
520
521/*
522 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
523 * are active, and the transceiver has set the CD line as a result of the
524 * jabber.
525 */
526#define ED_RSR_DFR 0x80
527
528/*
529 * receive ring discriptor
530 *
531 * The National Semiconductor DS8390 Network interface controller uses
532 * the following receive ring headers. The way this works is that the
533 * memory on the interface card is chopped up into 256 bytes blocks.
534 * A contiguous portion of those blocks are marked for receive packets
535 * by setting start and end block #'s in the NIC. For each packet that
536 * is put into the receive ring, one of these headers (4 bytes each) is
537 * tacked onto the front.
538 */
539struct ed_ring {
540 struct edr_status { /* received packet status */
541 u_char rs_prx:1, /* packet received intack */
542 rs_crc:1, /* crc error */
543 rs_fae:1, /* frame alignment error */
544 rs_fo:1, /* fifo overrun */
545 rs_mpa:1, /* packet received intack */
546 rs_phy:1, /* packet received intack */
547 rs_dis:1, /* packet received intack */
548 rs_dfr:1; /* packet received intack */
549 } ed_rcv_status; /* received packet status */
550 u_char next_packet; /* pointer to next packet */
551 u_short count; /* bytes in packet (length + 4) */
552};
553
554/*
555 * Common constants
556 */
557#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
558#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
559
560/*
561 * Vendor types
562 */
563#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
564#define ED_VENDOR_3COM 0x01 /* 3Com */
565#define ED_VENDOR_NOVELL 0x02 /* Novell */
566
567/*
568 * Compile-time config flags
569 */
570/*
571 * this sets the default for enabling/disablng the tranceiver
572 */
573#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
574
575/*
576 * This forces the board to be used in 8/16bit mode even if it
577 * autoconfigs differently
578 */
579#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
580#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
581
582/*
583 * This disables the use of double transmit buffers.
584 */
585#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
586
587/*
588 * This forces all operations with the NIC memory to use Programmed
589 * I/O (i.e. not via shared memory)
590 */
591#define ED_FLAGS_FORCE_PIO 0x0010
592
593/*
594 * Definitions for Western digital/SMC WD80x3 series ASIC
595 */
596/*
597 * Memory Select Register (MSR)
598 */
599#define ED_WD_MSR 0
600
601#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
602#define ED_WD_MSR_MENB 0x40 /* Memory enable */
603#define ED_WD_MSR_RST 0x80 /* Reset board */
604
605/*
606 * Interface Configuration Register (ICR)
607 */
608#define ED_WD_ICR 1
609
610#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
611#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
612#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
613#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
614#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
615#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
616#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
617#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
618
619/*
620 * IO Address Register (IAR)
621 */
622#define ED_WD_IAR 2
623
624/*
625 * EEROM Address Register
626 */
627#define ED_WD_EAR 3
628
629/*
630 * Interrupt Request Register (IRR)
631 */
632#define ED_WD_IRR 4
633
634#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
635#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
636#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
637#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
638#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
639
640/*
641 * The three bit of the encoded IRQ are decoded as follows:
642 *
643 * IR2 IR1 IR0 IRQ
644 * 0 0 0 2/9
645 * 0 0 1 3
646 * 0 1 0 5
647 * 0 1 1 7
648 * 1 0 0 10
649 * 1 0 1 11
650 * 1 1 0 15
651 * 1 1 1 4
652 */
653#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
654#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
655#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
656
657/*
658 * LA Address Register (LAAR)
659 */
660#define ED_WD_LAAR 5
661
662#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
663#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
664#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
665#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
666
667/* i/o base offset to station address/card-ID PROM */
668#define ED_WD_PROM 8
669
670/* i/o base offset to CARD ID */
671#define ED_WD_CARD_ID ED_WD_PROM+6
672
673/* Board type codes in card ID */
674#define ED_TYPE_WD8003S 0x02
675#define ED_TYPE_WD8003E 0x03
676#define ED_TYPE_WD8013EBT 0x05
677#define ED_TYPE_WD8013EP 0x27
678#define ED_TYPE_WD8013WC 0x28
679#define ED_TYPE_WD8013EBP 0x2c
680#define ED_TYPE_WD8013EPC 0x29
681#define ED_TYPE_SMC8216T 0x2a
682#define ED_TYPE_SMC8216C 0x2b
683
684/* Bit definitions in card ID */
685#define ED_WD_REV_MASK 0x1f /* Revision mask */
686#define ED_WD_SOFTCONFIG 0x20 /* Soft config */
687#define ED_WD_LARGERAM 0x40 /* Large RAM */
688#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
689
690/*
691 * Checksum total. All 8 bytes in station address PROM will add up to this
692 */
693#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
694
695#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
696#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
697#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
698
699#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
700
701/*
702 * Definitions for 3Com 3c503
703 */
704#define ED_3COM_NIC_OFFSET 0
705#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
706
707/*
708 * XXX - The I/O address range is fragmented in the 3c503; this is the
709 * number of regs at iobase.
710 */
711#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
712
713/* tx memory starts in second bank on 8bit cards */
714#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20
715
716/* tx memory starts in first bank on 16bit cards */
717#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0
718
719/* ...and rx memory starts in second bank */
720#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20
721
722
723/*
724 * Page Start Register. Must match PSTART in NIC
725 */
726#define ED_3COM_PSTR 0
727
728/*
729 * Page Stop Register. Must match PSTOP in NIC
730 */
731#define ED_3COM_PSPR 1
732
733/*
734 * Drq Timer Register. Determines number of bytes to be transfered during
735 * a DMA burst.
736 */
737#define ED_3COM_DQTR 2
738
739/*
740 * Base Configuration Register. Read-only register which contains the
741 * board-configured I/O base address of the adapter. Bit encoded.
742 */
743#define ED_3COM_BCFR 3
744
745#define ED_3COM_BCFR_2E0 0x01
746#define ED_3COM_BCFR_2A0 0x02
747#define ED_3COM_BCFR_280 0x04
748#define ED_3COM_BCFR_250 0x08
749#define ED_3COM_BCFR_350 0x10
750#define ED_3COM_BCFR_330 0x20
751#define ED_3COM_BCFR_310 0x40
752#define ED_3COM_BCFR_300 0x80
753
754/*
755 * EPROM Configuration Register. Read-only register which contains the
756 * board-configured memory base address. Bit encoded.
757 */
758#define ED_3COM_PCFR 4
759
760#define ED_3COM_PCFR_C8000 0x10
761#define ED_3COM_PCFR_CC000 0x20
762#define ED_3COM_PCFR_D8000 0x40
763#define ED_3COM_PCFR_DC000 0x80
764
765/*
766 * GA Configuration Register. Gate-Array Configuration Register.
767 */
768#define ED_3COM_GACFR 5
769
770/*
771 * mbs2 mbs1 mbs0 start address
772 * 0 0 0 0x0000
773 * 0 0 1 0x2000
774 * 0 1 0 0x4000
775 * 0 1 1 0x6000
776 *
777 * Note that with adapters with only 8K, the setting for 0x2000 must
778 * always be used.
779 */
780#define ED_3COM_GACFR_MBS0 0x01
781#define ED_3COM_GACFR_MBS1 0x02
782#define ED_3COM_GACFR_MBS2 0x04
783
784#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
785#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
786#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
787#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
788#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
789
790/*
791 * Control Register. Miscellaneous control functions.
792 */
793#define ED_3COM_CR 6
794
795#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
796#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
797#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
798#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
799#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
800#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
801#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
802#define ED_3COM_CR_START 0x80 /* Start DMA controller */
803
804/*
805 * Status Register. Miscellaneous status information.
806 */
807#define ED_3COM_STREG 7
808
809#define ED_3COM_STREG_REV 0x07 /* GA revision */
810#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
811#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
812#define ED_3COM_STREG_OFLW 0x20 /* Overflow */
813#define ED_3COM_STREG_UFLW 0x40 /* Underflow */
814#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
815
816/*
817 * Interrupt/DMA Configuration Register
818 */
819#define ED_3COM_IDCFR 8
820
821#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
822#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
823#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
824#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
825#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
826#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
827#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
828#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
829
830/*
831 * DMA Address Register MSB
832 */
833#define ED_3COM_DAMSB 9
834
835/*
836 * DMA Address Register LSB
837 */
838#define ED_3COM_DALSB 0x0a
839
840/*
841 * Vector Pointer Register 2
842 */
843#define ED_3COM_VPTR2 0x0b
844
845/*
846 * Vector Pointer Register 1
847 */
848#define ED_3COM_VPTR1 0x0c
849
850/*
851 * Vector Pointer Register 0
852 */
853#define ED_3COM_VPTR0 0x0d
854
855/*
856 * Register File Access MSB
857 */
858#define ED_3COM_RFMSB 0x0e
859
860/*
861 * Register File Access LSB
862 */
863#define ED_3COM_RFLSB 0x0f
864
865/*
866 * Definitions for Novell NE1000/2000 boards
867 */
868
869/*
870 * Board type codes
871 */
872#define ED_TYPE_NE1000 0x01
873#define ED_TYPE_NE2000 0x02
874
875/*
876 * Register offsets/total
877 */
878#define ED_NOVELL_NIC_OFFSET 0x00
879#define ED_NOVELL_ASIC_OFFSET 0x10
880#define ED_NOVELL_IO_PORTS 32
881
882/*
883 * Remote DMA data register; for reading or writing to the NIC mem
884 * via programmed I/O (offset from ASIC base)
885 */
886#define ED_NOVELL_DATA 0x00
887
888/*
889 * Reset register; reading from this register causes a board reset
890 */
891#define ED_NOVELL_RESET 0x0f
2 * National Semiconductor DS8390 NIC register definitions
3 *
4 * $Id: if_edreg.h,v 2.1 1993/11/22 10:52:33 davidg Exp davidg $
5 *
6 * Modification history
7 *
8 * Revision 2.1 1993/11/22 10:52:33 davidg
9 * patch to add support for SMC8216 (Elite-Ultra) boards
10 * from Glen H. Lowe
11 *
12 * Revision 2.0 93/09/29 00:37:15 davidg
13 * changed double buffering flag to multi buffering
14 * made changes/additions for 3c503 multi-buffering
15 * ...companion to Rev. 2.0 of 'ed' driver.
16 *
17 * Revision 1.1 93/06/23 03:01:07 davidg
18 * Initial revision
19 *
20 */
21
22/*
23 * Page 0 register offsets
24 */
25#define ED_P0_CR 0x00 /* Command Register */
26
27#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
28#define ED_P0_PSTART 0x01 /* Page Start register (write) */
29
30#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
31#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
32
33#define ED_P0_BNRY 0x03 /* Boundary Pointer */
34
35#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
36#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
37
38#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
39#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
40
41#define ED_P0_FIFO 0x06 /* FIFO register (read) */
42#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
43
44#define ED_P0_ISR 0x07 /* Interrupt Status Register */
45
46#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
47#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
48
49#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
50#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
51
52#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
53
54#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
55
56#define ED_P0_RSR 0x0c /* Receive Status (read) */
57#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
58
59#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
60#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
61
62#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
63#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
64
65#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
66#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
67
68/*
69 * Page 1 register offsets
70 */
71#define ED_P1_CR 0x00 /* Command Register */
72#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
73#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
74#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
75#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
76#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
77#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
78#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
79#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
80#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
81#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
82#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
83#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
84#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
85#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
86#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
87
88/*
89 * Page 2 register offsets
90 */
91#define ED_P2_CR 0x00 /* Command Register */
92#define ED_P2_PSTART 0x01 /* Page Start (read) */
93#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
94#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
95#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
96#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
97#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
98#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
99#define ED_P2_ACU 0x06 /* Address Counter Upper */
100#define ED_P2_ACL 0x07 /* Address Counter Lower */
101#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
102#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
103#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
104#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
105
106/*
107 * Command Register (CR) definitions
108 */
109
110/*
111 * STP: SToP. Software reset command. Takes the controller offline. No
112 * packets will be received or transmitted. Any reception or
113 * transmission in progress will continue to completion before
114 * entering reset state. To exit this state, the STP bit must
115 * reset and the STA bit must be set. The software reset has
116 * executed only when indicated by the RST bit in the ISR being
117 * set.
118 */
119#define ED_CR_STP 0x01
120
121/*
122 * STA: STArt. This bit is used to activate the NIC after either power-up,
123 * or when the NIC has been put in reset mode by software command
124 * or error.
125 */
126#define ED_CR_STA 0x02
127
128/*
129 * TXP: Transmit Packet. This bit must be set to indicate transmission of
130 * a packet. TXP is internally reset either after the transmission is
131 * completed or aborted. This bit should be set only after the Transmit
132 * Byte Count and Transmit Page Start register have been programmed.
133 */
134#define ED_CR_TXP 0x04
135
136/*
137 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
138 * of the remote DMA channel. RD2 can be set to abort any remote DMA
139 * command in progress. The Remote Byte Count registers should be cleared
140 * when a remote DMA has been aborted. The Remote Start Addresses are not
141 * restored to the starting address if the remote DMA is aborted.
142 *
143 * RD2 RD1 RD0 function
144 * 0 0 0 not allowed
145 * 0 0 1 remote read
146 * 0 1 0 remote write
147 * 0 1 1 send packet
148 * 1 X X abort
149 */
150#define ED_CR_RD0 0x08
151#define ED_CR_RD1 0x10
152#define ED_CR_RD2 0x20
153
154/*
155 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
156 * access.
157 *
158 * PS1 PS0 page
159 * 0 0 0
160 * 0 1 1
161 * 1 0 2
162 * 1 1 reserved
163 */
164#define ED_CR_PS0 0x40
165#define ED_CR_PS1 0x80
166/* bit encoded aliases */
167#define ED_CR_PAGE_0 0x00 /* (for consistency) */
168#define ED_CR_PAGE_1 0x40
169#define ED_CR_PAGE_2 0x80
170
171/*
172 * Interrupt Status Register (ISR) definitions
173 */
174
175/*
176 * PRX: Packet Received. Indicates packet received with no errors.
177 */
178#define ED_ISR_PRX 0x01
179
180/*
181 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
182 */
183#define ED_ISR_PTX 0x02
184
185/*
186 * RXE: Receive Error. Indicates that a packet was received with one or more
187 * the following errors: CRC error, frame alignment error, FIFO overrun,
188 * missed packet.
189 */
190#define ED_ISR_RXE 0x04
191
192/*
193 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
194 * resulted in one or more of the following errors: excessive
195 * collisions, FIFO underrun.
196 */
197#define ED_ISR_TXE 0x08
198
199/*
200 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
201 * would exceed (has exceeded?) the boundry pointer, resulting in data
202 * that was previously received and not yet read from the buffer to be
203 * overwritten.
204 */
205#define ED_ISR_OVW 0x10
206
207/*
208 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
209 * Counters has been set.
210 */
211#define ED_ISR_CNT 0x20
212
213/*
214 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
215 */
216#define ED_ISR_RDC 0x40
217
218/*
219 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
220 * Start Command is issued to the CR. This bit is also set when a receive
221 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
222 * packets have been removed from the ring. This is a read-only bit.
223 */
224#define ED_ISR_RST 0x80
225
226/*
227 * Interrupt Mask Register (IMR) definitions
228 */
229
230/*
231 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
232 * an interrupt.
233 */
234#define ED_IMR_PRXE 0x01
235
236/*
237 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
238 * a packet transmission completes.
239 */
240#define ED_IMR_PTXE 0x02
241
242/*
243 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
244 * packet is received with an error.
245 */
246#define ED_IMR_RXEE 0x04
247
248/*
249 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
250 * a transmission results in an error.
251 */
252#define ED_IMR_TXEE 0x08
253
254/*
255 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
256 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
257 */
258#define ED_IMR_OVWE 0x10
259
260/*
261 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
262 * the MSB of one or more of the Network Statistics counters has been set.
263 */
264#define ED_IMR_CNTE 0x20
265
266/*
267 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
268 * when a remote DMA transfer has completed.
269 */
270#define ED_IMR_RDCE 0x40
271
272/*
273 * bit 7 is unused/reserved
274 */
275
276/*
277 * Data Configuration Register (DCR) definitions
278 */
279
280/*
281 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
282 * both remote and local DMA transfers
283 */
284#define ED_DCR_WTS 0x01
285
286/*
287 * BOS: Byte Order Select. BOS sets the byte order for the host.
288 * Should be 0 for 80x86, and 1 for 68000 series processors
289 */
290#define ED_DCR_BOS 0x02
291
292/*
293 * LAS: Long Address Select. When LAS is 1, the contents of the remote
294 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
295 */
296#define ED_DCR_LAS 0x04
297
298/*
299 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
300 * of the TCR must also be programmed for loopback operation.
301 * When 1, normal operation is selected.
302 */
303#define ED_DCR_LS 0x08
304
305/*
306 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
307 * under program control. When 1, remote DMA is automatically initiated
308 * and the boundry pointer is automatically updated
309 */
310#define ED_DCR_AR 0x10
311
312/*
313 * FT0, FT1: Fifo Threshold select.
314 * FT1 FT0 Word-width Byte-width
315 * 0 0 1 word 2 bytes
316 * 0 1 2 words 4 bytes
317 * 1 0 4 words 8 bytes
318 * 1 1 8 words 12 bytes
319 *
320 * During transmission, the FIFO threshold indicates the number of bytes
321 * or words that the FIFO has filled from the local DMA before BREQ is
322 * asserted. The transmission threshold is 16 bytes minus the receiver
323 * threshold.
324 */
325#define ED_DCR_FT0 0x20
326#define ED_DCR_FT1 0x40
327
328/*
329 * bit 7 (0x80) is unused/reserved
330 */
331
332/*
333 * Transmit Configuration Register (TCR) definitions
334 */
335
336/*
337 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
338 * is not appended by the transmitter.
339 */
340#define ED_TCR_CRC 0x01
341
342/*
343 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
344 * to be performed.
345 *
346 * LB1 LB0 mode
347 * 0 0 0 - normal operation (DCR_LS = 0)
348 * 0 1 1 - internal loopback (DCR_LS = 0)
349 * 1 0 2 - external loopback (DCR_LS = 1)
350 * 1 1 3 - external loopback (DCR_LS = 0)
351 */
352#define ED_TCR_LB0 0x02
353#define ED_TCR_LB1 0x04
354
355/*
356 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
357 * another station to disable the NIC's transmitter by transmitting to
358 * a multicast address hashing to bit 62. Reception of a multicast address
359 * hashing to bit 63 enables the transmitter.
360 */
361#define ED_TCR_ATD 0x08
362
363/*
364 * OFST: Collision Offset enable. This bit when set modifies the backoff
365 * algorithm to allow prioritization of nodes.
366 */
367#define ED_TCR_OFST 0x10
368
369/*
370 * bits 5, 6, and 7 are unused/reserved
371 */
372
373/*
374 * Transmit Status Register (TSR) definitions
375 */
376
377/*
378 * PTX: Packet Transmitted. Indicates successful transmission of packet.
379 */
380#define ED_TSR_PTX 0x01
381
382/*
383 * bit 1 (0x02) is unused/reserved
384 */
385
386/*
387 * COL: Transmit Collided. Indicates that the transmission collided at least
388 * once with another station on the network.
389 */
390#define ED_TSR_COL 0x04
391
392/*
393 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
394 * excessive collisions.
395 */
396#define ED_TSR_ABT 0x08
397
398/*
399 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
400 * transmission of the packet. (Transmission is not aborted because
401 * of a loss of carrier)
402 */
403#define ED_TSR_CRS 0x10
404
405/*
406 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
407 * transmission memory before the FIFO emptied. Transmission of the
408 * packet was aborted.
409 */
410#define ED_TSR_FU 0x20
411
412/*
413 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
414 * isn't working correctly during a collision heartbeat test.
415 */
416#define ED_TSR_CDH 0x40
417
418/*
419 * OWC: Out of Window Collision: Indicates that a collision occurred after
420 * a slot time (51.2us). The transmission is rescheduled just as in
421 * normal collisions.
422 */
423#define ED_TSR_OWC 0x80
424
425/*
426 * Receiver Configuration Register (RCR) definitions
427 */
428
429/*
430 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
431 * packets with CRC and frame errors are not discarded.
432 */
433#define ED_RCR_SEP 0x01
434
435/*
436 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
437 * If set to 1, packets with less than 64 byte are not discarded.
438 */
439#define ED_RCR_AR 0x02
440
441/*
442 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
443 * accepted.
444 */
445#define ED_RCR_AB 0x04
446
447/*
448 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
449 * for a match in the hashing array. If clear, multicast packets are ignored.
450 */
451#define ED_RCR_AM 0x08
452
453/*
454 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
455 * accepted. If clear, a physical destination address must match this
456 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
457 * must also be set. In addition, the multicast hashing array must be set
458 * to all 1's so that all multicast addresses are accepted.
459 */
460#define ED_RCR_PRO 0x10
461
462/*
463 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
464 * but are not stored in the ring-buffer. If clear, packets are stored (normal
465 * operation).
466 */
467#define ED_RCR_MON 0x20
468
469/*
470 * bits 6 and 7 are unused/reserved.
471 */
472
473/*
474 * Receiver Status Register (RSR) definitions
475 */
476
477/*
478 * PRX: Packet Received without error.
479 */
480#define ED_RSR_PRX 0x01
481
482/*
483 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
484 * alignment errors.
485 */
486#define ED_RSR_CRC 0x02
487
488/*
489 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
490 * a byte boundry and the CRC did not match at the last byte boundry.
491 */
492#define ED_RSR_FAE 0x04
493
494/*
495 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
496 * causing it to overrun. Reception of the packet is aborted.
497 */
498#define ED_RSR_FO 0x08
499
500/*
501 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
502 * the ring-buffer because of insufficient buffer space (exceeding the
503 * boundry pointer), or because the transfer to the ring-buffer was inhibited
504 * by RCR_MON - monitor mode.
505 */
506#define ED_RSR_MPA 0x10
507
508/*
509 * PHY: Physical address. If 0, the packet received was sent to a physical address.
510 * If 1, the packet was accepted because of a multicast/broadcast address
511 * match.
512 */
513#define ED_RSR_PHY 0x20
514
515/*
516 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
517 * mode. Cleared when the receiver exits monitor mode.
518 */
519#define ED_RSR_DIS 0x40
520
521/*
522 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
523 * are active, and the transceiver has set the CD line as a result of the
524 * jabber.
525 */
526#define ED_RSR_DFR 0x80
527
528/*
529 * receive ring discriptor
530 *
531 * The National Semiconductor DS8390 Network interface controller uses
532 * the following receive ring headers. The way this works is that the
533 * memory on the interface card is chopped up into 256 bytes blocks.
534 * A contiguous portion of those blocks are marked for receive packets
535 * by setting start and end block #'s in the NIC. For each packet that
536 * is put into the receive ring, one of these headers (4 bytes each) is
537 * tacked onto the front.
538 */
539struct ed_ring {
540 struct edr_status { /* received packet status */
541 u_char rs_prx:1, /* packet received intack */
542 rs_crc:1, /* crc error */
543 rs_fae:1, /* frame alignment error */
544 rs_fo:1, /* fifo overrun */
545 rs_mpa:1, /* packet received intack */
546 rs_phy:1, /* packet received intack */
547 rs_dis:1, /* packet received intack */
548 rs_dfr:1; /* packet received intack */
549 } ed_rcv_status; /* received packet status */
550 u_char next_packet; /* pointer to next packet */
551 u_short count; /* bytes in packet (length + 4) */
552};
553
554/*
555 * Common constants
556 */
557#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
558#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
559
560/*
561 * Vendor types
562 */
563#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
564#define ED_VENDOR_3COM 0x01 /* 3Com */
565#define ED_VENDOR_NOVELL 0x02 /* Novell */
566
567/*
568 * Compile-time config flags
569 */
570/*
571 * this sets the default for enabling/disablng the tranceiver
572 */
573#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
574
575/*
576 * This forces the board to be used in 8/16bit mode even if it
577 * autoconfigs differently
578 */
579#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
580#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
581
582/*
583 * This disables the use of double transmit buffers.
584 */
585#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
586
587/*
588 * This forces all operations with the NIC memory to use Programmed
589 * I/O (i.e. not via shared memory)
590 */
591#define ED_FLAGS_FORCE_PIO 0x0010
592
593/*
594 * Definitions for Western digital/SMC WD80x3 series ASIC
595 */
596/*
597 * Memory Select Register (MSR)
598 */
599#define ED_WD_MSR 0
600
601#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
602#define ED_WD_MSR_MENB 0x40 /* Memory enable */
603#define ED_WD_MSR_RST 0x80 /* Reset board */
604
605/*
606 * Interface Configuration Register (ICR)
607 */
608#define ED_WD_ICR 1
609
610#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
611#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
612#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
613#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
614#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
615#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
616#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
617#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
618
619/*
620 * IO Address Register (IAR)
621 */
622#define ED_WD_IAR 2
623
624/*
625 * EEROM Address Register
626 */
627#define ED_WD_EAR 3
628
629/*
630 * Interrupt Request Register (IRR)
631 */
632#define ED_WD_IRR 4
633
634#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
635#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
636#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
637#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
638#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
639
640/*
641 * The three bit of the encoded IRQ are decoded as follows:
642 *
643 * IR2 IR1 IR0 IRQ
644 * 0 0 0 2/9
645 * 0 0 1 3
646 * 0 1 0 5
647 * 0 1 1 7
648 * 1 0 0 10
649 * 1 0 1 11
650 * 1 1 0 15
651 * 1 1 1 4
652 */
653#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
654#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
655#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
656
657/*
658 * LA Address Register (LAAR)
659 */
660#define ED_WD_LAAR 5
661
662#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
663#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
664#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
665#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
666
667/* i/o base offset to station address/card-ID PROM */
668#define ED_WD_PROM 8
669
670/* i/o base offset to CARD ID */
671#define ED_WD_CARD_ID ED_WD_PROM+6
672
673/* Board type codes in card ID */
674#define ED_TYPE_WD8003S 0x02
675#define ED_TYPE_WD8003E 0x03
676#define ED_TYPE_WD8013EBT 0x05
677#define ED_TYPE_WD8013EP 0x27
678#define ED_TYPE_WD8013WC 0x28
679#define ED_TYPE_WD8013EBP 0x2c
680#define ED_TYPE_WD8013EPC 0x29
681#define ED_TYPE_SMC8216T 0x2a
682#define ED_TYPE_SMC8216C 0x2b
683
684/* Bit definitions in card ID */
685#define ED_WD_REV_MASK 0x1f /* Revision mask */
686#define ED_WD_SOFTCONFIG 0x20 /* Soft config */
687#define ED_WD_LARGERAM 0x40 /* Large RAM */
688#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
689
690/*
691 * Checksum total. All 8 bytes in station address PROM will add up to this
692 */
693#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
694
695#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
696#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
697#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
698
699#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
700
701/*
702 * Definitions for 3Com 3c503
703 */
704#define ED_3COM_NIC_OFFSET 0
705#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
706
707/*
708 * XXX - The I/O address range is fragmented in the 3c503; this is the
709 * number of regs at iobase.
710 */
711#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
712
713/* tx memory starts in second bank on 8bit cards */
714#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20
715
716/* tx memory starts in first bank on 16bit cards */
717#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0
718
719/* ...and rx memory starts in second bank */
720#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20
721
722
723/*
724 * Page Start Register. Must match PSTART in NIC
725 */
726#define ED_3COM_PSTR 0
727
728/*
729 * Page Stop Register. Must match PSTOP in NIC
730 */
731#define ED_3COM_PSPR 1
732
733/*
734 * Drq Timer Register. Determines number of bytes to be transfered during
735 * a DMA burst.
736 */
737#define ED_3COM_DQTR 2
738
739/*
740 * Base Configuration Register. Read-only register which contains the
741 * board-configured I/O base address of the adapter. Bit encoded.
742 */
743#define ED_3COM_BCFR 3
744
745#define ED_3COM_BCFR_2E0 0x01
746#define ED_3COM_BCFR_2A0 0x02
747#define ED_3COM_BCFR_280 0x04
748#define ED_3COM_BCFR_250 0x08
749#define ED_3COM_BCFR_350 0x10
750#define ED_3COM_BCFR_330 0x20
751#define ED_3COM_BCFR_310 0x40
752#define ED_3COM_BCFR_300 0x80
753
754/*
755 * EPROM Configuration Register. Read-only register which contains the
756 * board-configured memory base address. Bit encoded.
757 */
758#define ED_3COM_PCFR 4
759
760#define ED_3COM_PCFR_C8000 0x10
761#define ED_3COM_PCFR_CC000 0x20
762#define ED_3COM_PCFR_D8000 0x40
763#define ED_3COM_PCFR_DC000 0x80
764
765/*
766 * GA Configuration Register. Gate-Array Configuration Register.
767 */
768#define ED_3COM_GACFR 5
769
770/*
771 * mbs2 mbs1 mbs0 start address
772 * 0 0 0 0x0000
773 * 0 0 1 0x2000
774 * 0 1 0 0x4000
775 * 0 1 1 0x6000
776 *
777 * Note that with adapters with only 8K, the setting for 0x2000 must
778 * always be used.
779 */
780#define ED_3COM_GACFR_MBS0 0x01
781#define ED_3COM_GACFR_MBS1 0x02
782#define ED_3COM_GACFR_MBS2 0x04
783
784#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
785#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
786#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
787#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
788#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
789
790/*
791 * Control Register. Miscellaneous control functions.
792 */
793#define ED_3COM_CR 6
794
795#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
796#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
797#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
798#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
799#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
800#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
801#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
802#define ED_3COM_CR_START 0x80 /* Start DMA controller */
803
804/*
805 * Status Register. Miscellaneous status information.
806 */
807#define ED_3COM_STREG 7
808
809#define ED_3COM_STREG_REV 0x07 /* GA revision */
810#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
811#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
812#define ED_3COM_STREG_OFLW 0x20 /* Overflow */
813#define ED_3COM_STREG_UFLW 0x40 /* Underflow */
814#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
815
816/*
817 * Interrupt/DMA Configuration Register
818 */
819#define ED_3COM_IDCFR 8
820
821#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
822#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
823#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
824#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
825#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
826#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
827#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
828#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
829
830/*
831 * DMA Address Register MSB
832 */
833#define ED_3COM_DAMSB 9
834
835/*
836 * DMA Address Register LSB
837 */
838#define ED_3COM_DALSB 0x0a
839
840/*
841 * Vector Pointer Register 2
842 */
843#define ED_3COM_VPTR2 0x0b
844
845/*
846 * Vector Pointer Register 1
847 */
848#define ED_3COM_VPTR1 0x0c
849
850/*
851 * Vector Pointer Register 0
852 */
853#define ED_3COM_VPTR0 0x0d
854
855/*
856 * Register File Access MSB
857 */
858#define ED_3COM_RFMSB 0x0e
859
860/*
861 * Register File Access LSB
862 */
863#define ED_3COM_RFLSB 0x0f
864
865/*
866 * Definitions for Novell NE1000/2000 boards
867 */
868
869/*
870 * Board type codes
871 */
872#define ED_TYPE_NE1000 0x01
873#define ED_TYPE_NE2000 0x02
874
875/*
876 * Register offsets/total
877 */
878#define ED_NOVELL_NIC_OFFSET 0x00
879#define ED_NOVELL_ASIC_OFFSET 0x10
880#define ED_NOVELL_IO_PORTS 32
881
882/*
883 * Remote DMA data register; for reading or writing to the NIC mem
884 * via programmed I/O (offset from ASIC base)
885 */
886#define ED_NOVELL_DATA 0x00
887
888/*
889 * Reset register; reading from this register causes a board reset
890 */
891#define ED_NOVELL_RESET 0x0f