1/*
2 * National Semiconductor DS8390 NIC register definitions
3 *
4 * $Id: if_edreg.h,v 1.12 1994/02/02 02:24:42 davidg Exp $
5 *
6 * Modification history
7 *
8 * Revision 2.2 1993/11/29 16:33:39 davidg
9 * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk>
10 * Add support for the 8013W board type
11 *
12 * Revision 2.1 1993/11/22 10:52:33 davidg
13 * patch to add support for SMC8216 (Elite-Ultra) boards
14 * from Glen H. Lowe
15 *
16 * Revision 2.0 93/09/29 00:37:15 davidg
17 * changed double buffering flag to multi buffering
18 * made changes/additions for 3c503 multi-buffering
19 * ...companion to Rev. 2.0 of 'ed' driver.
20 *
21 * Revision 1.1 93/06/23 03:01:07 davidg
22 * Initial revision
23 *
24 */
25
26/*
27 * Page 0 register offsets
28 */
29#define ED_P0_CR 0x00 /* Command Register */
30
31#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
32#define ED_P0_PSTART 0x01 /* Page Start register (write) */
33
34#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
35#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
36
37#define ED_P0_BNRY 0x03 /* Boundary Pointer */
38
39#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
40#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
41
42#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
43#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
44
45#define ED_P0_FIFO 0x06 /* FIFO register (read) */
46#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
47
48#define ED_P0_ISR 0x07 /* Interrupt Status Register */
49
50#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
51#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
52
53#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
54#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
55
56#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
57
58#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
59
60#define ED_P0_RSR 0x0c /* Receive Status (read) */
61#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
62
63#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
64#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
65
66#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
67#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
68
69#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
70#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
71
72/*
73 * Page 1 register offsets
74 */
75#define ED_P1_CR 0x00 /* Command Register */
76#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
77#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
78#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
79#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
80#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
81#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
82#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
83#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
84#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
85#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
86#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
87#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
88#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
89#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
90#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
91
92/*
93 * Page 2 register offsets
94 */
95#define ED_P2_CR 0x00 /* Command Register */
96#define ED_P2_PSTART 0x01 /* Page Start (read) */
97#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
98#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
99#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
100#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
101#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
102#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
103#define ED_P2_ACU 0x06 /* Address Counter Upper */
104#define ED_P2_ACL 0x07 /* Address Counter Lower */
105#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
106#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
107#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
108#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
109
110/*
111 * Command Register (CR) definitions
112 */
113
114/*
115 * STP: SToP. Software reset command. Takes the controller offline. No
116 * packets will be received or transmitted. Any reception or
117 * transmission in progress will continue to completion before
118 * entering reset state. To exit this state, the STP bit must
119 * reset and the STA bit must be set. The software reset has
120 * executed only when indicated by the RST bit in the ISR being
121 * set.
122 */
123#define ED_CR_STP 0x01
124
125/*
126 * STA: STArt. This bit is used to activate the NIC after either power-up,
127 * or when the NIC has been put in reset mode by software command
128 * or error.
129 */
130#define ED_CR_STA 0x02
131
132/*
133 * TXP: Transmit Packet. This bit must be set to indicate transmission of
134 * a packet. TXP is internally reset either after the transmission is
135 * completed or aborted. This bit should be set only after the Transmit
136 * Byte Count and Transmit Page Start register have been programmed.
137 */
138#define ED_CR_TXP 0x04
139
140/*
141 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
142 * of the remote DMA channel. RD2 can be set to abort any remote DMA
143 * command in progress. The Remote Byte Count registers should be cleared
144 * when a remote DMA has been aborted. The Remote Start Addresses are not
145 * restored to the starting address if the remote DMA is aborted.
146 *
147 * RD2 RD1 RD0 function
148 * 0 0 0 not allowed
149 * 0 0 1 remote read
150 * 0 1 0 remote write
151 * 0 1 1 send packet
152 * 1 X X abort
153 */
154#define ED_CR_RD0 0x08
155#define ED_CR_RD1 0x10
156#define ED_CR_RD2 0x20
157
158/*
159 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
160 * access.
161 *
162 * PS1 PS0 page
163 * 0 0 0
164 * 0 1 1
165 * 1 0 2
166 * 1 1 reserved
167 */
168#define ED_CR_PS0 0x40
169#define ED_CR_PS1 0x80
170/* bit encoded aliases */
171#define ED_CR_PAGE_0 0x00 /* (for consistency) */
172#define ED_CR_PAGE_1 0x40
173#define ED_CR_PAGE_2 0x80
174
175/*
176 * Interrupt Status Register (ISR) definitions
177 */
178
179/*
180 * PRX: Packet Received. Indicates packet received with no errors.
181 */
182#define ED_ISR_PRX 0x01
183
184/*
185 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
186 */
187#define ED_ISR_PTX 0x02
188
189/*
190 * RXE: Receive Error. Indicates that a packet was received with one or more
191 * the following errors: CRC error, frame alignment error, FIFO overrun,
192 * missed packet.
193 */
194#define ED_ISR_RXE 0x04
195
196/*
197 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
198 * resulted in one or more of the following errors: excessive
199 * collisions, FIFO underrun.
200 */
201#define ED_ISR_TXE 0x08
202
203/*
204 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
205 * would exceed (has exceeded?) the boundry pointer, resulting in data
206 * that was previously received and not yet read from the buffer to be
207 * overwritten.
208 */
209#define ED_ISR_OVW 0x10
210
211/*
212 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
213 * Counters has been set.
214 */
215#define ED_ISR_CNT 0x20
216
217/*
218 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
219 */
220#define ED_ISR_RDC 0x40
221
222/*
223 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
224 * Start Command is issued to the CR. This bit is also set when a receive
225 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
226 * packets have been removed from the ring. This is a read-only bit.
227 */
228#define ED_ISR_RST 0x80
229
230/*
231 * Interrupt Mask Register (IMR) definitions
232 */
233
234/*
235 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
236 * an interrupt.
237 */
238#define ED_IMR_PRXE 0x01
239
240/*
241 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
242 * a packet transmission completes.
243 */
244#define ED_IMR_PTXE 0x02
245
246/*
247 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
248 * packet is received with an error.
249 */
250#define ED_IMR_RXEE 0x04
251
252/*
253 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
254 * a transmission results in an error.
255 */
256#define ED_IMR_TXEE 0x08
257
258/*
259 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
260 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
261 */
262#define ED_IMR_OVWE 0x10
263
264/*
265 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
266 * the MSB of one or more of the Network Statistics counters has been set.
267 */
268#define ED_IMR_CNTE 0x20
269
270/*
271 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
272 * when a remote DMA transfer has completed.
273 */
274#define ED_IMR_RDCE 0x40
275
276/*
277 * bit 7 is unused/reserved
278 */
279
280/*
281 * Data Configuration Register (DCR) definitions
282 */
283
284/*
285 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
286 * both remote and local DMA transfers
287 */
288#define ED_DCR_WTS 0x01
289
290/*
291 * BOS: Byte Order Select. BOS sets the byte order for the host.
292 * Should be 0 for 80x86, and 1 for 68000 series processors
293 */
294#define ED_DCR_BOS 0x02
295
296/*
297 * LAS: Long Address Select. When LAS is 1, the contents of the remote
298 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
299 */
300#define ED_DCR_LAS 0x04
301
302/*
303 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
304 * of the TCR must also be programmed for loopback operation.
305 * When 1, normal operation is selected.
306 */
307#define ED_DCR_LS 0x08
308
309/*
310 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
311 * under program control. When 1, remote DMA is automatically initiated
312 * and the boundry pointer is automatically updated
313 */
314#define ED_DCR_AR 0x10
315
316/*
317 * FT0, FT1: Fifo Threshold select.
318 * FT1 FT0 Word-width Byte-width
319 * 0 0 1 word 2 bytes
320 * 0 1 2 words 4 bytes
321 * 1 0 4 words 8 bytes
322 * 1 1 8 words 12 bytes
323 *
324 * During transmission, the FIFO threshold indicates the number of bytes
325 * or words that the FIFO has filled from the local DMA before BREQ is
326 * asserted. The transmission threshold is 16 bytes minus the receiver
327 * threshold.
328 */
329#define ED_DCR_FT0 0x20
330#define ED_DCR_FT1 0x40
331
332/*
333 * bit 7 (0x80) is unused/reserved
334 */
335
336/*
337 * Transmit Configuration Register (TCR) definitions
338 */
339
340/*
341 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
342 * is not appended by the transmitter.
343 */
344#define ED_TCR_CRC 0x01
345
346/*
347 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
348 * to be performed.
349 *
350 * LB1 LB0 mode
351 * 0 0 0 - normal operation (DCR_LS = 0)
352 * 0 1 1 - internal loopback (DCR_LS = 0)
353 * 1 0 2 - external loopback (DCR_LS = 1)
354 * 1 1 3 - external loopback (DCR_LS = 0)
355 */
356#define ED_TCR_LB0 0x02
357#define ED_TCR_LB1 0x04
358
359/*
360 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
361 * another station to disable the NIC's transmitter by transmitting to
362 * a multicast address hashing to bit 62. Reception of a multicast address
363 * hashing to bit 63 enables the transmitter.
364 */
365#define ED_TCR_ATD 0x08
366
367/*
368 * OFST: Collision Offset enable. This bit when set modifies the backoff
369 * algorithm to allow prioritization of nodes.
370 */
371#define ED_TCR_OFST 0x10
372
373/*
374 * bits 5, 6, and 7 are unused/reserved
375 */
376
377/*
378 * Transmit Status Register (TSR) definitions
379 */
380
381/*
382 * PTX: Packet Transmitted. Indicates successful transmission of packet.
383 */
384#define ED_TSR_PTX 0x01
385
386/*
387 * bit 1 (0x02) is unused/reserved
388 */
389
390/*
391 * COL: Transmit Collided. Indicates that the transmission collided at least
392 * once with another station on the network.
393 */
394#define ED_TSR_COL 0x04
395
396/*
397 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
398 * excessive collisions.
399 */
400#define ED_TSR_ABT 0x08
401
402/*
403 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
404 * transmission of the packet. (Transmission is not aborted because
405 * of a loss of carrier)
406 */
407#define ED_TSR_CRS 0x10
408
409/*
410 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
411 * transmission memory before the FIFO emptied. Transmission of the
412 * packet was aborted.
413 */
414#define ED_TSR_FU 0x20
415
416/*
417 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
418 * isn't working correctly during a collision heartbeat test.
419 */
420#define ED_TSR_CDH 0x40
421
422/*
423 * OWC: Out of Window Collision: Indicates that a collision occurred after
424 * a slot time (51.2us). The transmission is rescheduled just as in
425 * normal collisions.
426 */
427#define ED_TSR_OWC 0x80
428
429/*
430 * Receiver Configuration Register (RCR) definitions
431 */
432
433/*
434 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
435 * packets with CRC and frame errors are not discarded.
436 */
437#define ED_RCR_SEP 0x01
438
439/*
440 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
441 * If set to 1, packets with less than 64 byte are not discarded.
442 */
443#define ED_RCR_AR 0x02
444
445/*
446 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
447 * accepted.
448 */
449#define ED_RCR_AB 0x04
450
451/*
452 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
453 * for a match in the hashing array. If clear, multicast packets are ignored.
454 */
455#define ED_RCR_AM 0x08
456
457/*
458 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
459 * accepted. If clear, a physical destination address must match this
460 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
461 * must also be set. In addition, the multicast hashing array must be set
462 * to all 1's so that all multicast addresses are accepted.
463 */
464#define ED_RCR_PRO 0x10
465
466/*
467 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
468 * but are not stored in the ring-buffer. If clear, packets are stored (normal
469 * operation).
470 */
471#define ED_RCR_MON 0x20
472
473/*
474 * bits 6 and 7 are unused/reserved.
475 */
476
477/*
478 * Receiver Status Register (RSR) definitions
479 */
480
481/*
482 * PRX: Packet Received without error.
483 */
484#define ED_RSR_PRX 0x01
485
486/*
487 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
488 * alignment errors.
489 */
490#define ED_RSR_CRC 0x02
491
492/*
493 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
494 * a byte boundry and the CRC did not match at the last byte boundry.
495 */
496#define ED_RSR_FAE 0x04
497
498/*
499 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
500 * causing it to overrun. Reception of the packet is aborted.
501 */
502#define ED_RSR_FO 0x08
503
504/*
505 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
506 * the ring-buffer because of insufficient buffer space (exceeding the
507 * boundry pointer), or because the transfer to the ring-buffer was inhibited
508 * by RCR_MON - monitor mode.
509 */
510#define ED_RSR_MPA 0x10
511
512/*
513 * PHY: Physical address. If 0, the packet received was sent to a physical address.
514 * If 1, the packet was accepted because of a multicast/broadcast address
515 * match.
516 */
517#define ED_RSR_PHY 0x20
518
519/*
520 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
521 * mode. Cleared when the receiver exits monitor mode.
522 */
523#define ED_RSR_DIS 0x40
524
525/*
526 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
527 * are active, and the transceiver has set the CD line as a result of the
528 * jabber.
529 */
530#define ED_RSR_DFR 0x80
531
532/*
533 * receive ring discriptor
534 *
535 * The National Semiconductor DS8390 Network interface controller uses
536 * the following receive ring headers. The way this works is that the
537 * memory on the interface card is chopped up into 256 bytes blocks.
538 * A contiguous portion of those blocks are marked for receive packets
539 * by setting start and end block #'s in the NIC. For each packet that
540 * is put into the receive ring, one of these headers (4 bytes each) is
541 * tacked onto the front.
542 */
543struct ed_ring {
544 struct edr_status { /* received packet status */
545 u_char rs_prx:1, /* packet received intack */
546 rs_crc:1, /* crc error */
547 rs_fae:1, /* frame alignment error */
548 rs_fo:1, /* fifo overrun */
549 rs_mpa:1, /* packet received intack */
550 rs_phy:1, /* packet received intack */
551 rs_dis:1, /* packet received intack */
552 rs_dfr:1; /* packet received intack */
553 } ed_rcv_status; /* received packet status */
554 u_char next_packet; /* pointer to next packet */
555 u_short count; /* bytes in packet (length + 4) */
556};
557
558/*
559 * Common constants
560 */
561#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
562#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
563
564/*
565 * Vendor types
566 */
567#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
568#define ED_VENDOR_3COM 0x01 /* 3Com */
569#define ED_VENDOR_NOVELL 0x02 /* Novell */
570
571/*
572 * Compile-time config flags
573 */
574/*
575 * this sets the default for enabling/disablng the tranceiver
576 */
577#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
578
579/*
580 * This forces the board to be used in 8/16bit mode even if it
581 * autoconfigs differently
582 */
583#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
584#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
585
586/*
587 * This disables the use of double transmit buffers.
588 */
589#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
590
591/*
592 * This forces all operations with the NIC memory to use Programmed
593 * I/O (i.e. not via shared memory)
594 */
595#define ED_FLAGS_FORCE_PIO 0x0010
596
597/*
598 * Definitions for Western digital/SMC WD80x3 series ASIC
599 */
600/*
601 * Memory Select Register (MSR)
602 */
603#define ED_WD_MSR 0
604
605#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
606#define ED_WD_MSR_MENB 0x40 /* Memory enable */
607#define ED_WD_MSR_RST 0x80 /* Reset board */
608#ifdef TOSH_ETHER
609#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
610#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
611#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits,
612 1 = 8 bits (R/W) */
613#endif
614
615
616/*
617 * Interface Configuration Register (ICR)
618 */
619#define ED_WD_ICR 1
620
621#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
622#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
623#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
624#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
625#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
626#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
627#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
628#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
629#ifdef TOSH_ETHER
630#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
631#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
632 0x02 = 16K, 0x01 = 8K */
633 /* 64K can only be used if mem address
634 above 1Mb */
635 /* IAR holds address A23-A16 (R/W) */
636#endif
637
638/*
639 * IO Address Register (IAR)
640 */
641#define ED_WD_IAR 2
642
643/*
644 * EEROM Address Register
645 */
646#define ED_WD_EAR 3
647
648/*
649 * Interrupt Request Register (IRR)
650 */
651#define ED_WD_IRR 4
652
653#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
654#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
655#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
656#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
657#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
658
659/*
660 * The three bit of the encoded IRQ are decoded as follows:
661 *
662 * IR2 IR1 IR0 IRQ
663 * 0 0 0 2/9
664 * 0 0 1 3
665 * 0 1 0 5
666 * 0 1 1 7
667 * 1 0 0 10
668 * 1 0 1 11
669 * 1 1 0 15
670 * 1 1 1 4
671 */
672#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
673#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
674#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
675
676/*
677 * LA Address Register (LAAR)
678 */
679#define ED_WD_LAAR 5
680
681#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
682#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
683#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
684#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
685
686/* i/o base offset to station address/card-ID PROM */
687#define ED_WD_PROM 8
688
689/* i/o base offset to CARD ID */
690#define ED_WD_CARD_ID ED_WD_PROM+6
691
692/* Board type codes in card ID */
693#define ED_TYPE_WD8003S 0x02
694#define ED_TYPE_WD8003E 0x03
695#define ED_TYPE_WD8013EBT 0x05
696#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
697#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
698#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */
699#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */
700#define ED_TYPE_WD8003W 0x24
701#define ED_TYPE_WD8003EB 0x25
702#define ED_TYPE_WD8013W 0x26
703#define ED_TYPE_WD8013EP 0x27
704#define ED_TYPE_WD8013WC 0x28
705#define ED_TYPE_WD8013EPC 0x29
706#define ED_TYPE_SMC8216T 0x2a
707#define ED_TYPE_SMC8216C 0x2b
708#define ED_TYPE_WD8013EBP 0x2c
709
710/* Bit definitions in card ID */
711#define ED_WD_REV_MASK 0x1f /* Revision mask */
712#define ED_WD_SOFTCONFIG 0x20 /* Soft config */
713#define ED_WD_LARGERAM 0x40 /* Large RAM */
714#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
715
716/*
717 * Checksum total. All 8 bytes in station address PROM will add up to this
718 */
719#ifdef TOSH_ETHER
720#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5
721#else
722#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
723#endif
724
725#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
726#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
727#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
728
729#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
730
731/*
732 * Definitions for 3Com 3c503
733 */
734#define ED_3COM_NIC_OFFSET 0
735#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
736
737/*
738 * XXX - The I/O address range is fragmented in the 3c503; this is the
739 * number of regs at iobase.
740 */
741#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
742
743/* tx memory starts in second bank on 8bit cards */
744#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20
745
746/* tx memory starts in first bank on 16bit cards */
747#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0
748
749/* ...and rx memory starts in second bank */
750#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20
751
752
753/*
754 * Page Start Register. Must match PSTART in NIC
755 */
756#define ED_3COM_PSTR 0
757
758/*
759 * Page Stop Register. Must match PSTOP in NIC
760 */
761#define ED_3COM_PSPR 1
762
763/*
764 * Drq Timer Register. Determines number of bytes to be transfered during
765 * a DMA burst.
766 */
767#define ED_3COM_DQTR 2
768
769/*
770 * Base Configuration Register. Read-only register which contains the
771 * board-configured I/O base address of the adapter. Bit encoded.
772 */
773#define ED_3COM_BCFR 3
774
775#define ED_3COM_BCFR_2E0 0x01
776#define ED_3COM_BCFR_2A0 0x02
777#define ED_3COM_BCFR_280 0x04
778#define ED_3COM_BCFR_250 0x08
779#define ED_3COM_BCFR_350 0x10
780#define ED_3COM_BCFR_330 0x20
781#define ED_3COM_BCFR_310 0x40
782#define ED_3COM_BCFR_300 0x80
783
784/*
785 * EPROM Configuration Register. Read-only register which contains the
786 * board-configured memory base address. Bit encoded.
787 */
788#define ED_3COM_PCFR 4
789
790#define ED_3COM_PCFR_C8000 0x10
791#define ED_3COM_PCFR_CC000 0x20
792#define ED_3COM_PCFR_D8000 0x40
793#define ED_3COM_PCFR_DC000 0x80
794
795/*
796 * GA Configuration Register. Gate-Array Configuration Register.
797 */
798#define ED_3COM_GACFR 5
799
800/*
801 * mbs2 mbs1 mbs0 start address
802 * 0 0 0 0x0000
803 * 0 0 1 0x2000
804 * 0 1 0 0x4000
805 * 0 1 1 0x6000
806 *
807 * Note that with adapters with only 8K, the setting for 0x2000 must
808 * always be used.
809 */
810#define ED_3COM_GACFR_MBS0 0x01
811#define ED_3COM_GACFR_MBS1 0x02
812#define ED_3COM_GACFR_MBS2 0x04
813
814#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
815#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
816#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
817#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
818#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
819
820/*
821 * Control Register. Miscellaneous control functions.
822 */
823#define ED_3COM_CR 6
824
825#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
826#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
827#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
828#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
829#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
830#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
831#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
832#define ED_3COM_CR_START 0x80 /* Start DMA controller */
833
834/*
835 * Status Register. Miscellaneous status information.
836 */
837#define ED_3COM_STREG 7
838
839#define ED_3COM_STREG_REV 0x07 /* GA revision */
840#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
841#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
842#define ED_3COM_STREG_OFLW 0x20 /* Overflow */
843#define ED_3COM_STREG_UFLW 0x40 /* Underflow */
844#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
845
846/*
847 * Interrupt/DMA Configuration Register
848 */
849#define ED_3COM_IDCFR 8
850
851#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
852#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
853#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
854#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
855#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
856#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
857#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
858#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
859
860/*
861 * DMA Address Register MSB
862 */
863#define ED_3COM_DAMSB 9
864
865/*
866 * DMA Address Register LSB
867 */
868#define ED_3COM_DALSB 0x0a
869
870/*
871 * Vector Pointer Register 2
872 */
873#define ED_3COM_VPTR2 0x0b
874
875/*
876 * Vector Pointer Register 1
877 */
878#define ED_3COM_VPTR1 0x0c
879
880/*
881 * Vector Pointer Register 0
882 */
883#define ED_3COM_VPTR0 0x0d
884
885/*
886 * Register File Access MSB
887 */
888#define ED_3COM_RFMSB 0x0e
889
890/*
891 * Register File Access LSB
892 */
893#define ED_3COM_RFLSB 0x0f
894
895/*
896 * Definitions for Novell NE1000/2000 boards
897 */
898
899/*
900 * Board type codes
901 */
902#define ED_TYPE_NE1000 0x01
903#define ED_TYPE_NE2000 0x02
904
905/*
906 * Register offsets/total
907 */
908#define ED_NOVELL_NIC_OFFSET 0x00
909#define ED_NOVELL_ASIC_OFFSET 0x10
910#define ED_NOVELL_IO_PORTS 32
911
912/*
913 * Remote DMA data register; for reading or writing to the NIC mem
914 * via programmed I/O (offset from ASIC base)
915 */
916#define ED_NOVELL_DATA 0x00
917
918/*
919 * Reset register; reading from this register causes a board reset
920 */
921#define ED_NOVELL_RESET 0x0f
2 * National Semiconductor DS8390 NIC register definitions
3 *
4 * $Id: if_edreg.h,v 1.12 1994/02/02 02:24:42 davidg Exp $
5 *
6 * Modification history
7 *
8 * Revision 2.2 1993/11/29 16:33:39 davidg
9 * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk>
10 * Add support for the 8013W board type
11 *
12 * Revision 2.1 1993/11/22 10:52:33 davidg
13 * patch to add support for SMC8216 (Elite-Ultra) boards
14 * from Glen H. Lowe
15 *
16 * Revision 2.0 93/09/29 00:37:15 davidg
17 * changed double buffering flag to multi buffering
18 * made changes/additions for 3c503 multi-buffering
19 * ...companion to Rev. 2.0 of 'ed' driver.
20 *
21 * Revision 1.1 93/06/23 03:01:07 davidg
22 * Initial revision
23 *
24 */
25
26/*
27 * Page 0 register offsets
28 */
29#define ED_P0_CR 0x00 /* Command Register */
30
31#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
32#define ED_P0_PSTART 0x01 /* Page Start register (write) */
33
34#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
35#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
36
37#define ED_P0_BNRY 0x03 /* Boundary Pointer */
38
39#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
40#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
41
42#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
43#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
44
45#define ED_P0_FIFO 0x06 /* FIFO register (read) */
46#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
47
48#define ED_P0_ISR 0x07 /* Interrupt Status Register */
49
50#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
51#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
52
53#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
54#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
55
56#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
57
58#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
59
60#define ED_P0_RSR 0x0c /* Receive Status (read) */
61#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
62
63#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
64#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
65
66#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
67#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
68
69#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
70#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
71
72/*
73 * Page 1 register offsets
74 */
75#define ED_P1_CR 0x00 /* Command Register */
76#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
77#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
78#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
79#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
80#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
81#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
82#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
83#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
84#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
85#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
86#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
87#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
88#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
89#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
90#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
91
92/*
93 * Page 2 register offsets
94 */
95#define ED_P2_CR 0x00 /* Command Register */
96#define ED_P2_PSTART 0x01 /* Page Start (read) */
97#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
98#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
99#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
100#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
101#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
102#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
103#define ED_P2_ACU 0x06 /* Address Counter Upper */
104#define ED_P2_ACL 0x07 /* Address Counter Lower */
105#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
106#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
107#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
108#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
109
110/*
111 * Command Register (CR) definitions
112 */
113
114/*
115 * STP: SToP. Software reset command. Takes the controller offline. No
116 * packets will be received or transmitted. Any reception or
117 * transmission in progress will continue to completion before
118 * entering reset state. To exit this state, the STP bit must
119 * reset and the STA bit must be set. The software reset has
120 * executed only when indicated by the RST bit in the ISR being
121 * set.
122 */
123#define ED_CR_STP 0x01
124
125/*
126 * STA: STArt. This bit is used to activate the NIC after either power-up,
127 * or when the NIC has been put in reset mode by software command
128 * or error.
129 */
130#define ED_CR_STA 0x02
131
132/*
133 * TXP: Transmit Packet. This bit must be set to indicate transmission of
134 * a packet. TXP is internally reset either after the transmission is
135 * completed or aborted. This bit should be set only after the Transmit
136 * Byte Count and Transmit Page Start register have been programmed.
137 */
138#define ED_CR_TXP 0x04
139
140/*
141 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
142 * of the remote DMA channel. RD2 can be set to abort any remote DMA
143 * command in progress. The Remote Byte Count registers should be cleared
144 * when a remote DMA has been aborted. The Remote Start Addresses are not
145 * restored to the starting address if the remote DMA is aborted.
146 *
147 * RD2 RD1 RD0 function
148 * 0 0 0 not allowed
149 * 0 0 1 remote read
150 * 0 1 0 remote write
151 * 0 1 1 send packet
152 * 1 X X abort
153 */
154#define ED_CR_RD0 0x08
155#define ED_CR_RD1 0x10
156#define ED_CR_RD2 0x20
157
158/*
159 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
160 * access.
161 *
162 * PS1 PS0 page
163 * 0 0 0
164 * 0 1 1
165 * 1 0 2
166 * 1 1 reserved
167 */
168#define ED_CR_PS0 0x40
169#define ED_CR_PS1 0x80
170/* bit encoded aliases */
171#define ED_CR_PAGE_0 0x00 /* (for consistency) */
172#define ED_CR_PAGE_1 0x40
173#define ED_CR_PAGE_2 0x80
174
175/*
176 * Interrupt Status Register (ISR) definitions
177 */
178
179/*
180 * PRX: Packet Received. Indicates packet received with no errors.
181 */
182#define ED_ISR_PRX 0x01
183
184/*
185 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
186 */
187#define ED_ISR_PTX 0x02
188
189/*
190 * RXE: Receive Error. Indicates that a packet was received with one or more
191 * the following errors: CRC error, frame alignment error, FIFO overrun,
192 * missed packet.
193 */
194#define ED_ISR_RXE 0x04
195
196/*
197 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
198 * resulted in one or more of the following errors: excessive
199 * collisions, FIFO underrun.
200 */
201#define ED_ISR_TXE 0x08
202
203/*
204 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
205 * would exceed (has exceeded?) the boundry pointer, resulting in data
206 * that was previously received and not yet read from the buffer to be
207 * overwritten.
208 */
209#define ED_ISR_OVW 0x10
210
211/*
212 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
213 * Counters has been set.
214 */
215#define ED_ISR_CNT 0x20
216
217/*
218 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
219 */
220#define ED_ISR_RDC 0x40
221
222/*
223 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
224 * Start Command is issued to the CR. This bit is also set when a receive
225 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
226 * packets have been removed from the ring. This is a read-only bit.
227 */
228#define ED_ISR_RST 0x80
229
230/*
231 * Interrupt Mask Register (IMR) definitions
232 */
233
234/*
235 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
236 * an interrupt.
237 */
238#define ED_IMR_PRXE 0x01
239
240/*
241 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
242 * a packet transmission completes.
243 */
244#define ED_IMR_PTXE 0x02
245
246/*
247 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
248 * packet is received with an error.
249 */
250#define ED_IMR_RXEE 0x04
251
252/*
253 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
254 * a transmission results in an error.
255 */
256#define ED_IMR_TXEE 0x08
257
258/*
259 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
260 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
261 */
262#define ED_IMR_OVWE 0x10
263
264/*
265 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
266 * the MSB of one or more of the Network Statistics counters has been set.
267 */
268#define ED_IMR_CNTE 0x20
269
270/*
271 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
272 * when a remote DMA transfer has completed.
273 */
274#define ED_IMR_RDCE 0x40
275
276/*
277 * bit 7 is unused/reserved
278 */
279
280/*
281 * Data Configuration Register (DCR) definitions
282 */
283
284/*
285 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
286 * both remote and local DMA transfers
287 */
288#define ED_DCR_WTS 0x01
289
290/*
291 * BOS: Byte Order Select. BOS sets the byte order for the host.
292 * Should be 0 for 80x86, and 1 for 68000 series processors
293 */
294#define ED_DCR_BOS 0x02
295
296/*
297 * LAS: Long Address Select. When LAS is 1, the contents of the remote
298 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
299 */
300#define ED_DCR_LAS 0x04
301
302/*
303 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
304 * of the TCR must also be programmed for loopback operation.
305 * When 1, normal operation is selected.
306 */
307#define ED_DCR_LS 0x08
308
309/*
310 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
311 * under program control. When 1, remote DMA is automatically initiated
312 * and the boundry pointer is automatically updated
313 */
314#define ED_DCR_AR 0x10
315
316/*
317 * FT0, FT1: Fifo Threshold select.
318 * FT1 FT0 Word-width Byte-width
319 * 0 0 1 word 2 bytes
320 * 0 1 2 words 4 bytes
321 * 1 0 4 words 8 bytes
322 * 1 1 8 words 12 bytes
323 *
324 * During transmission, the FIFO threshold indicates the number of bytes
325 * or words that the FIFO has filled from the local DMA before BREQ is
326 * asserted. The transmission threshold is 16 bytes minus the receiver
327 * threshold.
328 */
329#define ED_DCR_FT0 0x20
330#define ED_DCR_FT1 0x40
331
332/*
333 * bit 7 (0x80) is unused/reserved
334 */
335
336/*
337 * Transmit Configuration Register (TCR) definitions
338 */
339
340/*
341 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
342 * is not appended by the transmitter.
343 */
344#define ED_TCR_CRC 0x01
345
346/*
347 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
348 * to be performed.
349 *
350 * LB1 LB0 mode
351 * 0 0 0 - normal operation (DCR_LS = 0)
352 * 0 1 1 - internal loopback (DCR_LS = 0)
353 * 1 0 2 - external loopback (DCR_LS = 1)
354 * 1 1 3 - external loopback (DCR_LS = 0)
355 */
356#define ED_TCR_LB0 0x02
357#define ED_TCR_LB1 0x04
358
359/*
360 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
361 * another station to disable the NIC's transmitter by transmitting to
362 * a multicast address hashing to bit 62. Reception of a multicast address
363 * hashing to bit 63 enables the transmitter.
364 */
365#define ED_TCR_ATD 0x08
366
367/*
368 * OFST: Collision Offset enable. This bit when set modifies the backoff
369 * algorithm to allow prioritization of nodes.
370 */
371#define ED_TCR_OFST 0x10
372
373/*
374 * bits 5, 6, and 7 are unused/reserved
375 */
376
377/*
378 * Transmit Status Register (TSR) definitions
379 */
380
381/*
382 * PTX: Packet Transmitted. Indicates successful transmission of packet.
383 */
384#define ED_TSR_PTX 0x01
385
386/*
387 * bit 1 (0x02) is unused/reserved
388 */
389
390/*
391 * COL: Transmit Collided. Indicates that the transmission collided at least
392 * once with another station on the network.
393 */
394#define ED_TSR_COL 0x04
395
396/*
397 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
398 * excessive collisions.
399 */
400#define ED_TSR_ABT 0x08
401
402/*
403 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
404 * transmission of the packet. (Transmission is not aborted because
405 * of a loss of carrier)
406 */
407#define ED_TSR_CRS 0x10
408
409/*
410 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
411 * transmission memory before the FIFO emptied. Transmission of the
412 * packet was aborted.
413 */
414#define ED_TSR_FU 0x20
415
416/*
417 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
418 * isn't working correctly during a collision heartbeat test.
419 */
420#define ED_TSR_CDH 0x40
421
422/*
423 * OWC: Out of Window Collision: Indicates that a collision occurred after
424 * a slot time (51.2us). The transmission is rescheduled just as in
425 * normal collisions.
426 */
427#define ED_TSR_OWC 0x80
428
429/*
430 * Receiver Configuration Register (RCR) definitions
431 */
432
433/*
434 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
435 * packets with CRC and frame errors are not discarded.
436 */
437#define ED_RCR_SEP 0x01
438
439/*
440 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
441 * If set to 1, packets with less than 64 byte are not discarded.
442 */
443#define ED_RCR_AR 0x02
444
445/*
446 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
447 * accepted.
448 */
449#define ED_RCR_AB 0x04
450
451/*
452 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
453 * for a match in the hashing array. If clear, multicast packets are ignored.
454 */
455#define ED_RCR_AM 0x08
456
457/*
458 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
459 * accepted. If clear, a physical destination address must match this
460 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
461 * must also be set. In addition, the multicast hashing array must be set
462 * to all 1's so that all multicast addresses are accepted.
463 */
464#define ED_RCR_PRO 0x10
465
466/*
467 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
468 * but are not stored in the ring-buffer. If clear, packets are stored (normal
469 * operation).
470 */
471#define ED_RCR_MON 0x20
472
473/*
474 * bits 6 and 7 are unused/reserved.
475 */
476
477/*
478 * Receiver Status Register (RSR) definitions
479 */
480
481/*
482 * PRX: Packet Received without error.
483 */
484#define ED_RSR_PRX 0x01
485
486/*
487 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
488 * alignment errors.
489 */
490#define ED_RSR_CRC 0x02
491
492/*
493 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
494 * a byte boundry and the CRC did not match at the last byte boundry.
495 */
496#define ED_RSR_FAE 0x04
497
498/*
499 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
500 * causing it to overrun. Reception of the packet is aborted.
501 */
502#define ED_RSR_FO 0x08
503
504/*
505 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
506 * the ring-buffer because of insufficient buffer space (exceeding the
507 * boundry pointer), or because the transfer to the ring-buffer was inhibited
508 * by RCR_MON - monitor mode.
509 */
510#define ED_RSR_MPA 0x10
511
512/*
513 * PHY: Physical address. If 0, the packet received was sent to a physical address.
514 * If 1, the packet was accepted because of a multicast/broadcast address
515 * match.
516 */
517#define ED_RSR_PHY 0x20
518
519/*
520 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
521 * mode. Cleared when the receiver exits monitor mode.
522 */
523#define ED_RSR_DIS 0x40
524
525/*
526 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
527 * are active, and the transceiver has set the CD line as a result of the
528 * jabber.
529 */
530#define ED_RSR_DFR 0x80
531
532/*
533 * receive ring discriptor
534 *
535 * The National Semiconductor DS8390 Network interface controller uses
536 * the following receive ring headers. The way this works is that the
537 * memory on the interface card is chopped up into 256 bytes blocks.
538 * A contiguous portion of those blocks are marked for receive packets
539 * by setting start and end block #'s in the NIC. For each packet that
540 * is put into the receive ring, one of these headers (4 bytes each) is
541 * tacked onto the front.
542 */
543struct ed_ring {
544 struct edr_status { /* received packet status */
545 u_char rs_prx:1, /* packet received intack */
546 rs_crc:1, /* crc error */
547 rs_fae:1, /* frame alignment error */
548 rs_fo:1, /* fifo overrun */
549 rs_mpa:1, /* packet received intack */
550 rs_phy:1, /* packet received intack */
551 rs_dis:1, /* packet received intack */
552 rs_dfr:1; /* packet received intack */
553 } ed_rcv_status; /* received packet status */
554 u_char next_packet; /* pointer to next packet */
555 u_short count; /* bytes in packet (length + 4) */
556};
557
558/*
559 * Common constants
560 */
561#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
562#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
563
564/*
565 * Vendor types
566 */
567#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
568#define ED_VENDOR_3COM 0x01 /* 3Com */
569#define ED_VENDOR_NOVELL 0x02 /* Novell */
570
571/*
572 * Compile-time config flags
573 */
574/*
575 * this sets the default for enabling/disablng the tranceiver
576 */
577#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
578
579/*
580 * This forces the board to be used in 8/16bit mode even if it
581 * autoconfigs differently
582 */
583#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
584#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
585
586/*
587 * This disables the use of double transmit buffers.
588 */
589#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
590
591/*
592 * This forces all operations with the NIC memory to use Programmed
593 * I/O (i.e. not via shared memory)
594 */
595#define ED_FLAGS_FORCE_PIO 0x0010
596
597/*
598 * Definitions for Western digital/SMC WD80x3 series ASIC
599 */
600/*
601 * Memory Select Register (MSR)
602 */
603#define ED_WD_MSR 0
604
605#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
606#define ED_WD_MSR_MENB 0x40 /* Memory enable */
607#define ED_WD_MSR_RST 0x80 /* Reset board */
608#ifdef TOSH_ETHER
609#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
610#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
611#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits,
612 1 = 8 bits (R/W) */
613#endif
614
615
616/*
617 * Interface Configuration Register (ICR)
618 */
619#define ED_WD_ICR 1
620
621#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
622#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
623#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
624#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
625#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
626#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
627#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
628#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
629#ifdef TOSH_ETHER
630#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
631#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
632 0x02 = 16K, 0x01 = 8K */
633 /* 64K can only be used if mem address
634 above 1Mb */
635 /* IAR holds address A23-A16 (R/W) */
636#endif
637
638/*
639 * IO Address Register (IAR)
640 */
641#define ED_WD_IAR 2
642
643/*
644 * EEROM Address Register
645 */
646#define ED_WD_EAR 3
647
648/*
649 * Interrupt Request Register (IRR)
650 */
651#define ED_WD_IRR 4
652
653#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
654#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
655#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
656#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
657#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
658
659/*
660 * The three bit of the encoded IRQ are decoded as follows:
661 *
662 * IR2 IR1 IR0 IRQ
663 * 0 0 0 2/9
664 * 0 0 1 3
665 * 0 1 0 5
666 * 0 1 1 7
667 * 1 0 0 10
668 * 1 0 1 11
669 * 1 1 0 15
670 * 1 1 1 4
671 */
672#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
673#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
674#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
675
676/*
677 * LA Address Register (LAAR)
678 */
679#define ED_WD_LAAR 5
680
681#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
682#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
683#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
684#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
685
686/* i/o base offset to station address/card-ID PROM */
687#define ED_WD_PROM 8
688
689/* i/o base offset to CARD ID */
690#define ED_WD_CARD_ID ED_WD_PROM+6
691
692/* Board type codes in card ID */
693#define ED_TYPE_WD8003S 0x02
694#define ED_TYPE_WD8003E 0x03
695#define ED_TYPE_WD8013EBT 0x05
696#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
697#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
698#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */
699#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */
700#define ED_TYPE_WD8003W 0x24
701#define ED_TYPE_WD8003EB 0x25
702#define ED_TYPE_WD8013W 0x26
703#define ED_TYPE_WD8013EP 0x27
704#define ED_TYPE_WD8013WC 0x28
705#define ED_TYPE_WD8013EPC 0x29
706#define ED_TYPE_SMC8216T 0x2a
707#define ED_TYPE_SMC8216C 0x2b
708#define ED_TYPE_WD8013EBP 0x2c
709
710/* Bit definitions in card ID */
711#define ED_WD_REV_MASK 0x1f /* Revision mask */
712#define ED_WD_SOFTCONFIG 0x20 /* Soft config */
713#define ED_WD_LARGERAM 0x40 /* Large RAM */
714#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
715
716/*
717 * Checksum total. All 8 bytes in station address PROM will add up to this
718 */
719#ifdef TOSH_ETHER
720#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5
721#else
722#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
723#endif
724
725#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
726#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
727#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
728
729#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
730
731/*
732 * Definitions for 3Com 3c503
733 */
734#define ED_3COM_NIC_OFFSET 0
735#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
736
737/*
738 * XXX - The I/O address range is fragmented in the 3c503; this is the
739 * number of regs at iobase.
740 */
741#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
742
743/* tx memory starts in second bank on 8bit cards */
744#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20
745
746/* tx memory starts in first bank on 16bit cards */
747#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0
748
749/* ...and rx memory starts in second bank */
750#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20
751
752
753/*
754 * Page Start Register. Must match PSTART in NIC
755 */
756#define ED_3COM_PSTR 0
757
758/*
759 * Page Stop Register. Must match PSTOP in NIC
760 */
761#define ED_3COM_PSPR 1
762
763/*
764 * Drq Timer Register. Determines number of bytes to be transfered during
765 * a DMA burst.
766 */
767#define ED_3COM_DQTR 2
768
769/*
770 * Base Configuration Register. Read-only register which contains the
771 * board-configured I/O base address of the adapter. Bit encoded.
772 */
773#define ED_3COM_BCFR 3
774
775#define ED_3COM_BCFR_2E0 0x01
776#define ED_3COM_BCFR_2A0 0x02
777#define ED_3COM_BCFR_280 0x04
778#define ED_3COM_BCFR_250 0x08
779#define ED_3COM_BCFR_350 0x10
780#define ED_3COM_BCFR_330 0x20
781#define ED_3COM_BCFR_310 0x40
782#define ED_3COM_BCFR_300 0x80
783
784/*
785 * EPROM Configuration Register. Read-only register which contains the
786 * board-configured memory base address. Bit encoded.
787 */
788#define ED_3COM_PCFR 4
789
790#define ED_3COM_PCFR_C8000 0x10
791#define ED_3COM_PCFR_CC000 0x20
792#define ED_3COM_PCFR_D8000 0x40
793#define ED_3COM_PCFR_DC000 0x80
794
795/*
796 * GA Configuration Register. Gate-Array Configuration Register.
797 */
798#define ED_3COM_GACFR 5
799
800/*
801 * mbs2 mbs1 mbs0 start address
802 * 0 0 0 0x0000
803 * 0 0 1 0x2000
804 * 0 1 0 0x4000
805 * 0 1 1 0x6000
806 *
807 * Note that with adapters with only 8K, the setting for 0x2000 must
808 * always be used.
809 */
810#define ED_3COM_GACFR_MBS0 0x01
811#define ED_3COM_GACFR_MBS1 0x02
812#define ED_3COM_GACFR_MBS2 0x04
813
814#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
815#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
816#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
817#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
818#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
819
820/*
821 * Control Register. Miscellaneous control functions.
822 */
823#define ED_3COM_CR 6
824
825#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
826#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
827#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
828#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
829#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
830#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
831#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
832#define ED_3COM_CR_START 0x80 /* Start DMA controller */
833
834/*
835 * Status Register. Miscellaneous status information.
836 */
837#define ED_3COM_STREG 7
838
839#define ED_3COM_STREG_REV 0x07 /* GA revision */
840#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
841#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
842#define ED_3COM_STREG_OFLW 0x20 /* Overflow */
843#define ED_3COM_STREG_UFLW 0x40 /* Underflow */
844#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
845
846/*
847 * Interrupt/DMA Configuration Register
848 */
849#define ED_3COM_IDCFR 8
850
851#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
852#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
853#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
854#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
855#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
856#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
857#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
858#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
859
860/*
861 * DMA Address Register MSB
862 */
863#define ED_3COM_DAMSB 9
864
865/*
866 * DMA Address Register LSB
867 */
868#define ED_3COM_DALSB 0x0a
869
870/*
871 * Vector Pointer Register 2
872 */
873#define ED_3COM_VPTR2 0x0b
874
875/*
876 * Vector Pointer Register 1
877 */
878#define ED_3COM_VPTR1 0x0c
879
880/*
881 * Vector Pointer Register 0
882 */
883#define ED_3COM_VPTR0 0x0d
884
885/*
886 * Register File Access MSB
887 */
888#define ED_3COM_RFMSB 0x0e
889
890/*
891 * Register File Access LSB
892 */
893#define ED_3COM_RFLSB 0x0f
894
895/*
896 * Definitions for Novell NE1000/2000 boards
897 */
898
899/*
900 * Board type codes
901 */
902#define ED_TYPE_NE1000 0x01
903#define ED_TYPE_NE2000 0x02
904
905/*
906 * Register offsets/total
907 */
908#define ED_NOVELL_NIC_OFFSET 0x00
909#define ED_NOVELL_ASIC_OFFSET 0x10
910#define ED_NOVELL_IO_PORTS 32
911
912/*
913 * Remote DMA data register; for reading or writing to the NIC mem
914 * via programmed I/O (offset from ASIC base)
915 */
916#define ED_NOVELL_DATA 0x00
917
918/*
919 * Reset register; reading from this register causes a board reset
920 */
921#define ED_NOVELL_RESET 0x0f