1/*-
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 154895 2006-01-27 08:25:47Z imp $");
30
31/*
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
34 *
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
38 *
39 */
40
41#include "opt_ed.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/sockio.h>
46#include <sys/mbuf.h>
47#include <sys/kernel.h>
48#include <sys/socket.h>
49#include <sys/syslog.h>
50
51#include <sys/bus.h>
52
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56
57#include <net/ethernet.h>
58#include <net/if.h>
59#include <net/if_arp.h>
60#include <net/if_dl.h>
61#include <net/if_mib.h>
62#include <net/if_media.h>
63#include <net/if_types.h>
64
65#include <net/bpf.h>
66
67#include <dev/ed/if_edreg.h>
68#include <dev/ed/if_edvar.h>
69#include <sys/kdb.h>
70
71devclass_t ed_devclass;
72
73static void ed_init(void *);
74static void ed_init_locked(struct ed_softc *);
75static int ed_ioctl(struct ifnet *, u_long, caddr_t);
76static void ed_start(struct ifnet *);
77static void ed_start_locked(struct ifnet *);
78static void ed_reset(struct ifnet *);
79static void ed_watchdog(struct ifnet *);
80
81static void ed_ds_getmcaf(struct ed_softc *, uint32_t *);
82
83static void ed_get_packet(struct ed_softc *, bus_size_t, u_short);
84static void ed_stop_hw(struct ed_softc *sc);
85
86static __inline void ed_rint(struct ed_softc *);
87static __inline void ed_xmit(struct ed_softc *);
88static __inline void ed_ring_copy(struct ed_softc *, bus_size_t, char *,
89 u_short);
90static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *,
91 bus_size_t);
92
93static void ed_setrcr(struct ed_softc *);
94
95/*
96 * Generic probe routine for testing for the existance of a DS8390.
97 * Must be called after the NIC has just been reset. This routine
98 * works by looking at certain register values that are guaranteed
99 * to be initialized a certain way after power-up or reset. Seems
100 * not to currently work on the 83C690.
101 *
102 * Specifically:
103 *
104 * Register reset bits set bits
105 * Command Register (CR) TXP, STA RD2, STP
106 * Interrupt Status (ISR) RST
107 * Interrupt Mask (IMR) All bits
108 * Data Control (DCR) LAS
109 * Transmit Config. (TCR) LB1, LB0
110 *
111 * We only look at the CR and ISR registers, however, because looking at
112 * the others would require changing register pages (which would be
113 * intrusive if this isn't an 8390).
114 *
115 * Return 1 if 8390 was found, 0 if not.
116 */
117
118int
119ed_probe_generic8390(struct ed_softc *sc)
120{
121 if ((ed_nic_inb(sc, ED_P0_CR) &
122 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
123 (ED_CR_RD2 | ED_CR_STP))
124 return (0);
125 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
126 return (0);
127
128 return (1);
129}
130
131void
132ed_disable_16bit_access(struct ed_softc *sc)
133{
134 /*
135 * Disable 16 bit access to shared memory
136 */
137 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) {
138 if (sc->chip_type == ED_CHIP_TYPE_WD790)
139 ed_asic_outb(sc, ED_WD_MSR, 0x00);
140 ed_asic_outb(sc, ED_WD_LAAR,
141 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
142 }
143}
144
145void
146ed_enable_16bit_access(struct ed_softc *sc)
147{
148 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) {
149 ed_asic_outb(sc, ED_WD_LAAR,
150 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
151 if (sc->chip_type == ED_CHIP_TYPE_WD790)
152 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
153 }
154}
155
156/*
157 * Allocate a port resource with the given resource id.
158 */
159int
160ed_alloc_port(device_t dev, int rid, int size)
161{
162 struct ed_softc *sc = device_get_softc(dev);
163 struct resource *res;
164
165 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
166 0ul, ~0ul, size, RF_ACTIVE);
167 if (res) {
168 sc->port_rid = rid;
169 sc->port_res = res;
170 sc->port_used = size;
171 sc->port_bst = rman_get_bustag(res);
172 sc->port_bsh = rman_get_bushandle(res);
173 return (0);
174 }
175 return (ENOENT);
176}
177
178/*
179 * Allocate a memory resource with the given resource id.
180 */
181int
182ed_alloc_memory(device_t dev, int rid, int size)
183{
184 struct ed_softc *sc = device_get_softc(dev);
185 struct resource *res;
186
187 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
188 0ul, ~0ul, size, RF_ACTIVE);
189 if (res) {
190 sc->mem_rid = rid;
191 sc->mem_res = res;
192 sc->mem_used = size;
193 sc->mem_bst = rman_get_bustag(res);
194 sc->mem_bsh = rman_get_bushandle(res);
195 return (0);
196 }
197 return (ENOENT);
198}
199
200/*
201 * Allocate an irq resource with the given resource id.
202 */
203int
204ed_alloc_irq(device_t dev, int rid, int flags)
205{
206 struct ed_softc *sc = device_get_softc(dev);
207 struct resource *res;
208
209 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | flags);
210 if (res) {
211 sc->irq_rid = rid;
212 sc->irq_res = res;
213 return (0);
214 }
215 return (ENOENT);
216}
217
218/*
219 * Release all resources
220 */
221void
222ed_release_resources(device_t dev)
223{
224 struct ed_softc *sc = device_get_softc(dev);
225
226 if (sc->port_res) {
227 bus_deactivate_resource(dev, SYS_RES_IOPORT,
228 sc->port_rid, sc->port_res);
229 bus_release_resource(dev, SYS_RES_IOPORT,
230 sc->port_rid, sc->port_res);
231 sc->port_res = 0;
232 }
233 if (sc->mem_res) {
234 bus_deactivate_resource(dev, SYS_RES_MEMORY,
235 sc->mem_rid, sc->mem_res);
236 bus_release_resource(dev, SYS_RES_MEMORY,
237 sc->mem_rid, sc->mem_res);
238 sc->mem_res = 0;
239 }
240 if (sc->irq_res) {
241 bus_deactivate_resource(dev, SYS_RES_IRQ,
242 sc->irq_rid, sc->irq_res);
243 bus_release_resource(dev, SYS_RES_IRQ,
244 sc->irq_rid, sc->irq_res);
245 sc->irq_res = 0;
246 }
247 if (sc->ifp)
248 if_free(sc->ifp);
249}
250
251/*
252 * Install interface into kernel networking data structures
253 */
254int
255ed_attach(device_t dev)
256{
257 struct ed_softc *sc = device_get_softc(dev);
258 struct ifnet *ifp;
259
260 sc->dev = dev;
261 ED_LOCK_INIT(sc);
262 ifp = sc->ifp = if_alloc(IFT_ETHER);
263 if (ifp == NULL) {
264 device_printf(dev, "can not if_alloc()\n");
265 ED_LOCK_DESTROY(sc);
266 return (ENOSPC);
267 }
268
269 if (sc->readmem == NULL) {
270 if (sc->mem_shared) {
271 if (sc->isa16bit)
272 sc->readmem = ed_shmem_readmem16;
273 else
274 sc->readmem = ed_shmem_readmem8;
275 } else {
276 sc->readmem = ed_pio_readmem;
277 }
278 }
279
280 callout_init_mtx(&sc->tick_ch, ED_MUTEX(sc), 0);
281 /*
282 * Set interface to stopped condition (reset)
283 */
284 ed_stop_hw(sc);
285
286 /*
287 * Initialize ifnet structure
288 */
289 ifp->if_softc = sc;
290 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
291 ifp->if_start = ed_start;
292 ifp->if_ioctl = ed_ioctl;
293 ifp->if_watchdog = ed_watchdog;
294 ifp->if_init = ed_init;
295 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
296 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
297 IFQ_SET_READY(&ifp->if_snd);
298 ifp->if_linkmib = &sc->mibdata;
299 ifp->if_linkmiblen = sizeof sc->mibdata;
300 /*
301 * XXX - should do a better job.
302 */
303 if (sc->chip_type == ED_CHIP_TYPE_WD790)
304 sc->mibdata.dot3StatsEtherChipSet =
305 DOT3CHIPSET(dot3VendorWesternDigital,
306 dot3ChipSetWesternDigital83C790);
307 else
308 sc->mibdata.dot3StatsEtherChipSet =
309 DOT3CHIPSET(dot3VendorNational,
310 dot3ChipSetNational8390);
311 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
312
313 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
314 /*
315 * Set default state for LINK2 flag (used to disable the
316 * tranceiver for AUI operation), based on config option.
317 * We only set this flag before we attach the device, so there's
318 * no race. It is convenient to allow users to turn this off
319 * by default in the kernel config, but given our more advanced
320 * boot time configuration options, this might no longer be needed.
321 */
322 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
323 ifp->if_flags |= IFF_LINK2;
324
325 /*
326 * Attach the interface
327 */
328 ether_ifattach(ifp, sc->enaddr);
329 /* device attach does transition from UNCONFIGURED to IDLE state */
330
331 if (bootverbose || 1) {
332 if (sc->type_str && (*sc->type_str != 0))
333 device_printf(dev, "type %s ", sc->type_str);
334 else
335 device_printf(dev, "type unknown (0x%x) ", sc->type);
336
337#ifdef ED_HPP
338 if (sc->vendor == ED_VENDOR_HP)
339 printf("(%s %s IO)",
340 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
341 "16-bit" : "32-bit",
342 sc->hpp_mem_start ? "memory mapped" : "regular");
343 else
344#endif
345 printf("%s", sc->isa16bit ? "(16 bit)" : "(8 bit)");
346
347#if defined(ED_HPP) || defined(ED_3C503)
348 printf("%s", (((sc->vendor == ED_VENDOR_3COM) ||
349 (sc->vendor == ED_VENDOR_HP)) &&
350 (ifp->if_flags & IFF_LINK2)) ?
351 " tranceiver disabled" : "");
352#endif
353 printf("\n");
354 }
355 return (0);
356}
357
358/*
359 * Detach the driver from the hardware and other systems in the kernel.
360 */
361int
362ed_detach(device_t dev)
363{
364 struct ed_softc *sc = device_get_softc(dev);
365 struct ifnet *ifp = sc->ifp;
366
367 ED_ASSERT_UNLOCKED(sc);
368 ED_LOCK(sc);
369 if (bus_child_present(dev))
370 ed_stop(sc);
371 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
372 ED_UNLOCK(sc);
373 callout_drain(&sc->tick_ch);
374 ether_ifdetach(ifp);
375 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
376 ed_release_resources(dev);
377 ED_LOCK_DESTROY(sc);
378 bus_generic_detach(dev);
379 return (0);
380}
381
382/*
383 * Reset interface.
384 */
385static void
386ed_reset(struct ifnet *ifp)
387{
388 struct ed_softc *sc = ifp->if_softc;
389
390 ED_ASSERT_LOCKED(sc);
391 /*
392 * Stop interface and re-initialize.
393 */
394 ed_stop(sc);
395 ed_init_locked(sc);
396}
397
398static void
399ed_stop_hw(struct ed_softc *sc)
400{
401 int n = 5000;
402
403 /*
404 * Stop everything on the interface, and select page 0 registers.
405 */
406 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
407
408 /*
409 * Wait for interface to enter stopped state, but limit # of checks to
410 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
411 * just in case it's an old one.
412 */
413 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
414 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n)
415 continue;
416}
417
418/*
419 * Take interface offline.
420 */
421void
422ed_stop(struct ed_softc *sc)
423{
424 ED_ASSERT_LOCKED(sc);
425 if (sc->sc_tick)
426 callout_stop(&sc->tick_ch);
427 ed_stop_hw(sc);
428}
429
430/*
431 * Device timeout/watchdog routine. Entered if the device neglects to
432 * generate an interrupt after a transmit has been started on it.
433 */
434static void
435ed_watchdog(struct ifnet *ifp)
436{
437 struct ed_softc *sc = ifp->if_softc;
438
439 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
440 ifp->if_oerrors++;
441
442 ED_LOCK(sc);
443 ed_reset(ifp);
444 ED_UNLOCK(sc);
445}
446
447/*
448 * Initialize device.
449 */
450static void
451ed_init(void *xsc)
452{
453 struct ed_softc *sc = xsc;
454
455 ED_ASSERT_UNLOCKED(sc);
456 ED_LOCK(sc);
457 ed_init_locked(sc);
458 ED_UNLOCK(sc);
459}
460
461static void
462ed_init_locked(struct ed_softc *sc)
463{
464 struct ifnet *ifp = sc->ifp;
465 int i;
466
467 ED_ASSERT_LOCKED(sc);
468
469 /*
470 * Initialize the NIC in the exact order outlined in the NS manual.
471 * This init procedure is "mandatory"...don't change what or when
472 * things happen.
473 */
474
475 /* reset transmitter flags */
476 sc->xmit_busy = 0;
477 ifp->if_timer = 0;
478
479 sc->txb_inuse = 0;
480 sc->txb_new = 0;
481 sc->txb_next_tx = 0;
482
483 /* This variable is used below - don't move this assignment */
484 sc->next_packet = sc->rec_page_start + 1;
485
486 /*
487 * Set interface for page 0, Remote DMA complete, Stopped
488 */
489 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
490
491 if (sc->isa16bit)
492 /*
493 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
494 * order=80x86, word-wide DMA xfers,
495 */
496 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
497 else
498 /*
499 * Same as above, but byte-wide DMA xfers
500 */
501 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
502
503 /*
504 * Clear Remote Byte Count Registers
505 */
506 ed_nic_outb(sc, ED_P0_RBCR0, 0);
507 ed_nic_outb(sc, ED_P0_RBCR1, 0);
508
509 /*
510 * For the moment, don't store incoming packets in memory.
511 */
512 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
513
514 /*
515 * Place NIC in internal loopback mode
516 */
517 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
518
519 /*
520 * Initialize transmit/receive (ring-buffer) Page Start
521 */
522 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
523 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
524 /* Set lower bits of byte addressable framing to 0 */
525 if (sc->chip_type == ED_CHIP_TYPE_WD790)
526 ed_nic_outb(sc, 0x09, 0);
527
528 /*
529 * Initialize Receiver (ring-buffer) Page Stop and Boundry
530 */
531 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
532 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
533
534 /*
535 * Clear all interrupts. A '1' in each bit position clears the
536 * corresponding flag.
537 */
538 ed_nic_outb(sc, ED_P0_ISR, 0xff);
539
540 /*
541 * Enable the following interrupts: receive/transmit complete,
542 * receive/transmit error, and Receiver OverWrite.
543 *
544 * Counter overflow and Remote DMA complete are *not* enabled.
545 */
546 ed_nic_outb(sc, ED_P0_IMR,
547 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
548
549 /*
550 * Program Command Register for page 1
551 */
552 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
553
554 /*
555 * Copy out our station address
556 */
557 for (i = 0; i < ETHER_ADDR_LEN; ++i)
558 ed_nic_outb(sc, ED_P1_PAR(i), IF_LLADDR(sc->ifp)[i]);
559
560 /*
561 * Set Current Page pointer to next_packet (initialized above)
562 */
563 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
564
565 /*
566 * Program Receiver Configuration Register and multicast filter. CR is
567 * set to page 0 on return.
568 */
569 ed_setrcr(sc);
570
571 /*
572 * Take interface out of loopback
573 */
574 ed_nic_outb(sc, ED_P0_TCR, 0);
575
576 if (sc->sc_mediachg)
577 sc->sc_mediachg(sc);
578
579 /*
580 * Set 'running' flag, and clear output active flag.
581 */
582 ifp->if_drv_flags |= IFF_DRV_RUNNING;
583 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
584
585 /*
586 * ...and attempt to start output
587 */
588 ed_start_locked(ifp);
589
590 if (sc->sc_tick)
591 callout_reset(&sc->tick_ch, hz, sc->sc_tick, sc);
592}
593
594/*
595 * This routine actually starts the transmission on the interface
596 */
597static __inline void
598ed_xmit(struct ed_softc *sc)
599{
600 struct ifnet *ifp = sc->ifp;
601 unsigned short len;
602
603 len = sc->txb_len[sc->txb_next_tx];
604
605 /*
606 * Set NIC for page 0 register access
607 */
608 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
609
610 /*
611 * Set TX buffer start page
612 */
613 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
614 sc->txb_next_tx * ED_TXBUF_SIZE);
615
616 /*
617 * Set TX length
618 */
619 ed_nic_outb(sc, ED_P0_TBCR0, len);
620 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
621
622 /*
623 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
624 */
625 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
626 sc->xmit_busy = 1;
627
628 /*
629 * Point to next transmit buffer slot and wrap if necessary.
630 */
631 sc->txb_next_tx++;
632 if (sc->txb_next_tx == sc->txb_cnt)
633 sc->txb_next_tx = 0;
634
635 /*
636 * Set a timer just in case we never hear from the board again
637 */
638 ifp->if_timer = 2;
639}
640
641/*
642 * Start output on interface.
643 * We make two assumptions here:
644 * 1) that the current priority is set to splimp _before_ this code
645 * is called *and* is returned to the appropriate priority after
646 * return
647 * 2) that the IFF_DRV_OACTIVE flag is checked before this code is called
648 * (i.e. that the output part of the interface is idle)
649 */
650static void
651ed_start(struct ifnet *ifp)
652{
653 struct ed_softc *sc = ifp->if_softc;
654
655 ED_ASSERT_UNLOCKED(sc);
656 ED_LOCK(sc);
657 ed_start_locked(ifp);
658 ED_UNLOCK(sc);
659}
660
661static void
662ed_start_locked(struct ifnet *ifp)
663{
664 struct ed_softc *sc = ifp->if_softc;
665 struct mbuf *m0, *m;
666 bus_size_t buffer;
667 int len;
668
669 ED_ASSERT_LOCKED(sc);
670outloop:
671
672 /*
673 * First, see if there are buffered packets and an idle transmitter -
674 * should never happen at this point.
675 */
676 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
677 printf("ed: packets buffered, but transmitter idle\n");
678 ed_xmit(sc);
679 }
680
681 /*
682 * See if there is room to put another packet in the buffer.
683 */
684 if (sc->txb_inuse == sc->txb_cnt) {
685
686 /*
687 * No room. Indicate this to the outside world and exit.
688 */
689 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
690 return;
691 }
692 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
693 if (m == 0) {
694
695 /*
696 * We are using the !OACTIVE flag to indicate to the outside
697 * world that we can accept an additional packet rather than
698 * that the transmitter is _actually_ active. Indeed, the
699 * transmitter may be active, but if we haven't filled all the
700 * buffers with data then we still want to accept more.
701 */
702 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
703 return;
704 }
705
706 /*
707 * Copy the mbuf chain into the transmit buffer
708 */
709 m0 = m;
710
711 /* txb_new points to next open buffer slot */
712 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
713
714 if (sc->mem_shared) {
715 /*
716 * Special case setup for 16 bit boards...
717 */
718 if (sc->isa16bit) {
719 switch (sc->vendor) {
720#ifdef ED_3C503
721 /*
722 * For 16bit 3Com boards (which have 16k of
723 * memory), we have the xmit buffers in a
724 * different page of memory ('page 0') - so
725 * change pages.
726 */
727 case ED_VENDOR_3COM:
728 ed_asic_outb(sc, ED_3COM_GACFR,
729 ED_3COM_GACFR_RSEL);
730 break;
731#endif
732 /*
733 * Enable 16bit access to shared memory on
734 * WD/SMC boards.
735 *
736 * XXX - same as ed_enable_16bit_access()
737 */
738 case ED_VENDOR_WD_SMC:
739 ed_asic_outb(sc, ED_WD_LAAR,
740 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
741 if (sc->chip_type == ED_CHIP_TYPE_WD790)
742 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
743 break;
744 }
745 }
746 for (len = 0; m != 0; m = m->m_next) {
747 if (sc->isa16bit)
748 bus_space_write_region_2(sc->mem_bst,
749 sc->mem_bsh, buffer,
750 mtod(m, uint16_t *), (m->m_len + 1)/ 2);
751 else
752 bus_space_write_region_1(sc->mem_bst,
753 sc->mem_bsh, buffer,
754 mtod(m, uint8_t *), m->m_len);
755 buffer += m->m_len;
756 len += m->m_len;
757 }
758
759 /*
760 * Restore previous shared memory access
761 */
762 if (sc->isa16bit) {
763 switch (sc->vendor) {
764#ifdef ED_3C503
765 case ED_VENDOR_3COM:
766 ed_asic_outb(sc, ED_3COM_GACFR,
767 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
768 break;
769#endif
770 case ED_VENDOR_WD_SMC:
771 /* XXX - same as ed_disable_16bit_access() */
772 if (sc->chip_type == ED_CHIP_TYPE_WD790)
773 ed_asic_outb(sc, ED_WD_MSR, 0x00);
774 ed_asic_outb(sc, ED_WD_LAAR,
775 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
776 break;
777 }
778 }
779 } else {
780 len = ed_pio_write_mbufs(sc, m, buffer);
781 if (len == 0) {
782 m_freem(m0);
783 goto outloop;
784 }
785 }
786
787 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
788
789 sc->txb_inuse++;
790
791 /*
792 * Point to next buffer slot and wrap if necessary.
793 */
794 sc->txb_new++;
795 if (sc->txb_new == sc->txb_cnt)
796 sc->txb_new = 0;
797
798 if (sc->xmit_busy == 0)
799 ed_xmit(sc);
800
801 /*
802 * Tap off here if there is a bpf listener.
803 */
804 BPF_MTAP(ifp, m0);
805
806 m_freem(m0);
807
808 /*
809 * Loop back to the top to possibly buffer more packets
810 */
811 goto outloop;
812}
813
814/*
815 * Ethernet interface receiver interrupt.
816 */
817static __inline void
818ed_rint(struct ed_softc *sc)
819{
820 struct ifnet *ifp = sc->ifp;
821 u_char boundry;
822 u_short len;
823 struct ed_ring packet_hdr;
824 bus_size_t packet_ptr;
825
826 ED_ASSERT_LOCKED(sc);
827
828 /*
829 * Set NIC to page 1 registers to get 'current' pointer
830 */
831 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
832
833 /*
834 * 'sc->next_packet' is the logical beginning of the ring-buffer -
835 * i.e. it points to where new data has been buffered. The 'CURR'
836 * (current) register points to the logical end of the ring-buffer -
837 * i.e. it points to where additional new data will be added. We loop
838 * here until the logical beginning equals the logical end (or in
839 * other words, until the ring-buffer is empty).
840 */
841 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
842
843 /* get pointer to this buffer's header structure */
844 packet_ptr = sc->mem_ring +
845 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
846
847 /*
848 * The byte count includes a 4 byte header that was added by
849 * the NIC.
850 */
851 sc->readmem(sc, packet_ptr, (char *) &packet_hdr,
852 sizeof(packet_hdr));
853 len = packet_hdr.count;
854 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
855 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
856 /*
857 * Length is a wild value. There's a good chance that
858 * this was caused by the NIC being old and buggy.
859 * The bug is that the length low byte is duplicated in
860 * the high byte. Try to recalculate the length based on
861 * the pointer to the next packet.
862 */
863 /*
864 * NOTE: sc->next_packet is pointing at the current packet.
865 */
866 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
867 if (packet_hdr.next_packet >= sc->next_packet)
868 len += (packet_hdr.next_packet -
869 sc->next_packet) * ED_PAGE_SIZE;
870 else
871 len +=
872 ((packet_hdr.next_packet - sc->rec_page_start) +
873 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
874 /*
875 * because buffers are aligned on 256-byte boundary,
876 * the length computed above is off by 256 in almost
877 * all cases. Fix it...
878 */
879 if (len & 0xff)
880 len -= 256;
881 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
882 + sizeof(struct ed_ring)))
883 sc->mibdata.dot3StatsFrameTooLongs++;
884 }
885
886 /*
887 * Be fairly liberal about what we allow as a "reasonable" length
888 * so that a [crufty] packet will make it to BPF (and can thus
889 * be analyzed). Note that all that is really important is that
890 * we have a length that will fit into one mbuf cluster or less;
891 * the upper layer protocols can then figure out the length from
892 * their own length field(s).
893 * But make sure that we have at least a full ethernet header
894 * or we would be unable to call ether_input() later.
895 */
896 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
897 (len <= MCLBYTES) &&
898 (packet_hdr.next_packet >= sc->rec_page_start) &&
899 (packet_hdr.next_packet < sc->rec_page_stop)) {
900 /*
901 * Go get packet.
902 */
903 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
904 len - sizeof(struct ed_ring));
905 ifp->if_ipackets++;
906 } else {
907 /*
908 * Really BAD. The ring pointers are corrupted.
909 */
910 log(LOG_ERR,
911 "%s: NIC memory corrupt - invalid packet length %d\n",
912 ifp->if_xname, len);
913 ifp->if_ierrors++;
914 ed_reset(ifp);
915 return;
916 }
917
918 /*
919 * Update next packet pointer
920 */
921 sc->next_packet = packet_hdr.next_packet;
922
923 /*
924 * Update NIC boundry pointer - being careful to keep it one
925 * buffer behind. (as recommended by NS databook)
926 */
927 boundry = sc->next_packet - 1;
928 if (boundry < sc->rec_page_start)
929 boundry = sc->rec_page_stop - 1;
930
931 /*
932 * Set NIC to page 0 registers to update boundry register
933 */
934 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
935 ed_nic_outb(sc, ED_P0_BNRY, boundry);
936
937 /*
938 * Set NIC to page 1 registers before looping to top (prepare
939 * to get 'CURR' current pointer)
940 */
941 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
942 }
943}
944
945/*
946 * Ethernet interface interrupt processor
947 */
948void
949edintr(void *arg)
950{
951 struct ed_softc *sc = (struct ed_softc*) arg;
952 struct ifnet *ifp = sc->ifp;
953 u_char isr;
954 int count;
955
956 ED_LOCK(sc);
957 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
958 ED_UNLOCK(sc);
959 return;
960 }
961 /*
962 * Set NIC to page 0 registers
963 */
964 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
965
966 /*
967 * loop until there are no more new interrupts. When the card
968 * goes away, the hardware will read back 0xff. Looking at
969 * the interrupts, it would appear that 0xff is impossible,
970 * or at least extremely unlikely.
971 */
972 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
973
974 /*
975 * reset all the bits that we are 'acknowledging' by writing a
976 * '1' to each bit position that was set (writing a '1'
977 * *clears* the bit)
978 */
979 ed_nic_outb(sc, ED_P0_ISR, isr);
980
981 /*
982 * XXX workaround for AX88190
983 * We limit this to 5000 iterations. At 1us per inb/outb,
984 * this translates to about 15ms, which should be plenty
985 * of time, and also gives protection in the card eject
986 * case.
987 */
988 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
989 count = 5000; /* 15ms */
990 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
991 ed_nic_outb(sc, ED_P0_ISR,0);
992 ed_nic_outb(sc, ED_P0_ISR,isr);
993 }
994 if (count == 0)
995 break;
996 }
997
998 /*
999 * Handle transmitter interrupts. Handle these first because
1000 * the receiver will reset the board under some conditions.
1001 */
1002 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
1003 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
1004
1005 /*
1006 * Check for transmit error. If a TX completed with an
1007 * error, we end up throwing the packet away. Really
1008 * the only error that is possible is excessive
1009 * collisions, and in this case it is best to allow
1010 * the automatic mechanisms of TCP to backoff the
1011 * flow. Of course, with UDP we're screwed, but this
1012 * is expected when a network is heavily loaded.
1013 */
1014 (void) ed_nic_inb(sc, ED_P0_TSR);
1015 if (isr & ED_ISR_TXE) {
1016 u_char tsr;
1017
1018 /*
1019 * Excessive collisions (16)
1020 */
1021 tsr = ed_nic_inb(sc, ED_P0_TSR);
1022 if ((tsr & ED_TSR_ABT)
1023 && (collisions == 0)) {
1024
1025 /*
1026 * When collisions total 16, the
1027 * P0_NCR will indicate 0, and the
1028 * TSR_ABT is set.
1029 */
1030 collisions = 16;
1031 sc->mibdata.dot3StatsExcessiveCollisions++;
1032 sc->mibdata.dot3StatsCollFrequencies[15]++;
1033 }
1034 if (tsr & ED_TSR_OWC)
1035 sc->mibdata.dot3StatsLateCollisions++;
1036 if (tsr & ED_TSR_CDH)
1037 sc->mibdata.dot3StatsSQETestErrors++;
1038 if (tsr & ED_TSR_CRS)
1039 sc->mibdata.dot3StatsCarrierSenseErrors++;
1040 if (tsr & ED_TSR_FU)
1041 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
1042
1043 /*
1044 * update output errors counter
1045 */
1046 ifp->if_oerrors++;
1047 } else {
1048
1049 /*
1050 * Update total number of successfully
1051 * transmitted packets.
1052 */
1053 ifp->if_opackets++;
1054 }
1055
1056 /*
1057 * reset tx busy and output active flags
1058 */
1059 sc->xmit_busy = 0;
1060 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1061
1062 /*
1063 * clear watchdog timer
1064 */
1065 ifp->if_timer = 0;
1066
1067 /*
1068 * Add in total number of collisions on last
1069 * transmission.
1070 */
1071 ifp->if_collisions += collisions;
1072 switch(collisions) {
1073 case 0:
1074 case 16:
1075 break;
1076 case 1:
1077 sc->mibdata.dot3StatsSingleCollisionFrames++;
1078 sc->mibdata.dot3StatsCollFrequencies[0]++;
1079 break;
1080 default:
1081 sc->mibdata.dot3StatsMultipleCollisionFrames++;
1082 sc->mibdata.
1083 dot3StatsCollFrequencies[collisions-1]
1084 ++;
1085 break;
1086 }
1087
1088 /*
1089 * Decrement buffer in-use count if not zero (can only
1090 * be zero if a transmitter interrupt occured while
1091 * not actually transmitting). If data is ready to
1092 * transmit, start it transmitting, otherwise defer
1093 * until after handling receiver
1094 */
1095 if (sc->txb_inuse && --sc->txb_inuse)
1096 ed_xmit(sc);
1097 }
1098
1099 /*
1100 * Handle receiver interrupts
1101 */
1102 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
1103
1104 /*
1105 * Overwrite warning. In order to make sure that a
1106 * lockup of the local DMA hasn't occurred, we reset
1107 * and re-init the NIC. The NSC manual suggests only a
1108 * partial reset/re-init is necessary - but some chips
1109 * seem to want more. The DMA lockup has been seen
1110 * only with early rev chips - Methinks this bug was
1111 * fixed in later revs. -DG
1112 */
1113 if (isr & ED_ISR_OVW) {
1114 ifp->if_ierrors++;
1115#ifdef DIAGNOSTIC
1116 log(LOG_WARNING,
1117 "%s: warning - receiver ring buffer overrun\n",
1118 ifp->if_xname);
1119#endif
1120
1121 /*
1122 * Stop/reset/re-init NIC
1123 */
1124 ed_reset(ifp);
1125 } else {
1126
1127 /*
1128 * Receiver Error. One or more of: CRC error,
1129 * frame alignment error FIFO overrun, or
1130 * missed packet.
1131 */
1132 if (isr & ED_ISR_RXE) {
1133 u_char rsr;
1134 rsr = ed_nic_inb(sc, ED_P0_RSR);
1135 if (rsr & ED_RSR_CRC)
1136 sc->mibdata.dot3StatsFCSErrors++;
1137 if (rsr & ED_RSR_FAE)
1138 sc->mibdata.dot3StatsAlignmentErrors++;
1139 if (rsr & ED_RSR_FO)
1140 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
1141 ifp->if_ierrors++;
1142#ifdef ED_DEBUG
1143 if_printf(ifp, "receive error %x\n",
1144 ed_nic_inb(sc, ED_P0_RSR));
1145#endif
1146 }
1147
1148 /*
1149 * Go get the packet(s) XXX - Doing this on an
1150 * error is dubious because there shouldn't be
1151 * any data to get (we've configured the
1152 * interface to not accept packets with
1153 * errors).
1154 */
1155
1156 /*
1157 * Enable 16bit access to shared memory first
1158 * on WD/SMC boards.
1159 */
1160 ed_enable_16bit_access(sc);
1161 ed_rint(sc);
1162 ed_disable_16bit_access(sc);
1163 }
1164 }
1165
1166 /*
1167 * If it looks like the transmitter can take more data,
1168 * attempt to start output on the interface. This is done
1169 * after handling the receiver to give the receiver priority.
1170 */
1171 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
1172 ed_start_locked(ifp);
1173
1174 /*
1175 * return NIC CR to standard state: page 0, remote DMA
1176 * complete, start (toggling the TXP bit off, even if was just
1177 * set in the transmit routine, is *okay* - it is 'edge'
1178 * triggered from low to high)
1179 */
1180 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1181
1182 /*
1183 * If the Network Talley Counters overflow, read them to reset
1184 * them. It appears that old 8390's won't clear the ISR flag
1185 * otherwise - resulting in an infinite loop.
1186 */
1187 if (isr & ED_ISR_CNT) {
1188 (void) ed_nic_inb(sc, ED_P0_CNTR0);
1189 (void) ed_nic_inb(sc, ED_P0_CNTR1);
1190 (void) ed_nic_inb(sc, ED_P0_CNTR2);
1191 }
1192 }
1193 ED_UNLOCK(sc);
1194}
1195
1196/*
1197 * Process an ioctl request.
1198 */
1199static int
1200ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1201{
1202 struct ed_softc *sc = ifp->if_softc;
1203 struct ifreq *ifr = (struct ifreq *)data;
1204 int error = 0;
1205
1206 /*
1207 * XXX really needed?
1208 */
1209 if (sc == NULL) {
1210 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1211 return (ENXIO);
1212 }
1213
1214 switch (command) {
1215 case SIOCSIFFLAGS:
1216 /*
1217 * If the interface is marked up and stopped, then start it.
1218 * If we're up and already running, then it may be a mediachg.
1219 * If it is marked down and running, then stop it.
1220 */
1221 ED_LOCK(sc);
1222 if (ifp->if_flags & IFF_UP) {
1223 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1224 ed_init_locked(sc);
1225 else if (sc->sc_mediachg)
1226 sc->sc_mediachg(sc);
1227 } else {
1228 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1229 ed_stop(sc);
1230 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1231 }
1232 }
1233
1234 /*
1235 * Promiscuous flag may have changed, so reprogram the RCR.
1236 */
1237 ed_setrcr(sc);
1238
1239 ED_UNLOCK(sc);
1240 break;
1241
1242 case SIOCADDMULTI:
1243 case SIOCDELMULTI:
1244 /*
1245 * Multicast list has changed; set the hardware filter
1246 * accordingly.
1247 */
1248 ED_LOCK(sc);
1249 ed_setrcr(sc);
1250 ED_UNLOCK(sc);
1251 error = 0;
1252 break;
1253
1254 case SIOCGIFMEDIA:
1255 case SIOCSIFMEDIA:
1256 if (sc->sc_media_ioctl == NULL) {
1257 error = EINVAL;
1258 break;
1259 }
1260 sc->sc_media_ioctl(sc, ifr, command);
1261 break;
1262
1263 default:
1264 error = ether_ioctl(ifp, command, data);
1265 break;
1266 }
1267 return (error);
1268}
1269
1270/*
1271 * Given a source and destination address, copy 'amount' of a packet from
1272 * the ring buffer into a linear destination buffer. Takes into account
1273 * ring-wrap.
1274 */
1275static __inline void
1276ed_ring_copy(struct ed_softc *sc, bus_size_t src, char *dst, u_short amount)
1277{
1278 u_short tmp_amount;
1279
1280 /* does copy wrap to lower addr in ring buffer? */
1281 if (src + amount > sc->mem_end) {
1282 tmp_amount = sc->mem_end - src;
1283 /* copy amount up to end of NIC memory */
1284 sc->readmem(sc, src, dst, tmp_amount);
1285 amount -= tmp_amount;
1286 src = sc->mem_ring;
1287 dst += tmp_amount;
1288 }
1289 sc->readmem(sc, src, dst, amount);
1290}
1291
1292/*
1293 * Retreive packet from shared memory and send to the next level up via
1294 * ether_input().
1295 */
1296static void
1297ed_get_packet(struct ed_softc *sc, bus_size_t buf, u_short len)
1298{
1299 struct ifnet *ifp = sc->ifp;
1300 struct ether_header *eh;
1301 struct mbuf *m;
1302
1303 /* Allocate a header mbuf */
1304 MGETHDR(m, M_DONTWAIT, MT_DATA);
1305 if (m == NULL)
1306 return;
1307 m->m_pkthdr.rcvif = ifp;
1308 m->m_pkthdr.len = m->m_len = len;
1309
1310 /*
1311 * We always put the received packet in a single buffer -
1312 * either with just an mbuf header or in a cluster attached
1313 * to the header. The +2 is to compensate for the alignment
1314 * fixup below.
1315 */
1316 if ((len + 2) > MHLEN) {
1317 /* Attach an mbuf cluster */
1318 MCLGET(m, M_DONTWAIT);
1319
1320 /* Insist on getting a cluster */
1321 if ((m->m_flags & M_EXT) == 0) {
1322 m_freem(m);
1323 return;
1324 }
1325 }
1326
1327 /*
1328 * The +2 is to longword align the start of the real packet.
1329 * This is important for NFS.
1330 */
1331 m->m_data += 2;
1332 eh = mtod(m, struct ether_header *);
1333
1334 /*
1335 * Get packet, including link layer address, from interface.
1336 */
1337 ed_ring_copy(sc, buf, (char *)eh, len);
1338
1339 m->m_pkthdr.len = m->m_len = len;
1340
1341 ED_UNLOCK(sc);
1342 (*ifp->if_input)(ifp, m);
1343 ED_LOCK(sc);
1344}
1345
1346/*
1347 * Supporting routines
1348 */
1349
1350/*
1351 * Given a NIC memory source address and a host memory destination
1352 * address, copy 'amount' from NIC to host using shared memory.
1353 * The 'amount' is rounded up to a word - okay as long as mbufs
1354 * are word sized. That's what the +1 is below.
1355 * This routine accesses things as 16 bit quantities.
1356 */
1357void
1358ed_shmem_readmem16(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1359 uint16_t amount)
1360{
1361 bus_space_read_region_2(sc->mem_bst, sc->mem_bsh, src, (uint16_t *)dst,
1362 amount + 1 / 2);
1363}
1364
1365/*
1366 * Given a NIC memory source address and a host memory destination
1367 * address, copy 'amount' from NIC to host using shared memory.
1368 * This routine accesses things as 8 bit quantities.
1369 */
1370void
1371ed_shmem_readmem8(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1372 uint16_t amount)
1373{
1374 bus_space_read_region_1(sc->mem_bst, sc->mem_bsh, src, dst, amount);
1375}
1376
1377/*
1378 * Given a NIC memory source address and a host memory destination
1379 * address, copy 'amount' from NIC to host using Programmed I/O.
1380 * The 'amount' is rounded up to a word - okay as long as mbufs
1381 * are word sized.
1382 * This routine is currently Novell-specific.
1383 */
1384void
1385ed_pio_readmem(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1386 uint16_t amount)
1387{
1388 /* Regular Novell cards */
1389 /* select page 0 registers */
1390 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1391
1392 /* round up to a word */
1393 if (amount & 1)
1394 ++amount;
1395
1396 /* set up DMA byte count */
1397 ed_nic_outb(sc, ED_P0_RBCR0, amount);
1398 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
1399
1400 /* set up source address in NIC mem */
1401 ed_nic_outb(sc, ED_P0_RSAR0, src);
1402 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
1403
1404 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
1405
1406 if (sc->isa16bit)
1407 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
1408 else
1409 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
1410}
1411
1412/*
1413 * Stripped down routine for writing a linear buffer to NIC memory.
1414 * Only used in the probe routine to test the memory. 'len' must
1415 * be even.
1416 */
1417void
1418ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len)
1419{
1420 int maxwait = 200; /* about 240us */
1421
1422 /* select page 0 registers */
1423 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1424
1425 /* reset remote DMA complete flag */
1426 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1427
1428 /* set up DMA byte count */
1429 ed_nic_outb(sc, ED_P0_RBCR0, len);
1430 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
1431
1432 /* set up destination address in NIC mem */
1433 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1434 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1435
1436 /* set remote DMA write */
1437 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1438
1439 if (sc->isa16bit)
1440 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
1441 else
1442 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
1443
1444 /*
1445 * Wait for remote DMA complete. This is necessary because on the
1446 * transmit side, data is handled internally by the NIC in bursts and
1447 * we can't start another remote DMA until this one completes. Not
1448 * waiting causes really bad things to happen - like the NIC
1449 * irrecoverably jamming the ISA bus.
1450 */
1451 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
1452 --maxwait)
1453 continue;
1454}
1455
1456/*
1457 * Write an mbuf chain to the destination NIC memory address using
1458 * programmed I/O.
1459 */
1460static u_short
1461ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
1462{
1463 struct ifnet *ifp = sc->ifp;
1464 unsigned short total_len, dma_len;
1465 struct mbuf *mp;
1466 int maxwait = 200; /* about 240us */
1467
1468 ED_ASSERT_LOCKED(sc);
1469
1470#ifdef ED_HPP
1471 /* HP PC Lan+ cards need special handling */
1472 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS)
1473 return ed_hpp_write_mbufs(sc, m, dst);
1474#endif
1475
1476 /* Regular Novell cards */
1477 /* First, count up the total number of bytes to copy */
1478 for (total_len = 0, mp = m; mp; mp = mp->m_next)
1479 total_len += mp->m_len;
1480
1481 dma_len = total_len;
1482 if (sc->isa16bit && (dma_len & 1))
1483 dma_len++;
1484
1485 /* select page 0 registers */
1486 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1487
1488 /* reset remote DMA complete flag */
1489 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1490
1491 /* set up DMA byte count */
1492 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
1493 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
1494
1495 /* set up destination address in NIC mem */
1496 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1497 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1498
1499 /* set remote DMA write */
1500 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1501
1502 /*
1503 * Transfer the mbuf chain to the NIC memory.
1504 * 16-bit cards require that data be transferred as words, and only words.
1505 * So that case requires some extra code to patch over odd-length mbufs.
1506 */
1507
1508 if (!sc->isa16bit) {
1509 /* NE1000s are easy */
1510 while (m) {
1511 if (m->m_len)
1512 ed_asic_outsb(sc, ED_NOVELL_DATA,
1513 m->m_data, m->m_len);
1514 m = m->m_next;
1515 }
1516 } else {
1517 /* NE2000s are a pain */
1518 unsigned char *data;
1519 int len, wantbyte;
1520 unsigned char savebyte[2];
1521
1522 wantbyte = 0;
1523
1524 while (m) {
1525 len = m->m_len;
1526 if (len) {
1527 data = mtod(m, caddr_t);
1528 /* finish the last word */
1529 if (wantbyte) {
1530 savebyte[1] = *data;
1531 ed_asic_outw(sc, ED_NOVELL_DATA,
1532 *(u_short *)savebyte);
1533 data++;
1534 len--;
1535 wantbyte = 0;
1536 }
1537 /* output contiguous words */
1538 if (len > 1) {
1539 ed_asic_outsw(sc, ED_NOVELL_DATA,
1540 data, len >> 1);
1541 data += len & ~1;
1542 len &= 1;
1543 }
1544 /* save last byte, if necessary */
1545 if (len == 1) {
1546 savebyte[0] = *data;
1547 wantbyte = 1;
1548 }
1549 }
1550 m = m->m_next;
1551 }
1552 /* spit last byte */
1553 if (wantbyte)
1554 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
1555 }
1556
1557 /*
1558 * Wait for remote DMA complete. This is necessary because on the
1559 * transmit side, data is handled internally by the NIC in bursts and
1560 * we can't start another remote DMA until this one completes. Not
1561 * waiting causes really bad things to happen - like the NIC
1562 * irrecoverably jamming the ISA bus.
1563 */
1564 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
1565 --maxwait)
1566 continue;
1567
1568 if (!maxwait) {
1569 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
1570 ifp->if_xname);
1571 ed_reset(ifp);
1572 return(0);
1573 }
1574 return (total_len);
1575}
1576
1577static void
1578ed_setrcr(struct ed_softc *sc)
1579{
1580 struct ifnet *ifp = sc->ifp;
1581 int i;
1582 u_char reg1;
1583
1584 ED_ASSERT_LOCKED(sc);
1585
1586 /* Bit 6 in AX88190 RCR register must be set. */
1587 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
1588 reg1 = ED_RCR_INTT;
1589 else
1590 reg1 = 0x00;
1591
1592 /* set page 1 registers */
1593 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1594
1595 if (ifp->if_flags & IFF_PROMISC) {
1596
1597 /*
1598 * Reconfigure the multicast filter.
1599 */
1600 for (i = 0; i < 8; i++)
1601 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
1602
1603 /*
1604 * And turn on promiscuous mode. Also enable reception of
1605 * runts and packets with CRC & alignment errors.
1606 */
1607 /* Set page 0 registers */
1608 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1609
1610 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
1611 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
1612 } else {
1613 /* set up multicast addresses and filter modes */
1614 if (ifp->if_flags & IFF_MULTICAST) {
1615 uint32_t mcaf[2];
1616
1617 if (ifp->if_flags & IFF_ALLMULTI) {
1618 mcaf[0] = 0xffffffff;
1619 mcaf[1] = 0xffffffff;
1620 } else
1621 ed_ds_getmcaf(sc, mcaf);
1622
1623 /*
1624 * Set multicast filter on chip.
1625 */
1626 for (i = 0; i < 8; i++)
1627 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
1628
1629 /* Set page 0 registers */
1630 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1631
1632 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
1633 } else {
1634
1635 /*
1636 * Initialize multicast address hashing registers to
1637 * not accept multicasts.
1638 */
1639 for (i = 0; i < 8; ++i)
1640 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
1641
1642 /* Set page 0 registers */
1643 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1644
1645 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
1646 }
1647 }
1648
1649 /*
1650 * Start interface.
1651 */
1652 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1653}
1654
1655/*
1656 * Compute the multicast address filter from the
1657 * list of multicast addresses we need to listen to.
1658 */
1659static void
1660ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf)
1661{
1662 uint32_t index;
1663 u_char *af = (u_char *) mcaf;
1664 struct ifmultiaddr *ifma;
1665
1666 mcaf[0] = 0;
1667 mcaf[1] = 0;
1668
1669 IF_ADDR_LOCK(sc->ifp);
1670 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
1671 if (ifma->ifma_addr->sa_family != AF_LINK)
1672 continue;
1673 index = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1674 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1675 af[index >> 3] |= 1 << (index & 7);
1676 }
1677 IF_ADDR_UNLOCK(sc->ifp);
1678}
1679
1680int
1681ed_isa_mem_ok(device_t dev, u_long pmem, u_int memsize)
1682{
1683 if (pmem < 0xa0000 || pmem + memsize > 0x1000000) {
1684 device_printf(dev, "Invalid ISA memory address range "
1685 "configured: 0x%lx - 0x%lx\n", pmem, pmem + memsize);
1686 return (ENXIO);
1687 }
1688 return (0);
1689}
1690
1691int
1692ed_clear_memory(device_t dev)
1693{
1694 struct ed_softc *sc = device_get_softc(dev);
1695 bus_size_t i;
1696
1697 bus_space_set_region_1(sc->mem_bst, sc->mem_bsh, sc->mem_start,
1698 0, sc->mem_size);
1699
1700 for (i = 0; i < sc->mem_size; i++) {
1701 if (bus_space_read_1(sc->mem_bst, sc->mem_bsh,
1702 sc->mem_start + i)) {
1703 device_printf(dev, "failed to clear shared memory at "
1704 "0x%jx - check configuration\n",
1705 (uintmax_t)rman_get_start(sc->mem_res) + i);
1706 return (ENXIO);
1707 }
1708 }
1709 return (0);
1710}
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 154895 2006-01-27 08:25:47Z imp $");
30
31/*
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
34 *
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
38 *
39 */
40
41#include "opt_ed.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/sockio.h>
46#include <sys/mbuf.h>
47#include <sys/kernel.h>
48#include <sys/socket.h>
49#include <sys/syslog.h>
50
51#include <sys/bus.h>
52
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56
57#include <net/ethernet.h>
58#include <net/if.h>
59#include <net/if_arp.h>
60#include <net/if_dl.h>
61#include <net/if_mib.h>
62#include <net/if_media.h>
63#include <net/if_types.h>
64
65#include <net/bpf.h>
66
67#include <dev/ed/if_edreg.h>
68#include <dev/ed/if_edvar.h>
69#include <sys/kdb.h>
70
71devclass_t ed_devclass;
72
73static void ed_init(void *);
74static void ed_init_locked(struct ed_softc *);
75static int ed_ioctl(struct ifnet *, u_long, caddr_t);
76static void ed_start(struct ifnet *);
77static void ed_start_locked(struct ifnet *);
78static void ed_reset(struct ifnet *);
79static void ed_watchdog(struct ifnet *);
80
81static void ed_ds_getmcaf(struct ed_softc *, uint32_t *);
82
83static void ed_get_packet(struct ed_softc *, bus_size_t, u_short);
84static void ed_stop_hw(struct ed_softc *sc);
85
86static __inline void ed_rint(struct ed_softc *);
87static __inline void ed_xmit(struct ed_softc *);
88static __inline void ed_ring_copy(struct ed_softc *, bus_size_t, char *,
89 u_short);
90static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *,
91 bus_size_t);
92
93static void ed_setrcr(struct ed_softc *);
94
95/*
96 * Generic probe routine for testing for the existance of a DS8390.
97 * Must be called after the NIC has just been reset. This routine
98 * works by looking at certain register values that are guaranteed
99 * to be initialized a certain way after power-up or reset. Seems
100 * not to currently work on the 83C690.
101 *
102 * Specifically:
103 *
104 * Register reset bits set bits
105 * Command Register (CR) TXP, STA RD2, STP
106 * Interrupt Status (ISR) RST
107 * Interrupt Mask (IMR) All bits
108 * Data Control (DCR) LAS
109 * Transmit Config. (TCR) LB1, LB0
110 *
111 * We only look at the CR and ISR registers, however, because looking at
112 * the others would require changing register pages (which would be
113 * intrusive if this isn't an 8390).
114 *
115 * Return 1 if 8390 was found, 0 if not.
116 */
117
118int
119ed_probe_generic8390(struct ed_softc *sc)
120{
121 if ((ed_nic_inb(sc, ED_P0_CR) &
122 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
123 (ED_CR_RD2 | ED_CR_STP))
124 return (0);
125 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
126 return (0);
127
128 return (1);
129}
130
131void
132ed_disable_16bit_access(struct ed_softc *sc)
133{
134 /*
135 * Disable 16 bit access to shared memory
136 */
137 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) {
138 if (sc->chip_type == ED_CHIP_TYPE_WD790)
139 ed_asic_outb(sc, ED_WD_MSR, 0x00);
140 ed_asic_outb(sc, ED_WD_LAAR,
141 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
142 }
143}
144
145void
146ed_enable_16bit_access(struct ed_softc *sc)
147{
148 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) {
149 ed_asic_outb(sc, ED_WD_LAAR,
150 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
151 if (sc->chip_type == ED_CHIP_TYPE_WD790)
152 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
153 }
154}
155
156/*
157 * Allocate a port resource with the given resource id.
158 */
159int
160ed_alloc_port(device_t dev, int rid, int size)
161{
162 struct ed_softc *sc = device_get_softc(dev);
163 struct resource *res;
164
165 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
166 0ul, ~0ul, size, RF_ACTIVE);
167 if (res) {
168 sc->port_rid = rid;
169 sc->port_res = res;
170 sc->port_used = size;
171 sc->port_bst = rman_get_bustag(res);
172 sc->port_bsh = rman_get_bushandle(res);
173 return (0);
174 }
175 return (ENOENT);
176}
177
178/*
179 * Allocate a memory resource with the given resource id.
180 */
181int
182ed_alloc_memory(device_t dev, int rid, int size)
183{
184 struct ed_softc *sc = device_get_softc(dev);
185 struct resource *res;
186
187 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
188 0ul, ~0ul, size, RF_ACTIVE);
189 if (res) {
190 sc->mem_rid = rid;
191 sc->mem_res = res;
192 sc->mem_used = size;
193 sc->mem_bst = rman_get_bustag(res);
194 sc->mem_bsh = rman_get_bushandle(res);
195 return (0);
196 }
197 return (ENOENT);
198}
199
200/*
201 * Allocate an irq resource with the given resource id.
202 */
203int
204ed_alloc_irq(device_t dev, int rid, int flags)
205{
206 struct ed_softc *sc = device_get_softc(dev);
207 struct resource *res;
208
209 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | flags);
210 if (res) {
211 sc->irq_rid = rid;
212 sc->irq_res = res;
213 return (0);
214 }
215 return (ENOENT);
216}
217
218/*
219 * Release all resources
220 */
221void
222ed_release_resources(device_t dev)
223{
224 struct ed_softc *sc = device_get_softc(dev);
225
226 if (sc->port_res) {
227 bus_deactivate_resource(dev, SYS_RES_IOPORT,
228 sc->port_rid, sc->port_res);
229 bus_release_resource(dev, SYS_RES_IOPORT,
230 sc->port_rid, sc->port_res);
231 sc->port_res = 0;
232 }
233 if (sc->mem_res) {
234 bus_deactivate_resource(dev, SYS_RES_MEMORY,
235 sc->mem_rid, sc->mem_res);
236 bus_release_resource(dev, SYS_RES_MEMORY,
237 sc->mem_rid, sc->mem_res);
238 sc->mem_res = 0;
239 }
240 if (sc->irq_res) {
241 bus_deactivate_resource(dev, SYS_RES_IRQ,
242 sc->irq_rid, sc->irq_res);
243 bus_release_resource(dev, SYS_RES_IRQ,
244 sc->irq_rid, sc->irq_res);
245 sc->irq_res = 0;
246 }
247 if (sc->ifp)
248 if_free(sc->ifp);
249}
250
251/*
252 * Install interface into kernel networking data structures
253 */
254int
255ed_attach(device_t dev)
256{
257 struct ed_softc *sc = device_get_softc(dev);
258 struct ifnet *ifp;
259
260 sc->dev = dev;
261 ED_LOCK_INIT(sc);
262 ifp = sc->ifp = if_alloc(IFT_ETHER);
263 if (ifp == NULL) {
264 device_printf(dev, "can not if_alloc()\n");
265 ED_LOCK_DESTROY(sc);
266 return (ENOSPC);
267 }
268
269 if (sc->readmem == NULL) {
270 if (sc->mem_shared) {
271 if (sc->isa16bit)
272 sc->readmem = ed_shmem_readmem16;
273 else
274 sc->readmem = ed_shmem_readmem8;
275 } else {
276 sc->readmem = ed_pio_readmem;
277 }
278 }
279
280 callout_init_mtx(&sc->tick_ch, ED_MUTEX(sc), 0);
281 /*
282 * Set interface to stopped condition (reset)
283 */
284 ed_stop_hw(sc);
285
286 /*
287 * Initialize ifnet structure
288 */
289 ifp->if_softc = sc;
290 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
291 ifp->if_start = ed_start;
292 ifp->if_ioctl = ed_ioctl;
293 ifp->if_watchdog = ed_watchdog;
294 ifp->if_init = ed_init;
295 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
296 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
297 IFQ_SET_READY(&ifp->if_snd);
298 ifp->if_linkmib = &sc->mibdata;
299 ifp->if_linkmiblen = sizeof sc->mibdata;
300 /*
301 * XXX - should do a better job.
302 */
303 if (sc->chip_type == ED_CHIP_TYPE_WD790)
304 sc->mibdata.dot3StatsEtherChipSet =
305 DOT3CHIPSET(dot3VendorWesternDigital,
306 dot3ChipSetWesternDigital83C790);
307 else
308 sc->mibdata.dot3StatsEtherChipSet =
309 DOT3CHIPSET(dot3VendorNational,
310 dot3ChipSetNational8390);
311 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
312
313 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
314 /*
315 * Set default state for LINK2 flag (used to disable the
316 * tranceiver for AUI operation), based on config option.
317 * We only set this flag before we attach the device, so there's
318 * no race. It is convenient to allow users to turn this off
319 * by default in the kernel config, but given our more advanced
320 * boot time configuration options, this might no longer be needed.
321 */
322 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
323 ifp->if_flags |= IFF_LINK2;
324
325 /*
326 * Attach the interface
327 */
328 ether_ifattach(ifp, sc->enaddr);
329 /* device attach does transition from UNCONFIGURED to IDLE state */
330
331 if (bootverbose || 1) {
332 if (sc->type_str && (*sc->type_str != 0))
333 device_printf(dev, "type %s ", sc->type_str);
334 else
335 device_printf(dev, "type unknown (0x%x) ", sc->type);
336
337#ifdef ED_HPP
338 if (sc->vendor == ED_VENDOR_HP)
339 printf("(%s %s IO)",
340 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
341 "16-bit" : "32-bit",
342 sc->hpp_mem_start ? "memory mapped" : "regular");
343 else
344#endif
345 printf("%s", sc->isa16bit ? "(16 bit)" : "(8 bit)");
346
347#if defined(ED_HPP) || defined(ED_3C503)
348 printf("%s", (((sc->vendor == ED_VENDOR_3COM) ||
349 (sc->vendor == ED_VENDOR_HP)) &&
350 (ifp->if_flags & IFF_LINK2)) ?
351 " tranceiver disabled" : "");
352#endif
353 printf("\n");
354 }
355 return (0);
356}
357
358/*
359 * Detach the driver from the hardware and other systems in the kernel.
360 */
361int
362ed_detach(device_t dev)
363{
364 struct ed_softc *sc = device_get_softc(dev);
365 struct ifnet *ifp = sc->ifp;
366
367 ED_ASSERT_UNLOCKED(sc);
368 ED_LOCK(sc);
369 if (bus_child_present(dev))
370 ed_stop(sc);
371 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
372 ED_UNLOCK(sc);
373 callout_drain(&sc->tick_ch);
374 ether_ifdetach(ifp);
375 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
376 ed_release_resources(dev);
377 ED_LOCK_DESTROY(sc);
378 bus_generic_detach(dev);
379 return (0);
380}
381
382/*
383 * Reset interface.
384 */
385static void
386ed_reset(struct ifnet *ifp)
387{
388 struct ed_softc *sc = ifp->if_softc;
389
390 ED_ASSERT_LOCKED(sc);
391 /*
392 * Stop interface and re-initialize.
393 */
394 ed_stop(sc);
395 ed_init_locked(sc);
396}
397
398static void
399ed_stop_hw(struct ed_softc *sc)
400{
401 int n = 5000;
402
403 /*
404 * Stop everything on the interface, and select page 0 registers.
405 */
406 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
407
408 /*
409 * Wait for interface to enter stopped state, but limit # of checks to
410 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
411 * just in case it's an old one.
412 */
413 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
414 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n)
415 continue;
416}
417
418/*
419 * Take interface offline.
420 */
421void
422ed_stop(struct ed_softc *sc)
423{
424 ED_ASSERT_LOCKED(sc);
425 if (sc->sc_tick)
426 callout_stop(&sc->tick_ch);
427 ed_stop_hw(sc);
428}
429
430/*
431 * Device timeout/watchdog routine. Entered if the device neglects to
432 * generate an interrupt after a transmit has been started on it.
433 */
434static void
435ed_watchdog(struct ifnet *ifp)
436{
437 struct ed_softc *sc = ifp->if_softc;
438
439 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
440 ifp->if_oerrors++;
441
442 ED_LOCK(sc);
443 ed_reset(ifp);
444 ED_UNLOCK(sc);
445}
446
447/*
448 * Initialize device.
449 */
450static void
451ed_init(void *xsc)
452{
453 struct ed_softc *sc = xsc;
454
455 ED_ASSERT_UNLOCKED(sc);
456 ED_LOCK(sc);
457 ed_init_locked(sc);
458 ED_UNLOCK(sc);
459}
460
461static void
462ed_init_locked(struct ed_softc *sc)
463{
464 struct ifnet *ifp = sc->ifp;
465 int i;
466
467 ED_ASSERT_LOCKED(sc);
468
469 /*
470 * Initialize the NIC in the exact order outlined in the NS manual.
471 * This init procedure is "mandatory"...don't change what or when
472 * things happen.
473 */
474
475 /* reset transmitter flags */
476 sc->xmit_busy = 0;
477 ifp->if_timer = 0;
478
479 sc->txb_inuse = 0;
480 sc->txb_new = 0;
481 sc->txb_next_tx = 0;
482
483 /* This variable is used below - don't move this assignment */
484 sc->next_packet = sc->rec_page_start + 1;
485
486 /*
487 * Set interface for page 0, Remote DMA complete, Stopped
488 */
489 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
490
491 if (sc->isa16bit)
492 /*
493 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
494 * order=80x86, word-wide DMA xfers,
495 */
496 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
497 else
498 /*
499 * Same as above, but byte-wide DMA xfers
500 */
501 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
502
503 /*
504 * Clear Remote Byte Count Registers
505 */
506 ed_nic_outb(sc, ED_P0_RBCR0, 0);
507 ed_nic_outb(sc, ED_P0_RBCR1, 0);
508
509 /*
510 * For the moment, don't store incoming packets in memory.
511 */
512 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
513
514 /*
515 * Place NIC in internal loopback mode
516 */
517 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
518
519 /*
520 * Initialize transmit/receive (ring-buffer) Page Start
521 */
522 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
523 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
524 /* Set lower bits of byte addressable framing to 0 */
525 if (sc->chip_type == ED_CHIP_TYPE_WD790)
526 ed_nic_outb(sc, 0x09, 0);
527
528 /*
529 * Initialize Receiver (ring-buffer) Page Stop and Boundry
530 */
531 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
532 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
533
534 /*
535 * Clear all interrupts. A '1' in each bit position clears the
536 * corresponding flag.
537 */
538 ed_nic_outb(sc, ED_P0_ISR, 0xff);
539
540 /*
541 * Enable the following interrupts: receive/transmit complete,
542 * receive/transmit error, and Receiver OverWrite.
543 *
544 * Counter overflow and Remote DMA complete are *not* enabled.
545 */
546 ed_nic_outb(sc, ED_P0_IMR,
547 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
548
549 /*
550 * Program Command Register for page 1
551 */
552 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
553
554 /*
555 * Copy out our station address
556 */
557 for (i = 0; i < ETHER_ADDR_LEN; ++i)
558 ed_nic_outb(sc, ED_P1_PAR(i), IF_LLADDR(sc->ifp)[i]);
559
560 /*
561 * Set Current Page pointer to next_packet (initialized above)
562 */
563 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
564
565 /*
566 * Program Receiver Configuration Register and multicast filter. CR is
567 * set to page 0 on return.
568 */
569 ed_setrcr(sc);
570
571 /*
572 * Take interface out of loopback
573 */
574 ed_nic_outb(sc, ED_P0_TCR, 0);
575
576 if (sc->sc_mediachg)
577 sc->sc_mediachg(sc);
578
579 /*
580 * Set 'running' flag, and clear output active flag.
581 */
582 ifp->if_drv_flags |= IFF_DRV_RUNNING;
583 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
584
585 /*
586 * ...and attempt to start output
587 */
588 ed_start_locked(ifp);
589
590 if (sc->sc_tick)
591 callout_reset(&sc->tick_ch, hz, sc->sc_tick, sc);
592}
593
594/*
595 * This routine actually starts the transmission on the interface
596 */
597static __inline void
598ed_xmit(struct ed_softc *sc)
599{
600 struct ifnet *ifp = sc->ifp;
601 unsigned short len;
602
603 len = sc->txb_len[sc->txb_next_tx];
604
605 /*
606 * Set NIC for page 0 register access
607 */
608 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
609
610 /*
611 * Set TX buffer start page
612 */
613 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
614 sc->txb_next_tx * ED_TXBUF_SIZE);
615
616 /*
617 * Set TX length
618 */
619 ed_nic_outb(sc, ED_P0_TBCR0, len);
620 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
621
622 /*
623 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
624 */
625 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
626 sc->xmit_busy = 1;
627
628 /*
629 * Point to next transmit buffer slot and wrap if necessary.
630 */
631 sc->txb_next_tx++;
632 if (sc->txb_next_tx == sc->txb_cnt)
633 sc->txb_next_tx = 0;
634
635 /*
636 * Set a timer just in case we never hear from the board again
637 */
638 ifp->if_timer = 2;
639}
640
641/*
642 * Start output on interface.
643 * We make two assumptions here:
644 * 1) that the current priority is set to splimp _before_ this code
645 * is called *and* is returned to the appropriate priority after
646 * return
647 * 2) that the IFF_DRV_OACTIVE flag is checked before this code is called
648 * (i.e. that the output part of the interface is idle)
649 */
650static void
651ed_start(struct ifnet *ifp)
652{
653 struct ed_softc *sc = ifp->if_softc;
654
655 ED_ASSERT_UNLOCKED(sc);
656 ED_LOCK(sc);
657 ed_start_locked(ifp);
658 ED_UNLOCK(sc);
659}
660
661static void
662ed_start_locked(struct ifnet *ifp)
663{
664 struct ed_softc *sc = ifp->if_softc;
665 struct mbuf *m0, *m;
666 bus_size_t buffer;
667 int len;
668
669 ED_ASSERT_LOCKED(sc);
670outloop:
671
672 /*
673 * First, see if there are buffered packets and an idle transmitter -
674 * should never happen at this point.
675 */
676 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
677 printf("ed: packets buffered, but transmitter idle\n");
678 ed_xmit(sc);
679 }
680
681 /*
682 * See if there is room to put another packet in the buffer.
683 */
684 if (sc->txb_inuse == sc->txb_cnt) {
685
686 /*
687 * No room. Indicate this to the outside world and exit.
688 */
689 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
690 return;
691 }
692 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
693 if (m == 0) {
694
695 /*
696 * We are using the !OACTIVE flag to indicate to the outside
697 * world that we can accept an additional packet rather than
698 * that the transmitter is _actually_ active. Indeed, the
699 * transmitter may be active, but if we haven't filled all the
700 * buffers with data then we still want to accept more.
701 */
702 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
703 return;
704 }
705
706 /*
707 * Copy the mbuf chain into the transmit buffer
708 */
709 m0 = m;
710
711 /* txb_new points to next open buffer slot */
712 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
713
714 if (sc->mem_shared) {
715 /*
716 * Special case setup for 16 bit boards...
717 */
718 if (sc->isa16bit) {
719 switch (sc->vendor) {
720#ifdef ED_3C503
721 /*
722 * For 16bit 3Com boards (which have 16k of
723 * memory), we have the xmit buffers in a
724 * different page of memory ('page 0') - so
725 * change pages.
726 */
727 case ED_VENDOR_3COM:
728 ed_asic_outb(sc, ED_3COM_GACFR,
729 ED_3COM_GACFR_RSEL);
730 break;
731#endif
732 /*
733 * Enable 16bit access to shared memory on
734 * WD/SMC boards.
735 *
736 * XXX - same as ed_enable_16bit_access()
737 */
738 case ED_VENDOR_WD_SMC:
739 ed_asic_outb(sc, ED_WD_LAAR,
740 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
741 if (sc->chip_type == ED_CHIP_TYPE_WD790)
742 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
743 break;
744 }
745 }
746 for (len = 0; m != 0; m = m->m_next) {
747 if (sc->isa16bit)
748 bus_space_write_region_2(sc->mem_bst,
749 sc->mem_bsh, buffer,
750 mtod(m, uint16_t *), (m->m_len + 1)/ 2);
751 else
752 bus_space_write_region_1(sc->mem_bst,
753 sc->mem_bsh, buffer,
754 mtod(m, uint8_t *), m->m_len);
755 buffer += m->m_len;
756 len += m->m_len;
757 }
758
759 /*
760 * Restore previous shared memory access
761 */
762 if (sc->isa16bit) {
763 switch (sc->vendor) {
764#ifdef ED_3C503
765 case ED_VENDOR_3COM:
766 ed_asic_outb(sc, ED_3COM_GACFR,
767 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
768 break;
769#endif
770 case ED_VENDOR_WD_SMC:
771 /* XXX - same as ed_disable_16bit_access() */
772 if (sc->chip_type == ED_CHIP_TYPE_WD790)
773 ed_asic_outb(sc, ED_WD_MSR, 0x00);
774 ed_asic_outb(sc, ED_WD_LAAR,
775 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
776 break;
777 }
778 }
779 } else {
780 len = ed_pio_write_mbufs(sc, m, buffer);
781 if (len == 0) {
782 m_freem(m0);
783 goto outloop;
784 }
785 }
786
787 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
788
789 sc->txb_inuse++;
790
791 /*
792 * Point to next buffer slot and wrap if necessary.
793 */
794 sc->txb_new++;
795 if (sc->txb_new == sc->txb_cnt)
796 sc->txb_new = 0;
797
798 if (sc->xmit_busy == 0)
799 ed_xmit(sc);
800
801 /*
802 * Tap off here if there is a bpf listener.
803 */
804 BPF_MTAP(ifp, m0);
805
806 m_freem(m0);
807
808 /*
809 * Loop back to the top to possibly buffer more packets
810 */
811 goto outloop;
812}
813
814/*
815 * Ethernet interface receiver interrupt.
816 */
817static __inline void
818ed_rint(struct ed_softc *sc)
819{
820 struct ifnet *ifp = sc->ifp;
821 u_char boundry;
822 u_short len;
823 struct ed_ring packet_hdr;
824 bus_size_t packet_ptr;
825
826 ED_ASSERT_LOCKED(sc);
827
828 /*
829 * Set NIC to page 1 registers to get 'current' pointer
830 */
831 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
832
833 /*
834 * 'sc->next_packet' is the logical beginning of the ring-buffer -
835 * i.e. it points to where new data has been buffered. The 'CURR'
836 * (current) register points to the logical end of the ring-buffer -
837 * i.e. it points to where additional new data will be added. We loop
838 * here until the logical beginning equals the logical end (or in
839 * other words, until the ring-buffer is empty).
840 */
841 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
842
843 /* get pointer to this buffer's header structure */
844 packet_ptr = sc->mem_ring +
845 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
846
847 /*
848 * The byte count includes a 4 byte header that was added by
849 * the NIC.
850 */
851 sc->readmem(sc, packet_ptr, (char *) &packet_hdr,
852 sizeof(packet_hdr));
853 len = packet_hdr.count;
854 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
855 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
856 /*
857 * Length is a wild value. There's a good chance that
858 * this was caused by the NIC being old and buggy.
859 * The bug is that the length low byte is duplicated in
860 * the high byte. Try to recalculate the length based on
861 * the pointer to the next packet.
862 */
863 /*
864 * NOTE: sc->next_packet is pointing at the current packet.
865 */
866 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
867 if (packet_hdr.next_packet >= sc->next_packet)
868 len += (packet_hdr.next_packet -
869 sc->next_packet) * ED_PAGE_SIZE;
870 else
871 len +=
872 ((packet_hdr.next_packet - sc->rec_page_start) +
873 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
874 /*
875 * because buffers are aligned on 256-byte boundary,
876 * the length computed above is off by 256 in almost
877 * all cases. Fix it...
878 */
879 if (len & 0xff)
880 len -= 256;
881 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
882 + sizeof(struct ed_ring)))
883 sc->mibdata.dot3StatsFrameTooLongs++;
884 }
885
886 /*
887 * Be fairly liberal about what we allow as a "reasonable" length
888 * so that a [crufty] packet will make it to BPF (and can thus
889 * be analyzed). Note that all that is really important is that
890 * we have a length that will fit into one mbuf cluster or less;
891 * the upper layer protocols can then figure out the length from
892 * their own length field(s).
893 * But make sure that we have at least a full ethernet header
894 * or we would be unable to call ether_input() later.
895 */
896 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
897 (len <= MCLBYTES) &&
898 (packet_hdr.next_packet >= sc->rec_page_start) &&
899 (packet_hdr.next_packet < sc->rec_page_stop)) {
900 /*
901 * Go get packet.
902 */
903 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
904 len - sizeof(struct ed_ring));
905 ifp->if_ipackets++;
906 } else {
907 /*
908 * Really BAD. The ring pointers are corrupted.
909 */
910 log(LOG_ERR,
911 "%s: NIC memory corrupt - invalid packet length %d\n",
912 ifp->if_xname, len);
913 ifp->if_ierrors++;
914 ed_reset(ifp);
915 return;
916 }
917
918 /*
919 * Update next packet pointer
920 */
921 sc->next_packet = packet_hdr.next_packet;
922
923 /*
924 * Update NIC boundry pointer - being careful to keep it one
925 * buffer behind. (as recommended by NS databook)
926 */
927 boundry = sc->next_packet - 1;
928 if (boundry < sc->rec_page_start)
929 boundry = sc->rec_page_stop - 1;
930
931 /*
932 * Set NIC to page 0 registers to update boundry register
933 */
934 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
935 ed_nic_outb(sc, ED_P0_BNRY, boundry);
936
937 /*
938 * Set NIC to page 1 registers before looping to top (prepare
939 * to get 'CURR' current pointer)
940 */
941 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
942 }
943}
944
945/*
946 * Ethernet interface interrupt processor
947 */
948void
949edintr(void *arg)
950{
951 struct ed_softc *sc = (struct ed_softc*) arg;
952 struct ifnet *ifp = sc->ifp;
953 u_char isr;
954 int count;
955
956 ED_LOCK(sc);
957 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
958 ED_UNLOCK(sc);
959 return;
960 }
961 /*
962 * Set NIC to page 0 registers
963 */
964 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
965
966 /*
967 * loop until there are no more new interrupts. When the card
968 * goes away, the hardware will read back 0xff. Looking at
969 * the interrupts, it would appear that 0xff is impossible,
970 * or at least extremely unlikely.
971 */
972 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
973
974 /*
975 * reset all the bits that we are 'acknowledging' by writing a
976 * '1' to each bit position that was set (writing a '1'
977 * *clears* the bit)
978 */
979 ed_nic_outb(sc, ED_P0_ISR, isr);
980
981 /*
982 * XXX workaround for AX88190
983 * We limit this to 5000 iterations. At 1us per inb/outb,
984 * this translates to about 15ms, which should be plenty
985 * of time, and also gives protection in the card eject
986 * case.
987 */
988 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
989 count = 5000; /* 15ms */
990 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
991 ed_nic_outb(sc, ED_P0_ISR,0);
992 ed_nic_outb(sc, ED_P0_ISR,isr);
993 }
994 if (count == 0)
995 break;
996 }
997
998 /*
999 * Handle transmitter interrupts. Handle these first because
1000 * the receiver will reset the board under some conditions.
1001 */
1002 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
1003 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
1004
1005 /*
1006 * Check for transmit error. If a TX completed with an
1007 * error, we end up throwing the packet away. Really
1008 * the only error that is possible is excessive
1009 * collisions, and in this case it is best to allow
1010 * the automatic mechanisms of TCP to backoff the
1011 * flow. Of course, with UDP we're screwed, but this
1012 * is expected when a network is heavily loaded.
1013 */
1014 (void) ed_nic_inb(sc, ED_P0_TSR);
1015 if (isr & ED_ISR_TXE) {
1016 u_char tsr;
1017
1018 /*
1019 * Excessive collisions (16)
1020 */
1021 tsr = ed_nic_inb(sc, ED_P0_TSR);
1022 if ((tsr & ED_TSR_ABT)
1023 && (collisions == 0)) {
1024
1025 /*
1026 * When collisions total 16, the
1027 * P0_NCR will indicate 0, and the
1028 * TSR_ABT is set.
1029 */
1030 collisions = 16;
1031 sc->mibdata.dot3StatsExcessiveCollisions++;
1032 sc->mibdata.dot3StatsCollFrequencies[15]++;
1033 }
1034 if (tsr & ED_TSR_OWC)
1035 sc->mibdata.dot3StatsLateCollisions++;
1036 if (tsr & ED_TSR_CDH)
1037 sc->mibdata.dot3StatsSQETestErrors++;
1038 if (tsr & ED_TSR_CRS)
1039 sc->mibdata.dot3StatsCarrierSenseErrors++;
1040 if (tsr & ED_TSR_FU)
1041 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
1042
1043 /*
1044 * update output errors counter
1045 */
1046 ifp->if_oerrors++;
1047 } else {
1048
1049 /*
1050 * Update total number of successfully
1051 * transmitted packets.
1052 */
1053 ifp->if_opackets++;
1054 }
1055
1056 /*
1057 * reset tx busy and output active flags
1058 */
1059 sc->xmit_busy = 0;
1060 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1061
1062 /*
1063 * clear watchdog timer
1064 */
1065 ifp->if_timer = 0;
1066
1067 /*
1068 * Add in total number of collisions on last
1069 * transmission.
1070 */
1071 ifp->if_collisions += collisions;
1072 switch(collisions) {
1073 case 0:
1074 case 16:
1075 break;
1076 case 1:
1077 sc->mibdata.dot3StatsSingleCollisionFrames++;
1078 sc->mibdata.dot3StatsCollFrequencies[0]++;
1079 break;
1080 default:
1081 sc->mibdata.dot3StatsMultipleCollisionFrames++;
1082 sc->mibdata.
1083 dot3StatsCollFrequencies[collisions-1]
1084 ++;
1085 break;
1086 }
1087
1088 /*
1089 * Decrement buffer in-use count if not zero (can only
1090 * be zero if a transmitter interrupt occured while
1091 * not actually transmitting). If data is ready to
1092 * transmit, start it transmitting, otherwise defer
1093 * until after handling receiver
1094 */
1095 if (sc->txb_inuse && --sc->txb_inuse)
1096 ed_xmit(sc);
1097 }
1098
1099 /*
1100 * Handle receiver interrupts
1101 */
1102 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
1103
1104 /*
1105 * Overwrite warning. In order to make sure that a
1106 * lockup of the local DMA hasn't occurred, we reset
1107 * and re-init the NIC. The NSC manual suggests only a
1108 * partial reset/re-init is necessary - but some chips
1109 * seem to want more. The DMA lockup has been seen
1110 * only with early rev chips - Methinks this bug was
1111 * fixed in later revs. -DG
1112 */
1113 if (isr & ED_ISR_OVW) {
1114 ifp->if_ierrors++;
1115#ifdef DIAGNOSTIC
1116 log(LOG_WARNING,
1117 "%s: warning - receiver ring buffer overrun\n",
1118 ifp->if_xname);
1119#endif
1120
1121 /*
1122 * Stop/reset/re-init NIC
1123 */
1124 ed_reset(ifp);
1125 } else {
1126
1127 /*
1128 * Receiver Error. One or more of: CRC error,
1129 * frame alignment error FIFO overrun, or
1130 * missed packet.
1131 */
1132 if (isr & ED_ISR_RXE) {
1133 u_char rsr;
1134 rsr = ed_nic_inb(sc, ED_P0_RSR);
1135 if (rsr & ED_RSR_CRC)
1136 sc->mibdata.dot3StatsFCSErrors++;
1137 if (rsr & ED_RSR_FAE)
1138 sc->mibdata.dot3StatsAlignmentErrors++;
1139 if (rsr & ED_RSR_FO)
1140 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
1141 ifp->if_ierrors++;
1142#ifdef ED_DEBUG
1143 if_printf(ifp, "receive error %x\n",
1144 ed_nic_inb(sc, ED_P0_RSR));
1145#endif
1146 }
1147
1148 /*
1149 * Go get the packet(s) XXX - Doing this on an
1150 * error is dubious because there shouldn't be
1151 * any data to get (we've configured the
1152 * interface to not accept packets with
1153 * errors).
1154 */
1155
1156 /*
1157 * Enable 16bit access to shared memory first
1158 * on WD/SMC boards.
1159 */
1160 ed_enable_16bit_access(sc);
1161 ed_rint(sc);
1162 ed_disable_16bit_access(sc);
1163 }
1164 }
1165
1166 /*
1167 * If it looks like the transmitter can take more data,
1168 * attempt to start output on the interface. This is done
1169 * after handling the receiver to give the receiver priority.
1170 */
1171 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
1172 ed_start_locked(ifp);
1173
1174 /*
1175 * return NIC CR to standard state: page 0, remote DMA
1176 * complete, start (toggling the TXP bit off, even if was just
1177 * set in the transmit routine, is *okay* - it is 'edge'
1178 * triggered from low to high)
1179 */
1180 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1181
1182 /*
1183 * If the Network Talley Counters overflow, read them to reset
1184 * them. It appears that old 8390's won't clear the ISR flag
1185 * otherwise - resulting in an infinite loop.
1186 */
1187 if (isr & ED_ISR_CNT) {
1188 (void) ed_nic_inb(sc, ED_P0_CNTR0);
1189 (void) ed_nic_inb(sc, ED_P0_CNTR1);
1190 (void) ed_nic_inb(sc, ED_P0_CNTR2);
1191 }
1192 }
1193 ED_UNLOCK(sc);
1194}
1195
1196/*
1197 * Process an ioctl request.
1198 */
1199static int
1200ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1201{
1202 struct ed_softc *sc = ifp->if_softc;
1203 struct ifreq *ifr = (struct ifreq *)data;
1204 int error = 0;
1205
1206 /*
1207 * XXX really needed?
1208 */
1209 if (sc == NULL) {
1210 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1211 return (ENXIO);
1212 }
1213
1214 switch (command) {
1215 case SIOCSIFFLAGS:
1216 /*
1217 * If the interface is marked up and stopped, then start it.
1218 * If we're up and already running, then it may be a mediachg.
1219 * If it is marked down and running, then stop it.
1220 */
1221 ED_LOCK(sc);
1222 if (ifp->if_flags & IFF_UP) {
1223 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1224 ed_init_locked(sc);
1225 else if (sc->sc_mediachg)
1226 sc->sc_mediachg(sc);
1227 } else {
1228 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1229 ed_stop(sc);
1230 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1231 }
1232 }
1233
1234 /*
1235 * Promiscuous flag may have changed, so reprogram the RCR.
1236 */
1237 ed_setrcr(sc);
1238
1239 ED_UNLOCK(sc);
1240 break;
1241
1242 case SIOCADDMULTI:
1243 case SIOCDELMULTI:
1244 /*
1245 * Multicast list has changed; set the hardware filter
1246 * accordingly.
1247 */
1248 ED_LOCK(sc);
1249 ed_setrcr(sc);
1250 ED_UNLOCK(sc);
1251 error = 0;
1252 break;
1253
1254 case SIOCGIFMEDIA:
1255 case SIOCSIFMEDIA:
1256 if (sc->sc_media_ioctl == NULL) {
1257 error = EINVAL;
1258 break;
1259 }
1260 sc->sc_media_ioctl(sc, ifr, command);
1261 break;
1262
1263 default:
1264 error = ether_ioctl(ifp, command, data);
1265 break;
1266 }
1267 return (error);
1268}
1269
1270/*
1271 * Given a source and destination address, copy 'amount' of a packet from
1272 * the ring buffer into a linear destination buffer. Takes into account
1273 * ring-wrap.
1274 */
1275static __inline void
1276ed_ring_copy(struct ed_softc *sc, bus_size_t src, char *dst, u_short amount)
1277{
1278 u_short tmp_amount;
1279
1280 /* does copy wrap to lower addr in ring buffer? */
1281 if (src + amount > sc->mem_end) {
1282 tmp_amount = sc->mem_end - src;
1283 /* copy amount up to end of NIC memory */
1284 sc->readmem(sc, src, dst, tmp_amount);
1285 amount -= tmp_amount;
1286 src = sc->mem_ring;
1287 dst += tmp_amount;
1288 }
1289 sc->readmem(sc, src, dst, amount);
1290}
1291
1292/*
1293 * Retreive packet from shared memory and send to the next level up via
1294 * ether_input().
1295 */
1296static void
1297ed_get_packet(struct ed_softc *sc, bus_size_t buf, u_short len)
1298{
1299 struct ifnet *ifp = sc->ifp;
1300 struct ether_header *eh;
1301 struct mbuf *m;
1302
1303 /* Allocate a header mbuf */
1304 MGETHDR(m, M_DONTWAIT, MT_DATA);
1305 if (m == NULL)
1306 return;
1307 m->m_pkthdr.rcvif = ifp;
1308 m->m_pkthdr.len = m->m_len = len;
1309
1310 /*
1311 * We always put the received packet in a single buffer -
1312 * either with just an mbuf header or in a cluster attached
1313 * to the header. The +2 is to compensate for the alignment
1314 * fixup below.
1315 */
1316 if ((len + 2) > MHLEN) {
1317 /* Attach an mbuf cluster */
1318 MCLGET(m, M_DONTWAIT);
1319
1320 /* Insist on getting a cluster */
1321 if ((m->m_flags & M_EXT) == 0) {
1322 m_freem(m);
1323 return;
1324 }
1325 }
1326
1327 /*
1328 * The +2 is to longword align the start of the real packet.
1329 * This is important for NFS.
1330 */
1331 m->m_data += 2;
1332 eh = mtod(m, struct ether_header *);
1333
1334 /*
1335 * Get packet, including link layer address, from interface.
1336 */
1337 ed_ring_copy(sc, buf, (char *)eh, len);
1338
1339 m->m_pkthdr.len = m->m_len = len;
1340
1341 ED_UNLOCK(sc);
1342 (*ifp->if_input)(ifp, m);
1343 ED_LOCK(sc);
1344}
1345
1346/*
1347 * Supporting routines
1348 */
1349
1350/*
1351 * Given a NIC memory source address and a host memory destination
1352 * address, copy 'amount' from NIC to host using shared memory.
1353 * The 'amount' is rounded up to a word - okay as long as mbufs
1354 * are word sized. That's what the +1 is below.
1355 * This routine accesses things as 16 bit quantities.
1356 */
1357void
1358ed_shmem_readmem16(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1359 uint16_t amount)
1360{
1361 bus_space_read_region_2(sc->mem_bst, sc->mem_bsh, src, (uint16_t *)dst,
1362 amount + 1 / 2);
1363}
1364
1365/*
1366 * Given a NIC memory source address and a host memory destination
1367 * address, copy 'amount' from NIC to host using shared memory.
1368 * This routine accesses things as 8 bit quantities.
1369 */
1370void
1371ed_shmem_readmem8(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1372 uint16_t amount)
1373{
1374 bus_space_read_region_1(sc->mem_bst, sc->mem_bsh, src, dst, amount);
1375}
1376
1377/*
1378 * Given a NIC memory source address and a host memory destination
1379 * address, copy 'amount' from NIC to host using Programmed I/O.
1380 * The 'amount' is rounded up to a word - okay as long as mbufs
1381 * are word sized.
1382 * This routine is currently Novell-specific.
1383 */
1384void
1385ed_pio_readmem(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
1386 uint16_t amount)
1387{
1388 /* Regular Novell cards */
1389 /* select page 0 registers */
1390 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1391
1392 /* round up to a word */
1393 if (amount & 1)
1394 ++amount;
1395
1396 /* set up DMA byte count */
1397 ed_nic_outb(sc, ED_P0_RBCR0, amount);
1398 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
1399
1400 /* set up source address in NIC mem */
1401 ed_nic_outb(sc, ED_P0_RSAR0, src);
1402 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
1403
1404 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
1405
1406 if (sc->isa16bit)
1407 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
1408 else
1409 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
1410}
1411
1412/*
1413 * Stripped down routine for writing a linear buffer to NIC memory.
1414 * Only used in the probe routine to test the memory. 'len' must
1415 * be even.
1416 */
1417void
1418ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len)
1419{
1420 int maxwait = 200; /* about 240us */
1421
1422 /* select page 0 registers */
1423 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1424
1425 /* reset remote DMA complete flag */
1426 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1427
1428 /* set up DMA byte count */
1429 ed_nic_outb(sc, ED_P0_RBCR0, len);
1430 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
1431
1432 /* set up destination address in NIC mem */
1433 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1434 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1435
1436 /* set remote DMA write */
1437 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1438
1439 if (sc->isa16bit)
1440 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
1441 else
1442 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
1443
1444 /*
1445 * Wait for remote DMA complete. This is necessary because on the
1446 * transmit side, data is handled internally by the NIC in bursts and
1447 * we can't start another remote DMA until this one completes. Not
1448 * waiting causes really bad things to happen - like the NIC
1449 * irrecoverably jamming the ISA bus.
1450 */
1451 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
1452 --maxwait)
1453 continue;
1454}
1455
1456/*
1457 * Write an mbuf chain to the destination NIC memory address using
1458 * programmed I/O.
1459 */
1460static u_short
1461ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
1462{
1463 struct ifnet *ifp = sc->ifp;
1464 unsigned short total_len, dma_len;
1465 struct mbuf *mp;
1466 int maxwait = 200; /* about 240us */
1467
1468 ED_ASSERT_LOCKED(sc);
1469
1470#ifdef ED_HPP
1471 /* HP PC Lan+ cards need special handling */
1472 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS)
1473 return ed_hpp_write_mbufs(sc, m, dst);
1474#endif
1475
1476 /* Regular Novell cards */
1477 /* First, count up the total number of bytes to copy */
1478 for (total_len = 0, mp = m; mp; mp = mp->m_next)
1479 total_len += mp->m_len;
1480
1481 dma_len = total_len;
1482 if (sc->isa16bit && (dma_len & 1))
1483 dma_len++;
1484
1485 /* select page 0 registers */
1486 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1487
1488 /* reset remote DMA complete flag */
1489 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1490
1491 /* set up DMA byte count */
1492 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
1493 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
1494
1495 /* set up destination address in NIC mem */
1496 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1497 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1498
1499 /* set remote DMA write */
1500 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1501
1502 /*
1503 * Transfer the mbuf chain to the NIC memory.
1504 * 16-bit cards require that data be transferred as words, and only words.
1505 * So that case requires some extra code to patch over odd-length mbufs.
1506 */
1507
1508 if (!sc->isa16bit) {
1509 /* NE1000s are easy */
1510 while (m) {
1511 if (m->m_len)
1512 ed_asic_outsb(sc, ED_NOVELL_DATA,
1513 m->m_data, m->m_len);
1514 m = m->m_next;
1515 }
1516 } else {
1517 /* NE2000s are a pain */
1518 unsigned char *data;
1519 int len, wantbyte;
1520 unsigned char savebyte[2];
1521
1522 wantbyte = 0;
1523
1524 while (m) {
1525 len = m->m_len;
1526 if (len) {
1527 data = mtod(m, caddr_t);
1528 /* finish the last word */
1529 if (wantbyte) {
1530 savebyte[1] = *data;
1531 ed_asic_outw(sc, ED_NOVELL_DATA,
1532 *(u_short *)savebyte);
1533 data++;
1534 len--;
1535 wantbyte = 0;
1536 }
1537 /* output contiguous words */
1538 if (len > 1) {
1539 ed_asic_outsw(sc, ED_NOVELL_DATA,
1540 data, len >> 1);
1541 data += len & ~1;
1542 len &= 1;
1543 }
1544 /* save last byte, if necessary */
1545 if (len == 1) {
1546 savebyte[0] = *data;
1547 wantbyte = 1;
1548 }
1549 }
1550 m = m->m_next;
1551 }
1552 /* spit last byte */
1553 if (wantbyte)
1554 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
1555 }
1556
1557 /*
1558 * Wait for remote DMA complete. This is necessary because on the
1559 * transmit side, data is handled internally by the NIC in bursts and
1560 * we can't start another remote DMA until this one completes. Not
1561 * waiting causes really bad things to happen - like the NIC
1562 * irrecoverably jamming the ISA bus.
1563 */
1564 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) &&
1565 --maxwait)
1566 continue;
1567
1568 if (!maxwait) {
1569 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
1570 ifp->if_xname);
1571 ed_reset(ifp);
1572 return(0);
1573 }
1574 return (total_len);
1575}
1576
1577static void
1578ed_setrcr(struct ed_softc *sc)
1579{
1580 struct ifnet *ifp = sc->ifp;
1581 int i;
1582 u_char reg1;
1583
1584 ED_ASSERT_LOCKED(sc);
1585
1586 /* Bit 6 in AX88190 RCR register must be set. */
1587 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
1588 reg1 = ED_RCR_INTT;
1589 else
1590 reg1 = 0x00;
1591
1592 /* set page 1 registers */
1593 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1594
1595 if (ifp->if_flags & IFF_PROMISC) {
1596
1597 /*
1598 * Reconfigure the multicast filter.
1599 */
1600 for (i = 0; i < 8; i++)
1601 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
1602
1603 /*
1604 * And turn on promiscuous mode. Also enable reception of
1605 * runts and packets with CRC & alignment errors.
1606 */
1607 /* Set page 0 registers */
1608 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1609
1610 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
1611 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
1612 } else {
1613 /* set up multicast addresses and filter modes */
1614 if (ifp->if_flags & IFF_MULTICAST) {
1615 uint32_t mcaf[2];
1616
1617 if (ifp->if_flags & IFF_ALLMULTI) {
1618 mcaf[0] = 0xffffffff;
1619 mcaf[1] = 0xffffffff;
1620 } else
1621 ed_ds_getmcaf(sc, mcaf);
1622
1623 /*
1624 * Set multicast filter on chip.
1625 */
1626 for (i = 0; i < 8; i++)
1627 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
1628
1629 /* Set page 0 registers */
1630 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1631
1632 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
1633 } else {
1634
1635 /*
1636 * Initialize multicast address hashing registers to
1637 * not accept multicasts.
1638 */
1639 for (i = 0; i < 8; ++i)
1640 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
1641
1642 /* Set page 0 registers */
1643 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1644
1645 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
1646 }
1647 }
1648
1649 /*
1650 * Start interface.
1651 */
1652 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1653}
1654
1655/*
1656 * Compute the multicast address filter from the
1657 * list of multicast addresses we need to listen to.
1658 */
1659static void
1660ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf)
1661{
1662 uint32_t index;
1663 u_char *af = (u_char *) mcaf;
1664 struct ifmultiaddr *ifma;
1665
1666 mcaf[0] = 0;
1667 mcaf[1] = 0;
1668
1669 IF_ADDR_LOCK(sc->ifp);
1670 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
1671 if (ifma->ifma_addr->sa_family != AF_LINK)
1672 continue;
1673 index = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1674 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1675 af[index >> 3] |= 1 << (index & 7);
1676 }
1677 IF_ADDR_UNLOCK(sc->ifp);
1678}
1679
1680int
1681ed_isa_mem_ok(device_t dev, u_long pmem, u_int memsize)
1682{
1683 if (pmem < 0xa0000 || pmem + memsize > 0x1000000) {
1684 device_printf(dev, "Invalid ISA memory address range "
1685 "configured: 0x%lx - 0x%lx\n", pmem, pmem + memsize);
1686 return (ENXIO);
1687 }
1688 return (0);
1689}
1690
1691int
1692ed_clear_memory(device_t dev)
1693{
1694 struct ed_softc *sc = device_get_softc(dev);
1695 bus_size_t i;
1696
1697 bus_space_set_region_1(sc->mem_bst, sc->mem_bsh, sc->mem_start,
1698 0, sc->mem_size);
1699
1700 for (i = 0; i < sc->mem_size; i++) {
1701 if (bus_space_read_1(sc->mem_bst, sc->mem_bsh,
1702 sc->mem_start + i)) {
1703 device_printf(dev, "failed to clear shared memory at "
1704 "0x%jx - check configuration\n",
1705 (uintmax_t)rman_get_start(sc->mem_res) + i);
1706 return (ENXIO);
1707 }
1708 }
1709 return (0);
1710}