1/*
2 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
3 * adapters. By David Greenman, 29-April-1993
4 *
5 * Copyright (C) 1993, David Greenman. This software may be used, modified,
6 * copied, distributed, and sold, in both source and binary form provided
7 * that the above copyright and these terms are retained. Under no
8 * circumstances is the author responsible for the proper functioning
9 * of this software, nor does the author assume any responsibility
10 * for damages incurred with its use.
11 *
12 * Currently supports the Western Digital/SMC 8003 and 8013 series,
13 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
14 * and a variety of similar clones.
15 *
16 * Thanks to Charles Hannum for proving to me with example code that the
17 * NE1000/2000 support could be added with minimal impact. Without
18 * this, I wouldn't have proceeded in this direction.
19 *
20 */
21
22/*
23 * $Id: if_ed.c,v 1.31 1994/02/02 02:24:38 davidg Exp $
24 */
25
26#include "ed.h"
27#if NED > 0
28/* bpfilter included here in case it is needed in future net includes */
29#include "bpfilter.h"
30
31#include "param.h"
32#include "systm.h"
33#include "errno.h"
34#include "ioctl.h"
35#include "mbuf.h"
36#include "socket.h"
37#include "syslog.h"
38
39#include "net/if.h"
40#include "net/if_dl.h"
41#include "net/if_types.h"
42#include "net/netisr.h"
43
44#ifdef INET
45#include "netinet/in.h"
46#include "netinet/in_systm.h"
47#include "netinet/in_var.h"
48#include "netinet/ip.h"
49#include "netinet/if_ether.h"
50#endif
51
52#ifdef NS
53#include "netns/ns.h"
54#include "netns/ns_if.h"
55#endif
56
57#if NBPFILTER > 0
58#include "net/bpf.h"
59#include "net/bpfdesc.h"
60#endif
61
62#include "i386/isa/isa.h"
63#include "i386/isa/isa_device.h"
64#include "i386/isa/icu.h"
65#include "i386/isa/if_edreg.h"
66
67#include "i386/include/pio.h"
68
69/* For backwards compatibility */
70#ifndef IFF_ALTPHYS
71#define IFF_ALTPHYS IFF_LLC0
72#endif
73
74/*
75 * ed_softc: per line info and status
76 */
77struct ed_softc {
78 struct arpcom arpcom; /* ethernet common */
79
80 char *type_str; /* pointer to type string */
81 u_char vendor; /* interface vendor */
82 u_char type; /* interface type code */
83
84 u_short asic_addr; /* ASIC I/O bus address */
85 u_short nic_addr; /* NIC (DS8390) I/O bus address */
86
87/*
88 * The following 'proto' variable is part of a work-around for 8013EBT asics
89 * being write-only. It's sort of a prototype/shadow of the real thing.
90 */
91 u_char wd_laar_proto;
92 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
93 int is790; /* set by the probe code if the card is 790 based */
94
95 caddr_t bpf; /* BPF "magic cookie" */
96 caddr_t mem_start; /* NIC memory start address */
97 caddr_t mem_end; /* NIC memory end address */
98 u_long mem_size; /* total NIC memory size */
99 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
100
101 u_char mem_shared; /* NIC memory is shared with host */
102 u_char xmit_busy; /* transmitter is busy */
103 u_char txb_cnt; /* number of transmit buffers */
104 u_char txb_inuse; /* number of TX buffers currently in-use*/
105
106 u_char txb_new; /* pointer to where new buffer will be added */
107 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
108 u_short txb_len[8]; /* buffered xmit buffer lengths */
109 u_char tx_page_start; /* first page of TX buffer area */
110 u_char rec_page_start; /* first page of RX ring-buffer */
111 u_char rec_page_stop; /* last page of RX ring-buffer */
112 u_char next_packet; /* pointer to next unread RX packet */
113} ed_softc[NED];
114
115int ed_attach(struct isa_device *);
116void ed_init(int);
117void edintr(int);
118int ed_ioctl(struct ifnet *, int, caddr_t);
119int ed_probe(struct isa_device *);
120void ed_start(struct ifnet *);
121void ed_reset(int, int);
122void ed_watchdog(int);
123
124static void ed_get_packet(struct ed_softc *, char *, int /*u_short*/);
125static void ed_stop(int);
126
127static inline void ed_rint();
128static inline void ed_xmit();
129static inline char *ed_ring_copy();
130
131void ed_pio_readmem(), ed_pio_writemem();
132u_short ed_pio_write_mbufs();
133
134extern int ether_output();
135
136struct trailer_header {
137 u_short ether_type;
138 u_short ether_residual;
139};
140
141struct isa_driver eddriver = {
142 ed_probe,
143 ed_attach,
144 "ed"
145};
146/*
147 * Interrupt conversion table for WD/SMC ASIC
148 * (IRQ* are defined in icu.h)
149 */
150static unsigned short ed_intr_mask[] = {
151 IRQ9,
152 IRQ3,
153 IRQ5,
154 IRQ7,
155 IRQ10,
156 IRQ11,
157 IRQ15,
158 IRQ4
159};
160
161/*
162 * Interrupt conversion table for 585/790 Combo
163 */
164static unsigned short ed_790_intr_mask[] = {
165 0,
166 IRQ9,
167 IRQ3,
168 IRQ4,
169 IRQ5,
170 IRQ10,
171 IRQ11,
172 IRQ15
173};
174#define ETHER_MIN_LEN 64
175#define ETHER_MAX_LEN 1518
176#define ETHER_ADDR_LEN 6
177#define ETHER_HDR_SIZE 14
178
179/*
180 * Determine if the device is present
181 *
182 * on entry:
183 * a pointer to an isa_device struct
184 * on exit:
185 * NULL if device not found
186 * or # of i/o addresses used (if found)
187 */
188int
189ed_probe(isa_dev)
190 struct isa_device *isa_dev;
191{
192 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
193 int nports;
194
195 if (nports = ed_probe_WD80x3(isa_dev))
196 return (nports);
197
198 if (nports = ed_probe_3Com(isa_dev))
199 return (nports);
200
201 if (nports = ed_probe_Novell(isa_dev))
202 return (nports);
203
204 return(0);
205}
206
207/*
208 * Generic probe routine for testing for the existance of a DS8390.
209 * Must be called after the NIC has just been reset. This routine
210 * works by looking at certain register values that are gauranteed
211 * to be initialized a certain way after power-up or reset. Seems
212 * not to currently work on the 83C690.
213 *
214 * Specifically:
215 *
216 * Register reset bits set bits
217 * Command Register (CR) TXP, STA RD2, STP
218 * Interrupt Status (ISR) RST
219 * Interrupt Mask (IMR) All bits
220 * Data Control (DCR) LAS
221 * Transmit Config. (TCR) LB1, LB0
222 *
223 * We only look at the CR and ISR registers, however, because looking at
224 * the others would require changing register pages (which would be
225 * intrusive if this isn't an 8390).
226 *
227 * Return 1 if 8390 was found, 0 if not.
228 */
229
230int
231ed_probe_generic8390(sc)
232 struct ed_softc *sc;
233{
234 if ((inb(sc->nic_addr + ED_P0_CR) &
235 (ED_CR_RD2|ED_CR_TXP|ED_CR_STA|ED_CR_STP)) !=
236 (ED_CR_RD2|ED_CR_STP))
237 return (0);
238 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
239 return (0);
240
241 return(1);
242}
243
244/*
245 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
246 */
247int
248ed_probe_WD80x3(isa_dev)
249 struct isa_device *isa_dev;
250{
251 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
252 int i;
253 u_int memsize;
254 u_char iptr, isa16bit, sum;
255
256 sc->asic_addr = isa_dev->id_iobase;
257 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
258 sc->is790 = 0;
259
260#ifdef TOSH_ETHER
261 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
262 DELAY(10000);
263#endif
264 /*
265 * Attempt to do a checksum over the station address PROM.
266 * If it fails, it's probably not a SMC/WD board. There
267 * is a problem with this, though: some clone WD boards
268 * don't pass the checksum test. Danpex boards for one.
269 */
270 for (sum = 0, i = 0; i < 8; ++i)
271 sum += inb(sc->asic_addr + ED_WD_PROM + i);
272
273 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
274 /*
275 * Checksum is invalid. This often happens with cheap
276 * WD8003E clones. In this case, the checksum byte
277 * (the eighth byte) seems to always be zero.
278 */
279 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
280 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
281 return(0);
282 }
283
284 /* reset card to force it into a known state. */
285#ifdef TOSH_ETHER
286 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
287#else
288 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
289#endif
290 DELAY(100);
291 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
292 /* wait in the case this card is reading it's EEROM */
293 DELAY(5000);
294
295 sc->vendor = ED_VENDOR_WD_SMC;
296 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
297
298 /*
299 * Set initial values for width/size.
300 */
301 memsize = 8192;
302 isa16bit = 0;
303 switch (sc->type) {
304 case ED_TYPE_WD8003S:
305 sc->type_str = "WD8003S";
306 break;
307 case ED_TYPE_WD8003E:
308 sc->type_str = "WD8003E";
309 break;
310 case ED_TYPE_WD8003EB:
311 sc->type_str = "WD8003EB";
312 break;
313 case ED_TYPE_WD8003W:
314 sc->type_str = "WD8003W";
315 break;
316 case ED_TYPE_WD8013EBT:
317 sc->type_str = "WD8013EBT";
318 memsize = 16384;
319 isa16bit = 1;
320 break;
321 case ED_TYPE_WD8013W:
322 sc->type_str = "WD8013W";
323 memsize = 16384;
324 isa16bit = 1;
325 break;
326 case ED_TYPE_WD8013EP: /* also WD8003EP */
327 if (inb(sc->asic_addr + ED_WD_ICR)
328 & ED_WD_ICR_16BIT) {
329 isa16bit = 1;
330 memsize = 16384;
331 sc->type_str = "WD8013EP";
332 } else {
333 sc->type_str = "WD8003EP";
334 }
335 break;
336 case ED_TYPE_WD8013WC:
337 sc->type_str = "WD8013WC";
338 memsize = 16384;
339 isa16bit = 1;
340 break;
341 case ED_TYPE_WD8013EBP:
342 sc->type_str = "WD8013EBP";
343 memsize = 16384;
344 isa16bit = 1;
345 break;
346 case ED_TYPE_WD8013EPC:
347 sc->type_str = "WD8013EPC";
348 memsize = 16384;
349 isa16bit = 1;
350 break;
351 case ED_TYPE_SMC8216C:
352 sc->type_str = "SMC8216/SMC8216C";
353 memsize = 16384;
354 isa16bit = 1;
355 sc->is790 = 1;
356 break;
357 case ED_TYPE_SMC8216T:
358 sc->type_str = "SMC8216T";
359 memsize = 16384;
360 isa16bit = 1;
361 sc->is790 = 1;
362 break;
363#ifdef TOSH_ETHER
364 case ED_TYPE_TOSHIBA1:
365 sc->type_str = "Toshiba1";
366 memsize = 32768;
367 isa16bit = 1;
368 break;
369 case ED_TYPE_TOSHIBA4:
370 sc->type_str = "Toshiba4";
371 memsize = 32768;
372 isa16bit = 1;
373 break;
374#endif
375 default:
376 sc->type_str = "";
377 break;
378 }
379 /*
380 * Make some adjustments to initial values depending on what is
381 * found in the ICR.
382 */
383 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
384#ifdef TOSH_ETHER
385 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
386#endif
387 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
388 isa16bit = 0;
389 memsize = 8192;
390 }
391
392#if ED_DEBUG
393 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
394 sc->type,sc->type_str,isa16bit,memsize,isa_dev->id_msize);
395 for (i=0; i<8; i++)
396 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
397#endif
398 /*
399 * Allow the user to override the autoconfiguration
400 */
401 if (isa_dev->id_msize)
402 memsize = isa_dev->id_msize;
403 /*
404 * (note that if the user specifies both of the following flags
405 * that '8bit' mode intentionally has precedence)
406 */
407 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
408 isa16bit = 1;
409 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
410 isa16bit = 0;
411
412 /*
413 * Check 83C584 interrupt configuration register if this board has one
414 * XXX - we could also check the IO address register. But why
415 * bother...if we get past this, it *has* to be correct.
416 */
417 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
418 /*
419 * Assemble together the encoded interrupt number.
420 */
421 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
422 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
423 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
424 /*
425 * Translate it using translation table, and check for correctness.
426 */
427 if (ed_intr_mask[iptr] != isa_dev->id_irq) {
428 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d\n",
429 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_intr_mask[iptr]) - 1);
430 return(0);
431 }
432 /*
433 * Enable the interrupt.
434 */
435 outb(isa_dev->id_iobase + ED_WD_IRR,
436 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
437 }
438 if (sc->is790) {
439 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) | 0x80);
440 iptr = ((inb(isa_dev->id_iobase + 0x0d) & 0x0c ) >> 2) |
441 ((inb(isa_dev->id_iobase + 0x0d) & 0x40) >> 4);
442 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) & ~0x80);
443
444 if (ed_790_intr_mask[iptr] != isa_dev->id_irq) {
445 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d %d\n",
446 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_790_intr_mask[iptr]) -1, iptr);
447 return 0;
448 }
449 outb(isa_dev->id_iobase + 0x06, inb(isa_dev->id_iobase + 0x06) | 0x01);
450 }
451
452 sc->isa16bit = isa16bit;
453
454#ifdef notyet /* XXX - I'm not sure if PIO mode is even possible on WD/SMC boards */
455 /*
456 * The following allows the WD/SMC boards to be used in Programmed I/O
457 * mode - without mapping the NIC memory shared. ...Not the prefered
458 * way, but it might be the only way.
459 */
460 if (isa_dev->id_flags & ED_FLAGS_FORCE_PIO) {
461 sc->mem_shared = 0;
462 isa_dev->id_maddr = 0;
463 } else {
464 sc->mem_shared = 1;
465 }
466#else
467 sc->mem_shared = 1;
468#endif
469 isa_dev->id_msize = memsize;
470
471 sc->mem_start = (caddr_t)isa_dev->id_maddr;
472
473 /*
474 * allocate one xmit buffer if < 16k, two buffers otherwise
475 */
476 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
477 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
478 sc->txb_cnt = 1;
479 sc->rec_page_start = ED_TXBUF_SIZE;
480 } else {
481 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2);
482 sc->txb_cnt = 2;
483 sc->rec_page_start = ED_TXBUF_SIZE * 2;
484 }
485 sc->mem_size = memsize;
486 sc->mem_end = sc->mem_start + memsize;
487 sc->rec_page_stop = memsize / ED_PAGE_SIZE;
488 sc->tx_page_start = ED_WD_PAGE_OFFSET;
489
490 /*
491 * Get station address from on-board ROM
492 */
493 for (i = 0; i < ETHER_ADDR_LEN; ++i)
494 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
495
496 if (sc->mem_shared) {
497 /*
498 * Set address and enable interface shared memory.
499 */
500 if(!sc->is790) {
501#ifdef TOSH_ETHER
502 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
503 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
504 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
505
506#else
507 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
508 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
509#endif
510 } else {
511 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
512 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80));
513 outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
514 ((kvtop(sc->mem_start) >> 11) & 0x40) |
515 (inb(sc->asic_addr + 0x0b) & 0xb0));
516 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80));
517 }
518
519 /*
520 * Set upper address bits and 8/16 bit access to shared memory
521 */
522 if (isa16bit) {
523 if (sc->is790) {
524 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
525 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
526 } else {
527 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
528 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
529 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
530 }
531 } else {
532 if ((sc->type & ED_WD_SOFTCONFIG) ||
533#ifdef TOSH_ETHER
534 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
535#endif
536 (sc->type == ED_TYPE_WD8013EBT) && (!sc->is790)) {
537 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
538 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
539 }
540 }
541
542 /*
543 * Now zero memory and verify that it is clear
544 */
545 bzero(sc->mem_start, memsize);
546
547 for (i = 0; i < memsize; ++i)
548 if (sc->mem_start[i]) {
549 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
550 isa_dev->id_unit, kvtop(sc->mem_start + i));
551
552 /*
553 * Disable 16 bit access to shared memory
554 */
555 if (isa16bit)
556 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
557 ~ED_WD_LAAR_M16EN));
558
559 return(0);
560 }
561
562 /*
563 * Disable 16bit access to shared memory - we leave it disabled so
564 * that 1) machines reboot properly when the board is set
565 * 16 bit mode and there are conflicting 8bit devices/ROMS
566 * in the same 128k address space as this boards shared
567 * memory. and 2) so that other 8 bit devices with shared
568 * memory can be used in this 128k region, too.
569 */
570 if (isa16bit)
571 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
572 ~ED_WD_LAAR_M16EN));
573
574 }
575
576 return (ED_WD_IO_PORTS);
577}
578
579/*
580 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
581 */
582int
583ed_probe_3Com(isa_dev)
584 struct isa_device *isa_dev;
585{
586 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
587 int i;
588 u_int memsize;
589 u_char isa16bit, sum;
590
591 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
592 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
593
594 /*
595 * Verify that the kernel configured I/O address matches the board
596 * configured address
597 */
598 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
599 case ED_3COM_BCFR_300:
600 if (isa_dev->id_iobase != 0x300)
601 return(0);
602 break;
603 case ED_3COM_BCFR_310:
604 if (isa_dev->id_iobase != 0x310)
605 return(0);
606 break;
607 case ED_3COM_BCFR_330:
608 if (isa_dev->id_iobase != 0x330)
609 return(0);
610 break;
611 case ED_3COM_BCFR_350:
612 if (isa_dev->id_iobase != 0x350)
613 return(0);
614 break;
615 case ED_3COM_BCFR_250:
616 if (isa_dev->id_iobase != 0x250)
617 return(0);
618 break;
619 case ED_3COM_BCFR_280:
620 if (isa_dev->id_iobase != 0x280)
621 return(0);
622 break;
623 case ED_3COM_BCFR_2A0:
624 if (isa_dev->id_iobase != 0x2a0)
625 return(0);
626 break;
627 case ED_3COM_BCFR_2E0:
628 if (isa_dev->id_iobase != 0x2e0)
629 return(0);
630 break;
631 default:
632 return(0);
633 }
634
635 /*
636 * Verify that the kernel shared memory address matches the
637 * board configured address.
638 */
639 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
640 case ED_3COM_PCFR_DC000:
641 if (kvtop(isa_dev->id_maddr) != 0xdc000)
642 return(0);
643 break;
644 case ED_3COM_PCFR_D8000:
645 if (kvtop(isa_dev->id_maddr) != 0xd8000)
646 return(0);
647 break;
648 case ED_3COM_PCFR_CC000:
649 if (kvtop(isa_dev->id_maddr) != 0xcc000)
650 return(0);
651 break;
652 case ED_3COM_PCFR_C8000:
653 if (kvtop(isa_dev->id_maddr) != 0xc8000)
654 return(0);
655 break;
656 default:
657 return(0);
658 }
659
660
661 /*
662 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
663 * sequence because it'll lock up if the cable isn't connected
664 * if we don't.
665 */
666 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
667
668 /*
669 * Wait for a while, then un-reset it
670 */
671 DELAY(50);
672 /*
673 * The 3Com ASIC defaults to rather strange settings for the CR after
674 * a reset - it's important to set it again after the following
675 * outb (this is done when we map the PROM below).
676 */
677 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
678
679 /*
680 * Wait a bit for the NIC to recover from the reset
681 */
682 DELAY(5000);
683
684 sc->vendor = ED_VENDOR_3COM;
685 sc->type_str = "3c503";
686
687 sc->mem_shared = 1;
688
689 /*
690 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k
691 * window to it.
692 */
693 memsize = 8192;
694
695 /*
696 * Get station address from on-board ROM
697 */
698 /*
699 * First, map ethernet address PROM over the top of where the NIC
700 * registers normally appear.
701 */
702 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
703
704 for (i = 0; i < ETHER_ADDR_LEN; ++i)
705 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
706
707 /*
708 * Unmap PROM - select NIC registers. The proper setting of the
709 * tranceiver is set in ed_init so that the attach code
710 * is given a chance to set the default based on a compile-time
711 * config option
712 */
713 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
714
715 /*
716 * Determine if this is an 8bit or 16bit board
717 */
718
719 /*
720 * select page 0 registers
721 */
722 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
723
724 /*
725 * Attempt to clear WTS bit. If it doesn't clear, then this is a
726 * 16bit board.
727 */
728 outb(sc->nic_addr + ED_P0_DCR, 0);
729
730 /*
731 * select page 2 registers
732 */
733 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2|ED_CR_RD2|ED_CR_STP);
734
735 /*
736 * The 3c503 forces the WTS bit to a one if this is a 16bit board
737 */
738 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
739 isa16bit = 1;
740 else
741 isa16bit = 0;
742
743 /*
744 * select page 0 registers
745 */
746 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2|ED_CR_STP);
747
748 sc->mem_start = (caddr_t)isa_dev->id_maddr;
749 sc->mem_size = memsize;
750 sc->mem_end = sc->mem_start + memsize;
751
752 /*
753 * We have an entire 8k window to put the transmit buffers on the
754 * 16bit boards. But since the 16bit 3c503's shared memory
755 * is only fast enough to overlap the loading of one full-size
756 * packet, trying to load more than 2 buffers can actually
757 * leave the transmitter idle during the load. So 2 seems
758 * the best value. (Although a mix of variable-sized packets
759 * might change this assumption. Nonetheless, we optimize for
760 * linear transfers of same-size packets.)
761 */
762 if (isa16bit) {
763 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
764 sc->txb_cnt = 1;
765 else
766 sc->txb_cnt = 2;
767
768 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
769 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
770 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
771 ED_3COM_RX_PAGE_OFFSET_16BIT;
772 sc->mem_ring = sc->mem_start;
773 } else {
774 sc->txb_cnt = 1;
775 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
776 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
777 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
778 ED_3COM_TX_PAGE_OFFSET_8BIT;
779 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
780 }
781
782 sc->isa16bit = isa16bit;
783
784 /*
785 * Initialize GA page start/stop registers. Probably only needed
786 * if doing DMA, but what the hell.
787 */
788 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
789 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
790
791 /*
792 * Set IRQ. 3c503 only allows a choice of irq 2-5.
793 */
794 switch (isa_dev->id_irq) {
795 case IRQ2:
796 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
797 break;
798 case IRQ3:
799 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
800 break;
801 case IRQ4:
802 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
803 break;
804 case IRQ5:
805 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
806 break;
807 default:
808 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n",
809 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
810 return(0);
811 }
812
813 /*
814 * Initialize GA configuration register. Set bank and enable shared mem.
815 */
816 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
817 ED_3COM_GACFR_MBS0);
818
819 /*
820 * Initialize "Vector Pointer" registers. These gawd-awful things
821 * are compared to 20 bits of the address on ISA, and if they
822 * match, the shared memory is disabled. We set them to
823 * 0xffff0...allegedly the reset vector.
824 */
825 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
826 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
827 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
828
829 /*
830 * Zero memory and verify that it is clear
831 */
832 bzero(sc->mem_start, memsize);
833
834 for (i = 0; i < memsize; ++i)
835 if (sc->mem_start[i]) {
836 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
837 isa_dev->id_unit, kvtop(sc->mem_start + i));
838 return(0);
839 }
840
841 isa_dev->id_msize = memsize;
842 return(ED_3COM_IO_PORTS);
843}
844
845/*
846 * Probe and vendor-specific initialization routine for NE1000/2000 boards
847 */
848int
849ed_probe_Novell(isa_dev)
850 struct isa_device *isa_dev;
851{
852 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
853 u_int memsize, n;
854 u_char romdata[16], isa16bit = 0, tmp;
855 static char test_pattern[32] = "THIS is A memory TEST pattern";
856 char test_buffer[32];
857
858 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET;
859 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET;
860
861 /* XXX - do Novell-specific probe here */
862
863 /* Reset the board */
864 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
865
866 /*
867 * I don't know if this is necessary; probably cruft leftover from
868 * Clarkson packet driver code. Doesn't do a thing on the boards
869 * I've tested. -DG [note that a outb(0x84, 0) seems to work
870 * here, and is non-invasive...but some boards don't seem to reset
871 * and I don't have complete documentation on what the 'right'
872 * thing to do is...so we do the invasive thing for now. Yuck.]
873 */
874 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
875 DELAY(5000);
876
877 /*
878 * This is needed because some NE clones apparently don't reset the
879 * NIC properly (or the NIC chip doesn't reset fully on power-up)
880 * XXX - this makes the probe invasive! ...Done against my better
881 * judgement. -DLG
882 */
883 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
884
885 DELAY(5000);
886
887 /* Make sure that we really have an 8390 based board */
888 if (!ed_probe_generic8390(sc))
889 return(0);
890
891 sc->vendor = ED_VENDOR_NOVELL;
892 sc->mem_shared = 0;
893 isa_dev->id_maddr = 0;
894
895 /*
896 * Test the ability to read and write to the NIC memory. This has
897 * the side affect of determining if this is an NE1000 or an NE2000.
898 */
899
900 /*
901 * This prevents packets from being stored in the NIC memory when
902 * the readmem routine turns on the start bit in the CR.
903 */
904 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
905
906 /* Temporarily initialize DCR for byte operations */
907 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
908
909 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
910 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
911
912 sc->isa16bit = 0;
913
914 /*
915 * Write a test pattern in byte mode. If this fails, then there
916 * probably isn't any memory at 8k - which likely means
917 * that the board is an NE2000.
918 */
919 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
920 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
921
922 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
923 /* not an NE1000 - try NE2000 */
924
925 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS|ED_DCR_FT1|ED_DCR_LS);
926 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
927 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
928
929 sc->isa16bit = 1;
930 /*
931 * Write a test pattern in word mode. If this also fails, then
932 * we don't know what this board is.
933 */
934 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
935 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
936
937 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
938 return(0); /* not an NE2000 either */
939
940 sc->type = ED_TYPE_NE2000;
941 sc->type_str = "NE2000";
942 } else {
943 sc->type = ED_TYPE_NE1000;
944 sc->type_str = "NE1000";
945 }
946
947 /* 8k of memory plus an additional 8k if 16bit */
948 memsize = 8192 + sc->isa16bit * 8192;
949
950#if 0 /* probably not useful - NE boards only come two ways */
951 /* allow kernel config file overrides */
952 if (isa_dev->id_msize)
953 memsize = isa_dev->id_msize;
954#endif
955
956 sc->mem_size = memsize;
957
958 /* NIC memory doesn't start at zero on an NE board */
959 /* The start address is tied to the bus width */
960 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
961 sc->mem_end = sc->mem_start + memsize;
962 sc->tx_page_start = memsize / ED_PAGE_SIZE;
963
964 /*
965 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
966 * otherwise).
967 */
968 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING))
969 sc->txb_cnt = 1;
970 else
971 sc->txb_cnt = 2;
972
973 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
974 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
975
976 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
977
978 ed_pio_readmem(sc, 0, romdata, 16);
979 for (n = 0; n < ETHER_ADDR_LEN; n++)
980 sc->arpcom.ac_enaddr[n] = romdata[n*(sc->isa16bit+1)];
981
982 /* clear any pending interrupts that might have occurred above */
983 outb(sc->nic_addr + ED_P0_ISR, 0xff);
984
985 return(ED_NOVELL_IO_PORTS);
986}
987
988/*
989 * Install interface into kernel networking data structures
990 */
991int
992ed_attach(isa_dev)
993 struct isa_device *isa_dev;
994{
995 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
996 struct ifnet *ifp = &sc->arpcom.ac_if;
997 struct ifaddr *ifa;
998 struct sockaddr_dl *sdl;
999
1000 /*
1001 * Set interface to stopped condition (reset)
1002 */
1003 ed_stop(isa_dev->id_unit);
1004
1005 /*
1006 * Initialize ifnet structure
1007 */
1008 ifp->if_unit = isa_dev->id_unit;
1009 ifp->if_name = "ed" ;
1010 ifp->if_mtu = ETHERMTU;
1011 ifp->if_init = ed_init;
1012 ifp->if_output = ether_output;
1013 ifp->if_start = ed_start;
1014 ifp->if_ioctl = ed_ioctl;
1015 ifp->if_reset = ed_reset;
1016 ifp->if_watchdog = ed_watchdog;
1017
1018 /*
1019 * Set default state for ALTPHYS flag (used to disable the tranceiver
1020 * for AUI operation), based on compile-time config option.
1021 */
1022 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER)
1023 ifp->if_flags =
1024 (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_ALTPHYS);
1025 else
1026 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS);
1027
1028 /*
1029 * Attach the interface
1030 */
1031 if_attach(ifp);
1032
1033 /*
1034 * Search down the ifa address list looking for the AF_LINK type entry
1035 */
1036 ifa = ifp->if_addrlist;
1037 while ((ifa != 0) && (ifa->ifa_addr != 0) &&
1038 (ifa->ifa_addr->sa_family != AF_LINK))
1039 ifa = ifa->ifa_next;
1040 /*
1041 * If we find an AF_LINK type entry we fill in the hardware address.
1042 * This is useful for netstat(1) to keep track of which interface
1043 * is which.
1044 */
1045 if ((ifa != 0) && (ifa->ifa_addr != 0)) {
1046 /*
1047 * Fill in the link-level address for this interface
1048 */
1049 sdl = (struct sockaddr_dl *)ifa->ifa_addr;
1050 sdl->sdl_type = IFT_ETHER;
1051 sdl->sdl_alen = ETHER_ADDR_LEN;
1052 sdl->sdl_slen = 0;
1053 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN);
1054 }
1055
1056 /*
1057 * Print additional info when attached
1058 */
1059 printf("ed%d: address %s, ", isa_dev->id_unit,
1060 ether_sprintf(sc->arpcom.ac_enaddr));
1061
1062 if (sc->type_str && (*sc->type_str != 0))
1063 printf("type %s ", sc->type_str);
1064 else
1065 printf("type unknown (0x%x) ", sc->type);
1066
1067 printf("%s ",sc->isa16bit ? "(16 bit)" : "(8 bit)");
1068
1069 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) &&
1070 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1071
1072 /*
1073 * If BPF is in the kernel, call the attach for it
1074 */
1075#if NBPFILTER > 0
1076 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
1077#endif
1078 return 1;
1079}
1080
1081/*
1082 * Reset interface.
1083 */
1084void
1085ed_reset(unit, uban)
1086 int unit;
1087 int uban; /* XXX */
1088{
1089 int s;
1090
1091 s = splimp();
1092
1093 /*
1094 * Stop interface and re-initialize.
1095 */
1096 ed_stop(unit);
1097 ed_init(unit);
1098
1099 (void) splx(s);
1100}
1101
1102/*
1103 * Take interface offline.
1104 */
1105void
1106ed_stop(unit)
1107 int unit;
1108{
1109 struct ed_softc *sc = &ed_softc[unit];
1110 int n = 5000;
1111
1112 /*
1113 * Stop everything on the interface, and select page 0 registers.
1114 */
1115 if (sc->is790) {
1116 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1117 } else {
1118 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1119 }
1120 /*
1121 * Wait for interface to enter stopped state, but limit # of checks
1122 * to 'n' (about 5ms). It shouldn't even take 5us on modern
1123 * DS8390's, but just in case it's an old one.
1124 */
1125 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1126
1127}
1128
1129/*
1130 * Device timeout/watchdog routine. Entered if the device neglects to
1131 * generate an interrupt after a transmit has been started on it.
1132 */
1133void
1134ed_watchdog(unit)
1135 int unit;
1136{
1137 struct ed_softc *sc = &ed_softc[unit];
1138
1139 log(LOG_ERR, "ed%d: device timeout\n", unit);
1140 ++sc->arpcom.ac_if.if_oerrors;
1141
1142 ed_reset(unit, 0);
1143}
1144
1145/*
1146 * Initialize device.
1147 */
1148void
1149ed_init(unit)
1150 int unit;
1151{
1152 struct ed_softc *sc = &ed_softc[unit];
1153 struct ifnet *ifp = &sc->arpcom.ac_if;
1154 int i, s;
1155 u_char command;
1156
1157
1158 /* address not known */
1159 if (ifp->if_addrlist == (struct ifaddr *)0) return;
1160
1161 /*
1162 * Initialize the NIC in the exact order outlined in the NS manual.
1163 * This init procedure is "mandatory"...don't change what or when
1164 * things happen.
1165 */
1166 s = splimp();
1167
1168 /* reset transmitter flags */
1169 sc->xmit_busy = 0;
1170 sc->arpcom.ac_if.if_timer = 0;
1171
1172 sc->txb_inuse = 0;
1173 sc->txb_new = 0;
1174 sc->txb_next_tx = 0;
1175
1176 /* This variable is used below - don't move this assignment */
1177 sc->next_packet = sc->rec_page_start + 1;
1178
1179 /*
1180 * Set interface for page 0, Remote DMA complete, Stopped
1181 */
1182 if (sc->is790) {
1183 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1184 } else {
1185 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1186 }
1187 if (sc->isa16bit) {
1188 /*
1189 * Set FIFO threshold to 8, No auto-init Remote DMA,
1190 * byte order=80x86, word-wide DMA xfers,
1191 */
1192 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS|ED_DCR_LS);
1193 } else {
1194 /*
1195 * Same as above, but byte-wide DMA xfers
1196 */
1197 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
1198 }
1199
1200 /*
1201 * Clear Remote Byte Count Registers
1202 */
1203 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1204 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1205
1206 /*
1207 * Enable reception of broadcast packets
1208 */
1209 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
1210
1211 /*
1212 * Place NIC in internal loopback mode
1213 */
1214 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1215
1216 /*
1217 * Initialize transmit/receive (ring-buffer) Page Start
1218 */
1219 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1220 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1221 /* Set lower bits of byte addressable framing to 0 */
1222 if (sc->is790)
1223 outb(sc->nic_addr + 0x09, 0);
1224
1225 /*
1226 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1227 */
1228 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1229 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1230
1231 /*
1232 * Clear all interrupts. A '1' in each bit position clears the
1233 * corresponding flag.
1234 */
1235 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1236
1237 /*
1238 * Enable the following interrupts: receive/transmit complete,
1239 * receive/transmit error, and Receiver OverWrite.
1240 *
1241 * Counter overflow and Remote DMA complete are *not* enabled.
1242 */
1243 outb(sc->nic_addr + ED_P0_IMR,
1244 ED_IMR_PRXE|ED_IMR_PTXE|ED_IMR_RXEE|ED_IMR_TXEE|ED_IMR_OVWE);
1245
1246 /*
1247 * Program Command Register for page 1
1248 */
1249 if (sc->is790) {
1250 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STP);
1251 } else {
1252 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STP);
1253 }
1254 /*
1255 * Copy out our station address
1256 */
1257 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1258 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1259
1260#if NBPFILTER > 0
1261 /*
1262 * Initialize multicast address hashing registers to accept
1263 * all multicasts (only used when in promiscuous mode)
1264 */
1265 for (i = 0; i < 8; ++i)
1266 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
1267#endif
1268
1269 /*
1270 * Set Current Page pointer to next_packet (initialized above)
1271 */
1272 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1273
1274 /*
1275 * Set Command Register for page 0, Remote DMA complete,
1276 * and interface Start.
1277 */
1278 if (sc->is790) {
1279 outb(sc->nic_addr + ED_P1_CR, ED_CR_STA);
1280 } else {
1281 outb(sc->nic_addr + ED_P1_CR, ED_CR_RD2|ED_CR_STA);
1282 }
1283 /*
1284 * Take interface out of loopback
1285 */
1286 outb(sc->nic_addr + ED_P0_TCR, 0);
1287
1288 /*
1289 * If this is a 3Com board, the tranceiver must be software enabled
1290 * (there is no settable hardware default).
1291 */
1292 if (sc->vendor == ED_VENDOR_3COM) {
1293 if (ifp->if_flags & IFF_ALTPHYS) {
1294 outb(sc->asic_addr + ED_3COM_CR, 0);
1295 } else {
1296 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1297 }
1298 }
1299
1300 /*
1301 * Set 'running' flag, and clear output active flag.
1302 */
1303 ifp->if_flags |= IFF_RUNNING;
1304 ifp->if_flags &= ~IFF_OACTIVE;
1305
1306 /*
1307 * ...and attempt to start output
1308 */
1309 ed_start(ifp);
1310
1311 (void) splx(s);
1312}
1313
1314/*
1315 * This routine actually starts the transmission on the interface
1316 */
1317static inline void ed_xmit(ifp)
1318 struct ifnet *ifp;
1319{
1320 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1321 unsigned short len;
1322
1323 len = sc->txb_len[sc->txb_next_tx];
1324
1325 /*
1326 * Set NIC for page 0 register access
1327 */
1328 if (sc->is790) {
1329 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1330 } else {
1331 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1332 }
1333 /*
1334 * Set TX buffer start page
1335 */
1336 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1337 sc->txb_next_tx * ED_TXBUF_SIZE);
1338
1339 /*
1340 * Set TX length
1341 */
1342 outb(sc->nic_addr + ED_P0_TBCR0, len);
1343 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
1344
1345 /*
1346 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1347 */
1348 if (sc->is790) {
1349 outb(sc->nic_addr + ED_P0_CR, ED_CR_TXP | ED_CR_STA);
1350 } else {
1351 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA);
1352 }
1353 sc->xmit_busy = 1;
1354
1355 /*
1356 * Point to next transmit buffer slot and wrap if necessary.
1357 */
1358 sc->txb_next_tx++;
1359 if (sc->txb_next_tx == sc->txb_cnt)
1360 sc->txb_next_tx = 0;
1361
1362 /*
1363 * Set a timer just in case we never hear from the board again
1364 */
1365 ifp->if_timer = 2;
1366}
1367
1368/*
1369 * Start output on interface.
1370 * We make two assumptions here:
1371 * 1) that the current priority is set to splimp _before_ this code
1372 * is called *and* is returned to the appropriate priority after
1373 * return
1374 * 2) that the IFF_OACTIVE flag is checked before this code is called
1375 * (i.e. that the output part of the interface is idle)
1376 */
1377void
1378ed_start(ifp)
1379 struct ifnet *ifp;
1380{
1381 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1382 struct mbuf *m0, *m;
1383 caddr_t buffer;
1384 int len;
1385
1386outloop:
1387 /*
1388 * First, see if there are buffered packets and an idle
1389 * transmitter - should never happen at this point.
1390 */
1391 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1392 printf("ed: packets buffers, but transmitter idle\n");
1393 ed_xmit(ifp);
1394 }
1395
1396 /*
1397 * See if there is room to put another packet in the buffer.
1398 */
1399 if (sc->txb_inuse == sc->txb_cnt) {
1400 /*
1401 * No room. Indicate this to the outside world
1402 * and exit.
1403 */
1404 ifp->if_flags |= IFF_OACTIVE;
1405 return;
1406 }
1407
1408 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m);
1409 if (m == 0) {
1410 /*
1411 * We are using the !OACTIVE flag to indicate to the outside
1412 * world that we can accept an additional packet rather than
1413 * that the transmitter is _actually_ active. Indeed, the
1414 * transmitter may be active, but if we haven't filled all
1415 * the buffers with data then we still want to accept more.
1416 */
1417 ifp->if_flags &= ~IFF_OACTIVE;
1418 return;
1419 }
1420
1421 /*
1422 * Copy the mbuf chain into the transmit buffer
1423 */
1424
1425 m0 = m;
1426
1427 /* txb_new points to next open buffer slot */
1428 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
1429
1430 if (sc->mem_shared) {
1431 /*
1432 * Special case setup for 16 bit boards...
1433 */
1434 if (sc->isa16bit) {
1435 switch (sc->vendor) {
1436 /*
1437 * For 16bit 3Com boards (which have 16k of memory),
1438 * we have the xmit buffers in a different page
1439 * of memory ('page 0') - so change pages.
1440 */
1441 case ED_VENDOR_3COM:
1442 outb(sc->asic_addr + ED_3COM_GACFR,
1443 ED_3COM_GACFR_RSEL);
1444 break;
1445 /*
1446 * Enable 16bit access to shared memory on WD/SMC boards
1447 * Don't update wd_laar_proto because we want to restore the
1448 * previous state (because an arp reply in the input code
1449 * may cause a call-back to ed_start)
1450 * XXX - the call-back to 'start' is a bug, IMHO.
1451 */
1452 case ED_VENDOR_WD_SMC:
1453 outb(sc->asic_addr + ED_WD_LAAR,
1454 (sc->wd_laar_proto | ED_WD_LAAR_M16EN));
1455 }
1456 }
1457
1458 for (len = 0; m != 0; m = m->m_next) {
1459 bcopy(mtod(m, caddr_t), buffer, m->m_len);
1460 buffer += m->m_len;
1461 len += m->m_len;
1462 }
1463
1464 /*
1465 * Restore previous shared memory access
1466 */
1467 if (sc->isa16bit) {
1468 switch (sc->vendor) {
1469 case ED_VENDOR_3COM:
1470 outb(sc->asic_addr + ED_3COM_GACFR,
1471 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
1472 break;
1473 case ED_VENDOR_WD_SMC:
1474 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
1475 break;
1476 }
1477 }
1478 } else {
1479 len = ed_pio_write_mbufs(sc, m, buffer);
1480 }
1481
1482 sc->txb_len[sc->txb_new] = MAX(len, ETHER_MIN_LEN);
1483
1484 sc->txb_inuse++;
1485
1486 /*
1487 * Point to next buffer slot and wrap if necessary.
1488 */
1489 sc->txb_new++;
1490 if (sc->txb_new == sc->txb_cnt)
1491 sc->txb_new = 0;
1492
1493 if (sc->xmit_busy == 0)
1494 ed_xmit(ifp);
1495 /*
1496 * If there is BPF support in the configuration, tap off here.
1497 * The following has support for converting trailer packets
1498 * back to normal.
1499 * XXX - support for trailer packets in BPF should be moved into
1500 * the bpf code proper to avoid code duplication in all of
1501 * the drivers.
1502 */
1503#if NBPFILTER > 0
1504 if (sc->bpf) {
1505 u_short etype;
1506 int off, datasize, resid;
1507 struct ether_header *eh;
1508 struct trailer_header trailer_header;
1509 char ether_packet[ETHER_MAX_LEN];
1510 char *ep;
1511
1512 ep = ether_packet;
1513
1514 /*
1515 * We handle trailers below:
1516 * Copy ether header first, then residual data,
1517 * then data. Put all this in a temporary buffer
1518 * 'ether_packet' and send off to bpf. Since the
1519 * system has generated this packet, we assume
1520 * that all of the offsets in the packet are
1521 * correct; if they're not, the system will almost
1522 * certainly crash in m_copydata.
1523 * We make no assumptions about how the data is
1524 * arranged in the mbuf chain (i.e. how much
1525 * data is in each mbuf, if mbuf clusters are
1526 * used, etc.), which is why we use m_copydata
1527 * to get the ether header rather than assume
1528 * that this is located in the first mbuf.
1529 */
1530 /* copy ether header */
1531 m_copydata(m0, 0, sizeof(struct ether_header), ep);
1532 eh = (struct ether_header *) ep;
1533 ep += sizeof(struct ether_header);
1534 etype = ntohs(eh->ether_type);
1535 if (etype >= ETHERTYPE_TRAIL &&
1536 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
1537 datasize = ((etype - ETHERTYPE_TRAIL) << 9);
1538 off = datasize + sizeof(struct ether_header);
1539
1540 /* copy trailer_header into a data structure */
1541 m_copydata(m0, off, sizeof(struct trailer_header),
1542 (caddr_t)&trailer_header.ether_type);
1543
1544 /* copy residual data */
1545 m_copydata(m0, off+sizeof(struct trailer_header),
1546 resid = ntohs(trailer_header.ether_residual) -
1547 sizeof(struct trailer_header), ep);
1548 ep += resid;
1549
1550 /* copy data */
1551 m_copydata(m0, sizeof(struct ether_header),
1552 datasize, ep);
1553 ep += datasize;
1554
1555 /* restore original ether packet type */
1556 eh->ether_type = trailer_header.ether_type;
1557
1558 bpf_tap(sc->bpf, ether_packet, ep - ether_packet);
1559 } else
1560 bpf_mtap(sc->bpf, m0);
1561 }
1562#endif
1563
1564 m_freem(m0);
1565
1566 /*
1567 * Loop back to the top to possibly buffer more packets
1568 */
1569 goto outloop;
1570}
1571
1572/*
1573 * Ethernet interface receiver interrupt.
1574 */
1575static inline void
1576ed_rint(unit)
1577 int unit;
1578{
1579 register struct ed_softc *sc = &ed_softc[unit];
1580 u_char boundry, current;
1581 u_short len;
1582 struct ed_ring packet_hdr;
1583 char *packet_ptr;
1584
1585 /*
1586 * Set NIC to page 1 registers to get 'current' pointer
1587 */
1588 if (sc->is790) {
1589 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1590 } else {
1591 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1592 }
1593 /*
1594 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
1595 * it points to where new data has been buffered. The 'CURR'
1596 * (current) register points to the logical end of the ring-buffer
1597 * - i.e. it points to where additional new data will be added.
1598 * We loop here until the logical beginning equals the logical
1599 * end (or in other words, until the ring-buffer is empty).
1600 */
1601 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
1602
1603 /* get pointer to this buffer's header structure */
1604 packet_ptr = sc->mem_ring +
1605 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
1606
1607 /*
1608 * The byte count includes the FCS - Frame Check Sequence (a
1609 * 32 bit CRC).
1610 */
1611 if (sc->mem_shared)
1612 packet_hdr = *(struct ed_ring *)packet_ptr;
1613 else
1614 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr,
1615 sizeof(packet_hdr));
1616 len = packet_hdr.count;
1617 if ((len >= ETHER_MIN_LEN) && (len <= ETHER_MAX_LEN)) {
1618 /*
1619 * Go get packet. len - 4 removes CRC from length.
1620 */
1621 ed_get_packet(sc, packet_ptr + 4, len - 4);
1622 ++sc->arpcom.ac_if.if_ipackets;
1623 } else {
1624 /*
1625 * Really BAD...probably indicates that the ring pointers
1626 * are corrupted. Also seen on early rev chips under
1627 * high load - the byte order of the length gets switched.
1628 */
1629 log(LOG_ERR,
1630 "ed%d: NIC memory corrupt - invalid packet length %d\n",
1631 unit, len);
1632 ++sc->arpcom.ac_if.if_ierrors;
1633 ed_reset(unit, 0);
1634 return;
1635 }
1636
1637 /*
1638 * Update next packet pointer
1639 */
1640 sc->next_packet = packet_hdr.next_packet;
1641
1642 /*
1643 * Update NIC boundry pointer - being careful to keep it
1644 * one buffer behind. (as recommended by NS databook)
1645 */
1646 boundry = sc->next_packet - 1;
1647 if (boundry < sc->rec_page_start)
1648 boundry = sc->rec_page_stop - 1;
1649
1650 /*
1651 * Set NIC to page 0 registers to update boundry register
1652 */
1653 if (sc->is790) {
1654 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1655 } else {
1656 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1657 }
1658 outb(sc->nic_addr + ED_P0_BNRY, boundry);
1659
1660 /*
1661 * Set NIC to page 1 registers before looping to top (prepare to
1662 * get 'CURR' current pointer)
1663 */
1664 if (sc->is790) {
1665 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1666 } else {
1667 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1668 }
1669 }
1670}
1671
1672/*
1673 * Ethernet interface interrupt processor
1674 */
1675void
1676edintr(unit)
1677 int unit;
1678{
1679 struct ed_softc *sc = &ed_softc[unit];
1680 u_char isr;
1681
1682 /*
1683 * Set NIC to page 0 registers
1684 */
1685 if (sc->is790) {
1686 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1687 } else {
1688 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1689 }
1690 /*
1691 * loop until there are no more new interrupts
1692 */
1693 while (isr = inb(sc->nic_addr + ED_P0_ISR)) {
1694
1695 /*
1696 * reset all the bits that we are 'acknowledging'
1697 * by writing a '1' to each bit position that was set
1698 * (writing a '1' *clears* the bit)
1699 */
1700 outb(sc->nic_addr + ED_P0_ISR, isr);
1701
1702 /*
1703 * Handle transmitter interrupts. Handle these first
1704 * because the receiver will reset the board under
1705 * some conditions.
1706 */
1707 if (isr & (ED_ISR_PTX|ED_ISR_TXE)) {
1708 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
1709
1710 /*
1711 * Check for transmit error. If a TX completed with an
1712 * error, we end up throwing the packet away. Really
1713 * the only error that is possible is excessive
1714 * collisions, and in this case it is best to allow the
1715 * automatic mechanisms of TCP to backoff the flow. Of
1716 * course, with UDP we're screwed, but this is expected
1717 * when a network is heavily loaded.
1718 */
1719 (void) inb(sc->nic_addr + ED_P0_TSR);
1720 if (isr & ED_ISR_TXE) {
1721
1722 /*
1723 * Excessive collisions (16)
1724 */
1725 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT)
1726 && (collisions == 0)) {
1727 /*
1728 * When collisions total 16, the
1729 * P0_NCR will indicate 0, and the
1730 * TSR_ABT is set.
1731 */
1732 collisions = 16;
1733 }
1734
1735 /*
1736 * update output errors counter
1737 */
1738 ++sc->arpcom.ac_if.if_oerrors;
1739 } else {
1740 /*
1741 * Update total number of successfully
1742 * transmitted packets.
1743 */
1744 ++sc->arpcom.ac_if.if_opackets;
1745 }
1746
1747 /*
1748 * reset tx busy and output active flags
1749 */
1750 sc->xmit_busy = 0;
1751 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
1752
1753 /*
1754 * clear watchdog timer
1755 */
1756 sc->arpcom.ac_if.if_timer = 0;
1757
1758 /*
1759 * Add in total number of collisions on last
1760 * transmission.
1761 */
1762 sc->arpcom.ac_if.if_collisions += collisions;
1763
1764 /*
1765 * Decrement buffer in-use count if not zero (can only
1766 * be zero if a transmitter interrupt occured while
1767 * not actually transmitting).
1768 * If data is ready to transmit, start it transmitting,
1769 * otherwise defer until after handling receiver
1770 */
1771 if (sc->txb_inuse && --sc->txb_inuse)
1772 ed_xmit(&sc->arpcom.ac_if);
1773 }
1774
1775 /*
1776 * Handle receiver interrupts
1777 */
1778 if (isr & (ED_ISR_PRX|ED_ISR_RXE|ED_ISR_OVW)) {
1779 /*
1780 * Overwrite warning. In order to make sure that a lockup
1781 * of the local DMA hasn't occurred, we reset and
1782 * re-init the NIC. The NSC manual suggests only a
1783 * partial reset/re-init is necessary - but some
1784 * chips seem to want more. The DMA lockup has been
1785 * seen only with early rev chips - Methinks this
1786 * bug was fixed in later revs. -DG
1787 */
1788 if (isr & ED_ISR_OVW) {
1789 ++sc->arpcom.ac_if.if_ierrors;
1790#ifdef DIAGNOSTIC
1791 log(LOG_WARNING,
1792 "ed%d: warning - receiver ring buffer overrun\n",
1793 unit);
1794#endif
1795 /*
1796 * Stop/reset/re-init NIC
1797 */
1798 ed_reset(unit, 0);
1799 } else {
1800
1801 /*
1802 * Receiver Error. One or more of: CRC error, frame
1803 * alignment error FIFO overrun, or missed packet.
1804 */
1805 if (isr & ED_ISR_RXE) {
1806 ++sc->arpcom.ac_if.if_ierrors;
1807#ifdef ED_DEBUG
1808 printf("ed%d: receive error %x\n", unit,
1809 inb(sc->nic_addr + ED_P0_RSR));
1810#endif
1811 }
1812
1813 /*
1814 * Go get the packet(s)
1815 * XXX - Doing this on an error is dubious
1816 * because there shouldn't be any data to
1817 * get (we've configured the interface to
1818 * not accept packets with errors).
1819 */
1820
1821 /*
1822 * Enable 16bit access to shared memory first
1823 * on WD/SMC boards.
1824 */
1825 if (sc->isa16bit &&
1826 (sc->vendor == ED_VENDOR_WD_SMC)) {
1827
1828 outb(sc->asic_addr + ED_WD_LAAR,
1829 (sc->wd_laar_proto |=
1830 ED_WD_LAAR_M16EN));
1831 }
1832
1833 ed_rint (unit);
1834
1835 /* disable 16bit access */
1836 if (sc->isa16bit &&
1837 (sc->vendor == ED_VENDOR_WD_SMC)) {
1838
1839 outb(sc->asic_addr + ED_WD_LAAR,
1840 (sc->wd_laar_proto &=
1841 ~ED_WD_LAAR_M16EN));
1842 }
1843 }
1844 }
1845
1846 /*
1847 * If it looks like the transmitter can take more data,
1848 * attempt to start output on the interface.
1849 * This is done after handling the receiver to
1850 * give the receiver priority.
1851 */
1852 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0)
1853 ed_start(&sc->arpcom.ac_if);
1854
1855 /*
1856 * return NIC CR to standard state: page 0, remote DMA complete,
1857 * start (toggling the TXP bit off, even if was just set
1858 * in the transmit routine, is *okay* - it is 'edge'
1859 * triggered from low to high)
1860 */
1861 if (sc->is790) {
1862 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1863 } else {
1864 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1865 }
1866 /*
1867 * If the Network Talley Counters overflow, read them to
1868 * reset them. It appears that old 8390's won't
1869 * clear the ISR flag otherwise - resulting in an
1870 * infinite loop.
1871 */
1872 if (isr & ED_ISR_CNT) {
1873 (void) inb(sc->nic_addr + ED_P0_CNTR0);
1874 (void) inb(sc->nic_addr + ED_P0_CNTR1);
1875 (void) inb(sc->nic_addr + ED_P0_CNTR2);
1876 }
1877 }
1878}
1879
1880/*
1881 * Process an ioctl request. This code needs some work - it looks
1882 * pretty ugly.
1883 */
1884int
1885ed_ioctl(ifp, command, data)
1886 register struct ifnet *ifp;
1887 int command;
1888 caddr_t data;
1889{
1890 register struct ifaddr *ifa = (struct ifaddr *)data;
1891 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1892 struct ifreq *ifr = (struct ifreq *)data;
1893 int s, error = 0;
1894
1895 s = splimp();
1896
1897 switch (command) {
1898
1899 case SIOCSIFADDR:
1900 ifp->if_flags |= IFF_UP;
1901
1902 switch (ifa->ifa_addr->sa_family) {
1903#ifdef INET
1904 case AF_INET:
1905 ed_init(ifp->if_unit); /* before arpwhohas */
1906 /*
1907 * See if another station has *our* IP address.
1908 * i.e.: There is an address conflict! If a
1909 * conflict exists, a message is sent to the
1910 * console.
1911 */
1912 ((struct arpcom *)ifp)->ac_ipaddr = IA_SIN(ifa)->sin_addr;
1913 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr);
1914 break;
1915#endif
1916#ifdef NS
1917 /*
1918 * XXX - This code is probably wrong
1919 */
1920 case AF_NS:
1921 {
1922 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
1923
1924 if (ns_nullhost(*ina))
1925 ina->x_host =
1926 *(union ns_host *)(sc->arpcom.ac_enaddr);
1927 else {
1928 /*
1929 *
1930 */
1931 bcopy((caddr_t)ina->x_host.c_host,
1932 (caddr_t)sc->arpcom.ac_enaddr,
1933 sizeof(sc->arpcom.ac_enaddr));
1934 }
1935 /*
1936 * Set new address
1937 */
1938 ed_init(ifp->if_unit);
1939 break;
1940 }
1941#endif
1942 default:
1943 ed_init(ifp->if_unit);
1944 break;
1945 }
1946 break;
1947
1948 case SIOCGIFADDR:
1949 {
1950 struct sockaddr *sa;
1951 sa = (struct sockaddr *)&ifr->ifr_data;
1952 bcopy((caddr_t)sc->arpcom.ac_enaddr,
1953 (caddr_t) sa->sa_data, ETHER_ADDR_LEN);
1954 }
1955 break;
1956
1957 case SIOCSIFFLAGS:
1958 /*
1959 * If interface is marked down and it is running, then stop it
1960 */
1961 if (((ifp->if_flags & IFF_UP) == 0) &&
1962 (ifp->if_flags & IFF_RUNNING)) {
1963 ed_stop(ifp->if_unit);
1964 ifp->if_flags &= ~IFF_RUNNING;
1965 } else {
1966 /*
1967 * If interface is marked up and it is stopped, then start it
1968 */
1969 if ((ifp->if_flags & IFF_UP) &&
1970 ((ifp->if_flags & IFF_RUNNING) == 0))
1971 ed_init(ifp->if_unit);
1972 }
1973#if NBPFILTER > 0
1974 if (ifp->if_flags & IFF_PROMISC) {
1975 /*
1976 * Set promiscuous mode on interface.
1977 * XXX - for multicasts to work, we would need to
1978 * write 1's in all bits of multicast
1979 * hashing array. For now we assume that
1980 * this was done in ed_init().
1981 */
1982 outb(sc->nic_addr + ED_P0_RCR,
1983 ED_RCR_PRO|ED_RCR_AM|ED_RCR_AB);
1984 } else {
1985 /*
1986 * XXX - for multicasts to work, we would need to
1987 * rewrite the multicast hashing array with the
1988 * proper hash (would have been destroyed above).
1989 */
1990 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
1991 }
1992#endif
1993 /*
1994 * An unfortunate hack to provide the (required) software control
1995 * of the tranceiver for 3Com boards. The ALTPHYS flag disables
1996 * the tranceiver if set.
1997 */
1998 if (sc->vendor == ED_VENDOR_3COM) {
1999 if (ifp->if_flags & IFF_ALTPHYS) {
2000 outb(sc->asic_addr + ED_3COM_CR, 0);
2001 } else {
2002 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2003 }
2004 }
2005
2006 break;
2007
2008 default:
2009 error = EINVAL;
2010 }
2011 (void) splx(s);
2012 return (error);
2013}
2014
2015/*
2016 * Macro to calculate a new address within shared memory when given an offset
2017 * from an address, taking into account ring-wrap.
2018 */
2019#define ringoffset(sc, start, off, type) \
2020 ((type)( ((caddr_t)(start)+(off) >= (sc)->mem_end) ? \
2021 (((caddr_t)(start)+(off))) - (sc)->mem_end \
2022 + (sc)->mem_ring: \
2023 ((caddr_t)(start)+(off)) ))
2024
2025/*
2026 * Retreive packet from shared memory and send to the next level up via
2027 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2028 */
2029static void
2030ed_get_packet(sc, buf, len)
2031 struct ed_softc *sc;
2032 char *buf;
2033 u_short len;
2034{
2035 struct ether_header *eh;
2036 struct mbuf *m, *head = 0, *ed_ring_to_mbuf();
2037 u_short off;
2038 int resid;
2039 u_short etype;
2040 struct trailer_header trailer_header;
2041
2042 /* Allocate a header mbuf */
2043 MGETHDR(m, M_DONTWAIT, MT_DATA);
2044 if (m == 0)
2045 goto bad;
2046 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2047 m->m_pkthdr.len = len;
2048 m->m_len = 0;
2049 head = m;
2050
2051 /* The following sillines is to make NFS happy */
2052#define EROUND ((sizeof(struct ether_header) + 3) & ~3)
2053#define EOFF (EROUND - sizeof(struct ether_header))
2054
2055 /*
2056 * The following assumes there is room for
2057 * the ether header in the header mbuf
2058 */
2059 head->m_data += EOFF;
2060 eh = mtod(head, struct ether_header *);
2061
2062 if (sc->mem_shared)
2063 bcopy(buf, mtod(head, caddr_t), sizeof(struct ether_header));
2064 else
2065 ed_pio_readmem(sc, buf, mtod(head, caddr_t),
2066 sizeof(struct ether_header));
2067 buf += sizeof(struct ether_header);
2068 head->m_len += sizeof(struct ether_header);
2069 len -= sizeof(struct ether_header);
2070
2071 etype = ntohs((u_short)eh->ether_type);
2072
2073 /*
2074 * Deal with trailer protocol:
2075 * If trailer protocol, calculate the datasize as 'off',
2076 * which is also the offset to the trailer header.
2077 * Set resid to the amount of packet data following the
2078 * trailer header.
2079 * Finally, copy residual data into mbuf chain.
2080 */
2081 if (etype >= ETHERTYPE_TRAIL &&
2082 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
2083
2084 off = (etype - ETHERTYPE_TRAIL) << 9;
2085 if ((off + sizeof(struct trailer_header)) > len)
2086 goto bad; /* insanity */
2087
2088 /*
2089 * If we have shared memory, we can get info directly from the
2090 * stored packet, otherwise we must get a local copy
2091 * of the trailer header using PIO.
2092 */
2093 if (sc->mem_shared) {
2094 eh->ether_type = *ringoffset(sc, buf, off, u_short *);
2095 resid = ntohs(*ringoffset(sc, buf, off+2, u_short *));
2096 } else {
2097 struct trailer_header trailer_header;
2098 ed_pio_readmem(sc,
2099 ringoffset(sc, buf, off, caddr_t),
2100 (char *) &trailer_header,
2101 sizeof(trailer_header));
2102 eh->ether_type = trailer_header.ether_type;
2103 resid = trailer_header.ether_residual;
2104 }
2105
2106 if ((off + resid) > len) goto bad; /* insanity */
2107
2108 resid -= sizeof(struct trailer_header);
2109 if (resid < 0) goto bad; /* insanity */
2110
2111 m = ed_ring_to_mbuf(sc, ringoffset(sc, buf, off+4, char *),
2112 head, resid);
2113 if (m == 0) goto bad;
2114
2115 len = off;
2116 head->m_pkthdr.len -= 4; /* subtract trailer header */
2117 }
2118
2119 /*
2120 * Pull packet off interface. Or if this was a trailer packet,
2121 * the data portion is appended.
2122 */
2123 m = ed_ring_to_mbuf(sc, buf, m, len);
2124 if (m == 0) goto bad;
2125
2126#if NBPFILTER > 0
2127 /*
2128 * Check if there's a BPF listener on this interface.
2129 * If so, hand off the raw packet to bpf.
2130 */
2131 if (sc->bpf) {
2132 bpf_mtap(sc->bpf, head);
2133
2134 /*
2135 * Note that the interface cannot be in promiscuous mode if
2136 * there are no BPF listeners. And if we are in promiscuous
2137 * mode, we have to check if this packet is really ours.
2138 *
2139 * XXX This test does not support multicasts.
2140 */
2141 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2142 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2143 sizeof(eh->ether_dhost)) != 0 &&
2144 bcmp(eh->ether_dhost, etherbroadcastaddr,
2145 sizeof(eh->ether_dhost)) != 0) {
2146
2147 m_freem(head);
2148 return;
2149 }
2150 }
2151#endif
2152
2153 /*
2154 * Fix up data start offset in mbuf to point past ether header
2155 */
2156 m_adj(head, sizeof(struct ether_header));
2157
2158 /*
2159 * silly ether_input routine needs 'type' in host byte order
2160 */
2161 eh->ether_type = ntohs(eh->ether_type);
2162
2163 ether_input(&sc->arpcom.ac_if, eh, head);
2164 return;
2165
2166bad: if (head)
2167 m_freem(head);
2168 return;
2169}
2170
2171/*
2172 * Supporting routines
2173 */
2174
2175/*
2176 * Given a NIC memory source address and a host memory destination
2177 * address, copy 'amount' from NIC to host using Programmed I/O.
2178 * The 'amount' is rounded up to a word - okay as long as mbufs
2179 * are word sized.
2180 * This routine is currently Novell-specific.
2181 */
2182void
2183ed_pio_readmem(sc,src,dst,amount)
2184 struct ed_softc *sc;
2185 unsigned short src;
2186 unsigned char *dst;
2187 unsigned short amount;
2188{
2189 unsigned short tmp_amount;
2190
2191 /* select page 0 registers */
2192 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2193
2194 /* round up to a word */
2195 tmp_amount = amount;
2196 if (amount & 1) ++amount;
2197
2198 /* set up DMA byte count */
2199 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2200 outb(sc->nic_addr + ED_P0_RBCR1, amount>>8);
2201
2202 /* set up source address in NIC mem */
2203 outb(sc->nic_addr + ED_P0_RSAR0, src);
2204 outb(sc->nic_addr + ED_P0_RSAR1, src>>8);
2205
2206 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2207
2208 if (sc->isa16bit) {
2209 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount/2);
2210 } else
2211 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2212
2213}
2214
2215/*
2216 * Stripped down routine for writing a linear buffer to NIC memory.
2217 * Only used in the probe routine to test the memory. 'len' must
2218 * be even.
2219 */
2220void
2221ed_pio_writemem(sc,src,dst,len)
2222 struct ed_softc *sc;
2223 char *src;
2224 unsigned short dst;
2225 unsigned short len;
2226{
2227 int maxwait=100; /* about 120us */
2228
2229 /* select page 0 registers */
2230 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2231
2232 /* reset remote DMA complete flag */
2233 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2234
2235 /* set up DMA byte count */
2236 outb(sc->nic_addr + ED_P0_RBCR0, len);
2237 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2238
2239 /* set up destination address in NIC mem */
2240 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2241 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2242
2243 /* set remote DMA write */
2244 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2245
2246 if (sc->isa16bit)
2247 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len/2);
2248 else
2249 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2250 /*
2251 * Wait for remote DMA complete. This is necessary because on the
2252 * transmit side, data is handled internally by the NIC in bursts
2253 * and we can't start another remote DMA until this one completes.
2254 * Not waiting causes really bad things to happen - like the NIC
2255 * irrecoverably jamming the ISA bus.
2256 */
2257 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2258}
2259
2260/*
2261 * Write an mbuf chain to the destination NIC memory address using
2262 * programmed I/O.
2263 */
2264u_short
2265ed_pio_write_mbufs(sc,m,dst)
2266 struct ed_softc *sc;
2267 struct mbuf *m;
2268 unsigned short dst;
2269{
2270 unsigned short len, mb_offset;
2271 struct mbuf *mp;
2272 unsigned char residual[2];
2273 int maxwait=100; /* about 120us */
2274
2275 /* First, count up the total number of bytes to copy */
2276 for (len = 0, mp = m; mp; mp = mp->m_next)
2277 len += mp->m_len;
2278
2279 /* select page 0 registers */
2280 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2281
2282 /* reset remote DMA complete flag */
2283 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2284
2285 /* set up DMA byte count */
2286 outb(sc->nic_addr + ED_P0_RBCR0, len);
2287 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2288
2289 /* set up destination address in NIC mem */
2290 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2291 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2292
2293 /* set remote DMA write */
2294 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2295
2296 mb_offset = 0;
2297 /*
2298 * Transfer the mbuf chain to the NIC memory.
2299 * The following code isn't too pretty. The problem is that we can only
2300 * transfer words to the board, and if an mbuf has an odd number
2301 * of bytes in it, this is a problem. It's not a simple matter of
2302 * just removing a byte from the next mbuf (adjusting data++ and
2303 * len--) because this will hose-over the mbuf chain which might
2304 * be needed later for BPF. Instead, we maintain an offset
2305 * (mb_offset) which let's us skip over the first byte in the
2306 * following mbuf.
2307 */
2308 while (m) {
2309 if (m->m_len - mb_offset) {
2310 if (sc->isa16bit) {
2311 if ((m->m_len - mb_offset) > 1)
2312 outsw(sc->asic_addr + ED_NOVELL_DATA,
2313 mtod(m, caddr_t) + mb_offset,
2314 (m->m_len - mb_offset) / 2);
2315
2316 /*
2317 * if odd number of bytes, get the odd byte from
2318 * the next mbuf with data
2319 */
2320 if ((m->m_len - mb_offset) & 1) {
2321 /* first the last byte in current mbuf */
2322 residual[0] = *(mtod(m, caddr_t) +
2323 m->m_len - 1);
2324
2325 /* advance past any empty mbufs */
2326 while (m->m_next && (m->m_next->m_len == 0))
2327 m = m->m_next;
2328
2329 if (m->m_next) {
2330 /* remove first byte in next mbuf */
2331 residual[1] = *(mtod(m->m_next, caddr_t));
2332 mb_offset = 1;
2333 }
2334
2335 outw(sc->asic_addr + ED_NOVELL_DATA,
2336 *((unsigned short *) residual));
2337 } else
2338 mb_offset = 0;
2339 } else
2340 outsb(sc->asic_addr + ED_NOVELL_DATA, m->m_data, m->m_len);
2341
2342 }
2343 m = m->m_next;
2344 }
2345
2346 /*
2347 * Wait for remote DMA complete. This is necessary because on the
2348 * transmit side, data is handled internally by the NIC in bursts
2349 * and we can't start another remote DMA until this one completes.
2350 * Not waiting causes really bad things to happen - like the NIC
2351 * irrecoverably jamming the ISA bus.
2352 */
2353 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2354
2355 if (!maxwait) {
2356 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2357 sc->arpcom.ac_if.if_unit);
2358 ed_reset(sc->arpcom.ac_if.if_unit, 0);
2359 }
2360
2361 return(len);
2362}
2363
2364/*
2365 * Given a source and destination address, copy 'amount' of a packet from
2366 * the ring buffer into a linear destination buffer. Takes into account
2367 * ring-wrap.
2368 */
2369static inline char *
2370ed_ring_copy(sc,src,dst,amount)
2371 struct ed_softc *sc;
2372 char *src;
2373 char *dst;
2374 u_short amount;
2375{
2376 u_short tmp_amount;
2377
2378 /* does copy wrap to lower addr in ring buffer? */
2379 if (src + amount > sc->mem_end) {
2380 tmp_amount = sc->mem_end - src;
2381
2382 /* copy amount up to end of NIC memory */
2383 if (sc->mem_shared)
2384 bcopy(src,dst,tmp_amount);
2385 else
2386 ed_pio_readmem(sc,src,dst,tmp_amount);
2387
2388 amount -= tmp_amount;
2389 src = sc->mem_ring;
2390 dst += tmp_amount;
2391 }
2392
2393 if (sc->mem_shared)
2394 bcopy(src, dst, amount);
2395 else
2396 ed_pio_readmem(sc, src, dst, amount);
2397
2398 return(src + amount);
2399}
2400
2401/*
2402 * Copy data from receive buffer to end of mbuf chain
2403 * allocate additional mbufs as needed. return pointer
2404 * to last mbuf in chain.
2405 * sc = ed info (softc)
2406 * src = pointer in ed ring buffer
2407 * dst = pointer to last mbuf in mbuf chain to copy to
2408 * amount = amount of data to copy
2409 */
2410struct mbuf *
2411ed_ring_to_mbuf(sc,src,dst,total_len)
2412 struct ed_softc *sc;
2413 char *src;
2414 struct mbuf *dst;
2415 u_short total_len;
2416{
2417 register struct mbuf *m = dst;
2418
2419 while (total_len) {
2420 register u_short amount = min(total_len, M_TRAILINGSPACE(m));
2421
2422 if (amount == 0) { /* no more data in this mbuf, alloc another */
2423 /*
2424 * If there is enough data for an mbuf cluster, attempt
2425 * to allocate one of those, otherwise, a regular
2426 * mbuf will do.
2427 * Note that a regular mbuf is always required, even if
2428 * we get a cluster - getting a cluster does not
2429 * allocate any mbufs, and one is needed to assign
2430 * the cluster to. The mbuf that has a cluster
2431 * extension can not be used to contain data - only
2432 * the cluster can contain data.
2433 */
2434 dst = m;
2435 MGET(m, M_DONTWAIT, MT_DATA);
2436 if (m == 0)
2437 return (0);
2438
2439 if (total_len >= MINCLSIZE)
2440 MCLGET(m, M_DONTWAIT);
2441
2442 m->m_len = 0;
2443 dst->m_next = m;
2444 amount = min(total_len, M_TRAILINGSPACE(m));
2445 }
2446
2447 src = ed_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount);
2448
2449 m->m_len += amount;
2450 total_len -= amount;
2451
2452 }
2453 return (m);
2454}
2455#endif
2 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
3 * adapters. By David Greenman, 29-April-1993
4 *
5 * Copyright (C) 1993, David Greenman. This software may be used, modified,
6 * copied, distributed, and sold, in both source and binary form provided
7 * that the above copyright and these terms are retained. Under no
8 * circumstances is the author responsible for the proper functioning
9 * of this software, nor does the author assume any responsibility
10 * for damages incurred with its use.
11 *
12 * Currently supports the Western Digital/SMC 8003 and 8013 series,
13 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
14 * and a variety of similar clones.
15 *
16 * Thanks to Charles Hannum for proving to me with example code that the
17 * NE1000/2000 support could be added with minimal impact. Without
18 * this, I wouldn't have proceeded in this direction.
19 *
20 */
21
22/*
23 * $Id: if_ed.c,v 1.31 1994/02/02 02:24:38 davidg Exp $
24 */
25
26#include "ed.h"
27#if NED > 0
28/* bpfilter included here in case it is needed in future net includes */
29#include "bpfilter.h"
30
31#include "param.h"
32#include "systm.h"
33#include "errno.h"
34#include "ioctl.h"
35#include "mbuf.h"
36#include "socket.h"
37#include "syslog.h"
38
39#include "net/if.h"
40#include "net/if_dl.h"
41#include "net/if_types.h"
42#include "net/netisr.h"
43
44#ifdef INET
45#include "netinet/in.h"
46#include "netinet/in_systm.h"
47#include "netinet/in_var.h"
48#include "netinet/ip.h"
49#include "netinet/if_ether.h"
50#endif
51
52#ifdef NS
53#include "netns/ns.h"
54#include "netns/ns_if.h"
55#endif
56
57#if NBPFILTER > 0
58#include "net/bpf.h"
59#include "net/bpfdesc.h"
60#endif
61
62#include "i386/isa/isa.h"
63#include "i386/isa/isa_device.h"
64#include "i386/isa/icu.h"
65#include "i386/isa/if_edreg.h"
66
67#include "i386/include/pio.h"
68
69/* For backwards compatibility */
70#ifndef IFF_ALTPHYS
71#define IFF_ALTPHYS IFF_LLC0
72#endif
73
74/*
75 * ed_softc: per line info and status
76 */
77struct ed_softc {
78 struct arpcom arpcom; /* ethernet common */
79
80 char *type_str; /* pointer to type string */
81 u_char vendor; /* interface vendor */
82 u_char type; /* interface type code */
83
84 u_short asic_addr; /* ASIC I/O bus address */
85 u_short nic_addr; /* NIC (DS8390) I/O bus address */
86
87/*
88 * The following 'proto' variable is part of a work-around for 8013EBT asics
89 * being write-only. It's sort of a prototype/shadow of the real thing.
90 */
91 u_char wd_laar_proto;
92 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
93 int is790; /* set by the probe code if the card is 790 based */
94
95 caddr_t bpf; /* BPF "magic cookie" */
96 caddr_t mem_start; /* NIC memory start address */
97 caddr_t mem_end; /* NIC memory end address */
98 u_long mem_size; /* total NIC memory size */
99 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
100
101 u_char mem_shared; /* NIC memory is shared with host */
102 u_char xmit_busy; /* transmitter is busy */
103 u_char txb_cnt; /* number of transmit buffers */
104 u_char txb_inuse; /* number of TX buffers currently in-use*/
105
106 u_char txb_new; /* pointer to where new buffer will be added */
107 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
108 u_short txb_len[8]; /* buffered xmit buffer lengths */
109 u_char tx_page_start; /* first page of TX buffer area */
110 u_char rec_page_start; /* first page of RX ring-buffer */
111 u_char rec_page_stop; /* last page of RX ring-buffer */
112 u_char next_packet; /* pointer to next unread RX packet */
113} ed_softc[NED];
114
115int ed_attach(struct isa_device *);
116void ed_init(int);
117void edintr(int);
118int ed_ioctl(struct ifnet *, int, caddr_t);
119int ed_probe(struct isa_device *);
120void ed_start(struct ifnet *);
121void ed_reset(int, int);
122void ed_watchdog(int);
123
124static void ed_get_packet(struct ed_softc *, char *, int /*u_short*/);
125static void ed_stop(int);
126
127static inline void ed_rint();
128static inline void ed_xmit();
129static inline char *ed_ring_copy();
130
131void ed_pio_readmem(), ed_pio_writemem();
132u_short ed_pio_write_mbufs();
133
134extern int ether_output();
135
136struct trailer_header {
137 u_short ether_type;
138 u_short ether_residual;
139};
140
141struct isa_driver eddriver = {
142 ed_probe,
143 ed_attach,
144 "ed"
145};
146/*
147 * Interrupt conversion table for WD/SMC ASIC
148 * (IRQ* are defined in icu.h)
149 */
150static unsigned short ed_intr_mask[] = {
151 IRQ9,
152 IRQ3,
153 IRQ5,
154 IRQ7,
155 IRQ10,
156 IRQ11,
157 IRQ15,
158 IRQ4
159};
160
161/*
162 * Interrupt conversion table for 585/790 Combo
163 */
164static unsigned short ed_790_intr_mask[] = {
165 0,
166 IRQ9,
167 IRQ3,
168 IRQ4,
169 IRQ5,
170 IRQ10,
171 IRQ11,
172 IRQ15
173};
174#define ETHER_MIN_LEN 64
175#define ETHER_MAX_LEN 1518
176#define ETHER_ADDR_LEN 6
177#define ETHER_HDR_SIZE 14
178
179/*
180 * Determine if the device is present
181 *
182 * on entry:
183 * a pointer to an isa_device struct
184 * on exit:
185 * NULL if device not found
186 * or # of i/o addresses used (if found)
187 */
188int
189ed_probe(isa_dev)
190 struct isa_device *isa_dev;
191{
192 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
193 int nports;
194
195 if (nports = ed_probe_WD80x3(isa_dev))
196 return (nports);
197
198 if (nports = ed_probe_3Com(isa_dev))
199 return (nports);
200
201 if (nports = ed_probe_Novell(isa_dev))
202 return (nports);
203
204 return(0);
205}
206
207/*
208 * Generic probe routine for testing for the existance of a DS8390.
209 * Must be called after the NIC has just been reset. This routine
210 * works by looking at certain register values that are gauranteed
211 * to be initialized a certain way after power-up or reset. Seems
212 * not to currently work on the 83C690.
213 *
214 * Specifically:
215 *
216 * Register reset bits set bits
217 * Command Register (CR) TXP, STA RD2, STP
218 * Interrupt Status (ISR) RST
219 * Interrupt Mask (IMR) All bits
220 * Data Control (DCR) LAS
221 * Transmit Config. (TCR) LB1, LB0
222 *
223 * We only look at the CR and ISR registers, however, because looking at
224 * the others would require changing register pages (which would be
225 * intrusive if this isn't an 8390).
226 *
227 * Return 1 if 8390 was found, 0 if not.
228 */
229
230int
231ed_probe_generic8390(sc)
232 struct ed_softc *sc;
233{
234 if ((inb(sc->nic_addr + ED_P0_CR) &
235 (ED_CR_RD2|ED_CR_TXP|ED_CR_STA|ED_CR_STP)) !=
236 (ED_CR_RD2|ED_CR_STP))
237 return (0);
238 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
239 return (0);
240
241 return(1);
242}
243
244/*
245 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
246 */
247int
248ed_probe_WD80x3(isa_dev)
249 struct isa_device *isa_dev;
250{
251 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
252 int i;
253 u_int memsize;
254 u_char iptr, isa16bit, sum;
255
256 sc->asic_addr = isa_dev->id_iobase;
257 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
258 sc->is790 = 0;
259
260#ifdef TOSH_ETHER
261 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
262 DELAY(10000);
263#endif
264 /*
265 * Attempt to do a checksum over the station address PROM.
266 * If it fails, it's probably not a SMC/WD board. There
267 * is a problem with this, though: some clone WD boards
268 * don't pass the checksum test. Danpex boards for one.
269 */
270 for (sum = 0, i = 0; i < 8; ++i)
271 sum += inb(sc->asic_addr + ED_WD_PROM + i);
272
273 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
274 /*
275 * Checksum is invalid. This often happens with cheap
276 * WD8003E clones. In this case, the checksum byte
277 * (the eighth byte) seems to always be zero.
278 */
279 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
280 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
281 return(0);
282 }
283
284 /* reset card to force it into a known state. */
285#ifdef TOSH_ETHER
286 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
287#else
288 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
289#endif
290 DELAY(100);
291 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
292 /* wait in the case this card is reading it's EEROM */
293 DELAY(5000);
294
295 sc->vendor = ED_VENDOR_WD_SMC;
296 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
297
298 /*
299 * Set initial values for width/size.
300 */
301 memsize = 8192;
302 isa16bit = 0;
303 switch (sc->type) {
304 case ED_TYPE_WD8003S:
305 sc->type_str = "WD8003S";
306 break;
307 case ED_TYPE_WD8003E:
308 sc->type_str = "WD8003E";
309 break;
310 case ED_TYPE_WD8003EB:
311 sc->type_str = "WD8003EB";
312 break;
313 case ED_TYPE_WD8003W:
314 sc->type_str = "WD8003W";
315 break;
316 case ED_TYPE_WD8013EBT:
317 sc->type_str = "WD8013EBT";
318 memsize = 16384;
319 isa16bit = 1;
320 break;
321 case ED_TYPE_WD8013W:
322 sc->type_str = "WD8013W";
323 memsize = 16384;
324 isa16bit = 1;
325 break;
326 case ED_TYPE_WD8013EP: /* also WD8003EP */
327 if (inb(sc->asic_addr + ED_WD_ICR)
328 & ED_WD_ICR_16BIT) {
329 isa16bit = 1;
330 memsize = 16384;
331 sc->type_str = "WD8013EP";
332 } else {
333 sc->type_str = "WD8003EP";
334 }
335 break;
336 case ED_TYPE_WD8013WC:
337 sc->type_str = "WD8013WC";
338 memsize = 16384;
339 isa16bit = 1;
340 break;
341 case ED_TYPE_WD8013EBP:
342 sc->type_str = "WD8013EBP";
343 memsize = 16384;
344 isa16bit = 1;
345 break;
346 case ED_TYPE_WD8013EPC:
347 sc->type_str = "WD8013EPC";
348 memsize = 16384;
349 isa16bit = 1;
350 break;
351 case ED_TYPE_SMC8216C:
352 sc->type_str = "SMC8216/SMC8216C";
353 memsize = 16384;
354 isa16bit = 1;
355 sc->is790 = 1;
356 break;
357 case ED_TYPE_SMC8216T:
358 sc->type_str = "SMC8216T";
359 memsize = 16384;
360 isa16bit = 1;
361 sc->is790 = 1;
362 break;
363#ifdef TOSH_ETHER
364 case ED_TYPE_TOSHIBA1:
365 sc->type_str = "Toshiba1";
366 memsize = 32768;
367 isa16bit = 1;
368 break;
369 case ED_TYPE_TOSHIBA4:
370 sc->type_str = "Toshiba4";
371 memsize = 32768;
372 isa16bit = 1;
373 break;
374#endif
375 default:
376 sc->type_str = "";
377 break;
378 }
379 /*
380 * Make some adjustments to initial values depending on what is
381 * found in the ICR.
382 */
383 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
384#ifdef TOSH_ETHER
385 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
386#endif
387 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
388 isa16bit = 0;
389 memsize = 8192;
390 }
391
392#if ED_DEBUG
393 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
394 sc->type,sc->type_str,isa16bit,memsize,isa_dev->id_msize);
395 for (i=0; i<8; i++)
396 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
397#endif
398 /*
399 * Allow the user to override the autoconfiguration
400 */
401 if (isa_dev->id_msize)
402 memsize = isa_dev->id_msize;
403 /*
404 * (note that if the user specifies both of the following flags
405 * that '8bit' mode intentionally has precedence)
406 */
407 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
408 isa16bit = 1;
409 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
410 isa16bit = 0;
411
412 /*
413 * Check 83C584 interrupt configuration register if this board has one
414 * XXX - we could also check the IO address register. But why
415 * bother...if we get past this, it *has* to be correct.
416 */
417 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
418 /*
419 * Assemble together the encoded interrupt number.
420 */
421 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
422 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
423 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
424 /*
425 * Translate it using translation table, and check for correctness.
426 */
427 if (ed_intr_mask[iptr] != isa_dev->id_irq) {
428 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d\n",
429 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_intr_mask[iptr]) - 1);
430 return(0);
431 }
432 /*
433 * Enable the interrupt.
434 */
435 outb(isa_dev->id_iobase + ED_WD_IRR,
436 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
437 }
438 if (sc->is790) {
439 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) | 0x80);
440 iptr = ((inb(isa_dev->id_iobase + 0x0d) & 0x0c ) >> 2) |
441 ((inb(isa_dev->id_iobase + 0x0d) & 0x40) >> 4);
442 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) & ~0x80);
443
444 if (ed_790_intr_mask[iptr] != isa_dev->id_irq) {
445 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d %d\n",
446 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_790_intr_mask[iptr]) -1, iptr);
447 return 0;
448 }
449 outb(isa_dev->id_iobase + 0x06, inb(isa_dev->id_iobase + 0x06) | 0x01);
450 }
451
452 sc->isa16bit = isa16bit;
453
454#ifdef notyet /* XXX - I'm not sure if PIO mode is even possible on WD/SMC boards */
455 /*
456 * The following allows the WD/SMC boards to be used in Programmed I/O
457 * mode - without mapping the NIC memory shared. ...Not the prefered
458 * way, but it might be the only way.
459 */
460 if (isa_dev->id_flags & ED_FLAGS_FORCE_PIO) {
461 sc->mem_shared = 0;
462 isa_dev->id_maddr = 0;
463 } else {
464 sc->mem_shared = 1;
465 }
466#else
467 sc->mem_shared = 1;
468#endif
469 isa_dev->id_msize = memsize;
470
471 sc->mem_start = (caddr_t)isa_dev->id_maddr;
472
473 /*
474 * allocate one xmit buffer if < 16k, two buffers otherwise
475 */
476 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
477 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
478 sc->txb_cnt = 1;
479 sc->rec_page_start = ED_TXBUF_SIZE;
480 } else {
481 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2);
482 sc->txb_cnt = 2;
483 sc->rec_page_start = ED_TXBUF_SIZE * 2;
484 }
485 sc->mem_size = memsize;
486 sc->mem_end = sc->mem_start + memsize;
487 sc->rec_page_stop = memsize / ED_PAGE_SIZE;
488 sc->tx_page_start = ED_WD_PAGE_OFFSET;
489
490 /*
491 * Get station address from on-board ROM
492 */
493 for (i = 0; i < ETHER_ADDR_LEN; ++i)
494 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
495
496 if (sc->mem_shared) {
497 /*
498 * Set address and enable interface shared memory.
499 */
500 if(!sc->is790) {
501#ifdef TOSH_ETHER
502 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
503 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
504 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
505
506#else
507 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
508 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
509#endif
510 } else {
511 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
512 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80));
513 outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
514 ((kvtop(sc->mem_start) >> 11) & 0x40) |
515 (inb(sc->asic_addr + 0x0b) & 0xb0));
516 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80));
517 }
518
519 /*
520 * Set upper address bits and 8/16 bit access to shared memory
521 */
522 if (isa16bit) {
523 if (sc->is790) {
524 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
525 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
526 } else {
527 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
528 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
529 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
530 }
531 } else {
532 if ((sc->type & ED_WD_SOFTCONFIG) ||
533#ifdef TOSH_ETHER
534 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
535#endif
536 (sc->type == ED_TYPE_WD8013EBT) && (!sc->is790)) {
537 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
538 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
539 }
540 }
541
542 /*
543 * Now zero memory and verify that it is clear
544 */
545 bzero(sc->mem_start, memsize);
546
547 for (i = 0; i < memsize; ++i)
548 if (sc->mem_start[i]) {
549 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
550 isa_dev->id_unit, kvtop(sc->mem_start + i));
551
552 /*
553 * Disable 16 bit access to shared memory
554 */
555 if (isa16bit)
556 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
557 ~ED_WD_LAAR_M16EN));
558
559 return(0);
560 }
561
562 /*
563 * Disable 16bit access to shared memory - we leave it disabled so
564 * that 1) machines reboot properly when the board is set
565 * 16 bit mode and there are conflicting 8bit devices/ROMS
566 * in the same 128k address space as this boards shared
567 * memory. and 2) so that other 8 bit devices with shared
568 * memory can be used in this 128k region, too.
569 */
570 if (isa16bit)
571 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
572 ~ED_WD_LAAR_M16EN));
573
574 }
575
576 return (ED_WD_IO_PORTS);
577}
578
579/*
580 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
581 */
582int
583ed_probe_3Com(isa_dev)
584 struct isa_device *isa_dev;
585{
586 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
587 int i;
588 u_int memsize;
589 u_char isa16bit, sum;
590
591 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
592 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
593
594 /*
595 * Verify that the kernel configured I/O address matches the board
596 * configured address
597 */
598 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
599 case ED_3COM_BCFR_300:
600 if (isa_dev->id_iobase != 0x300)
601 return(0);
602 break;
603 case ED_3COM_BCFR_310:
604 if (isa_dev->id_iobase != 0x310)
605 return(0);
606 break;
607 case ED_3COM_BCFR_330:
608 if (isa_dev->id_iobase != 0x330)
609 return(0);
610 break;
611 case ED_3COM_BCFR_350:
612 if (isa_dev->id_iobase != 0x350)
613 return(0);
614 break;
615 case ED_3COM_BCFR_250:
616 if (isa_dev->id_iobase != 0x250)
617 return(0);
618 break;
619 case ED_3COM_BCFR_280:
620 if (isa_dev->id_iobase != 0x280)
621 return(0);
622 break;
623 case ED_3COM_BCFR_2A0:
624 if (isa_dev->id_iobase != 0x2a0)
625 return(0);
626 break;
627 case ED_3COM_BCFR_2E0:
628 if (isa_dev->id_iobase != 0x2e0)
629 return(0);
630 break;
631 default:
632 return(0);
633 }
634
635 /*
636 * Verify that the kernel shared memory address matches the
637 * board configured address.
638 */
639 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
640 case ED_3COM_PCFR_DC000:
641 if (kvtop(isa_dev->id_maddr) != 0xdc000)
642 return(0);
643 break;
644 case ED_3COM_PCFR_D8000:
645 if (kvtop(isa_dev->id_maddr) != 0xd8000)
646 return(0);
647 break;
648 case ED_3COM_PCFR_CC000:
649 if (kvtop(isa_dev->id_maddr) != 0xcc000)
650 return(0);
651 break;
652 case ED_3COM_PCFR_C8000:
653 if (kvtop(isa_dev->id_maddr) != 0xc8000)
654 return(0);
655 break;
656 default:
657 return(0);
658 }
659
660
661 /*
662 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
663 * sequence because it'll lock up if the cable isn't connected
664 * if we don't.
665 */
666 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
667
668 /*
669 * Wait for a while, then un-reset it
670 */
671 DELAY(50);
672 /*
673 * The 3Com ASIC defaults to rather strange settings for the CR after
674 * a reset - it's important to set it again after the following
675 * outb (this is done when we map the PROM below).
676 */
677 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
678
679 /*
680 * Wait a bit for the NIC to recover from the reset
681 */
682 DELAY(5000);
683
684 sc->vendor = ED_VENDOR_3COM;
685 sc->type_str = "3c503";
686
687 sc->mem_shared = 1;
688
689 /*
690 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k
691 * window to it.
692 */
693 memsize = 8192;
694
695 /*
696 * Get station address from on-board ROM
697 */
698 /*
699 * First, map ethernet address PROM over the top of where the NIC
700 * registers normally appear.
701 */
702 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
703
704 for (i = 0; i < ETHER_ADDR_LEN; ++i)
705 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
706
707 /*
708 * Unmap PROM - select NIC registers. The proper setting of the
709 * tranceiver is set in ed_init so that the attach code
710 * is given a chance to set the default based on a compile-time
711 * config option
712 */
713 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
714
715 /*
716 * Determine if this is an 8bit or 16bit board
717 */
718
719 /*
720 * select page 0 registers
721 */
722 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
723
724 /*
725 * Attempt to clear WTS bit. If it doesn't clear, then this is a
726 * 16bit board.
727 */
728 outb(sc->nic_addr + ED_P0_DCR, 0);
729
730 /*
731 * select page 2 registers
732 */
733 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2|ED_CR_RD2|ED_CR_STP);
734
735 /*
736 * The 3c503 forces the WTS bit to a one if this is a 16bit board
737 */
738 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
739 isa16bit = 1;
740 else
741 isa16bit = 0;
742
743 /*
744 * select page 0 registers
745 */
746 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2|ED_CR_STP);
747
748 sc->mem_start = (caddr_t)isa_dev->id_maddr;
749 sc->mem_size = memsize;
750 sc->mem_end = sc->mem_start + memsize;
751
752 /*
753 * We have an entire 8k window to put the transmit buffers on the
754 * 16bit boards. But since the 16bit 3c503's shared memory
755 * is only fast enough to overlap the loading of one full-size
756 * packet, trying to load more than 2 buffers can actually
757 * leave the transmitter idle during the load. So 2 seems
758 * the best value. (Although a mix of variable-sized packets
759 * might change this assumption. Nonetheless, we optimize for
760 * linear transfers of same-size packets.)
761 */
762 if (isa16bit) {
763 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
764 sc->txb_cnt = 1;
765 else
766 sc->txb_cnt = 2;
767
768 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
769 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
770 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
771 ED_3COM_RX_PAGE_OFFSET_16BIT;
772 sc->mem_ring = sc->mem_start;
773 } else {
774 sc->txb_cnt = 1;
775 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
776 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
777 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
778 ED_3COM_TX_PAGE_OFFSET_8BIT;
779 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
780 }
781
782 sc->isa16bit = isa16bit;
783
784 /*
785 * Initialize GA page start/stop registers. Probably only needed
786 * if doing DMA, but what the hell.
787 */
788 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
789 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
790
791 /*
792 * Set IRQ. 3c503 only allows a choice of irq 2-5.
793 */
794 switch (isa_dev->id_irq) {
795 case IRQ2:
796 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
797 break;
798 case IRQ3:
799 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
800 break;
801 case IRQ4:
802 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
803 break;
804 case IRQ5:
805 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
806 break;
807 default:
808 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n",
809 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
810 return(0);
811 }
812
813 /*
814 * Initialize GA configuration register. Set bank and enable shared mem.
815 */
816 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
817 ED_3COM_GACFR_MBS0);
818
819 /*
820 * Initialize "Vector Pointer" registers. These gawd-awful things
821 * are compared to 20 bits of the address on ISA, and if they
822 * match, the shared memory is disabled. We set them to
823 * 0xffff0...allegedly the reset vector.
824 */
825 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
826 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
827 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
828
829 /*
830 * Zero memory and verify that it is clear
831 */
832 bzero(sc->mem_start, memsize);
833
834 for (i = 0; i < memsize; ++i)
835 if (sc->mem_start[i]) {
836 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
837 isa_dev->id_unit, kvtop(sc->mem_start + i));
838 return(0);
839 }
840
841 isa_dev->id_msize = memsize;
842 return(ED_3COM_IO_PORTS);
843}
844
845/*
846 * Probe and vendor-specific initialization routine for NE1000/2000 boards
847 */
848int
849ed_probe_Novell(isa_dev)
850 struct isa_device *isa_dev;
851{
852 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
853 u_int memsize, n;
854 u_char romdata[16], isa16bit = 0, tmp;
855 static char test_pattern[32] = "THIS is A memory TEST pattern";
856 char test_buffer[32];
857
858 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET;
859 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET;
860
861 /* XXX - do Novell-specific probe here */
862
863 /* Reset the board */
864 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
865
866 /*
867 * I don't know if this is necessary; probably cruft leftover from
868 * Clarkson packet driver code. Doesn't do a thing on the boards
869 * I've tested. -DG [note that a outb(0x84, 0) seems to work
870 * here, and is non-invasive...but some boards don't seem to reset
871 * and I don't have complete documentation on what the 'right'
872 * thing to do is...so we do the invasive thing for now. Yuck.]
873 */
874 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
875 DELAY(5000);
876
877 /*
878 * This is needed because some NE clones apparently don't reset the
879 * NIC properly (or the NIC chip doesn't reset fully on power-up)
880 * XXX - this makes the probe invasive! ...Done against my better
881 * judgement. -DLG
882 */
883 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
884
885 DELAY(5000);
886
887 /* Make sure that we really have an 8390 based board */
888 if (!ed_probe_generic8390(sc))
889 return(0);
890
891 sc->vendor = ED_VENDOR_NOVELL;
892 sc->mem_shared = 0;
893 isa_dev->id_maddr = 0;
894
895 /*
896 * Test the ability to read and write to the NIC memory. This has
897 * the side affect of determining if this is an NE1000 or an NE2000.
898 */
899
900 /*
901 * This prevents packets from being stored in the NIC memory when
902 * the readmem routine turns on the start bit in the CR.
903 */
904 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
905
906 /* Temporarily initialize DCR for byte operations */
907 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
908
909 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
910 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
911
912 sc->isa16bit = 0;
913
914 /*
915 * Write a test pattern in byte mode. If this fails, then there
916 * probably isn't any memory at 8k - which likely means
917 * that the board is an NE2000.
918 */
919 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
920 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
921
922 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
923 /* not an NE1000 - try NE2000 */
924
925 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS|ED_DCR_FT1|ED_DCR_LS);
926 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
927 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
928
929 sc->isa16bit = 1;
930 /*
931 * Write a test pattern in word mode. If this also fails, then
932 * we don't know what this board is.
933 */
934 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
935 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
936
937 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
938 return(0); /* not an NE2000 either */
939
940 sc->type = ED_TYPE_NE2000;
941 sc->type_str = "NE2000";
942 } else {
943 sc->type = ED_TYPE_NE1000;
944 sc->type_str = "NE1000";
945 }
946
947 /* 8k of memory plus an additional 8k if 16bit */
948 memsize = 8192 + sc->isa16bit * 8192;
949
950#if 0 /* probably not useful - NE boards only come two ways */
951 /* allow kernel config file overrides */
952 if (isa_dev->id_msize)
953 memsize = isa_dev->id_msize;
954#endif
955
956 sc->mem_size = memsize;
957
958 /* NIC memory doesn't start at zero on an NE board */
959 /* The start address is tied to the bus width */
960 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
961 sc->mem_end = sc->mem_start + memsize;
962 sc->tx_page_start = memsize / ED_PAGE_SIZE;
963
964 /*
965 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
966 * otherwise).
967 */
968 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING))
969 sc->txb_cnt = 1;
970 else
971 sc->txb_cnt = 2;
972
973 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
974 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
975
976 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
977
978 ed_pio_readmem(sc, 0, romdata, 16);
979 for (n = 0; n < ETHER_ADDR_LEN; n++)
980 sc->arpcom.ac_enaddr[n] = romdata[n*(sc->isa16bit+1)];
981
982 /* clear any pending interrupts that might have occurred above */
983 outb(sc->nic_addr + ED_P0_ISR, 0xff);
984
985 return(ED_NOVELL_IO_PORTS);
986}
987
988/*
989 * Install interface into kernel networking data structures
990 */
991int
992ed_attach(isa_dev)
993 struct isa_device *isa_dev;
994{
995 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
996 struct ifnet *ifp = &sc->arpcom.ac_if;
997 struct ifaddr *ifa;
998 struct sockaddr_dl *sdl;
999
1000 /*
1001 * Set interface to stopped condition (reset)
1002 */
1003 ed_stop(isa_dev->id_unit);
1004
1005 /*
1006 * Initialize ifnet structure
1007 */
1008 ifp->if_unit = isa_dev->id_unit;
1009 ifp->if_name = "ed" ;
1010 ifp->if_mtu = ETHERMTU;
1011 ifp->if_init = ed_init;
1012 ifp->if_output = ether_output;
1013 ifp->if_start = ed_start;
1014 ifp->if_ioctl = ed_ioctl;
1015 ifp->if_reset = ed_reset;
1016 ifp->if_watchdog = ed_watchdog;
1017
1018 /*
1019 * Set default state for ALTPHYS flag (used to disable the tranceiver
1020 * for AUI operation), based on compile-time config option.
1021 */
1022 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER)
1023 ifp->if_flags =
1024 (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_ALTPHYS);
1025 else
1026 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS);
1027
1028 /*
1029 * Attach the interface
1030 */
1031 if_attach(ifp);
1032
1033 /*
1034 * Search down the ifa address list looking for the AF_LINK type entry
1035 */
1036 ifa = ifp->if_addrlist;
1037 while ((ifa != 0) && (ifa->ifa_addr != 0) &&
1038 (ifa->ifa_addr->sa_family != AF_LINK))
1039 ifa = ifa->ifa_next;
1040 /*
1041 * If we find an AF_LINK type entry we fill in the hardware address.
1042 * This is useful for netstat(1) to keep track of which interface
1043 * is which.
1044 */
1045 if ((ifa != 0) && (ifa->ifa_addr != 0)) {
1046 /*
1047 * Fill in the link-level address for this interface
1048 */
1049 sdl = (struct sockaddr_dl *)ifa->ifa_addr;
1050 sdl->sdl_type = IFT_ETHER;
1051 sdl->sdl_alen = ETHER_ADDR_LEN;
1052 sdl->sdl_slen = 0;
1053 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN);
1054 }
1055
1056 /*
1057 * Print additional info when attached
1058 */
1059 printf("ed%d: address %s, ", isa_dev->id_unit,
1060 ether_sprintf(sc->arpcom.ac_enaddr));
1061
1062 if (sc->type_str && (*sc->type_str != 0))
1063 printf("type %s ", sc->type_str);
1064 else
1065 printf("type unknown (0x%x) ", sc->type);
1066
1067 printf("%s ",sc->isa16bit ? "(16 bit)" : "(8 bit)");
1068
1069 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) &&
1070 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1071
1072 /*
1073 * If BPF is in the kernel, call the attach for it
1074 */
1075#if NBPFILTER > 0
1076 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
1077#endif
1078 return 1;
1079}
1080
1081/*
1082 * Reset interface.
1083 */
1084void
1085ed_reset(unit, uban)
1086 int unit;
1087 int uban; /* XXX */
1088{
1089 int s;
1090
1091 s = splimp();
1092
1093 /*
1094 * Stop interface and re-initialize.
1095 */
1096 ed_stop(unit);
1097 ed_init(unit);
1098
1099 (void) splx(s);
1100}
1101
1102/*
1103 * Take interface offline.
1104 */
1105void
1106ed_stop(unit)
1107 int unit;
1108{
1109 struct ed_softc *sc = &ed_softc[unit];
1110 int n = 5000;
1111
1112 /*
1113 * Stop everything on the interface, and select page 0 registers.
1114 */
1115 if (sc->is790) {
1116 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1117 } else {
1118 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1119 }
1120 /*
1121 * Wait for interface to enter stopped state, but limit # of checks
1122 * to 'n' (about 5ms). It shouldn't even take 5us on modern
1123 * DS8390's, but just in case it's an old one.
1124 */
1125 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1126
1127}
1128
1129/*
1130 * Device timeout/watchdog routine. Entered if the device neglects to
1131 * generate an interrupt after a transmit has been started on it.
1132 */
1133void
1134ed_watchdog(unit)
1135 int unit;
1136{
1137 struct ed_softc *sc = &ed_softc[unit];
1138
1139 log(LOG_ERR, "ed%d: device timeout\n", unit);
1140 ++sc->arpcom.ac_if.if_oerrors;
1141
1142 ed_reset(unit, 0);
1143}
1144
1145/*
1146 * Initialize device.
1147 */
1148void
1149ed_init(unit)
1150 int unit;
1151{
1152 struct ed_softc *sc = &ed_softc[unit];
1153 struct ifnet *ifp = &sc->arpcom.ac_if;
1154 int i, s;
1155 u_char command;
1156
1157
1158 /* address not known */
1159 if (ifp->if_addrlist == (struct ifaddr *)0) return;
1160
1161 /*
1162 * Initialize the NIC in the exact order outlined in the NS manual.
1163 * This init procedure is "mandatory"...don't change what or when
1164 * things happen.
1165 */
1166 s = splimp();
1167
1168 /* reset transmitter flags */
1169 sc->xmit_busy = 0;
1170 sc->arpcom.ac_if.if_timer = 0;
1171
1172 sc->txb_inuse = 0;
1173 sc->txb_new = 0;
1174 sc->txb_next_tx = 0;
1175
1176 /* This variable is used below - don't move this assignment */
1177 sc->next_packet = sc->rec_page_start + 1;
1178
1179 /*
1180 * Set interface for page 0, Remote DMA complete, Stopped
1181 */
1182 if (sc->is790) {
1183 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1184 } else {
1185 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1186 }
1187 if (sc->isa16bit) {
1188 /*
1189 * Set FIFO threshold to 8, No auto-init Remote DMA,
1190 * byte order=80x86, word-wide DMA xfers,
1191 */
1192 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS|ED_DCR_LS);
1193 } else {
1194 /*
1195 * Same as above, but byte-wide DMA xfers
1196 */
1197 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
1198 }
1199
1200 /*
1201 * Clear Remote Byte Count Registers
1202 */
1203 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1204 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1205
1206 /*
1207 * Enable reception of broadcast packets
1208 */
1209 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
1210
1211 /*
1212 * Place NIC in internal loopback mode
1213 */
1214 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1215
1216 /*
1217 * Initialize transmit/receive (ring-buffer) Page Start
1218 */
1219 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1220 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1221 /* Set lower bits of byte addressable framing to 0 */
1222 if (sc->is790)
1223 outb(sc->nic_addr + 0x09, 0);
1224
1225 /*
1226 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1227 */
1228 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1229 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1230
1231 /*
1232 * Clear all interrupts. A '1' in each bit position clears the
1233 * corresponding flag.
1234 */
1235 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1236
1237 /*
1238 * Enable the following interrupts: receive/transmit complete,
1239 * receive/transmit error, and Receiver OverWrite.
1240 *
1241 * Counter overflow and Remote DMA complete are *not* enabled.
1242 */
1243 outb(sc->nic_addr + ED_P0_IMR,
1244 ED_IMR_PRXE|ED_IMR_PTXE|ED_IMR_RXEE|ED_IMR_TXEE|ED_IMR_OVWE);
1245
1246 /*
1247 * Program Command Register for page 1
1248 */
1249 if (sc->is790) {
1250 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STP);
1251 } else {
1252 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STP);
1253 }
1254 /*
1255 * Copy out our station address
1256 */
1257 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1258 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1259
1260#if NBPFILTER > 0
1261 /*
1262 * Initialize multicast address hashing registers to accept
1263 * all multicasts (only used when in promiscuous mode)
1264 */
1265 for (i = 0; i < 8; ++i)
1266 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
1267#endif
1268
1269 /*
1270 * Set Current Page pointer to next_packet (initialized above)
1271 */
1272 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1273
1274 /*
1275 * Set Command Register for page 0, Remote DMA complete,
1276 * and interface Start.
1277 */
1278 if (sc->is790) {
1279 outb(sc->nic_addr + ED_P1_CR, ED_CR_STA);
1280 } else {
1281 outb(sc->nic_addr + ED_P1_CR, ED_CR_RD2|ED_CR_STA);
1282 }
1283 /*
1284 * Take interface out of loopback
1285 */
1286 outb(sc->nic_addr + ED_P0_TCR, 0);
1287
1288 /*
1289 * If this is a 3Com board, the tranceiver must be software enabled
1290 * (there is no settable hardware default).
1291 */
1292 if (sc->vendor == ED_VENDOR_3COM) {
1293 if (ifp->if_flags & IFF_ALTPHYS) {
1294 outb(sc->asic_addr + ED_3COM_CR, 0);
1295 } else {
1296 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1297 }
1298 }
1299
1300 /*
1301 * Set 'running' flag, and clear output active flag.
1302 */
1303 ifp->if_flags |= IFF_RUNNING;
1304 ifp->if_flags &= ~IFF_OACTIVE;
1305
1306 /*
1307 * ...and attempt to start output
1308 */
1309 ed_start(ifp);
1310
1311 (void) splx(s);
1312}
1313
1314/*
1315 * This routine actually starts the transmission on the interface
1316 */
1317static inline void ed_xmit(ifp)
1318 struct ifnet *ifp;
1319{
1320 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1321 unsigned short len;
1322
1323 len = sc->txb_len[sc->txb_next_tx];
1324
1325 /*
1326 * Set NIC for page 0 register access
1327 */
1328 if (sc->is790) {
1329 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1330 } else {
1331 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1332 }
1333 /*
1334 * Set TX buffer start page
1335 */
1336 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1337 sc->txb_next_tx * ED_TXBUF_SIZE);
1338
1339 /*
1340 * Set TX length
1341 */
1342 outb(sc->nic_addr + ED_P0_TBCR0, len);
1343 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
1344
1345 /*
1346 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1347 */
1348 if (sc->is790) {
1349 outb(sc->nic_addr + ED_P0_CR, ED_CR_TXP | ED_CR_STA);
1350 } else {
1351 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA);
1352 }
1353 sc->xmit_busy = 1;
1354
1355 /*
1356 * Point to next transmit buffer slot and wrap if necessary.
1357 */
1358 sc->txb_next_tx++;
1359 if (sc->txb_next_tx == sc->txb_cnt)
1360 sc->txb_next_tx = 0;
1361
1362 /*
1363 * Set a timer just in case we never hear from the board again
1364 */
1365 ifp->if_timer = 2;
1366}
1367
1368/*
1369 * Start output on interface.
1370 * We make two assumptions here:
1371 * 1) that the current priority is set to splimp _before_ this code
1372 * is called *and* is returned to the appropriate priority after
1373 * return
1374 * 2) that the IFF_OACTIVE flag is checked before this code is called
1375 * (i.e. that the output part of the interface is idle)
1376 */
1377void
1378ed_start(ifp)
1379 struct ifnet *ifp;
1380{
1381 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1382 struct mbuf *m0, *m;
1383 caddr_t buffer;
1384 int len;
1385
1386outloop:
1387 /*
1388 * First, see if there are buffered packets and an idle
1389 * transmitter - should never happen at this point.
1390 */
1391 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1392 printf("ed: packets buffers, but transmitter idle\n");
1393 ed_xmit(ifp);
1394 }
1395
1396 /*
1397 * See if there is room to put another packet in the buffer.
1398 */
1399 if (sc->txb_inuse == sc->txb_cnt) {
1400 /*
1401 * No room. Indicate this to the outside world
1402 * and exit.
1403 */
1404 ifp->if_flags |= IFF_OACTIVE;
1405 return;
1406 }
1407
1408 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m);
1409 if (m == 0) {
1410 /*
1411 * We are using the !OACTIVE flag to indicate to the outside
1412 * world that we can accept an additional packet rather than
1413 * that the transmitter is _actually_ active. Indeed, the
1414 * transmitter may be active, but if we haven't filled all
1415 * the buffers with data then we still want to accept more.
1416 */
1417 ifp->if_flags &= ~IFF_OACTIVE;
1418 return;
1419 }
1420
1421 /*
1422 * Copy the mbuf chain into the transmit buffer
1423 */
1424
1425 m0 = m;
1426
1427 /* txb_new points to next open buffer slot */
1428 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
1429
1430 if (sc->mem_shared) {
1431 /*
1432 * Special case setup for 16 bit boards...
1433 */
1434 if (sc->isa16bit) {
1435 switch (sc->vendor) {
1436 /*
1437 * For 16bit 3Com boards (which have 16k of memory),
1438 * we have the xmit buffers in a different page
1439 * of memory ('page 0') - so change pages.
1440 */
1441 case ED_VENDOR_3COM:
1442 outb(sc->asic_addr + ED_3COM_GACFR,
1443 ED_3COM_GACFR_RSEL);
1444 break;
1445 /*
1446 * Enable 16bit access to shared memory on WD/SMC boards
1447 * Don't update wd_laar_proto because we want to restore the
1448 * previous state (because an arp reply in the input code
1449 * may cause a call-back to ed_start)
1450 * XXX - the call-back to 'start' is a bug, IMHO.
1451 */
1452 case ED_VENDOR_WD_SMC:
1453 outb(sc->asic_addr + ED_WD_LAAR,
1454 (sc->wd_laar_proto | ED_WD_LAAR_M16EN));
1455 }
1456 }
1457
1458 for (len = 0; m != 0; m = m->m_next) {
1459 bcopy(mtod(m, caddr_t), buffer, m->m_len);
1460 buffer += m->m_len;
1461 len += m->m_len;
1462 }
1463
1464 /*
1465 * Restore previous shared memory access
1466 */
1467 if (sc->isa16bit) {
1468 switch (sc->vendor) {
1469 case ED_VENDOR_3COM:
1470 outb(sc->asic_addr + ED_3COM_GACFR,
1471 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
1472 break;
1473 case ED_VENDOR_WD_SMC:
1474 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
1475 break;
1476 }
1477 }
1478 } else {
1479 len = ed_pio_write_mbufs(sc, m, buffer);
1480 }
1481
1482 sc->txb_len[sc->txb_new] = MAX(len, ETHER_MIN_LEN);
1483
1484 sc->txb_inuse++;
1485
1486 /*
1487 * Point to next buffer slot and wrap if necessary.
1488 */
1489 sc->txb_new++;
1490 if (sc->txb_new == sc->txb_cnt)
1491 sc->txb_new = 0;
1492
1493 if (sc->xmit_busy == 0)
1494 ed_xmit(ifp);
1495 /*
1496 * If there is BPF support in the configuration, tap off here.
1497 * The following has support for converting trailer packets
1498 * back to normal.
1499 * XXX - support for trailer packets in BPF should be moved into
1500 * the bpf code proper to avoid code duplication in all of
1501 * the drivers.
1502 */
1503#if NBPFILTER > 0
1504 if (sc->bpf) {
1505 u_short etype;
1506 int off, datasize, resid;
1507 struct ether_header *eh;
1508 struct trailer_header trailer_header;
1509 char ether_packet[ETHER_MAX_LEN];
1510 char *ep;
1511
1512 ep = ether_packet;
1513
1514 /*
1515 * We handle trailers below:
1516 * Copy ether header first, then residual data,
1517 * then data. Put all this in a temporary buffer
1518 * 'ether_packet' and send off to bpf. Since the
1519 * system has generated this packet, we assume
1520 * that all of the offsets in the packet are
1521 * correct; if they're not, the system will almost
1522 * certainly crash in m_copydata.
1523 * We make no assumptions about how the data is
1524 * arranged in the mbuf chain (i.e. how much
1525 * data is in each mbuf, if mbuf clusters are
1526 * used, etc.), which is why we use m_copydata
1527 * to get the ether header rather than assume
1528 * that this is located in the first mbuf.
1529 */
1530 /* copy ether header */
1531 m_copydata(m0, 0, sizeof(struct ether_header), ep);
1532 eh = (struct ether_header *) ep;
1533 ep += sizeof(struct ether_header);
1534 etype = ntohs(eh->ether_type);
1535 if (etype >= ETHERTYPE_TRAIL &&
1536 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
1537 datasize = ((etype - ETHERTYPE_TRAIL) << 9);
1538 off = datasize + sizeof(struct ether_header);
1539
1540 /* copy trailer_header into a data structure */
1541 m_copydata(m0, off, sizeof(struct trailer_header),
1542 (caddr_t)&trailer_header.ether_type);
1543
1544 /* copy residual data */
1545 m_copydata(m0, off+sizeof(struct trailer_header),
1546 resid = ntohs(trailer_header.ether_residual) -
1547 sizeof(struct trailer_header), ep);
1548 ep += resid;
1549
1550 /* copy data */
1551 m_copydata(m0, sizeof(struct ether_header),
1552 datasize, ep);
1553 ep += datasize;
1554
1555 /* restore original ether packet type */
1556 eh->ether_type = trailer_header.ether_type;
1557
1558 bpf_tap(sc->bpf, ether_packet, ep - ether_packet);
1559 } else
1560 bpf_mtap(sc->bpf, m0);
1561 }
1562#endif
1563
1564 m_freem(m0);
1565
1566 /*
1567 * Loop back to the top to possibly buffer more packets
1568 */
1569 goto outloop;
1570}
1571
1572/*
1573 * Ethernet interface receiver interrupt.
1574 */
1575static inline void
1576ed_rint(unit)
1577 int unit;
1578{
1579 register struct ed_softc *sc = &ed_softc[unit];
1580 u_char boundry, current;
1581 u_short len;
1582 struct ed_ring packet_hdr;
1583 char *packet_ptr;
1584
1585 /*
1586 * Set NIC to page 1 registers to get 'current' pointer
1587 */
1588 if (sc->is790) {
1589 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1590 } else {
1591 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1592 }
1593 /*
1594 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
1595 * it points to where new data has been buffered. The 'CURR'
1596 * (current) register points to the logical end of the ring-buffer
1597 * - i.e. it points to where additional new data will be added.
1598 * We loop here until the logical beginning equals the logical
1599 * end (or in other words, until the ring-buffer is empty).
1600 */
1601 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
1602
1603 /* get pointer to this buffer's header structure */
1604 packet_ptr = sc->mem_ring +
1605 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
1606
1607 /*
1608 * The byte count includes the FCS - Frame Check Sequence (a
1609 * 32 bit CRC).
1610 */
1611 if (sc->mem_shared)
1612 packet_hdr = *(struct ed_ring *)packet_ptr;
1613 else
1614 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr,
1615 sizeof(packet_hdr));
1616 len = packet_hdr.count;
1617 if ((len >= ETHER_MIN_LEN) && (len <= ETHER_MAX_LEN)) {
1618 /*
1619 * Go get packet. len - 4 removes CRC from length.
1620 */
1621 ed_get_packet(sc, packet_ptr + 4, len - 4);
1622 ++sc->arpcom.ac_if.if_ipackets;
1623 } else {
1624 /*
1625 * Really BAD...probably indicates that the ring pointers
1626 * are corrupted. Also seen on early rev chips under
1627 * high load - the byte order of the length gets switched.
1628 */
1629 log(LOG_ERR,
1630 "ed%d: NIC memory corrupt - invalid packet length %d\n",
1631 unit, len);
1632 ++sc->arpcom.ac_if.if_ierrors;
1633 ed_reset(unit, 0);
1634 return;
1635 }
1636
1637 /*
1638 * Update next packet pointer
1639 */
1640 sc->next_packet = packet_hdr.next_packet;
1641
1642 /*
1643 * Update NIC boundry pointer - being careful to keep it
1644 * one buffer behind. (as recommended by NS databook)
1645 */
1646 boundry = sc->next_packet - 1;
1647 if (boundry < sc->rec_page_start)
1648 boundry = sc->rec_page_stop - 1;
1649
1650 /*
1651 * Set NIC to page 0 registers to update boundry register
1652 */
1653 if (sc->is790) {
1654 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1655 } else {
1656 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1657 }
1658 outb(sc->nic_addr + ED_P0_BNRY, boundry);
1659
1660 /*
1661 * Set NIC to page 1 registers before looping to top (prepare to
1662 * get 'CURR' current pointer)
1663 */
1664 if (sc->is790) {
1665 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1666 } else {
1667 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1668 }
1669 }
1670}
1671
1672/*
1673 * Ethernet interface interrupt processor
1674 */
1675void
1676edintr(unit)
1677 int unit;
1678{
1679 struct ed_softc *sc = &ed_softc[unit];
1680 u_char isr;
1681
1682 /*
1683 * Set NIC to page 0 registers
1684 */
1685 if (sc->is790) {
1686 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1687 } else {
1688 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1689 }
1690 /*
1691 * loop until there are no more new interrupts
1692 */
1693 while (isr = inb(sc->nic_addr + ED_P0_ISR)) {
1694
1695 /*
1696 * reset all the bits that we are 'acknowledging'
1697 * by writing a '1' to each bit position that was set
1698 * (writing a '1' *clears* the bit)
1699 */
1700 outb(sc->nic_addr + ED_P0_ISR, isr);
1701
1702 /*
1703 * Handle transmitter interrupts. Handle these first
1704 * because the receiver will reset the board under
1705 * some conditions.
1706 */
1707 if (isr & (ED_ISR_PTX|ED_ISR_TXE)) {
1708 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
1709
1710 /*
1711 * Check for transmit error. If a TX completed with an
1712 * error, we end up throwing the packet away. Really
1713 * the only error that is possible is excessive
1714 * collisions, and in this case it is best to allow the
1715 * automatic mechanisms of TCP to backoff the flow. Of
1716 * course, with UDP we're screwed, but this is expected
1717 * when a network is heavily loaded.
1718 */
1719 (void) inb(sc->nic_addr + ED_P0_TSR);
1720 if (isr & ED_ISR_TXE) {
1721
1722 /*
1723 * Excessive collisions (16)
1724 */
1725 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT)
1726 && (collisions == 0)) {
1727 /*
1728 * When collisions total 16, the
1729 * P0_NCR will indicate 0, and the
1730 * TSR_ABT is set.
1731 */
1732 collisions = 16;
1733 }
1734
1735 /*
1736 * update output errors counter
1737 */
1738 ++sc->arpcom.ac_if.if_oerrors;
1739 } else {
1740 /*
1741 * Update total number of successfully
1742 * transmitted packets.
1743 */
1744 ++sc->arpcom.ac_if.if_opackets;
1745 }
1746
1747 /*
1748 * reset tx busy and output active flags
1749 */
1750 sc->xmit_busy = 0;
1751 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
1752
1753 /*
1754 * clear watchdog timer
1755 */
1756 sc->arpcom.ac_if.if_timer = 0;
1757
1758 /*
1759 * Add in total number of collisions on last
1760 * transmission.
1761 */
1762 sc->arpcom.ac_if.if_collisions += collisions;
1763
1764 /*
1765 * Decrement buffer in-use count if not zero (can only
1766 * be zero if a transmitter interrupt occured while
1767 * not actually transmitting).
1768 * If data is ready to transmit, start it transmitting,
1769 * otherwise defer until after handling receiver
1770 */
1771 if (sc->txb_inuse && --sc->txb_inuse)
1772 ed_xmit(&sc->arpcom.ac_if);
1773 }
1774
1775 /*
1776 * Handle receiver interrupts
1777 */
1778 if (isr & (ED_ISR_PRX|ED_ISR_RXE|ED_ISR_OVW)) {
1779 /*
1780 * Overwrite warning. In order to make sure that a lockup
1781 * of the local DMA hasn't occurred, we reset and
1782 * re-init the NIC. The NSC manual suggests only a
1783 * partial reset/re-init is necessary - but some
1784 * chips seem to want more. The DMA lockup has been
1785 * seen only with early rev chips - Methinks this
1786 * bug was fixed in later revs. -DG
1787 */
1788 if (isr & ED_ISR_OVW) {
1789 ++sc->arpcom.ac_if.if_ierrors;
1790#ifdef DIAGNOSTIC
1791 log(LOG_WARNING,
1792 "ed%d: warning - receiver ring buffer overrun\n",
1793 unit);
1794#endif
1795 /*
1796 * Stop/reset/re-init NIC
1797 */
1798 ed_reset(unit, 0);
1799 } else {
1800
1801 /*
1802 * Receiver Error. One or more of: CRC error, frame
1803 * alignment error FIFO overrun, or missed packet.
1804 */
1805 if (isr & ED_ISR_RXE) {
1806 ++sc->arpcom.ac_if.if_ierrors;
1807#ifdef ED_DEBUG
1808 printf("ed%d: receive error %x\n", unit,
1809 inb(sc->nic_addr + ED_P0_RSR));
1810#endif
1811 }
1812
1813 /*
1814 * Go get the packet(s)
1815 * XXX - Doing this on an error is dubious
1816 * because there shouldn't be any data to
1817 * get (we've configured the interface to
1818 * not accept packets with errors).
1819 */
1820
1821 /*
1822 * Enable 16bit access to shared memory first
1823 * on WD/SMC boards.
1824 */
1825 if (sc->isa16bit &&
1826 (sc->vendor == ED_VENDOR_WD_SMC)) {
1827
1828 outb(sc->asic_addr + ED_WD_LAAR,
1829 (sc->wd_laar_proto |=
1830 ED_WD_LAAR_M16EN));
1831 }
1832
1833 ed_rint (unit);
1834
1835 /* disable 16bit access */
1836 if (sc->isa16bit &&
1837 (sc->vendor == ED_VENDOR_WD_SMC)) {
1838
1839 outb(sc->asic_addr + ED_WD_LAAR,
1840 (sc->wd_laar_proto &=
1841 ~ED_WD_LAAR_M16EN));
1842 }
1843 }
1844 }
1845
1846 /*
1847 * If it looks like the transmitter can take more data,
1848 * attempt to start output on the interface.
1849 * This is done after handling the receiver to
1850 * give the receiver priority.
1851 */
1852 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0)
1853 ed_start(&sc->arpcom.ac_if);
1854
1855 /*
1856 * return NIC CR to standard state: page 0, remote DMA complete,
1857 * start (toggling the TXP bit off, even if was just set
1858 * in the transmit routine, is *okay* - it is 'edge'
1859 * triggered from low to high)
1860 */
1861 if (sc->is790) {
1862 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1863 } else {
1864 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1865 }
1866 /*
1867 * If the Network Talley Counters overflow, read them to
1868 * reset them. It appears that old 8390's won't
1869 * clear the ISR flag otherwise - resulting in an
1870 * infinite loop.
1871 */
1872 if (isr & ED_ISR_CNT) {
1873 (void) inb(sc->nic_addr + ED_P0_CNTR0);
1874 (void) inb(sc->nic_addr + ED_P0_CNTR1);
1875 (void) inb(sc->nic_addr + ED_P0_CNTR2);
1876 }
1877 }
1878}
1879
1880/*
1881 * Process an ioctl request. This code needs some work - it looks
1882 * pretty ugly.
1883 */
1884int
1885ed_ioctl(ifp, command, data)
1886 register struct ifnet *ifp;
1887 int command;
1888 caddr_t data;
1889{
1890 register struct ifaddr *ifa = (struct ifaddr *)data;
1891 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1892 struct ifreq *ifr = (struct ifreq *)data;
1893 int s, error = 0;
1894
1895 s = splimp();
1896
1897 switch (command) {
1898
1899 case SIOCSIFADDR:
1900 ifp->if_flags |= IFF_UP;
1901
1902 switch (ifa->ifa_addr->sa_family) {
1903#ifdef INET
1904 case AF_INET:
1905 ed_init(ifp->if_unit); /* before arpwhohas */
1906 /*
1907 * See if another station has *our* IP address.
1908 * i.e.: There is an address conflict! If a
1909 * conflict exists, a message is sent to the
1910 * console.
1911 */
1912 ((struct arpcom *)ifp)->ac_ipaddr = IA_SIN(ifa)->sin_addr;
1913 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr);
1914 break;
1915#endif
1916#ifdef NS
1917 /*
1918 * XXX - This code is probably wrong
1919 */
1920 case AF_NS:
1921 {
1922 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
1923
1924 if (ns_nullhost(*ina))
1925 ina->x_host =
1926 *(union ns_host *)(sc->arpcom.ac_enaddr);
1927 else {
1928 /*
1929 *
1930 */
1931 bcopy((caddr_t)ina->x_host.c_host,
1932 (caddr_t)sc->arpcom.ac_enaddr,
1933 sizeof(sc->arpcom.ac_enaddr));
1934 }
1935 /*
1936 * Set new address
1937 */
1938 ed_init(ifp->if_unit);
1939 break;
1940 }
1941#endif
1942 default:
1943 ed_init(ifp->if_unit);
1944 break;
1945 }
1946 break;
1947
1948 case SIOCGIFADDR:
1949 {
1950 struct sockaddr *sa;
1951 sa = (struct sockaddr *)&ifr->ifr_data;
1952 bcopy((caddr_t)sc->arpcom.ac_enaddr,
1953 (caddr_t) sa->sa_data, ETHER_ADDR_LEN);
1954 }
1955 break;
1956
1957 case SIOCSIFFLAGS:
1958 /*
1959 * If interface is marked down and it is running, then stop it
1960 */
1961 if (((ifp->if_flags & IFF_UP) == 0) &&
1962 (ifp->if_flags & IFF_RUNNING)) {
1963 ed_stop(ifp->if_unit);
1964 ifp->if_flags &= ~IFF_RUNNING;
1965 } else {
1966 /*
1967 * If interface is marked up and it is stopped, then start it
1968 */
1969 if ((ifp->if_flags & IFF_UP) &&
1970 ((ifp->if_flags & IFF_RUNNING) == 0))
1971 ed_init(ifp->if_unit);
1972 }
1973#if NBPFILTER > 0
1974 if (ifp->if_flags & IFF_PROMISC) {
1975 /*
1976 * Set promiscuous mode on interface.
1977 * XXX - for multicasts to work, we would need to
1978 * write 1's in all bits of multicast
1979 * hashing array. For now we assume that
1980 * this was done in ed_init().
1981 */
1982 outb(sc->nic_addr + ED_P0_RCR,
1983 ED_RCR_PRO|ED_RCR_AM|ED_RCR_AB);
1984 } else {
1985 /*
1986 * XXX - for multicasts to work, we would need to
1987 * rewrite the multicast hashing array with the
1988 * proper hash (would have been destroyed above).
1989 */
1990 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
1991 }
1992#endif
1993 /*
1994 * An unfortunate hack to provide the (required) software control
1995 * of the tranceiver for 3Com boards. The ALTPHYS flag disables
1996 * the tranceiver if set.
1997 */
1998 if (sc->vendor == ED_VENDOR_3COM) {
1999 if (ifp->if_flags & IFF_ALTPHYS) {
2000 outb(sc->asic_addr + ED_3COM_CR, 0);
2001 } else {
2002 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2003 }
2004 }
2005
2006 break;
2007
2008 default:
2009 error = EINVAL;
2010 }
2011 (void) splx(s);
2012 return (error);
2013}
2014
2015/*
2016 * Macro to calculate a new address within shared memory when given an offset
2017 * from an address, taking into account ring-wrap.
2018 */
2019#define ringoffset(sc, start, off, type) \
2020 ((type)( ((caddr_t)(start)+(off) >= (sc)->mem_end) ? \
2021 (((caddr_t)(start)+(off))) - (sc)->mem_end \
2022 + (sc)->mem_ring: \
2023 ((caddr_t)(start)+(off)) ))
2024
2025/*
2026 * Retreive packet from shared memory and send to the next level up via
2027 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2028 */
2029static void
2030ed_get_packet(sc, buf, len)
2031 struct ed_softc *sc;
2032 char *buf;
2033 u_short len;
2034{
2035 struct ether_header *eh;
2036 struct mbuf *m, *head = 0, *ed_ring_to_mbuf();
2037 u_short off;
2038 int resid;
2039 u_short etype;
2040 struct trailer_header trailer_header;
2041
2042 /* Allocate a header mbuf */
2043 MGETHDR(m, M_DONTWAIT, MT_DATA);
2044 if (m == 0)
2045 goto bad;
2046 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2047 m->m_pkthdr.len = len;
2048 m->m_len = 0;
2049 head = m;
2050
2051 /* The following sillines is to make NFS happy */
2052#define EROUND ((sizeof(struct ether_header) + 3) & ~3)
2053#define EOFF (EROUND - sizeof(struct ether_header))
2054
2055 /*
2056 * The following assumes there is room for
2057 * the ether header in the header mbuf
2058 */
2059 head->m_data += EOFF;
2060 eh = mtod(head, struct ether_header *);
2061
2062 if (sc->mem_shared)
2063 bcopy(buf, mtod(head, caddr_t), sizeof(struct ether_header));
2064 else
2065 ed_pio_readmem(sc, buf, mtod(head, caddr_t),
2066 sizeof(struct ether_header));
2067 buf += sizeof(struct ether_header);
2068 head->m_len += sizeof(struct ether_header);
2069 len -= sizeof(struct ether_header);
2070
2071 etype = ntohs((u_short)eh->ether_type);
2072
2073 /*
2074 * Deal with trailer protocol:
2075 * If trailer protocol, calculate the datasize as 'off',
2076 * which is also the offset to the trailer header.
2077 * Set resid to the amount of packet data following the
2078 * trailer header.
2079 * Finally, copy residual data into mbuf chain.
2080 */
2081 if (etype >= ETHERTYPE_TRAIL &&
2082 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
2083
2084 off = (etype - ETHERTYPE_TRAIL) << 9;
2085 if ((off + sizeof(struct trailer_header)) > len)
2086 goto bad; /* insanity */
2087
2088 /*
2089 * If we have shared memory, we can get info directly from the
2090 * stored packet, otherwise we must get a local copy
2091 * of the trailer header using PIO.
2092 */
2093 if (sc->mem_shared) {
2094 eh->ether_type = *ringoffset(sc, buf, off, u_short *);
2095 resid = ntohs(*ringoffset(sc, buf, off+2, u_short *));
2096 } else {
2097 struct trailer_header trailer_header;
2098 ed_pio_readmem(sc,
2099 ringoffset(sc, buf, off, caddr_t),
2100 (char *) &trailer_header,
2101 sizeof(trailer_header));
2102 eh->ether_type = trailer_header.ether_type;
2103 resid = trailer_header.ether_residual;
2104 }
2105
2106 if ((off + resid) > len) goto bad; /* insanity */
2107
2108 resid -= sizeof(struct trailer_header);
2109 if (resid < 0) goto bad; /* insanity */
2110
2111 m = ed_ring_to_mbuf(sc, ringoffset(sc, buf, off+4, char *),
2112 head, resid);
2113 if (m == 0) goto bad;
2114
2115 len = off;
2116 head->m_pkthdr.len -= 4; /* subtract trailer header */
2117 }
2118
2119 /*
2120 * Pull packet off interface. Or if this was a trailer packet,
2121 * the data portion is appended.
2122 */
2123 m = ed_ring_to_mbuf(sc, buf, m, len);
2124 if (m == 0) goto bad;
2125
2126#if NBPFILTER > 0
2127 /*
2128 * Check if there's a BPF listener on this interface.
2129 * If so, hand off the raw packet to bpf.
2130 */
2131 if (sc->bpf) {
2132 bpf_mtap(sc->bpf, head);
2133
2134 /*
2135 * Note that the interface cannot be in promiscuous mode if
2136 * there are no BPF listeners. And if we are in promiscuous
2137 * mode, we have to check if this packet is really ours.
2138 *
2139 * XXX This test does not support multicasts.
2140 */
2141 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2142 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2143 sizeof(eh->ether_dhost)) != 0 &&
2144 bcmp(eh->ether_dhost, etherbroadcastaddr,
2145 sizeof(eh->ether_dhost)) != 0) {
2146
2147 m_freem(head);
2148 return;
2149 }
2150 }
2151#endif
2152
2153 /*
2154 * Fix up data start offset in mbuf to point past ether header
2155 */
2156 m_adj(head, sizeof(struct ether_header));
2157
2158 /*
2159 * silly ether_input routine needs 'type' in host byte order
2160 */
2161 eh->ether_type = ntohs(eh->ether_type);
2162
2163 ether_input(&sc->arpcom.ac_if, eh, head);
2164 return;
2165
2166bad: if (head)
2167 m_freem(head);
2168 return;
2169}
2170
2171/*
2172 * Supporting routines
2173 */
2174
2175/*
2176 * Given a NIC memory source address and a host memory destination
2177 * address, copy 'amount' from NIC to host using Programmed I/O.
2178 * The 'amount' is rounded up to a word - okay as long as mbufs
2179 * are word sized.
2180 * This routine is currently Novell-specific.
2181 */
2182void
2183ed_pio_readmem(sc,src,dst,amount)
2184 struct ed_softc *sc;
2185 unsigned short src;
2186 unsigned char *dst;
2187 unsigned short amount;
2188{
2189 unsigned short tmp_amount;
2190
2191 /* select page 0 registers */
2192 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2193
2194 /* round up to a word */
2195 tmp_amount = amount;
2196 if (amount & 1) ++amount;
2197
2198 /* set up DMA byte count */
2199 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2200 outb(sc->nic_addr + ED_P0_RBCR1, amount>>8);
2201
2202 /* set up source address in NIC mem */
2203 outb(sc->nic_addr + ED_P0_RSAR0, src);
2204 outb(sc->nic_addr + ED_P0_RSAR1, src>>8);
2205
2206 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2207
2208 if (sc->isa16bit) {
2209 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount/2);
2210 } else
2211 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2212
2213}
2214
2215/*
2216 * Stripped down routine for writing a linear buffer to NIC memory.
2217 * Only used in the probe routine to test the memory. 'len' must
2218 * be even.
2219 */
2220void
2221ed_pio_writemem(sc,src,dst,len)
2222 struct ed_softc *sc;
2223 char *src;
2224 unsigned short dst;
2225 unsigned short len;
2226{
2227 int maxwait=100; /* about 120us */
2228
2229 /* select page 0 registers */
2230 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2231
2232 /* reset remote DMA complete flag */
2233 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2234
2235 /* set up DMA byte count */
2236 outb(sc->nic_addr + ED_P0_RBCR0, len);
2237 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2238
2239 /* set up destination address in NIC mem */
2240 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2241 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2242
2243 /* set remote DMA write */
2244 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2245
2246 if (sc->isa16bit)
2247 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len/2);
2248 else
2249 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2250 /*
2251 * Wait for remote DMA complete. This is necessary because on the
2252 * transmit side, data is handled internally by the NIC in bursts
2253 * and we can't start another remote DMA until this one completes.
2254 * Not waiting causes really bad things to happen - like the NIC
2255 * irrecoverably jamming the ISA bus.
2256 */
2257 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2258}
2259
2260/*
2261 * Write an mbuf chain to the destination NIC memory address using
2262 * programmed I/O.
2263 */
2264u_short
2265ed_pio_write_mbufs(sc,m,dst)
2266 struct ed_softc *sc;
2267 struct mbuf *m;
2268 unsigned short dst;
2269{
2270 unsigned short len, mb_offset;
2271 struct mbuf *mp;
2272 unsigned char residual[2];
2273 int maxwait=100; /* about 120us */
2274
2275 /* First, count up the total number of bytes to copy */
2276 for (len = 0, mp = m; mp; mp = mp->m_next)
2277 len += mp->m_len;
2278
2279 /* select page 0 registers */
2280 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2281
2282 /* reset remote DMA complete flag */
2283 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2284
2285 /* set up DMA byte count */
2286 outb(sc->nic_addr + ED_P0_RBCR0, len);
2287 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2288
2289 /* set up destination address in NIC mem */
2290 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2291 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2292
2293 /* set remote DMA write */
2294 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2295
2296 mb_offset = 0;
2297 /*
2298 * Transfer the mbuf chain to the NIC memory.
2299 * The following code isn't too pretty. The problem is that we can only
2300 * transfer words to the board, and if an mbuf has an odd number
2301 * of bytes in it, this is a problem. It's not a simple matter of
2302 * just removing a byte from the next mbuf (adjusting data++ and
2303 * len--) because this will hose-over the mbuf chain which might
2304 * be needed later for BPF. Instead, we maintain an offset
2305 * (mb_offset) which let's us skip over the first byte in the
2306 * following mbuf.
2307 */
2308 while (m) {
2309 if (m->m_len - mb_offset) {
2310 if (sc->isa16bit) {
2311 if ((m->m_len - mb_offset) > 1)
2312 outsw(sc->asic_addr + ED_NOVELL_DATA,
2313 mtod(m, caddr_t) + mb_offset,
2314 (m->m_len - mb_offset) / 2);
2315
2316 /*
2317 * if odd number of bytes, get the odd byte from
2318 * the next mbuf with data
2319 */
2320 if ((m->m_len - mb_offset) & 1) {
2321 /* first the last byte in current mbuf */
2322 residual[0] = *(mtod(m, caddr_t) +
2323 m->m_len - 1);
2324
2325 /* advance past any empty mbufs */
2326 while (m->m_next && (m->m_next->m_len == 0))
2327 m = m->m_next;
2328
2329 if (m->m_next) {
2330 /* remove first byte in next mbuf */
2331 residual[1] = *(mtod(m->m_next, caddr_t));
2332 mb_offset = 1;
2333 }
2334
2335 outw(sc->asic_addr + ED_NOVELL_DATA,
2336 *((unsigned short *) residual));
2337 } else
2338 mb_offset = 0;
2339 } else
2340 outsb(sc->asic_addr + ED_NOVELL_DATA, m->m_data, m->m_len);
2341
2342 }
2343 m = m->m_next;
2344 }
2345
2346 /*
2347 * Wait for remote DMA complete. This is necessary because on the
2348 * transmit side, data is handled internally by the NIC in bursts
2349 * and we can't start another remote DMA until this one completes.
2350 * Not waiting causes really bad things to happen - like the NIC
2351 * irrecoverably jamming the ISA bus.
2352 */
2353 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2354
2355 if (!maxwait) {
2356 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2357 sc->arpcom.ac_if.if_unit);
2358 ed_reset(sc->arpcom.ac_if.if_unit, 0);
2359 }
2360
2361 return(len);
2362}
2363
2364/*
2365 * Given a source and destination address, copy 'amount' of a packet from
2366 * the ring buffer into a linear destination buffer. Takes into account
2367 * ring-wrap.
2368 */
2369static inline char *
2370ed_ring_copy(sc,src,dst,amount)
2371 struct ed_softc *sc;
2372 char *src;
2373 char *dst;
2374 u_short amount;
2375{
2376 u_short tmp_amount;
2377
2378 /* does copy wrap to lower addr in ring buffer? */
2379 if (src + amount > sc->mem_end) {
2380 tmp_amount = sc->mem_end - src;
2381
2382 /* copy amount up to end of NIC memory */
2383 if (sc->mem_shared)
2384 bcopy(src,dst,tmp_amount);
2385 else
2386 ed_pio_readmem(sc,src,dst,tmp_amount);
2387
2388 amount -= tmp_amount;
2389 src = sc->mem_ring;
2390 dst += tmp_amount;
2391 }
2392
2393 if (sc->mem_shared)
2394 bcopy(src, dst, amount);
2395 else
2396 ed_pio_readmem(sc, src, dst, amount);
2397
2398 return(src + amount);
2399}
2400
2401/*
2402 * Copy data from receive buffer to end of mbuf chain
2403 * allocate additional mbufs as needed. return pointer
2404 * to last mbuf in chain.
2405 * sc = ed info (softc)
2406 * src = pointer in ed ring buffer
2407 * dst = pointer to last mbuf in mbuf chain to copy to
2408 * amount = amount of data to copy
2409 */
2410struct mbuf *
2411ed_ring_to_mbuf(sc,src,dst,total_len)
2412 struct ed_softc *sc;
2413 char *src;
2414 struct mbuf *dst;
2415 u_short total_len;
2416{
2417 register struct mbuf *m = dst;
2418
2419 while (total_len) {
2420 register u_short amount = min(total_len, M_TRAILINGSPACE(m));
2421
2422 if (amount == 0) { /* no more data in this mbuf, alloc another */
2423 /*
2424 * If there is enough data for an mbuf cluster, attempt
2425 * to allocate one of those, otherwise, a regular
2426 * mbuf will do.
2427 * Note that a regular mbuf is always required, even if
2428 * we get a cluster - getting a cluster does not
2429 * allocate any mbufs, and one is needed to assign
2430 * the cluster to. The mbuf that has a cluster
2431 * extension can not be used to contain data - only
2432 * the cluster can contain data.
2433 */
2434 dst = m;
2435 MGET(m, M_DONTWAIT, MT_DATA);
2436 if (m == 0)
2437 return (0);
2438
2439 if (total_len >= MINCLSIZE)
2440 MCLGET(m, M_DONTWAIT);
2441
2442 m->m_len = 0;
2443 dst->m_next = m;
2444 amount = min(total_len, M_TRAILINGSPACE(m));
2445 }
2446
2447 src = ed_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount);
2448
2449 m->m_len += amount;
2450 total_len -= amount;
2451
2452 }
2453 return (m);
2454}
2455#endif