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i915_drm.h (182080) i915_drm.h (183573)
1/*-
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,

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20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,

--- 11 unchanged lines hidden (view full) ---

20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/drm/i915_drm.h 182080 2008-08-23 20:59:12Z rnoland $");
28__FBSDID("$FreeBSD: head/sys/dev/drm/i915_drm.h 183573 2008-10-03 16:59:11Z rnoland $");
29
30#ifndef _I915_DRM_H_
31#define _I915_DRM_H_
32
33/* Please note that modifications to all structs defined here are
34 * subject to backwards-compatibility constraints.
35 */
36

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174#define DRM_I915_CMDBUFFER 0x0b
175#define DRM_I915_DESTROY_HEAP 0x0c
176#define DRM_I915_SET_VBLANK_PIPE 0x0d
177#define DRM_I915_GET_VBLANK_PIPE 0x0e
178#define DRM_I915_VBLANK_SWAP 0x0f
179#define DRM_I915_MMIO 0x10
180#define DRM_I915_HWS_ADDR 0x11
181#define DRM_I915_EXECBUFFER 0x12
29
30#ifndef _I915_DRM_H_
31#define _I915_DRM_H_
32
33/* Please note that modifications to all structs defined here are
34 * subject to backwards-compatibility constraints.
35 */
36

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174#define DRM_I915_CMDBUFFER 0x0b
175#define DRM_I915_DESTROY_HEAP 0x0c
176#define DRM_I915_SET_VBLANK_PIPE 0x0d
177#define DRM_I915_GET_VBLANK_PIPE 0x0e
178#define DRM_I915_VBLANK_SWAP 0x0f
179#define DRM_I915_MMIO 0x10
180#define DRM_I915_HWS_ADDR 0x11
181#define DRM_I915_EXECBUFFER 0x12
182#define DRM_I915_GEM_INIT 0x13
183#define DRM_I915_GEM_EXECBUFFER 0x14
184#define DRM_I915_GEM_PIN 0x15
185#define DRM_I915_GEM_UNPIN 0x16
186#define DRM_I915_GEM_BUSY 0x17
187#define DRM_I915_GEM_THROTTLE 0x18
188#define DRM_I915_GEM_ENTERVT 0x19
189#define DRM_I915_GEM_LEAVEVT 0x1a
190#define DRM_I915_GEM_CREATE 0x1b
191#define DRM_I915_GEM_PREAD 0x1c
192#define DRM_I915_GEM_PWRITE 0x1d
193#define DRM_I915_GEM_MMAP 0x1e
194#define DRM_I915_GEM_SET_DOMAIN 0x1f
195#define DRM_I915_GEM_SW_FINISH 0x20
196#define DRM_I915_GEM_SET_TILING 0x21
197#define DRM_I915_GEM_GET_TILING 0x22
182
183#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
184#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
185#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
186#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
187#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
188#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
189#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
190#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
191#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
192#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
193#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
194#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
195#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
196#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
197#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
198#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
199#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
200#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
198
199#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
200#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
201#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
202#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
203#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
204#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
205#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
206#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
207#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
208#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
209#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
210#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
211#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
212#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
213#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
214#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
215#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
216#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
217#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
218#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
219#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
220#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
221#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
222#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
223#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
224#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
225#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
226#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
227#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
228#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
229#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
230#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
231#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
232#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
201
202/* Asynchronous page flipping:
203 */
204typedef struct drm_i915_flip {
205 /*
206 * This is really talking about planes, and we could rename it
207 * except for the fact that some of the duplicated i915_drm.h files
208 * out there check for HAVE_I915_FLIP and so might pick up this

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246} drm_i915_irq_wait_t;
247
248/* Ioctl to query kernel params:
249 */
250#define I915_PARAM_IRQ_ACTIVE 1
251#define I915_PARAM_ALLOW_BATCHBUFFER 2
252#define I915_PARAM_LAST_DISPATCH 3
253#define I915_PARAM_CHIPSET_ID 4
233
234/* Asynchronous page flipping:
235 */
236typedef struct drm_i915_flip {
237 /*
238 * This is really talking about planes, and we could rename it
239 * except for the fact that some of the duplicated i915_drm.h files
240 * out there check for HAVE_I915_FLIP and so might pick up this

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278} drm_i915_irq_wait_t;
279
280/* Ioctl to query kernel params:
281 */
282#define I915_PARAM_IRQ_ACTIVE 1
283#define I915_PARAM_ALLOW_BATCHBUFFER 2
284#define I915_PARAM_LAST_DISPATCH 3
285#define I915_PARAM_CHIPSET_ID 4
286#define I915_PARAM_HAS_GEM 5
254
255typedef struct drm_i915_getparam {
256 int param;
257 int __user *value;
258} drm_i915_getparam_t;
259
260/* Ioctl to set kernel params:
261 */

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393struct drm_i915_execbuffer {
394 uint64_t ops_list;
395 uint32_t num_buffers;
396 struct drm_i915_batchbuffer batch;
397 drm_context_t context; /* for lockless use in the future */
398 struct drm_fence_arg fence_arg;
399};
400
287
288typedef struct drm_i915_getparam {
289 int param;
290 int __user *value;
291} drm_i915_getparam_t;
292
293/* Ioctl to set kernel params:
294 */

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426struct drm_i915_execbuffer {
427 uint64_t ops_list;
428 uint32_t num_buffers;
429 struct drm_i915_batchbuffer batch;
430 drm_context_t context; /* for lockless use in the future */
431 struct drm_fence_arg fence_arg;
432};
433
434struct drm_i915_gem_init {
435 /**
436 * Beginning offset in the GTT to be managed by the DRM memory
437 * manager.
438 */
439 uint64_t gtt_start;
440 /**
441 * Ending offset in the GTT to be managed by the DRM memory
442 * manager.
443 */
444 uint64_t gtt_end;
445};
446
447struct drm_i915_gem_create {
448 /**
449 * Requested size for the object.
450 *
451 * The (page-aligned) allocated size for the object will be returned.
452 */
453 uint64_t size;
454 /**
455 * Returned handle for the object.
456 *
457 * Object handles are nonzero.
458 */
459 uint32_t handle;
460 uint32_t pad;
461};
462
463struct drm_i915_gem_pread {
464 /** Handle for the object being read. */
465 uint32_t handle;
466 uint32_t pad;
467 /** Offset into the object to read from */
468 uint64_t offset;
469 /** Length of data to read */
470 uint64_t size;
471 /** Pointer to write the data into. */
472 uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
473};
474
475struct drm_i915_gem_pwrite {
476 /** Handle for the object being written to. */
477 uint32_t handle;
478 uint32_t pad;
479 /** Offset into the object to write to */
480 uint64_t offset;
481 /** Length of data to write */
482 uint64_t size;
483 /** Pointer to read the data from. */
484 uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
485};
486
487struct drm_i915_gem_mmap {
488 /** Handle for the object being mapped. */
489 uint32_t handle;
490 uint32_t pad;
491 /** Offset in the object to map. */
492 uint64_t offset;
493 /**
494 * Length of data to map.
495 *
496 * The value will be page-aligned.
497 */
498 uint64_t size;
499 /** Returned pointer the data was mapped at */
500 uint64_t addr_ptr; /* void *, but pointers are not 32/64 compatible */
501};
502
503struct drm_i915_gem_set_domain {
504 /** Handle for the object */
505 uint32_t handle;
506
507 /** New read domains */
508 uint32_t read_domains;
509
510 /** New write domain */
511 uint32_t write_domain;
512};
513
514struct drm_i915_gem_sw_finish {
515 /** Handle for the object */
516 uint32_t handle;
517};
518
519struct drm_i915_gem_relocation_entry {
520 /**
521 * Handle of the buffer being pointed to by this relocation entry.
522 *
523 * It's appealing to make this be an index into the mm_validate_entry
524 * list to refer to the buffer, but this allows the driver to create
525 * a relocation list for state buffers and not re-write it per
526 * exec using the buffer.
527 */
528 uint32_t target_handle;
529
530 /**
531 * Value to be added to the offset of the target buffer to make up
532 * the relocation entry.
533 */
534 uint32_t delta;
535
536 /** Offset in the buffer the relocation entry will be written into */
537 uint64_t offset;
538
539 /**
540 * Offset value of the target buffer that the relocation entry was last
541 * written as.
542 *
543 * If the buffer has the same offset as last time, we can skip syncing
544 * and writing the relocation. This value is written back out by
545 * the execbuffer ioctl when the relocation is written.
546 */
547 uint64_t presumed_offset;
548
549 /**
550 * Target memory domains read by this operation.
551 */
552 uint32_t read_domains;
553
554 /**
555 * Target memory domains written by this operation.
556 *
557 * Note that only one domain may be written by the whole
558 * execbuffer operation, so that where there are conflicts,
559 * the application will get -EINVAL back.
560 */
561 uint32_t write_domain;
562};
563
564/** @{
565 * Intel memory domains
566 *
567 * Most of these just align with the various caches in
568 * the system and are used to flush and invalidate as
569 * objects end up cached in different domains.
570 */
571/** CPU cache */
572#define I915_GEM_DOMAIN_CPU 0x00000001
573/** Render cache, used by 2D and 3D drawing */
574#define I915_GEM_DOMAIN_RENDER 0x00000002
575/** Sampler cache, used by texture engine */
576#define I915_GEM_DOMAIN_SAMPLER 0x00000004
577/** Command queue, used to load batch buffers */
578#define I915_GEM_DOMAIN_COMMAND 0x00000008
579/** Instruction cache, used by shader programs */
580#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
581/** Vertex address cache */
582#define I915_GEM_DOMAIN_VERTEX 0x00000020
583/** GTT domain - aperture and scanout */
584#define I915_GEM_DOMAIN_GTT 0x00000040
585/** @} */
586
587struct drm_i915_gem_exec_object {
588 /**
589 * User's handle for a buffer to be bound into the GTT for this
590 * operation.
591 */
592 uint32_t handle;
593
594 /** Number of relocations to be performed on this buffer */
595 uint32_t relocation_count;
596 /**
597 * Pointer to array of struct drm_i915_gem_relocation_entry containing
598 * the relocations to be performed in this buffer.
599 */
600 uint64_t relocs_ptr;
601
602 /** Required alignment in graphics aperture */
603 uint64_t alignment;
604
605 /**
606 * Returned value of the updated offset of the object, for future
607 * presumed_offset writes.
608 */
609 uint64_t offset;
610};
611
612struct drm_i915_gem_execbuffer {
613 /**
614 * List of buffers to be validated with their relocations to be
615 * performend on them.
616 *
617 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
618 *
619 * These buffers must be listed in an order such that all relocations
620 * a buffer is performing refer to buffers that have already appeared
621 * in the validate list.
622 */
623 uint64_t buffers_ptr;
624 uint32_t buffer_count;
625
626 /** Offset in the batchbuffer to start execution from. */
627 uint32_t batch_start_offset;
628 /** Bytes used in batchbuffer from batch_start_offset */
629 uint32_t batch_len;
630 uint32_t DR1;
631 uint32_t DR4;
632 uint32_t num_cliprects;
633 uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */
634};
635
636struct drm_i915_gem_pin {
637 /** Handle of the buffer to be pinned. */
638 uint32_t handle;
639 uint32_t pad;
640
641 /** alignment required within the aperture */
642 uint64_t alignment;
643
644 /** Returned GTT offset of the buffer. */
645 uint64_t offset;
646};
647
648struct drm_i915_gem_unpin {
649 /** Handle of the buffer to be unpinned. */
650 uint32_t handle;
651 uint32_t pad;
652};
653
654struct drm_i915_gem_busy {
655 /** Handle of the buffer to check for busy */
656 uint32_t handle;
657
658 /** Return busy status (1 if busy, 0 if idle) */
659 uint32_t busy;
660};
661
662#define I915_TILING_NONE 0
663#define I915_TILING_X 1
664#define I915_TILING_Y 2
665
666#define I915_BIT_6_SWIZZLE_NONE 0
667#define I915_BIT_6_SWIZZLE_9 1
668#define I915_BIT_6_SWIZZLE_9_10 2
669#define I915_BIT_6_SWIZZLE_9_11 3
670#define I915_BIT_6_SWIZZLE_9_10_11 4
671/* Not seen by userland */
672#define I915_BIT_6_SWIZZLE_UNKNOWN 5
673
674struct drm_i915_gem_set_tiling {
675 /** Handle of the buffer to have its tiling state updated */
676 uint32_t handle;
677
678 /**
679 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
680 * I915_TILING_Y).
681 *
682 * This value is to be set on request, and will be updated by the
683 * kernel on successful return with the actual chosen tiling layout.
684 *
685 * The tiling mode may be demoted to I915_TILING_NONE when the system
686 * has bit 6 swizzling that can't be managed correctly by GEM.
687 *
688 * Buffer contents become undefined when changing tiling_mode.
689 */
690 uint32_t tiling_mode;
691
692 /**
693 * Stride in bytes for the object when in I915_TILING_X or
694 * I915_TILING_Y.
695 */
696 uint32_t stride;
697
698 /**
699 * Returned address bit 6 swizzling required for CPU access through
700 * mmap mapping.
701 */
702 uint32_t swizzle_mode;
703};
704
705struct drm_i915_gem_get_tiling {
706 /** Handle of the buffer to get tiling state for. */
707 uint32_t handle;
708
709 /**
710 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
711 * I915_TILING_Y).
712 */
713 uint32_t tiling_mode;
714
715 /**
716 * Returned address bit 6 swizzling required for CPU access through
717 * mmap mapping.
718 */
719 uint32_t swizzle_mode;
720};
721
401#endif /* _I915_DRM_H_ */
722#endif /* _I915_DRM_H_ */