1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: head/sys/dev/cxgbe/common/t4_hw.h 247122 2013-02-21 20:13:15Z np $
| 26 * $FreeBSD: head/sys/dev/cxgbe/common/t4_hw.h 248925 2013-03-30 02:26:20Z np $
|
27 *
28 */
29
30#ifndef __T4_HW_H
31#define __T4_HW_H
32
33#include "osdep.h"
34
35enum {
| 27 *
28 */
29
30#ifndef __T4_HW_H
31#define __T4_HW_H
32
33#include "osdep.h"
34
35enum {
|
36 NCHAN = 4, /* # of HW channels */
37 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
38 EEPROMSIZE = 17408, /* Serial EEPROM physical size */
39 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
40 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
41 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
42 TCB_SIZE = 128, /* TCB size */
43 NMTUS = 16, /* size of MTU table */
44 NCCTRL_WIN = 32, /* # of congestion control windows */
45 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
46 PM_NSTATS = 5, /* # of PM stats */
47 MBOX_LEN = 64, /* mailbox size in bytes */
48 TRACE_LEN = 112, /* length of trace data and mask */
49 FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
50 NWOL_PAT = 8, /* # of WoL patterns */
51 WOL_PAT_LEN = 128, /* length of WoL patterns */
| 36 NCHAN = 4, /* # of HW channels */
37 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
38 EEPROMSIZE = 17408, /* Serial EEPROM physical size */
39 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
40 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
41 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
42 TCB_SIZE = 128, /* TCB size */
43 NMTUS = 16, /* size of MTU table */
44 NCCTRL_WIN = 32, /* # of congestion control windows */
45 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
46 PM_NSTATS = 5, /* # of PM stats */
47 MBOX_LEN = 64, /* mailbox size in bytes */
48 TRACE_LEN = 112, /* length of trace data and mask */
49 FILTER_OPT_LEN = 36, /* filter tuple width of optional components */
50 NWOL_PAT = 8, /* # of WoL patterns */
51 WOL_PAT_LEN = 128, /* length of WoL patterns */
52 UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */
53 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */
54 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */
55 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */
|
52};
53
54enum {
55 CIM_NUM_IBQ = 6, /* # of CIM IBQs */
56 CIM_NUM_OBQ = 6, /* # of CIM OBQs */
| 56};
57
58enum {
59 CIM_NUM_IBQ = 6, /* # of CIM IBQs */
60 CIM_NUM_OBQ = 6, /* # of CIM OBQs */
|
| 61 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
|
57 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
58 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
59 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
60 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
61 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */
62 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
63 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
64};
65
66enum {
67 SF_PAGE_SIZE = 256, /* serial flash page size */
68 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
69};
70
71/* SGE context types */
72enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
73
74enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
75
76enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
77
78enum {
79 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
80 SGE_CTXT_SIZE = 24, /* size of SGE context */
81 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
82 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
| 62 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
63 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
64 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
65 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
66 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */
67 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
68 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
69};
70
71enum {
72 SF_PAGE_SIZE = 256, /* serial flash page size */
73 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
74};
75
76/* SGE context types */
77enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
78
79enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
80
81enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
82
83enum {
84 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
85 SGE_CTXT_SIZE = 24, /* size of SGE context */
86 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
87 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
|
| 88 SGE_MAX_IQ_SIZE = 65520,
|
83};
84
85struct sge_qstat { /* data written to SGE queue status entries */
86 volatile __be32 qid;
87 volatile __be16 cidx;
88 volatile __be16 pidx;
89};
90
91#define S_QSTAT_PIDX 0
92#define M_QSTAT_PIDX 0xffff
93#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
94
95#define S_QSTAT_CIDX 16
96#define M_QSTAT_CIDX 0xffff
97#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
98
99/*
100 * Structure for last 128 bits of response descriptors
101 */
102struct rsp_ctrl {
103 __be32 hdrbuflen_pidx;
104 __be32 pldbuflen_qid;
105 union {
106 u8 type_gen;
107 __be64 last_flit;
108 } u;
109};
110
111#define S_RSPD_NEWBUF 31
112#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
113#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
114
115#define S_RSPD_LEN 0
116#define M_RSPD_LEN 0x7fffffff
117#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
118#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
119
120#define S_RSPD_QID S_RSPD_LEN
121#define M_RSPD_QID M_RSPD_LEN
122#define V_RSPD_QID(x) V_RSPD_LEN(x)
123#define G_RSPD_QID(x) G_RSPD_LEN(x)
124
125#define S_RSPD_GEN 7
126#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
127#define F_RSPD_GEN V_RSPD_GEN(1U)
128
129#define S_RSPD_QOVFL 6
130#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
131#define F_RSPD_QOVFL V_RSPD_QOVFL(1U)
132
133#define S_RSPD_TYPE 4
134#define M_RSPD_TYPE 0x3
135#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
136#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
137
138/* Rx queue interrupt deferral fields: counter enable and timer index */
139#define S_QINTR_CNT_EN 0
140#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
141#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
142
143#define S_QINTR_TIMER_IDX 1
144#define M_QINTR_TIMER_IDX 0x7
145#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
146#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
147
148/* # of pages a pagepod can hold without needing another pagepod */
149#define PPOD_PAGES 4U
150
151struct pagepod {
152 __be64 vld_tid_pgsz_tag_color;
153 __be64 len_offset;
154 __be64 rsvd;
155 __be64 addr[PPOD_PAGES + 1];
156};
157
158#define S_PPOD_COLOR 0
159#define M_PPOD_COLOR 0x3F
160#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
161
162#define S_PPOD_TAG 6
163#define M_PPOD_TAG 0xFFFFFF
164#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
165#define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG)
166
167#define S_PPOD_PGSZ 30
168#define M_PPOD_PGSZ 0x3
169#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
170#define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ)
171
172#define S_PPOD_TID 32
173#define M_PPOD_TID 0xFFFFFF
174#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
175
176#define S_PPOD_VALID 56
177#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
178#define F_PPOD_VALID V_PPOD_VALID(1ULL)
179
180#define S_PPOD_LEN 32
181#define M_PPOD_LEN 0xFFFFFFFF
182#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
183
184#define S_PPOD_OFST 0
185#define M_PPOD_OFST 0xFFFFFFFF
186#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
187
188/*
189 * Flash layout.
190 */
191#define FLASH_START(start) ((start) * SF_SEC_SIZE)
192#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
193
194enum {
195 /*
196 * Various Expansion-ROM boot images, etc.
197 */
198 FLASH_EXP_ROM_START_SEC = 0,
199 FLASH_EXP_ROM_NSECS = 6,
200 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
201 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
202
203 /*
204 * iSCSI Boot Firmware Table (iBFT) and other driver-related
205 * parameters ...
206 */
207 FLASH_IBFT_START_SEC = 6,
208 FLASH_IBFT_NSECS = 1,
209 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
210 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
211
212 /*
213 * Boot configuration data.
214 */
215 FLASH_BOOTCFG_START_SEC = 7,
216 FLASH_BOOTCFG_NSECS = 1,
217 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
218 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
219
220 /*
221 * Location of firmware image in FLASH.
222 */
223 FLASH_FW_START_SEC = 8,
| 89};
90
91struct sge_qstat { /* data written to SGE queue status entries */
92 volatile __be32 qid;
93 volatile __be16 cidx;
94 volatile __be16 pidx;
95};
96
97#define S_QSTAT_PIDX 0
98#define M_QSTAT_PIDX 0xffff
99#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
100
101#define S_QSTAT_CIDX 16
102#define M_QSTAT_CIDX 0xffff
103#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
104
105/*
106 * Structure for last 128 bits of response descriptors
107 */
108struct rsp_ctrl {
109 __be32 hdrbuflen_pidx;
110 __be32 pldbuflen_qid;
111 union {
112 u8 type_gen;
113 __be64 last_flit;
114 } u;
115};
116
117#define S_RSPD_NEWBUF 31
118#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
119#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
120
121#define S_RSPD_LEN 0
122#define M_RSPD_LEN 0x7fffffff
123#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
124#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
125
126#define S_RSPD_QID S_RSPD_LEN
127#define M_RSPD_QID M_RSPD_LEN
128#define V_RSPD_QID(x) V_RSPD_LEN(x)
129#define G_RSPD_QID(x) G_RSPD_LEN(x)
130
131#define S_RSPD_GEN 7
132#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
133#define F_RSPD_GEN V_RSPD_GEN(1U)
134
135#define S_RSPD_QOVFL 6
136#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
137#define F_RSPD_QOVFL V_RSPD_QOVFL(1U)
138
139#define S_RSPD_TYPE 4
140#define M_RSPD_TYPE 0x3
141#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
142#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
143
144/* Rx queue interrupt deferral fields: counter enable and timer index */
145#define S_QINTR_CNT_EN 0
146#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
147#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
148
149#define S_QINTR_TIMER_IDX 1
150#define M_QINTR_TIMER_IDX 0x7
151#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
152#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
153
154/* # of pages a pagepod can hold without needing another pagepod */
155#define PPOD_PAGES 4U
156
157struct pagepod {
158 __be64 vld_tid_pgsz_tag_color;
159 __be64 len_offset;
160 __be64 rsvd;
161 __be64 addr[PPOD_PAGES + 1];
162};
163
164#define S_PPOD_COLOR 0
165#define M_PPOD_COLOR 0x3F
166#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
167
168#define S_PPOD_TAG 6
169#define M_PPOD_TAG 0xFFFFFF
170#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
171#define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG)
172
173#define S_PPOD_PGSZ 30
174#define M_PPOD_PGSZ 0x3
175#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
176#define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ)
177
178#define S_PPOD_TID 32
179#define M_PPOD_TID 0xFFFFFF
180#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
181
182#define S_PPOD_VALID 56
183#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
184#define F_PPOD_VALID V_PPOD_VALID(1ULL)
185
186#define S_PPOD_LEN 32
187#define M_PPOD_LEN 0xFFFFFFFF
188#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
189
190#define S_PPOD_OFST 0
191#define M_PPOD_OFST 0xFFFFFFFF
192#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
193
194/*
195 * Flash layout.
196 */
197#define FLASH_START(start) ((start) * SF_SEC_SIZE)
198#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
199
200enum {
201 /*
202 * Various Expansion-ROM boot images, etc.
203 */
204 FLASH_EXP_ROM_START_SEC = 0,
205 FLASH_EXP_ROM_NSECS = 6,
206 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
207 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
208
209 /*
210 * iSCSI Boot Firmware Table (iBFT) and other driver-related
211 * parameters ...
212 */
213 FLASH_IBFT_START_SEC = 6,
214 FLASH_IBFT_NSECS = 1,
215 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
216 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
217
218 /*
219 * Boot configuration data.
220 */
221 FLASH_BOOTCFG_START_SEC = 7,
222 FLASH_BOOTCFG_NSECS = 1,
223 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
224 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
225
226 /*
227 * Location of firmware image in FLASH.
228 */
229 FLASH_FW_START_SEC = 8,
|
224 FLASH_FW_NSECS = 8,
| 230 FLASH_FW_NSECS = 16,
|
225 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
226 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
227
228 /*
229 * iSCSI persistent/crash information.
230 */
231 FLASH_ISCSI_CRASH_START_SEC = 29,
232 FLASH_ISCSI_CRASH_NSECS = 1,
233 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
234 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
235
236 /*
237 * FCoE persistent/crash information.
238 */
239 FLASH_FCOE_CRASH_START_SEC = 30,
240 FLASH_FCOE_CRASH_NSECS = 1,
241 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
242 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
243
244 /*
245 * Location of Firmware Configuration File in FLASH. Since the FPGA
246 * "FLASH" is smaller we need to store the Configuration File in a
247 * different location -- which will overlap the end of the firmware
248 * image if firmware ever gets that large ...
249 */
250 FLASH_CFG_START_SEC = 31,
251 FLASH_CFG_NSECS = 1,
252 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
253 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
254
255 FLASH_FPGA_CFG_START_SEC = 15,
256 FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
257
258 /*
259 * Sectors 32-63 are reserved for FLASH failover.
260 */
261};
262
263#undef FLASH_START
264#undef FLASH_MAX_SIZE
265
266#endif /* __T4_HW_H */
| 231 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
232 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
233
234 /*
235 * iSCSI persistent/crash information.
236 */
237 FLASH_ISCSI_CRASH_START_SEC = 29,
238 FLASH_ISCSI_CRASH_NSECS = 1,
239 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
240 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
241
242 /*
243 * FCoE persistent/crash information.
244 */
245 FLASH_FCOE_CRASH_START_SEC = 30,
246 FLASH_FCOE_CRASH_NSECS = 1,
247 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
248 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
249
250 /*
251 * Location of Firmware Configuration File in FLASH. Since the FPGA
252 * "FLASH" is smaller we need to store the Configuration File in a
253 * different location -- which will overlap the end of the firmware
254 * image if firmware ever gets that large ...
255 */
256 FLASH_CFG_START_SEC = 31,
257 FLASH_CFG_NSECS = 1,
258 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
259 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
260
261 FLASH_FPGA_CFG_START_SEC = 15,
262 FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
263
264 /*
265 * Sectors 32-63 are reserved for FLASH failover.
266 */
267};
268
269#undef FLASH_START
270#undef FLASH_MAX_SIZE
271
272#endif /* __T4_HW_H */
|