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cxgb_vsc7323.c (170654) cxgb_vsc7323.c (171471)
1
2/**************************************************************************
3
4Copyright (c) 2007, Chelsio Inc.
5All rights reserved.
6
7Redistribution and use in source and binary forms, with or without
8modification, are permitted provided that the following conditions are met:

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24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27POSSIBILITY OF SUCH DAMAGE.
28
29***************************************************************************/
30
31#include <sys/cdefs.h>
1
2/**************************************************************************
3
4Copyright (c) 2007, Chelsio Inc.
5All rights reserved.
6
7Redistribution and use in source and binary forms, with or without
8modification, are permitted provided that the following conditions are met:

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24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27POSSIBILITY OF SUCH DAMAGE.
28
29***************************************************************************/
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_vsc7323.c 170654 2007-06-13 05:36:00Z kmacy $");
32__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_vsc7323.c 171471 2007-07-17 06:50:35Z kmacy $");
33
34#ifdef CONFIG_DEFINED
35#include <common/cxgb_common.h>
36#else
37#include <dev/cxgb/common/cxgb_common.h>
38#endif
39
40enum {

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110 { VSC_REG(7, 15, 0x19), 0xd6 },
111 { VSC_REG(7, 15, 7), 0xc },
112 { VSC_REG(7, 1, 0), 0x220 },
113 };
114 static struct addr_val_pair fifo_avp[] = {
115 { VSC_REG(2, 0, 0x2f), 0 },
116 { VSC_REG(2, 0, 0xf), 0xa0010291 },
117 { VSC_REG(2, 1, 0x2f), 1 },
33
34#ifdef CONFIG_DEFINED
35#include <common/cxgb_common.h>
36#else
37#include <dev/cxgb/common/cxgb_common.h>
38#endif
39
40enum {

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110 { VSC_REG(7, 15, 0x19), 0xd6 },
111 { VSC_REG(7, 15, 7), 0xc },
112 { VSC_REG(7, 1, 0), 0x220 },
113 };
114 static struct addr_val_pair fifo_avp[] = {
115 { VSC_REG(2, 0, 0x2f), 0 },
116 { VSC_REG(2, 0, 0xf), 0xa0010291 },
117 { VSC_REG(2, 1, 0x2f), 1 },
118 { VSC_REG(2, 1, 0xf), 0xa0026301 }
118 { VSC_REG(2, 1, 0xf), 0xa026301 }
119 };
120 static struct addr_val_pair xg_avp[] = {
121 { VSC_REG(1, 10, 0), 0x600b },
119 };
120 static struct addr_val_pair xg_avp[] = {
121 { VSC_REG(1, 10, 0), 0x600b },
122 { VSC_REG(1, 10, 2), 0x4000 },
122 { VSC_REG(1, 10, 1), 0x70600 }, //QUANTA = 96*1024*8/512
123 { VSC_REG(1, 10, 2), 0x2710 },
123 { VSC_REG(1, 10, 5), 0x65 },
124 { VSC_REG(1, 10, 5), 0x65 },
124 { VSC_REG(1, 10, 7), 3 },
125 { VSC_REG(1, 10, 7), 0x23 },
125 { VSC_REG(1, 10, 0x23), 0x800007bf },
126 { VSC_REG(1, 10, 0x23), 0x800007bf },
127 { VSC_REG(1, 10, 0x23), 0x000007bf },
128 { VSC_REG(1, 10, 0x23), 0x800007bf },
126 { VSC_REG(1, 10, 0x24), 4 }
127 };
128
129 int i, ret, ing_step, egr_step, ing_bot, egr_bot;
130
131 for (i = 0; i < ARRAY_SIZE(sys_avp); i++)
132 if ((ret = t3_elmr_blk_write(adap, sys_avp[i].reg_addr,
129 { VSC_REG(1, 10, 0x24), 4 }
130 };
131
132 int i, ret, ing_step, egr_step, ing_bot, egr_bot;
133
134 for (i = 0; i < ARRAY_SIZE(sys_avp); i++)
135 if ((ret = t3_elmr_blk_write(adap, sys_avp[i].reg_addr,
133 &sys_avp[i].val, 1)))
136 &sys_avp[i].val, 1)))
134 return ret;
135
137 return ret;
138
136
137 ing_step = 0xc0 / nports;
138 egr_step = 0x40 / nports;
139 ing_bot = egr_bot = 0;
140// ing_wm = ing_step * 64;
141// egr_wm = egr_step * 64;
142
143 /* {ING,EGR}_CONTROL.CLR = 1 here */
139 ing_step = 0xc0 / nports;
140 egr_step = 0x40 / nports;
141 ing_bot = egr_bot = 0;
142// ing_wm = ing_step * 64;
143// egr_wm = egr_step * 64;
144
145 /* {ING,EGR}_CONTROL.CLR = 1 here */
144 for (i = 0; i < nports; i++)
145 if ((ret = elmr_write(adap, VSC_REG(2, 0, 0x10 + i),
146 for (i = 0; i < nports; i++) {
147 if (
148 (ret = elmr_write(adap, VSC_REG(2, 0, 0x10 + i),
146 ((ing_bot + ing_step) << 16) | ing_bot)) ||
149 ((ing_bot + ing_step) << 16) | ing_bot)) ||
147 (ret = elmr_write(adap, VSC_REG(2, 0, 0x50 + i), 0)) ||
150 (ret = elmr_write(adap, VSC_REG(2, 0, 0x40 + i),
151 0x6000a00)) ||
152 (ret = elmr_write(adap, VSC_REG(2, 0, 0x50 + i), 1)) ||
148 (ret = elmr_write(adap, VSC_REG(2, 1, 0x10 + i),
149 ((egr_bot + egr_step) << 16) | egr_bot)) ||
150 (ret = elmr_write(adap, VSC_REG(2, 1, 0x40 + i),
151 0x2000280)) ||
152 (ret = elmr_write(adap, VSC_REG(2, 1, 0x50 + i), 0)))
153 return ret;
153 (ret = elmr_write(adap, VSC_REG(2, 1, 0x10 + i),
154 ((egr_bot + egr_step) << 16) | egr_bot)) ||
155 (ret = elmr_write(adap, VSC_REG(2, 1, 0x40 + i),
156 0x2000280)) ||
157 (ret = elmr_write(adap, VSC_REG(2, 1, 0x50 + i), 0)))
158 return ret;
159 ing_bot += ing_step;
160 egr_bot += egr_step;
161 }
154
162
155
156 for (i = 0; i < ARRAY_SIZE(fifo_avp); i++)
157 if ((ret = t3_elmr_blk_write(adap, fifo_avp[i].reg_addr,
163 for (i = 0; i < ARRAY_SIZE(fifo_avp); i++)
164 if ((ret = t3_elmr_blk_write(adap, fifo_avp[i].reg_addr,
158 &fifo_avp[i].val, 1)))
159 return ret;
165 &fifo_avp[i].val, 1)))
166 return ret;
160
161 for (i = 0; i < ARRAY_SIZE(xg_avp); i++)
162 if ((ret = t3_elmr_blk_write(adap, xg_avp[i].reg_addr,
163 &xg_avp[i].val, 1)))
164 return ret;
165
166 for (i = 0; i < nports; i++)
167 if ((ret = elmr_write(adap, VSC_REG(1, i, 0), 0xa59c)) ||

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193 0x91 | (clk << 1))) ||
194 (r = elmr_write(adap, VSC_REG(1, port, 0xb),
195 0x90 | (clk << 1))) ||
196 (r = elmr_write(adap, VSC_REG(1, port, 0),
197 0xa593 | (mode << 2))))
198 return r;
199 }
200
167
168 for (i = 0; i < ARRAY_SIZE(xg_avp); i++)
169 if ((ret = t3_elmr_blk_write(adap, xg_avp[i].reg_addr,
170 &xg_avp[i].val, 1)))
171 return ret;
172
173 for (i = 0; i < nports; i++)
174 if ((ret = elmr_write(adap, VSC_REG(1, i, 0), 0xa59c)) ||

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200 0x91 | (clk << 1))) ||
201 (r = elmr_write(adap, VSC_REG(1, port, 0xb),
202 0x90 | (clk << 1))) ||
203 (r = elmr_write(adap, VSC_REG(1, port, 0),
204 0xa593 | (mode << 2))))
205 return r;
206 }
207
201 r = (fc & PAUSE_RX) ? 0x6ffff : 0x2ffff;
208 r = (fc & PAUSE_RX) ? 0x60200 : 0x20200; //QUANTA = 32*1024*8/512
202 if (fc & PAUSE_TX)
203 r |= (1 << 19);
204 return elmr_write(adap, VSC_REG(1, port, 1), r);
205}
206
207int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port)
208{
209 return elmr_write(adap, VSC_REG(1, port, 2), mtu);
210}
211
212int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port)
213{
214 int ret;
209 if (fc & PAUSE_TX)
210 r |= (1 << 19);
211 return elmr_write(adap, VSC_REG(1, port, 1), r);
212}
213
214int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port)
215{
216 return elmr_write(adap, VSC_REG(1, port, 2), mtu);
217}
218
219int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port)
220{
221 int ret;
215
222
216 ret = elmr_write(adap, VSC_REG(1, port, 3),
223 ret = elmr_write(adap, VSC_REG(1, port, 3),
217 (addr[0] << 16) | (addr[1] << 8) | addr[2]);
224 (addr[0] << 16) | (addr[1] << 8) | addr[2]);
218 if (!ret)
219 ret = elmr_write(adap, VSC_REG(1, port, 4),
225 if (!ret)
226 ret = elmr_write(adap, VSC_REG(1, port, 4),
220 (addr[3] << 16) | (addr[4] << 8) | addr[5]);
227 (addr[3] << 16) | (addr[4] << 8) | addr[5]);
221 return ret;
222}
223
224int t3_vsc7323_enable(adapter_t *adap, int port, int which)
225{
226 int ret;
227 unsigned int v, orig;
228

--- 112 unchanged lines hidden --- 		228 return ret;
229}
230
231int t3_vsc7323_enable(adapter_t *adap, int port, int which)
232{
233 int ret;
234 unsigned int v, orig;
235

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