Deleted Added
sdiff udiff text old ( 176472 ) new ( 180583 )
full compact
cxgb_t3_hw.c (176472) cxgb_t3_hw.c (180583)
1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

--- 14 unchanged lines hidden (view full) ---

23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28***************************************************************************/
29
30#include <sys/cdefs.h>
1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

--- 14 unchanged lines hidden (view full) ---

23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28***************************************************************************/
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_hw.c 176472 2008-02-23 01:06:17Z kmacy $");
31__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_hw.c 180583 2008-07-18 06:12:31Z kmacy $");
32
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39

--- 416 unchanged lines hidden (view full) ---

456 if (duplex == DUPLEX_FULL)
457 ctl |= BMCR_FULLDPLX;
458 }
459 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */
460 ctl |= BMCR_ANENABLE;
461 return mdio_write(phy, 0, MII_BMCR, ctl);
462}
463
32
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39

--- 416 unchanged lines hidden (view full) ---

456 if (duplex == DUPLEX_FULL)
457 ctl |= BMCR_FULLDPLX;
458 }
459 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */
460 ctl |= BMCR_ANENABLE;
461 return mdio_write(phy, 0, MII_BMCR, ctl);
462}
463
464int t3_phy_lasi_intr_enable(struct cphy *phy)
465{
466 return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 1);
467}
468
469int t3_phy_lasi_intr_disable(struct cphy *phy)
470{
471 return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 0);
472}
473
474int t3_phy_lasi_intr_clear(struct cphy *phy)
475{
476 u32 val;
477
478 return mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &val);
479}
480
481int t3_phy_lasi_intr_handler(struct cphy *phy)
482{
483 unsigned int status;
484 int err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &status);
485
486 if (err)
487 return err;
488 return (status & 1) ? cphy_cause_link_change : 0;
489}
490
464static struct adapter_info t3_adap_info[] = {
465 { 1, 1, 0, 0, 0,
466 F_GPIO2_OEN | F_GPIO4_OEN |
491static struct adapter_info t3_adap_info[] = {
492 { 1, 1, 0, 0, 0,
493 F_GPIO2_OEN | F_GPIO4_OEN |
467 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
468 0,
494 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
469 &mi1_mdio_ops, "Chelsio PE9000" },
470 { 1, 1, 0, 0, 0,
471 F_GPIO2_OEN | F_GPIO4_OEN |
495 &mi1_mdio_ops, "Chelsio PE9000" },
496 { 1, 1, 0, 0, 0,
497 F_GPIO2_OEN | F_GPIO4_OEN |
472 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
473 0,
498 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
474 &mi1_mdio_ops, "Chelsio T302" },
475 { 1, 0, 0, 0, 0,
476 F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
477 F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
499 &mi1_mdio_ops, "Chelsio T302" },
500 { 1, 0, 0, 0, 0,
501 F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
502 F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
478 0, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
503 { 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
479 &mi1_mdio_ext_ops, "Chelsio T310" },
480 { 1, 1, 0, 0, 0,
481 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
482 F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
504 &mi1_mdio_ext_ops, "Chelsio T310" },
505 { 1, 1, 0, 0, 0,
506 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
507 F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
483 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
484 SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
508 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
509 { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
485 &mi1_mdio_ext_ops, "Chelsio T320" },
486 { 4, 0, 0, 0, 0,
487 F_GPIO5_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO5_OUT_VAL |
488 F_GPIO6_OUT_VAL | F_GPIO7_OUT_VAL,
510 &mi1_mdio_ext_ops, "Chelsio T320" },
511 { 4, 0, 0, 0, 0,
512 F_GPIO5_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO5_OUT_VAL |
513 F_GPIO6_OUT_VAL | F_GPIO7_OUT_VAL,
489 F_GPIO1 | F_GPIO2 | F_GPIO3 | F_GPIO4, SUPPORTED_AUI,
514 { S_GPIO1, S_GPIO2, S_GPIO3, S_GPIO4 }, SUPPORTED_AUI,
490 &mi1_mdio_ops, "Chelsio T304" },
491};
492
493/*
494 * Return the adapter_info structure with a given index. Out-of-range indices
495 * return NULL.
496 */
497const struct adapter_info *t3_get_adapter_info(unsigned int id)
498{
499 return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
500}
501
502static struct port_type_info port_types[] = {
503 { NULL },
504 { t3_ael1002_phy_prep },
505 { t3_vsc8211_phy_prep },
506 { t3_mv88e1xxx_phy_prep },
507 { t3_xaui_direct_phy_prep },
515 &mi1_mdio_ops, "Chelsio T304" },
516};
517
518/*
519 * Return the adapter_info structure with a given index. Out-of-range indices
520 * return NULL.
521 */
522const struct adapter_info *t3_get_adapter_info(unsigned int id)
523{
524 return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
525}
526
527static struct port_type_info port_types[] = {
528 { NULL },
529 { t3_ael1002_phy_prep },
530 { t3_vsc8211_phy_prep },
531 { t3_mv88e1xxx_phy_prep },
532 { t3_xaui_direct_phy_prep },
508 { NULL },
533 { t3_ael2005_phy_prep },
509 { t3_qt2045_phy_prep },
510 { t3_ael1006_phy_prep },
534 { t3_qt2045_phy_prep },
535 { t3_ael1006_phy_prep },
511 { NULL },
536 { t3_tn1010_phy_prep },
512};
513
514#define VPD_ENTRY(name, len) \
515 u8 name##_kword[2]; u8 name##_len; u8 name##_data[len]
516
517/*
518 * Partial EEPROM Vital Product Data structure. Includes only the ID and
519 * VPD-R sections.

--- 707 unchanged lines hidden (view full) ---

1227 int link_ok, speed, duplex, fc;
1228 struct port_info *pi = adap2pinfo(adapter, port_id);
1229 struct cphy *phy = &pi->phy;
1230 struct cmac *mac = &pi->mac;
1231 struct link_config *lc = &pi->link_config;
1232
1233 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
1234
537};
538
539#define VPD_ENTRY(name, len) \
540 u8 name##_kword[2]; u8 name##_len; u8 name##_data[len]
541
542/*
543 * Partial EEPROM Vital Product Data structure. Includes only the ID and
544 * VPD-R sections.

--- 707 unchanged lines hidden (view full) ---

1252 int link_ok, speed, duplex, fc;
1253 struct port_info *pi = adap2pinfo(adapter, port_id);
1254 struct cphy *phy = &pi->phy;
1255 struct cmac *mac = &pi->mac;
1256 struct link_config *lc = &pi->link_config;
1257
1258 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
1259
1260 if (lc->requested_fc & PAUSE_AUTONEG)
1261 fc &= lc->requested_fc;
1262 else
1263 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1264
1265 if (link_ok == lc->link_ok && speed == lc->speed &&
1266 duplex == lc->duplex && fc == lc->fc)
1267 return; /* nothing changed */
1268
1235 if (link_ok != lc->link_ok && adapter->params.rev > 0 &&
1236 uses_xaui(adapter)) {
1237 if (link_ok)
1238 t3b_pcs_reset(mac);
1239 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1240 link_ok ? F_TXACTENABLE | F_RXEN : 0);
1241 }
1242 lc->link_ok = (unsigned char)link_ok;
1243 lc->speed = speed < 0 ? SPEED_INVALID : speed;
1244 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
1269 if (link_ok != lc->link_ok && adapter->params.rev > 0 &&
1270 uses_xaui(adapter)) {
1271 if (link_ok)
1272 t3b_pcs_reset(mac);
1273 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1274 link_ok ? F_TXACTENABLE | F_RXEN : 0);
1275 }
1276 lc->link_ok = (unsigned char)link_ok;
1277 lc->speed = speed < 0 ? SPEED_INVALID : speed;
1278 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
1245 if (lc->requested_fc & PAUSE_AUTONEG)
1246 fc &= lc->requested_fc;
1247 else
1248 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1249
1250 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
1251 /* Set MAC speed, duplex, and flow control to match PHY. */
1252 t3_mac_set_speed_duplex_fc(mac, speed, duplex, fc);
1253 lc->fc = (unsigned char)fc;
1254 }
1255
1256 t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc);

--- 521 unchanged lines hidden (view full) ---

1778 return cause != 0;
1779}
1780
1781/*
1782 * Interrupt handler for PHY events.
1783 */
1784int t3_phy_intr_handler(adapter_t *adapter)
1785{
1279
1280 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
1281 /* Set MAC speed, duplex, and flow control to match PHY. */
1282 t3_mac_set_speed_duplex_fc(mac, speed, duplex, fc);
1283 lc->fc = (unsigned char)fc;
1284 }
1285
1286 t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc);

--- 521 unchanged lines hidden (view full) ---

1808 return cause != 0;
1809}
1810
1811/*
1812 * Interrupt handler for PHY events.
1813 */
1814int t3_phy_intr_handler(adapter_t *adapter)
1815{
1786 u32 mask, gpi = adapter_info(adapter)->gpio_intr;
1787 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1788
1789 for_each_port(adapter, i) {
1790 struct port_info *p = adap2pinfo(adapter, i);
1791
1816 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1817
1818 for_each_port(adapter, i) {
1819 struct port_info *p = adap2pinfo(adapter, i);
1820
1792 mask = gpi - (gpi & (gpi - 1));
1793 gpi -= mask;
1794
1795 if (!(p->phy.caps & SUPPORTED_IRQ))
1796 continue;
1797
1821 if (!(p->phy.caps & SUPPORTED_IRQ))
1822 continue;
1823
1798 if (cause & mask) {
1824 if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) {
1799 int phy_cause = p->phy.ops->intr_handler(&p->phy);
1800
1801 if (phy_cause & cphy_cause_link_change)
1802 t3_link_changed(adapter, i);
1803 if (phy_cause & cphy_cause_fifo_error)
1804 p->phy.fifo_errors++;
1805 }
1806 }

--- 57 unchanged lines hidden (view full) ---

1864 t3_os_ext_intr_handler(adapter);
1865
1866 /* Clear the interrupts just processed. */
1867 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
1868 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1869 return 1;
1870}
1871
1825 int phy_cause = p->phy.ops->intr_handler(&p->phy);
1826
1827 if (phy_cause & cphy_cause_link_change)
1828 t3_link_changed(adapter, i);
1829 if (phy_cause & cphy_cause_fifo_error)
1830 p->phy.fifo_errors++;
1831 }
1832 }

--- 57 unchanged lines hidden (view full) ---

1890 t3_os_ext_intr_handler(adapter);
1891
1892 /* Clear the interrupts just processed. */
1893 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
1894 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1895 return 1;
1896}
1897
1898static unsigned int calc_gpio_intr(adapter_t *adap)
1899{
1900 unsigned int i, gpi_intr = 0;
1901
1902 for_each_port(adap, i)
1903 if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) &&
1904 adapter_info(adap)->gpio_intr[i])
1905 gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i];
1906 return gpi_intr;
1907}
1908
1872/**
1873 * t3_intr_enable - enable interrupts
1874 * @adapter: the adapter whose interrupts should be enabled
1875 *
1876 * Enable interrupts by setting the interrupt enable registers of the
1877 * various HW modules and then enabling the top-level interrupt
1878 * concentrator.
1879 */

--- 26 unchanged lines hidden (view full) ---

1906 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1907 ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 |
1908 F_PBL_BOUND_ERR_CH1);
1909 } else {
1910 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
1911 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1912 }
1913
1909/**
1910 * t3_intr_enable - enable interrupts
1911 * @adapter: the adapter whose interrupts should be enabled
1912 *
1913 * Enable interrupts by setting the interrupt enable registers of the
1914 * various HW modules and then enabling the top-level interrupt
1915 * concentrator.
1916 */

--- 26 unchanged lines hidden (view full) ---

1943 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1944 ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 |
1945 F_PBL_BOUND_ERR_CH1);
1946 } else {
1947 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
1948 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1949 }
1950
1914 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW,
1915 adapter_info(adapter)->gpio_intr);
1916 t3_write_reg(adapter, A_T3DBG_INT_ENABLE,
1917 adapter_info(adapter)->gpio_intr);
1951 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter));
1952
1918 if (is_pcie(adapter))
1919 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1920 else
1921 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
1922 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
1923 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1924}
1925

--- 629 unchanged lines hidden (view full) ---

2555 unsigned int mask, unsigned int val)
2556{
2557 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2558 val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
2559 t3_write_reg(adap, A_TP_PIO_DATA, val);
2560}
2561
2562/**
1953 if (is_pcie(adapter))
1954 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1955 else
1956 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
1957 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
1958 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1959}
1960

--- 629 unchanged lines hidden (view full) ---

2590 unsigned int mask, unsigned int val)
2591{
2592 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2593 val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
2594 t3_write_reg(adap, A_TP_PIO_DATA, val);
2595}
2596
2597/**
2598 * t3_enable_filters - enable the HW filters
2599 * @adap: the adapter
2600 *
2601 * Enables the HW filters for NIC traffic.
2602 */
2603void t3_enable_filters(adapter_t *adap)
2604{
2605 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, 0);
2606 t3_set_reg_field(adap, A_MC5_DB_CONFIG, 0, F_FILTEREN);
2607 t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, 0, V_FIVETUPLELOOKUP(3));
2608 tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, 0, F_LOOKUPEVERYPKT);
2609}
2610
2611/**
2563 * pm_num_pages - calculate the number of pages of the payload memory
2564 * @mem_size: the size of the payload memory
2565 * @pg_size: the size of each payload memory page
2566 *
2567 * Calculate the number of pages, each of the given size, that fit in a
2568 * memory of the specified size, respecting the HW requirement that the
2569 * number of pages must be a multiple of 24.
2570 */

--- 83 unchanged lines hidden (view full) ---

2654
2655static void tp_config(adapter_t *adap, const struct tp_params *p)
2656{
2657 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2658 F_IPCHECKSUMOFFLOAD | F_UDPCHECKSUMOFFLOAD |
2659 F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
2660 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2661 F_MTUENABLE | V_WINDOWSCALEMODE(1) |
2612 * pm_num_pages - calculate the number of pages of the payload memory
2613 * @mem_size: the size of the payload memory
2614 * @pg_size: the size of each payload memory page
2615 *
2616 * Calculate the number of pages, each of the given size, that fit in a
2617 * memory of the specified size, respecting the HW requirement that the
2618 * number of pages must be a multiple of 24.
2619 */

--- 83 unchanged lines hidden (view full) ---

2703
2704static void tp_config(adapter_t *adap, const struct tp_params *p)
2705{
2706 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2707 F_IPCHECKSUMOFFLOAD | F_UDPCHECKSUMOFFLOAD |
2708 F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
2709 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2710 F_MTUENABLE | V_WINDOWSCALEMODE(1) |
2662 V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1));
2711 V_TIMESTAMPSMODE(1) | V_SACKMODE(1) | V_SACKRX(1));
2663 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2664 V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
2712 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2713 V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
2665 V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) |
2714 V_BYTETHRESHOLD(26880) | V_MSSTHRESHOLD(2) |
2666 F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1));
2667 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
2668 F_IPV6ENABLE | F_NICMODE);
2669 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2670 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2671 t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
2672 adap->params.rev > 0 ? F_ENABLEESND :
2673 F_T3A_ENABLEESND);

--- 25 unchanged lines hidden (view full) ---

2699
2700 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2701 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2702 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2703 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2704
2705 if (adap->params.nports > 2) {
2706 t3_set_reg_field(adap, A_TP_PC_CONFIG2, 0,
2715 F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1));
2716 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
2717 F_IPV6ENABLE | F_NICMODE);
2718 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2719 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2720 t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
2721 adap->params.rev > 0 ? F_ENABLEESND :
2722 F_T3A_ENABLEESND);

--- 25 unchanged lines hidden (view full) ---

2748
2749 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2750 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2751 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2752 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2753
2754 if (adap->params.nports > 2) {
2755 t3_set_reg_field(adap, A_TP_PC_CONFIG2, 0,
2707 F_ENABLETXPORTFROMDA | F_ENABLERXPORTFROMADDR);
2756 F_ENABLETXPORTFROMDA2 | F_ENABLETXPORTFROMDA |
2757 F_ENABLERXPORTFROMADDR);
2708 tp_wr_bits_indirect(adap, A_TP_QOS_RX_MAP_MODE,
2709 V_RXMAPMODE(M_RXMAPMODE), 0);
2710 tp_wr_indirect(adap, A_TP_INGRESS_CONFIG, V_BITPOS0(48) |
2711 V_BITPOS1(49) | V_BITPOS2(50) | V_BITPOS3(51) |
2712 F_ENABLEEXTRACT | F_ENABLEEXTRACTIONSFD |
2713 F_ENABLEINSERTION | F_ENABLEINSERTIONSFD);
2714 tp_wr_indirect(adap, A_TP_PREAMBLE_MSB, 0xfb000000);
2715 tp_wr_indirect(adap, A_TP_PREAMBLE_LSB, 0xd5);

--- 898 unchanged lines hidden (view full) ---

3614 F_CFG_CQE_SOP_MASK);
3615
3616 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3617 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
3618 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
3619 chan_init_hw(adapter, adapter->params.chan_map);
3620 t3_sge_init(adapter, &adapter->params.sge);
3621
2758 tp_wr_bits_indirect(adap, A_TP_QOS_RX_MAP_MODE,
2759 V_RXMAPMODE(M_RXMAPMODE), 0);
2760 tp_wr_indirect(adap, A_TP_INGRESS_CONFIG, V_BITPOS0(48) |
2761 V_BITPOS1(49) | V_BITPOS2(50) | V_BITPOS3(51) |
2762 F_ENABLEEXTRACT | F_ENABLEEXTRACTIONSFD |
2763 F_ENABLEINSERTION | F_ENABLEINSERTIONSFD);
2764 tp_wr_indirect(adap, A_TP_PREAMBLE_MSB, 0xfb000000);
2765 tp_wr_indirect(adap, A_TP_PREAMBLE_LSB, 0xd5);

--- 898 unchanged lines hidden (view full) ---

3664 F_CFG_CQE_SOP_MASK);
3665
3666 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3667 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
3668 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
3669 chan_init_hw(adapter, adapter->params.chan_map);
3670 t3_sge_init(adapter, &adapter->params.sge);
3671
3672 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter));
3673
3622 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3623 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3624 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
3625 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3626
3627 attempts = 100;
3628 do { /* wait for uP to initialize */
3629 msleep(20);

--- 378 unchanged lines hidden --- 		3674 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3675 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3676 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
3677 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3678
3679 attempts = 100;
3680 do { /* wait for uP to initialize */
3681 msleep(20);

--- 378 unchanged lines hidden ---