1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
--- 14 unchanged lines hidden (view full) ---
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28***************************************************************************/
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_hw.c 176472 2008-02-23 01:06:17Z kmacy $");
32
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39
--- 359 unchanged lines hidden (view full) ---
399 if (advert & ADVERTISED_Pause)
400 val |= ADVERTISE_PAUSE_CAP;
401 if (advert & ADVERTISED_Asym_Pause)
402 val |= ADVERTISE_PAUSE_ASYM;
403 return mdio_write(phy, 0, MII_ADVERTISE, val);
404}
405
406/**
407 * t3_phy_advertise_fiber - set fiber PHY advertisement register
408 * @phy: the PHY to operate on
409 * @advert: bitmap of capabilities the PHY should advertise
410 *
411 * Sets a fiber PHY's advertisement register to advertise the
412 * requested capabilities.
413 */
414int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert)
415{
416 unsigned int val = 0;
417
418 if (advert & ADVERTISED_1000baseT_Half)
419 val |= ADVERTISE_1000XHALF;
420 if (advert & ADVERTISED_1000baseT_Full)
421 val |= ADVERTISE_1000XFULL;
422 if (advert & ADVERTISED_Pause)
423 val |= ADVERTISE_1000XPAUSE;
424 if (advert & ADVERTISED_Asym_Pause)
425 val |= ADVERTISE_1000XPSE_ASYM;
426 return mdio_write(phy, 0, MII_ADVERTISE, val);
427}
428
429/**
430 * t3_set_phy_speed_duplex - force PHY speed and duplex
431 * @phy: the PHY to operate on
432 * @speed: requested PHY speed
433 * @duplex: requested PHY duplex
434 *
435 * Force a 10/100/1000 PHY's speed and duplex. This also disables
436 * auto-negotiation except for GigE, where auto-negotiation is mandatory.
437 */
--- 31 unchanged lines hidden (view full) ---
469 &mi1_mdio_ops, "Chelsio PE9000" },
470 { 1, 1, 0, 0, 0,
471 F_GPIO2_OEN | F_GPIO4_OEN |
472 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
473 0,
474 &mi1_mdio_ops, "Chelsio T302" },
475 { 1, 0, 0, 0, 0,
476 F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
477 F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
478 0, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
479 &mi1_mdio_ext_ops, "Chelsio T310" },
480 { 1, 1, 0, 0, 0,
481 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
482 F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
483 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
484 SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
485 &mi1_mdio_ext_ops, "Chelsio T320" },
486 { 4, 0, 0, 0, 0,
--- 7 unchanged lines hidden (view full) ---
494 * Return the adapter_info structure with a given index. Out-of-range indices
495 * return NULL.
496 */
497const struct adapter_info *t3_get_adapter_info(unsigned int id)
498{
499 return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
500}
501
502static struct port_type_info port_types[] = {
503 { NULL },
504 { t3_ael1002_phy_prep },
505 { t3_vsc8211_phy_prep },
506 { t3_mv88e1xxx_phy_prep },
507 { t3_xaui_direct_phy_prep },
508 { NULL },
509 { t3_qt2045_phy_prep },
510 { t3_ael1006_phy_prep },
511 { NULL },
512};
513
514#define VPD_ENTRY(name, len) \
515 u8 name##_kword[2]; u8 name##_len; u8 name##_data[len]
516
517/*
518 * Partial EEPROM Vital Product Data structure. Includes only the ID and
519 * VPD-R sections.
520 */
521struct t3_vpd {
522 u8 id_tag;
523 u8 id_len[2];
--- 161 unchanged lines hidden (view full) ---
685 }
686
687 for (i = 0; i < 6; i++)
688 p->eth_base[i] = hex2int(vpd.na_data[2 * i]) * 16 +
689 hex2int(vpd.na_data[2 * i + 1]);
690 return 0;
691}
692
693/* BIOS boot header */
694typedef struct boot_header_s {
695 u8 signature[2]; /* signature */
696 u8 length; /* image length (include header) */
697 u8 offset[4]; /* initialization vector */
698 u8 reserved[19]; /* reserved */
699 u8 exheader[2]; /* offset to expansion header */
700} boot_header_t;
701
702/* serial flash and firmware constants */
703enum {
704 SF_ATTEMPTS = 5, /* max retries for SF1 operations */
705 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
706 SF_SIZE = SF_SEC_SIZE * 8, /* serial flash size */
707
708 /* flash command opcodes */
709 SF_PROG_PAGE = 2, /* program page */
710 SF_WR_DISABLE = 4, /* disable writes */
711 SF_RD_STATUS = 5, /* read status register */
712 SF_WR_ENABLE = 6, /* enable writes */
713 SF_RD_DATA_FAST = 0xb, /* read flash */
714 SF_ERASE_SECTOR = 0xd8, /* erase sector */
715
716 FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */
717 FW_VERS_ADDR = 0x77ffc, /* flash address holding FW version */
718 FW_MIN_SIZE = 8, /* at least version and csum */
719 FW_MAX_SIZE = FW_VERS_ADDR - FW_FLASH_BOOT_ADDR,
720
721 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
722 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */
723 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */
724 BOOT_MIN_SIZE = sizeof(boot_header_t), /* at least basic header */
725 BOOT_MAX_SIZE = 0xff*BOOT_SIZE_INC /* 1 byte * length increment */
726};
727
728/**
729 * sf1_read - read data from the serial flash
730 * @adapter: the adapter
731 * @byte_cnt: number of bytes to read
732 * @cont: whether another operation will be chained
733 * @valp: where to store the read data
--- 106 unchanged lines hidden (view full) ---
840}
841
842/**
843 * t3_write_flash - write up to a page of data to the serial flash
844 * @adapter: the adapter
845 * @addr: the start address to write
846 * @n: length of data to write
847 * @data: the data to write
848 * @byte_oriented: whether to store data as bytes or as words
849 *
850 * Writes up to a page of data (256 bytes) to the serial flash starting
851 * at the given address.
852 * If @byte_oriented is set the write data is stored as a 32-bit
853 * big-endian array, otherwise in the processor's native endianess.
854 *
855 */
856static int t3_write_flash(adapter_t *adapter, unsigned int addr,
857 unsigned int n, const u8 *data,
858 int byte_oriented)
859{
860 int ret;
861 u32 buf[64];
862 unsigned int c, left, val, offset = addr & 0xff;
863
864 if (addr + n > SF_SIZE || offset + n > 256)
865 return -EINVAL;
866
867 val = swab32(addr) | SF_PROG_PAGE;
868
869 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
870 (ret = sf1_write(adapter, 4, 1, val)) != 0)
871 return ret;
872
873 for (left = n; left; left -= c) {
874 c = min(left, 4U);
875 val = *(const u32*)data;
876 data += c;
877 if (byte_oriented)
878 val = htonl(val);
879
880 ret = sf1_write(adapter, c, c != left, val);
881 if (ret)
882 return ret;
883 }
884 if ((ret = flash_wait_op(adapter, 5, 1)) != 0)
885 return ret;
886
887 /* Read the page to verify the write succeeded */
888 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
889 byte_oriented);
890 if (ret)
891 return ret;
892
893 if (memcmp(data - n, (u8 *)buf + offset, n))
894 return -EIO;
895 return 0;
896}
897
--- 20 unchanged lines hidden (view full) ---
918 return 0;
919}
920
921/**
922 * t3_check_tpsram_version - read the tp sram version
923 * @adapter: the adapter
924 *
925 */
926int t3_check_tpsram_version(adapter_t *adapter, int *must_load)
927{
928 int ret;
929 u32 vers;
930 unsigned int major, minor;
931
932 if (adapter->params.rev == T3_REV_A)
933 return 0;
934
935 *must_load = 1;
936
937 ret = t3_get_tp_version(adapter, &vers);
938 if (ret)
939 return ret;
940
941 vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
942
943 major = G_TP_VERSION_MAJOR(vers);
944 minor = G_TP_VERSION_MINOR(vers);
945
946 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
947 return 0;
948
949 if (major != TP_VERSION_MAJOR)
950 CH_ERR(adapter, "found wrong TP version (%u.%u), "
951 "driver needs version %d.%d\n", major, minor,
952 TP_VERSION_MAJOR, TP_VERSION_MINOR);
953 else {
954 *must_load = 0;
955 CH_ERR(adapter, "found wrong TP version (%u.%u), "
956 "driver compiled for version %d.%d\n", major, minor,
957 TP_VERSION_MAJOR, TP_VERSION_MINOR);
958 }
959 return -EINVAL;
960}
961
962/**
963 * t3_check_tpsram - check if provided protocol SRAM
964 * is compatible with this driver
965 * @adapter: the adapter
966 * @tp_sram: the firmware image to write
--- 39 unchanged lines hidden (view full) ---
1006
1007/**
1008 * t3_check_fw_version - check if the FW is compatible with this driver
1009 * @adapter: the adapter
1010 *
1011 * Checks if an adapter's FW is compatible with the driver. Returns 0
1012 * if the versions are compatible, a negative error otherwise.
1013 */
1014int t3_check_fw_version(adapter_t *adapter, int *must_load)
1015{
1016 int ret;
1017 u32 vers;
1018 unsigned int type, major, minor;
1019
1020 *must_load = 1;
1021 ret = t3_get_fw_version(adapter, &vers);
1022 if (ret)
1023 return ret;
1024
1025 type = G_FW_VERSION_TYPE(vers);
1026 major = G_FW_VERSION_MAJOR(vers);
1027 minor = G_FW_VERSION_MINOR(vers);
1028
1029 if (type == FW_VERSION_T3 && major == FW_VERSION_MAJOR &&
1030 minor == FW_VERSION_MINOR)
1031 return 0;
1032
1033 if (major != FW_VERSION_MAJOR)
1034 CH_ERR(adapter, "found wrong FW version(%u.%u), "
1035 "driver needs version %u.%u\n", major, minor,
1036 FW_VERSION_MAJOR, FW_VERSION_MINOR);
1037 else if ((int)minor < FW_VERSION_MINOR) {
1038 *must_load = 0;
1039 CH_WARN(adapter, "found old FW minor version(%u.%u), "
1040 "driver compiled for version %u.%u\n", major, minor,
1041 FW_VERSION_MAJOR, FW_VERSION_MINOR);
1042 } else {
1043 CH_WARN(adapter, "found newer FW version(%u.%u), "
1044 "driver compiled for version %u.%u\n", major, minor,
1045 FW_VERSION_MAJOR, FW_VERSION_MINOR);
1046 return 0;
1047 }
1048 return -EINVAL;
1049}
1050
1051/**
1052 * t3_flash_erase_sectors - erase a range of flash sectors
1053 * @adapter: the adapter
1054 * @start: the first sector to erase
1055 * @end: the last sector to erase
--- 30 unchanged lines hidden (view full) ---
1086{
1087 u32 csum;
1088 unsigned int i;
1089 const u32 *p = (const u32 *)fw_data;
1090 int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16;
1091
1092 if ((size & 3) || size < FW_MIN_SIZE)
1093 return -EINVAL;
1094 if (size - 8 > FW_MAX_SIZE)
1095 return -EFBIG;
1096
1097 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1098 csum += ntohl(p[i]);
1099 if (csum != 0xffffffff) {
1100 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1101 csum);
1102 return -EINVAL;
1103 }
1104
1105 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector);
1106 if (ret)
1107 goto out;
1108
1109 size -= 8; /* trim off version and checksum */
1110 for (addr = FW_FLASH_BOOT_ADDR; size; ) {
1111 unsigned int chunk_size = min(size, 256U);
1112
1113 ret = t3_write_flash(adapter, addr, chunk_size, fw_data, 1);
1114 if (ret)
1115 goto out;
1116
1117 addr += chunk_size;
1118 fw_data += chunk_size;
1119 size -= chunk_size;
1120 }
1121
1122 ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data, 1);
1123out:
1124 if (ret)
1125 CH_ERR(adapter, "firmware download failed, error %d\n", ret);
1126 return ret;
1127}
1128
1129/*
1130 * t3_load_boot - download boot flash
1131 * @adapter: the adapter
1132 * @boot_data: the boot image to write
1133 * @size: image size
1134 *
1135 * Write the supplied boot image to the card's serial flash.
1136 * The boot image has the following sections: a 28-byte header and the
1137 * boot image.
1138 */
1139int t3_load_boot(adapter_t *adapter, u8 *boot_data, unsigned int size)
1140{
1141 boot_header_t *header = (boot_header_t *)boot_data;
1142 int ret;
1143 unsigned int addr;
1144 unsigned int boot_sector = BOOT_FLASH_BOOT_ADDR >> 16;
1145 unsigned int boot_end = (BOOT_FLASH_BOOT_ADDR + size - 1) >> 16;
1146
1147 /*
1148 * Perform some primitive sanity testing to avoid accidentally
1149 * writing garbage over the boot sectors. We ought to check for
1150 * more but it's not worth it for now ...
1151 */
1152 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
1153 CH_ERR(adapter, "boot image too small/large\n");
1154 return -EFBIG;
1155 }
1156 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE) {
1157 CH_ERR(adapter, "boot image missing signature\n");
1158 return -EINVAL;
1159 }
1160 if (header->length * BOOT_SIZE_INC != size) {
1161 CH_ERR(adapter, "boot image header length != image length\n");
1162 return -EINVAL;
1163 }
1164
1165 ret = t3_flash_erase_sectors(adapter, boot_sector, boot_end);
1166 if (ret)
1167 goto out;
1168
1169 for (addr = BOOT_FLASH_BOOT_ADDR; size; ) {
1170 unsigned int chunk_size = min(size, 256U);
1171
1172 ret = t3_write_flash(adapter, addr, chunk_size, boot_data, 0);
1173 if (ret)
1174 goto out;
1175
1176 addr += chunk_size;
1177 boot_data += chunk_size;
1178 size -= chunk_size;
1179 }
1180
1181out:
1182 if (ret)
1183 CH_ERR(adapter, "boot image download failed, error %d\n", ret);
1184 return ret;
1185}
1186
1187#define CIM_CTL_BASE 0x2000
1188
1189/**
1190 * t3_cim_ctl_blk_read - read a block from CIM control region
1191 * @adap: the adapter
1192 * @addr: the start address within the CIM control region
1193 * @n: number of words to read
1194 * @valp: where to store the result
--- 91 unchanged lines hidden (view full) ---
1286 if (lc->autoneg == AUTONEG_DISABLE) {
1287 lc->speed = lc->requested_speed;
1288 lc->duplex = lc->requested_duplex;
1289 lc->fc = (unsigned char)fc;
1290 t3_mac_set_speed_duplex_fc(mac, lc->speed, lc->duplex,
1291 fc);
1292 /* Also disables autoneg */
1293 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
1294 } else
1295 phy->ops->autoneg_enable(phy);
1296 } else {
1297 t3_mac_set_speed_duplex_fc(mac, -1, -1, fc);
1298 lc->fc = (unsigned char)fc;
1299 phy->ops->reset(phy, 0);
1300 }
1301 return 0;
--- 56 unchanged lines hidden (view full) ---
1358 if (acts->stat_idx >= 0)
1359 stats[acts->stat_idx]++;
1360 }
1361 if (status) /* clear processed interrupts */
1362 t3_write_reg(adapter, reg, status);
1363 return fatal;
1364}
1365
1366#define SGE_INTR_MASK (F_RSPQDISABLED | \
1367 F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR | \
1368 F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \
1369 F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \
1370 V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \
1371 F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \
1372 F_HIRCQPARITYERROR)
1373#define MC5_INTR_MASK (F_PARITYERR | F_ACTRGNFULL | F_UNKNOWNCMD | \
1374 F_REQQPARERR | F_DISPQPARERR | F_DELACTEMPTY | \
1375 F_NFASRCHFAIL)
1376#define MC7_INTR_MASK (F_AE | F_UE | F_CE | V_PE(M_PE))
1377#define XGM_INTR_MASK (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \
1378 V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR) | \
1379 F_TXFIFO_UNDERRUN | F_RXFIFO_OVERFLOW)
1380#define PCIX_INTR_MASK (F_MSTDETPARERR | F_SIGTARABT | F_RCVTARABT | \
1381 F_RCVMSTABT | F_SIGSYSERR | F_DETPARERR | \
1382 F_SPLCMPDIS | F_UNXSPLCMP | F_RCVSPLCMPERR | \
1383 F_DETCORECCERR | F_DETUNCECCERR | F_PIOPARERR | \
1384 V_WFPARERR(M_WFPARERR) | V_RFPARERR(M_RFPARERR) | \
1385 V_CFPARERR(M_CFPARERR) /* | V_MSIXPARERR(M_MSIXPARERR) */)
1386#define PCIE_INTR_MASK (F_UNXSPLCPLERRR | F_UNXSPLCPLERRC | F_PCIE_PIOPARERR |\
1387 F_PCIE_WFPARERR | F_PCIE_RFPARERR | F_PCIE_CFPARERR | \
1388 /* V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR) | */ \
1389 F_RETRYBUFPARERR | F_RETRYLUTPARERR | F_RXPARERR | \
1390 F_TXPARERR | V_BISTERR(M_BISTERR))
1391#define ULPRX_INTR_MASK (F_PARERRDATA | F_PARERRPCMD | F_ARBPF1PERR | \
1392 F_ARBPF0PERR | F_ARBFPERR | F_PCMDMUXPERR | \
1393 F_DATASELFRAMEERR1 | F_DATASELFRAMEERR0)
1394#define ULPTX_INTR_MASK 0xfc
1395#define CPLSW_INTR_MASK (F_CIM_OP_MAP_PERR | F_TP_FRAMING_ERROR | \
1396 F_SGE_FRAMING_ERROR | F_CIM_FRAMING_ERROR | \
1397 F_ZERO_SWITCH_ERROR)
1398#define CIM_INTR_MASK (F_BLKWRPLINT | F_BLKRDPLINT | F_BLKWRCTLINT | \
1399 F_BLKRDCTLINT | F_BLKWRFLASHINT | F_BLKRDFLASHINT | \
1400 F_SGLWRFLASHINT | F_WRBLKFLASHINT | F_BLKWRBOOTINT | \
1401 F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT | \
1402 F_DRAMPARERR | F_ICACHEPARERR | F_DCACHEPARERR | \
1403 F_OBQSGEPARERR | F_OBQULPHIPARERR | F_OBQULPLOPARERR | \
1404 F_IBQSGELOPARERR | F_IBQSGEHIPARERR | F_IBQULPPARERR | \
1405 F_IBQTPPARERR | F_ITAGPARERR | F_DTAGPARERR)
1406#define PMTX_INTR_MASK (F_ZERO_C_CMD_ERROR | ICSPI_FRM_ERR | OESPI_FRM_ERR | \
1407 V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR) | \
1408 V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR))
1409#define PMRX_INTR_MASK (F_ZERO_E_CMD_ERROR | IESPI_FRM_ERR | OCSPI_FRM_ERR | \
1410 V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR) | \
1411 V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR))
1412#define MPS_INTR_MASK (V_TX0TPPARERRENB(M_TX0TPPARERRENB) | \
1413 V_TX1TPPARERRENB(M_TX1TPPARERRENB) | \
--- 52 unchanged lines hidden (view full) ---
1466 { F_UNXSPLCPLERRC,
1467 "PCI unexpected split completion DMA command error", -1, 1 },
1468 { F_PCIE_PIOPARERR, "PCI PIO FIFO parity error", -1, 1 },
1469 { F_PCIE_WFPARERR, "PCI write FIFO parity error", -1, 1 },
1470 { F_PCIE_RFPARERR, "PCI read FIFO parity error", -1, 1 },
1471 { F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1 },
1472 { V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR),
1473 "PCI MSI-X table/PBA parity error", -1, 1 },
1474 { F_RETRYBUFPARERR, "PCI retry buffer parity error", -1, 1 },
1475 { F_RETRYLUTPARERR, "PCI retry LUT parity error", -1, 1 },
1476 { F_RXPARERR, "PCI Rx parity error", -1, 1 },
1477 { F_TXPARERR, "PCI Tx parity error", -1, 1 },
1478 { V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1 },
1479 { 0 }
1480 };
1481
1482 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
1483 CH_ALERT(adapter, "PEX error code 0x%x\n",
1484 t3_read_reg(adapter, A_PCIE_PEX_ERR));
1485
--- 8 unchanged lines hidden (view full) ---
1494static void tp_intr_handler(adapter_t *adapter)
1495{
1496 static struct intr_info tp_intr_info[] = {
1497 { 0xffffff, "TP parity error", -1, 1 },
1498 { 0x1000000, "TP out of Rx pages", -1, 1 },
1499 { 0x2000000, "TP out of Tx pages", -1, 1 },
1500 { 0 }
1501 };
1502 static struct intr_info tp_intr_info_t3c[] = {
1503 { 0x1fffffff, "TP parity error", -1, 1 },
1504 { F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1 },
1505 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
1506 { 0 }
1507 };
1508
1509 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff,
1510 adapter->params.rev < T3_REV_C ?
1511 tp_intr_info : tp_intr_info_t3c, NULL))
1512 t3_fatal_err(adapter);
1513}
1514
1515/*
1516 * CIM interrupt handler.
1517 */
1518static void cim_intr_handler(adapter_t *adapter)
1519{
--- 5 unchanged lines hidden (view full) ---
1525 { F_WRBLKFLASHINT, "CIM write to cached flash space", -1, 1 },
1526 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
1527 { F_BLKRDFLASHINT, "CIM block read from flash space", -1, 1 },
1528 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
1529 { F_BLKRDCTLINT, "CIM block read from CTL space", -1, 1 },
1530 { F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1 },
1531 { F_BLKRDPLINT, "CIM block read from PL space", -1, 1 },
1532 { F_BLKWRPLINT, "CIM block write to PL space", -1, 1 },
1533 { F_DRAMPARERR, "CIM DRAM parity error", -1, 1 },
1534 { F_ICACHEPARERR, "CIM icache parity error", -1, 1 },
1535 { F_DCACHEPARERR, "CIM dcache parity error", -1, 1 },
1536 { F_OBQSGEPARERR, "CIM OBQ SGE parity error", -1, 1 },
1537 { F_OBQULPHIPARERR, "CIM OBQ ULPHI parity error", -1, 1 },
1538 { F_OBQULPLOPARERR, "CIM OBQ ULPLO parity error", -1, 1 },
1539 { F_IBQSGELOPARERR, "CIM IBQ SGELO parity error", -1, 1 },
1540 { F_IBQSGEHIPARERR, "CIM IBQ SGEHI parity error", -1, 1 },
1541 { F_IBQULPPARERR, "CIM IBQ ULP parity error", -1, 1 },
1542 { F_IBQTPPARERR, "CIM IBQ TP parity error", -1, 1 },
1543 { F_ITAGPARERR, "CIM itag parity error", -1, 1 },
1544 { F_DTAGPARERR, "CIM dtag parity error", -1, 1 },
1545 { 0 }
1546 };
1547
1548 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, CIM_INTR_MASK,
1549 cim_intr_info, NULL))
1550 t3_fatal_err(adapter);
1551}
1552
1553/*
1554 * ULP RX interrupt handler.
1555 */
1556static void ulprx_intr_handler(adapter_t *adapter)
1557{
1558 static struct intr_info ulprx_intr_info[] = {
1559 { F_PARERRDATA, "ULP RX data parity error", -1, 1 },
1560 { F_PARERRPCMD, "ULP RX command parity error", -1, 1 },
1561 { F_ARBPF1PERR, "ULP RX ArbPF1 parity error", -1, 1 },
1562 { F_ARBPF0PERR, "ULP RX ArbPF0 parity error", -1, 1 },
1563 { F_ARBFPERR, "ULP RX ArbF parity error", -1, 1 },
1564 { F_PCMDMUXPERR, "ULP RX PCMDMUX parity error", -1, 1 },
1565 { F_DATASELFRAMEERR1, "ULP RX frame error", -1, 1 },
1566 { F_DATASELFRAMEERR0, "ULP RX frame error", -1, 1 },
1567 { 0 }
1568 };
1569
1570 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff,
1571 ulprx_intr_info, NULL))
1572 t3_fatal_err(adapter);
1573}
1574
1575/*
1576 * ULP TX interrupt handler.
1577 */
1578static void ulptx_intr_handler(adapter_t *adapter)
1579{
1580 static struct intr_info ulptx_intr_info[] = {
1581 { F_PBL_BOUND_ERR_CH0, "ULP TX channel 0 PBL out of bounds",
1582 STAT_ULP_CH0_PBL_OOB, 0 },
1583 { F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds",
1584 STAT_ULP_CH1_PBL_OOB, 0 },
1585 { 0xfc, "ULP TX parity error", -1, 1 },
1586 { 0 }
1587 };
1588
1589 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff,
1590 ulptx_intr_info, adapter->irq_stats))
1591 t3_fatal_err(adapter);
1592}
1593
--- 58 unchanged lines hidden (view full) ---
1652}
1653
1654/*
1655 * CPL switch interrupt handler.
1656 */
1657static void cplsw_intr_handler(adapter_t *adapter)
1658{
1659 static struct intr_info cplsw_intr_info[] = {
1660 { F_CIM_OP_MAP_PERR, "CPL switch CIM parity error", -1, 1 },
1661 { F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1 },
1662 { F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1 },
1663 { F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1 },
1664 { F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1 },
1665 { F_ZERO_SWITCH_ERROR, "CPL switch no-switch error", -1, 1 },
1666 { 0 }
1667 };
1668
1669 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff,
--- 117 unchanged lines hidden (view full) ---
1787 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1788
1789 for_each_port(adapter, i) {
1790 struct port_info *p = adap2pinfo(adapter, i);
1791
1792 mask = gpi - (gpi & (gpi - 1));
1793 gpi -= mask;
1794
1795 if (!(p->phy.caps & SUPPORTED_IRQ))
1796 continue;
1797
1798 if (cause & mask) {
1799 int phy_cause = p->phy.ops->intr_handler(&p->phy);
1800
1801 if (phy_cause & cphy_cause_link_change)
1802 t3_link_changed(adapter, i);
1803 if (phy_cause & cphy_cause_fifo_error)
--- 79 unchanged lines hidden (view full) ---
1883 { A_SG_INT_ENABLE, SGE_INTR_MASK },
1884 { A_MC7_INT_ENABLE, MC7_INTR_MASK },
1885 { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR,
1886 MC7_INTR_MASK },
1887 { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR,
1888 MC7_INTR_MASK },
1889 { A_MC5_DB_INT_ENABLE, MC5_INTR_MASK },
1890 { A_ULPRX_INT_ENABLE, ULPRX_INTR_MASK },
1891 { A_PM1_TX_INT_ENABLE, PMTX_INTR_MASK },
1892 { A_PM1_RX_INT_ENABLE, PMRX_INTR_MASK },
1893 { A_CIM_HOST_INT_ENABLE, CIM_INTR_MASK },
1894 { A_MPS_INT_ENABLE, MPS_INTR_MASK },
1895 };
1896
1897 adapter->slow_intr_mask = PL_INTR_MASK;
1898
1899 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
1900 t3_write_reg(adapter, A_TP_INT_ENABLE,
1901 adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff);
1902
1903 if (adapter->params.rev > 0) {
1904 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
1905 CPLSW_INTR_MASK | F_CIM_OVFL_ERROR);
1906 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1907 ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 |
1908 F_PBL_BOUND_ERR_CH1);
1909 } else {
--- 135 unchanged lines hidden (view full) ---
2045 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
2046 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
2047 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2048 V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id));
2049 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2050 0, SG_CONTEXT_CMD_ATTEMPTS, 1);
2051}
2052
2053static int clear_sge_ctxt(adapter_t *adap, unsigned int id, unsigned int type)
2054{
2055 t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0);
2056 t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0);
2057 t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0);
2058 t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0);
2059 return t3_sge_write_context(adap, id, type);
2060}
2061
2062/**
2063 * t3_sge_init_ecntxt - initialize an SGE egress context
2064 * @adapter: the adapter to configure
2065 * @id: the context id
2066 * @gts_enable: whether to enable GTS for the context
2067 * @type: the egress context type
2068 * @respq: associated response queue
2069 * @base_addr: base address of queue
--- 485 unchanged lines hidden (view full) ---
2555 unsigned int mask, unsigned int val)
2556{
2557 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2558 val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
2559 t3_write_reg(adap, A_TP_PIO_DATA, val);
2560}
2561
2562/**
2563 * pm_num_pages - calculate the number of pages of the payload memory
2564 * @mem_size: the size of the payload memory
2565 * @pg_size: the size of each payload memory page
2566 *
2567 * Calculate the number of pages, each of the given size, that fit in a
2568 * memory of the specified size, respecting the HW requirement that the
2569 * number of pages must be a multiple of 24.
2570 */
--- 88 unchanged lines hidden (view full) ---
2659 F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
2660 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2661 F_MTUENABLE | V_WINDOWSCALEMODE(1) |
2662 V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1));
2663 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2664 V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
2665 V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) |
2666 F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1));
2667 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
2668 F_IPV6ENABLE | F_NICMODE);
2669 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2670 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2671 t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
2672 adap->params.rev > 0 ? F_ENABLEESND :
2673 F_T3A_ENABLEESND);
2674 t3_set_reg_field(adap, A_TP_PC_CONFIG,
2675 F_ENABLEEPCMDAFULL,
2676 F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK |
2677 F_TXCONGESTIONMODE | F_RXCONGESTIONMODE);
2678 t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL,
2679 F_ENABLEIPV6RSS | F_ENABLENONOFDTNLSYN |
2680 F_ENABLEARPMISS | F_DISBLEDAPARBIT0);
2681 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2682 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2683
2684 if (adap->params.rev > 0) {
2685 tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
2686 t3_set_reg_field(adap, A_TP_PARA_REG3, 0,
2687 F_TXPACEAUTO | F_TXPACEAUTOSTRICT);
2688 t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2689 tp_wr_indirect(adap, A_TP_VLAN_PRI_MAP, 0xfa50);
2690 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP0, 0xfac688);
2691 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP1, 0xfac688);
2692 } else
2693 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2694
2695 if (adap->params.rev == T3_REV_C)
2696 t3_set_reg_field(adap, A_TP_PC_CONFIG,
2697 V_TABLELATENCYDELTA(M_TABLELATENCYDELTA),
2698 V_TABLELATENCYDELTA(4));
2699
2700 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2701 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2702 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2703 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2704
2705 if (adap->params.nports > 2) {
2706 t3_set_reg_field(adap, A_TP_PC_CONFIG2, 0,
2707 F_ENABLETXPORTFROMDA | F_ENABLERXPORTFROMADDR);
--- 422 unchanged lines hidden (view full) ---
3130 if (kbps > 0) {
3131 kbps *= 125; /* -> bytes */
3132 for (cpt = 1; cpt <= 255; cpt++) {
3133 tps = clk / cpt;
3134 bpt = (kbps + tps / 2) / tps;
3135 if (bpt > 0 && bpt <= 255) {
3136 v = bpt * tps;
3137 delta = v >= kbps ? v - kbps : kbps - v;
3138 if (delta < mindelta) {
3139 mindelta = delta;
3140 selected_cpt = cpt;
3141 selected_bpt = bpt;
3142 }
3143 } else if (selected_cpt)
3144 break;
3145 }
3146 if (!selected_cpt)
--- 394 unchanged lines hidden (view full) ---
3541 else
3542 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
3543 V_ACKLAT(acklat));
3544
3545 t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
3546 V_REPLAYLMT(rpllmt));
3547
3548 t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
3549 t3_set_reg_field(adap, A_PCIE_CFG, 0,
3550 F_PCIE_DMASTOPEN | F_PCIE_CLIDECEN);
3551}
3552
3553/**
3554 * t3_init_hw - initialize and configure T3 HW modules
3555 * @adapter: the adapter
3556 * @fw_params: initial parameters to pass to firmware (optional)
3557 *
3558 * Initialize and configure T3 HW modules. This performs the
3559 * initialization steps that need to be done once after a card is reset.
3560 * MAC and PHY initialization is handled separarely whenever a port is
3561 * enabled.
3562 *
3563 * @fw_params are passed to FW and their value is platform dependent.
3564 * Only the top 8 bits are available for use, the rest must be 0.
3565 */
3566int t3_init_hw(adapter_t *adapter, u32 fw_params)
3567{
3568 int err = -EIO, attempts, i;
3569 const struct vpd_params *vpd = &adapter->params.vpd;
3570
3571 if (adapter->params.rev > 0)
3572 calibrate_xgm_t3b(adapter);
3573 else if (calibrate_xgm(adapter))
3574 goto out_err;
3575
3576 if (adapter->params.nports > 2)
--- 4 unchanged lines hidden (view full) ---
3581
3582 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
3583 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
3584 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
3585 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
3586 adapter->params.mc5.nfilters,
3587 adapter->params.mc5.nroutes))
3588 goto out_err;
3589
3590 for (i = 0; i < 32; i++)
3591 if (clear_sge_ctxt(adapter, i, F_CQ))
3592 goto out_err;
3593 }
3594
3595 if (tp_init(adapter, &adapter->params.tp))
3596 goto out_err;
3597
3598#ifdef CONFIG_CHELSIO_T3_CORE
3599 t3_tp_set_coalescing_size(adapter,
3600 min(adapter->params.sge.max_pkt_size,
3601 MAX_RX_COALESCING_LEN), 1);
3602 t3_tp_set_max_rxsize(adapter,
3603 min(adapter->params.sge.max_pkt_size, 16384U));
3604 ulp_config(adapter, &adapter->params.tp);
3605#endif
3606 if (is_pcie(adapter))
3607 config_pcie(adapter);
3608 else
3609 t3_set_reg_field(adapter, A_PCIX_CFG, 0,
3610 F_DMASTOPEN | F_CLIDECEN);
3611
3612 if (adapter->params.rev == T3_REV_C)
3613 t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0,
3614 F_CFG_CQE_SOP_MASK);
3615
3616 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3617 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
3618 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
3619 chan_init_hw(adapter, adapter->params.chan_map);
3620 t3_sge_init(adapter, &adapter->params.sge);
3621
3622 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3623 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3624 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
3625 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3626
3627 attempts = 100;
3628 do { /* wait for uP to initialize */
3629 msleep(20);
3630 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3631 if (!attempts) {
3632 CH_ERR(adapter, "uP initialization timed out\n");
3633 goto out_err;
3634 }
3635
--- 134 unchanged lines hidden (view full) ---
3770 3 : 2);
3771
3772 mi1_init(adapter, ai);
3773 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
3774 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1));
3775 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
3776 ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL);
3777 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
3778 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff));
3779
3780 if (adapter->params.rev == 0 || !uses_xaui(adapter))
3781 val |= F_ENRGMII;
3782
3783 /* Enable MAC clocks so we can access the registers */
3784 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3785 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
3786
--- 34 unchanged lines hidden (view full) ---
3821 if (devid != 0x1425)
3822 return -1;
3823
3824 if (save_and_restore_pcie)
3825 t3_os_pci_restore_state(adapter);
3826 return 0;
3827}
3828
3829static int __devinit init_parity(adapter_t *adap)
3830{
3831 int i, err, addr;
3832
3833 if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
3834 return -EBUSY;
3835
3836 for (err = i = 0; !err && i < 16; i++)
3837 err = clear_sge_ctxt(adap, i, F_EGRESS);
3838 for (i = 0xfff0; !err && i <= 0xffff; i++)
3839 err = clear_sge_ctxt(adap, i, F_EGRESS);
3840 for (i = 0; !err && i < SGE_QSETS; i++)
3841 err = clear_sge_ctxt(adap, i, F_RESPONSEQ);
3842 if (err)
3843 return err;
3844
3845 t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0);
3846 for (i = 0; i < 4; i++)
3847 for (addr = 0; addr <= M_IBQDBGADDR; addr++) {
3848 t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN |
3849 F_IBQDBGWR | V_IBQDBGQID(i) |
3850 V_IBQDBGADDR(addr));
3851 err = t3_wait_op_done(adap, A_CIM_IBQ_DBG_CFG,
3852 F_IBQDBGBUSY, 0, 2, 1);
3853 if (err)
3854 return err;
3855 }
3856 return 0;
3857}
3858
3859/**
3860 * t3_prep_adapter - prepare SW and HW for operation
3861 * @adapter: the adapter
3862 * @ai: contains information about the adapter type and properties
3863 *
3864 * Initialize adapter SW state for the various HW modules, set initial
3865 * values for some adapter tunables, take PHYs out of reset, and
3866 * initialize the MDIO interface.
--- 65 unchanged lines hidden (view full) ---
3932
3933#ifdef CONFIG_CHELSIO_T3_CORE
3934 init_mtus(adapter->params.mtus);
3935 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3936#endif
3937 }
3938
3939 early_hw_init(adapter, ai);
3940 ret = init_parity(adapter);
3941 if (ret)
3942 return ret;
3943
3944 if (adapter->params.nports > 2 &&
3945 (ret = t3_vsc7323_init(adapter, adapter->params.nports)))
3946 return ret;
3947
3948 for_each_port(adapter, i) {
3949 u8 hw_addr[6];
3950 const struct port_type_info *pti;
3951 struct port_info *p = adap2pinfo(adapter, i);
3952
3953 while (!adapter->params.vpd.port_type[j])
3954 ++j;
3955
3956 pti = &port_types[adapter->params.vpd.port_type[j]];
3957 ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
3958 ai->mdio_ops);
3959 if (ret)
3960 return ret;
3961 mac_prep(&p->mac, adapter, j);
3962 ++j;
3963
3964 /*
3965 * The VPD EEPROM stores the base Ethernet address for the
3966 * card. A port's address is derived from the base by adding
3967 * the port's index to the base's low octet.
3968 */
3969 memcpy(hw_addr, adapter->params.vpd.eth_base, 5);
3970 hw_addr[5] = adapter->params.vpd.eth_base[5] + i;
3971
3972 t3_os_set_hw_addr(adapter, i, hw_addr);
3973 init_link_config(&p->link_config, p->phy.caps);
3974 p->phy.ops->power_down(&p->phy, 1);
3975 if (!(p->phy.caps & SUPPORTED_IRQ))
3976 adapter->params.linkpoll_period = 10;
3977 }
3978
3979 return 0;
3980}
3981
3982void t3_led_ready(adapter_t *adapter)
3983{
--- 24 unchanged lines hidden ---
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
--- 14 unchanged lines hidden (view full) ---
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28***************************************************************************/
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_hw.c 176472 2008-02-23 01:06:17Z kmacy $");
32
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39
--- 359 unchanged lines hidden (view full) ---
399 if (advert & ADVERTISED_Pause)
400 val |= ADVERTISE_PAUSE_CAP;
401 if (advert & ADVERTISED_Asym_Pause)
402 val |= ADVERTISE_PAUSE_ASYM;
403 return mdio_write(phy, 0, MII_ADVERTISE, val);
404}
405
406/**
407 * t3_phy_advertise_fiber - set fiber PHY advertisement register
408 * @phy: the PHY to operate on
409 * @advert: bitmap of capabilities the PHY should advertise
410 *
411 * Sets a fiber PHY's advertisement register to advertise the
412 * requested capabilities.
413 */
414int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert)
415{
416 unsigned int val = 0;
417
418 if (advert & ADVERTISED_1000baseT_Half)
419 val |= ADVERTISE_1000XHALF;
420 if (advert & ADVERTISED_1000baseT_Full)
421 val |= ADVERTISE_1000XFULL;
422 if (advert & ADVERTISED_Pause)
423 val |= ADVERTISE_1000XPAUSE;
424 if (advert & ADVERTISED_Asym_Pause)
425 val |= ADVERTISE_1000XPSE_ASYM;
426 return mdio_write(phy, 0, MII_ADVERTISE, val);
427}
428
429/**
430 * t3_set_phy_speed_duplex - force PHY speed and duplex
431 * @phy: the PHY to operate on
432 * @speed: requested PHY speed
433 * @duplex: requested PHY duplex
434 *
435 * Force a 10/100/1000 PHY's speed and duplex. This also disables
436 * auto-negotiation except for GigE, where auto-negotiation is mandatory.
437 */
--- 31 unchanged lines hidden (view full) ---
469 &mi1_mdio_ops, "Chelsio PE9000" },
470 { 1, 1, 0, 0, 0,
471 F_GPIO2_OEN | F_GPIO4_OEN |
472 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
473 0,
474 &mi1_mdio_ops, "Chelsio T302" },
475 { 1, 0, 0, 0, 0,
476 F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
477 F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
478 0, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
479 &mi1_mdio_ext_ops, "Chelsio T310" },
480 { 1, 1, 0, 0, 0,
481 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
482 F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
483 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
484 SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
485 &mi1_mdio_ext_ops, "Chelsio T320" },
486 { 4, 0, 0, 0, 0,
--- 7 unchanged lines hidden (view full) ---
494 * Return the adapter_info structure with a given index. Out-of-range indices
495 * return NULL.
496 */
497const struct adapter_info *t3_get_adapter_info(unsigned int id)
498{
499 return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
500}
501
502static struct port_type_info port_types[] = {
503 { NULL },
504 { t3_ael1002_phy_prep },
505 { t3_vsc8211_phy_prep },
506 { t3_mv88e1xxx_phy_prep },
507 { t3_xaui_direct_phy_prep },
508 { NULL },
509 { t3_qt2045_phy_prep },
510 { t3_ael1006_phy_prep },
511 { NULL },
512};
513
514#define VPD_ENTRY(name, len) \
515 u8 name##_kword[2]; u8 name##_len; u8 name##_data[len]
516
517/*
518 * Partial EEPROM Vital Product Data structure. Includes only the ID and
519 * VPD-R sections.
520 */
521struct t3_vpd {
522 u8 id_tag;
523 u8 id_len[2];
--- 161 unchanged lines hidden (view full) ---
685 }
686
687 for (i = 0; i < 6; i++)
688 p->eth_base[i] = hex2int(vpd.na_data[2 * i]) * 16 +
689 hex2int(vpd.na_data[2 * i + 1]);
690 return 0;
691}
692
693/* BIOS boot header */
694typedef struct boot_header_s {
695 u8 signature[2]; /* signature */
696 u8 length; /* image length (include header) */
697 u8 offset[4]; /* initialization vector */
698 u8 reserved[19]; /* reserved */
699 u8 exheader[2]; /* offset to expansion header */
700} boot_header_t;
701
702/* serial flash and firmware constants */
703enum {
704 SF_ATTEMPTS = 5, /* max retries for SF1 operations */
705 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
706 SF_SIZE = SF_SEC_SIZE * 8, /* serial flash size */
707
708 /* flash command opcodes */
709 SF_PROG_PAGE = 2, /* program page */
710 SF_WR_DISABLE = 4, /* disable writes */
711 SF_RD_STATUS = 5, /* read status register */
712 SF_WR_ENABLE = 6, /* enable writes */
713 SF_RD_DATA_FAST = 0xb, /* read flash */
714 SF_ERASE_SECTOR = 0xd8, /* erase sector */
715
716 FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */
717 FW_VERS_ADDR = 0x77ffc, /* flash address holding FW version */
718 FW_MIN_SIZE = 8, /* at least version and csum */
719 FW_MAX_SIZE = FW_VERS_ADDR - FW_FLASH_BOOT_ADDR,
720
721 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
722 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */
723 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */
724 BOOT_MIN_SIZE = sizeof(boot_header_t), /* at least basic header */
725 BOOT_MAX_SIZE = 0xff*BOOT_SIZE_INC /* 1 byte * length increment */
726};
727
728/**
729 * sf1_read - read data from the serial flash
730 * @adapter: the adapter
731 * @byte_cnt: number of bytes to read
732 * @cont: whether another operation will be chained
733 * @valp: where to store the read data
--- 106 unchanged lines hidden (view full) ---
840}
841
842/**
843 * t3_write_flash - write up to a page of data to the serial flash
844 * @adapter: the adapter
845 * @addr: the start address to write
846 * @n: length of data to write
847 * @data: the data to write
848 * @byte_oriented: whether to store data as bytes or as words
849 *
850 * Writes up to a page of data (256 bytes) to the serial flash starting
851 * at the given address.
852 * If @byte_oriented is set the write data is stored as a 32-bit
853 * big-endian array, otherwise in the processor's native endianess.
854 *
855 */
856static int t3_write_flash(adapter_t *adapter, unsigned int addr,
857 unsigned int n, const u8 *data,
858 int byte_oriented)
859{
860 int ret;
861 u32 buf[64];
862 unsigned int c, left, val, offset = addr & 0xff;
863
864 if (addr + n > SF_SIZE || offset + n > 256)
865 return -EINVAL;
866
867 val = swab32(addr) | SF_PROG_PAGE;
868
869 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
870 (ret = sf1_write(adapter, 4, 1, val)) != 0)
871 return ret;
872
873 for (left = n; left; left -= c) {
874 c = min(left, 4U);
875 val = *(const u32*)data;
876 data += c;
877 if (byte_oriented)
878 val = htonl(val);
879
880 ret = sf1_write(adapter, c, c != left, val);
881 if (ret)
882 return ret;
883 }
884 if ((ret = flash_wait_op(adapter, 5, 1)) != 0)
885 return ret;
886
887 /* Read the page to verify the write succeeded */
888 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
889 byte_oriented);
890 if (ret)
891 return ret;
892
893 if (memcmp(data - n, (u8 *)buf + offset, n))
894 return -EIO;
895 return 0;
896}
897
--- 20 unchanged lines hidden (view full) ---
918 return 0;
919}
920
921/**
922 * t3_check_tpsram_version - read the tp sram version
923 * @adapter: the adapter
924 *
925 */
926int t3_check_tpsram_version(adapter_t *adapter, int *must_load)
927{
928 int ret;
929 u32 vers;
930 unsigned int major, minor;
931
932 if (adapter->params.rev == T3_REV_A)
933 return 0;
934
935 *must_load = 1;
936
937 ret = t3_get_tp_version(adapter, &vers);
938 if (ret)
939 return ret;
940
941 vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
942
943 major = G_TP_VERSION_MAJOR(vers);
944 minor = G_TP_VERSION_MINOR(vers);
945
946 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
947 return 0;
948
949 if (major != TP_VERSION_MAJOR)
950 CH_ERR(adapter, "found wrong TP version (%u.%u), "
951 "driver needs version %d.%d\n", major, minor,
952 TP_VERSION_MAJOR, TP_VERSION_MINOR);
953 else {
954 *must_load = 0;
955 CH_ERR(adapter, "found wrong TP version (%u.%u), "
956 "driver compiled for version %d.%d\n", major, minor,
957 TP_VERSION_MAJOR, TP_VERSION_MINOR);
958 }
959 return -EINVAL;
960}
961
962/**
963 * t3_check_tpsram - check if provided protocol SRAM
964 * is compatible with this driver
965 * @adapter: the adapter
966 * @tp_sram: the firmware image to write
--- 39 unchanged lines hidden (view full) ---
1006
1007/**
1008 * t3_check_fw_version - check if the FW is compatible with this driver
1009 * @adapter: the adapter
1010 *
1011 * Checks if an adapter's FW is compatible with the driver. Returns 0
1012 * if the versions are compatible, a negative error otherwise.
1013 */
1014int t3_check_fw_version(adapter_t *adapter, int *must_load)
1015{
1016 int ret;
1017 u32 vers;
1018 unsigned int type, major, minor;
1019
1020 *must_load = 1;
1021 ret = t3_get_fw_version(adapter, &vers);
1022 if (ret)
1023 return ret;
1024
1025 type = G_FW_VERSION_TYPE(vers);
1026 major = G_FW_VERSION_MAJOR(vers);
1027 minor = G_FW_VERSION_MINOR(vers);
1028
1029 if (type == FW_VERSION_T3 && major == FW_VERSION_MAJOR &&
1030 minor == FW_VERSION_MINOR)
1031 return 0;
1032
1033 if (major != FW_VERSION_MAJOR)
1034 CH_ERR(adapter, "found wrong FW version(%u.%u), "
1035 "driver needs version %u.%u\n", major, minor,
1036 FW_VERSION_MAJOR, FW_VERSION_MINOR);
1037 else if ((int)minor < FW_VERSION_MINOR) {
1038 *must_load = 0;
1039 CH_WARN(adapter, "found old FW minor version(%u.%u), "
1040 "driver compiled for version %u.%u\n", major, minor,
1041 FW_VERSION_MAJOR, FW_VERSION_MINOR);
1042 } else {
1043 CH_WARN(adapter, "found newer FW version(%u.%u), "
1044 "driver compiled for version %u.%u\n", major, minor,
1045 FW_VERSION_MAJOR, FW_VERSION_MINOR);
1046 return 0;
1047 }
1048 return -EINVAL;
1049}
1050
1051/**
1052 * t3_flash_erase_sectors - erase a range of flash sectors
1053 * @adapter: the adapter
1054 * @start: the first sector to erase
1055 * @end: the last sector to erase
--- 30 unchanged lines hidden (view full) ---
1086{
1087 u32 csum;
1088 unsigned int i;
1089 const u32 *p = (const u32 *)fw_data;
1090 int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16;
1091
1092 if ((size & 3) || size < FW_MIN_SIZE)
1093 return -EINVAL;
1094 if (size - 8 > FW_MAX_SIZE)
1095 return -EFBIG;
1096
1097 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1098 csum += ntohl(p[i]);
1099 if (csum != 0xffffffff) {
1100 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1101 csum);
1102 return -EINVAL;
1103 }
1104
1105 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector);
1106 if (ret)
1107 goto out;
1108
1109 size -= 8; /* trim off version and checksum */
1110 for (addr = FW_FLASH_BOOT_ADDR; size; ) {
1111 unsigned int chunk_size = min(size, 256U);
1112
1113 ret = t3_write_flash(adapter, addr, chunk_size, fw_data, 1);
1114 if (ret)
1115 goto out;
1116
1117 addr += chunk_size;
1118 fw_data += chunk_size;
1119 size -= chunk_size;
1120 }
1121
1122 ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data, 1);
1123out:
1124 if (ret)
1125 CH_ERR(adapter, "firmware download failed, error %d\n", ret);
1126 return ret;
1127}
1128
1129/*
1130 * t3_load_boot - download boot flash
1131 * @adapter: the adapter
1132 * @boot_data: the boot image to write
1133 * @size: image size
1134 *
1135 * Write the supplied boot image to the card's serial flash.
1136 * The boot image has the following sections: a 28-byte header and the
1137 * boot image.
1138 */
1139int t3_load_boot(adapter_t *adapter, u8 *boot_data, unsigned int size)
1140{
1141 boot_header_t *header = (boot_header_t *)boot_data;
1142 int ret;
1143 unsigned int addr;
1144 unsigned int boot_sector = BOOT_FLASH_BOOT_ADDR >> 16;
1145 unsigned int boot_end = (BOOT_FLASH_BOOT_ADDR + size - 1) >> 16;
1146
1147 /*
1148 * Perform some primitive sanity testing to avoid accidentally
1149 * writing garbage over the boot sectors. We ought to check for
1150 * more but it's not worth it for now ...
1151 */
1152 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
1153 CH_ERR(adapter, "boot image too small/large\n");
1154 return -EFBIG;
1155 }
1156 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE) {
1157 CH_ERR(adapter, "boot image missing signature\n");
1158 return -EINVAL;
1159 }
1160 if (header->length * BOOT_SIZE_INC != size) {
1161 CH_ERR(adapter, "boot image header length != image length\n");
1162 return -EINVAL;
1163 }
1164
1165 ret = t3_flash_erase_sectors(adapter, boot_sector, boot_end);
1166 if (ret)
1167 goto out;
1168
1169 for (addr = BOOT_FLASH_BOOT_ADDR; size; ) {
1170 unsigned int chunk_size = min(size, 256U);
1171
1172 ret = t3_write_flash(adapter, addr, chunk_size, boot_data, 0);
1173 if (ret)
1174 goto out;
1175
1176 addr += chunk_size;
1177 boot_data += chunk_size;
1178 size -= chunk_size;
1179 }
1180
1181out:
1182 if (ret)
1183 CH_ERR(adapter, "boot image download failed, error %d\n", ret);
1184 return ret;
1185}
1186
1187#define CIM_CTL_BASE 0x2000
1188
1189/**
1190 * t3_cim_ctl_blk_read - read a block from CIM control region
1191 * @adap: the adapter
1192 * @addr: the start address within the CIM control region
1193 * @n: number of words to read
1194 * @valp: where to store the result
--- 91 unchanged lines hidden (view full) ---
1286 if (lc->autoneg == AUTONEG_DISABLE) {
1287 lc->speed = lc->requested_speed;
1288 lc->duplex = lc->requested_duplex;
1289 lc->fc = (unsigned char)fc;
1290 t3_mac_set_speed_duplex_fc(mac, lc->speed, lc->duplex,
1291 fc);
1292 /* Also disables autoneg */
1293 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
1294 } else
1295 phy->ops->autoneg_enable(phy);
1296 } else {
1297 t3_mac_set_speed_duplex_fc(mac, -1, -1, fc);
1298 lc->fc = (unsigned char)fc;
1299 phy->ops->reset(phy, 0);
1300 }
1301 return 0;
--- 56 unchanged lines hidden (view full) ---
1358 if (acts->stat_idx >= 0)
1359 stats[acts->stat_idx]++;
1360 }
1361 if (status) /* clear processed interrupts */
1362 t3_write_reg(adapter, reg, status);
1363 return fatal;
1364}
1365
1366#define SGE_INTR_MASK (F_RSPQDISABLED | \
1367 F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR | \
1368 F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \
1369 F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \
1370 V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \
1371 F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \
1372 F_HIRCQPARITYERROR)
1373#define MC5_INTR_MASK (F_PARITYERR | F_ACTRGNFULL | F_UNKNOWNCMD | \
1374 F_REQQPARERR | F_DISPQPARERR | F_DELACTEMPTY | \
1375 F_NFASRCHFAIL)
1376#define MC7_INTR_MASK (F_AE | F_UE | F_CE | V_PE(M_PE))
1377#define XGM_INTR_MASK (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \
1378 V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR) | \
1379 F_TXFIFO_UNDERRUN | F_RXFIFO_OVERFLOW)
1380#define PCIX_INTR_MASK (F_MSTDETPARERR | F_SIGTARABT | F_RCVTARABT | \
1381 F_RCVMSTABT | F_SIGSYSERR | F_DETPARERR | \
1382 F_SPLCMPDIS | F_UNXSPLCMP | F_RCVSPLCMPERR | \
1383 F_DETCORECCERR | F_DETUNCECCERR | F_PIOPARERR | \
1384 V_WFPARERR(M_WFPARERR) | V_RFPARERR(M_RFPARERR) | \
1385 V_CFPARERR(M_CFPARERR) /* | V_MSIXPARERR(M_MSIXPARERR) */)
1386#define PCIE_INTR_MASK (F_UNXSPLCPLERRR | F_UNXSPLCPLERRC | F_PCIE_PIOPARERR |\
1387 F_PCIE_WFPARERR | F_PCIE_RFPARERR | F_PCIE_CFPARERR | \
1388 /* V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR) | */ \
1389 F_RETRYBUFPARERR | F_RETRYLUTPARERR | F_RXPARERR | \
1390 F_TXPARERR | V_BISTERR(M_BISTERR))
1391#define ULPRX_INTR_MASK (F_PARERRDATA | F_PARERRPCMD | F_ARBPF1PERR | \
1392 F_ARBPF0PERR | F_ARBFPERR | F_PCMDMUXPERR | \
1393 F_DATASELFRAMEERR1 | F_DATASELFRAMEERR0)
1394#define ULPTX_INTR_MASK 0xfc
1395#define CPLSW_INTR_MASK (F_CIM_OP_MAP_PERR | F_TP_FRAMING_ERROR | \
1396 F_SGE_FRAMING_ERROR | F_CIM_FRAMING_ERROR | \
1397 F_ZERO_SWITCH_ERROR)
1398#define CIM_INTR_MASK (F_BLKWRPLINT | F_BLKRDPLINT | F_BLKWRCTLINT | \
1399 F_BLKRDCTLINT | F_BLKWRFLASHINT | F_BLKRDFLASHINT | \
1400 F_SGLWRFLASHINT | F_WRBLKFLASHINT | F_BLKWRBOOTINT | \
1401 F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT | \
1402 F_DRAMPARERR | F_ICACHEPARERR | F_DCACHEPARERR | \
1403 F_OBQSGEPARERR | F_OBQULPHIPARERR | F_OBQULPLOPARERR | \
1404 F_IBQSGELOPARERR | F_IBQSGEHIPARERR | F_IBQULPPARERR | \
1405 F_IBQTPPARERR | F_ITAGPARERR | F_DTAGPARERR)
1406#define PMTX_INTR_MASK (F_ZERO_C_CMD_ERROR | ICSPI_FRM_ERR | OESPI_FRM_ERR | \
1407 V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR) | \
1408 V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR))
1409#define PMRX_INTR_MASK (F_ZERO_E_CMD_ERROR | IESPI_FRM_ERR | OCSPI_FRM_ERR | \
1410 V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR) | \
1411 V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR))
1412#define MPS_INTR_MASK (V_TX0TPPARERRENB(M_TX0TPPARERRENB) | \
1413 V_TX1TPPARERRENB(M_TX1TPPARERRENB) | \
--- 52 unchanged lines hidden (view full) ---
1466 { F_UNXSPLCPLERRC,
1467 "PCI unexpected split completion DMA command error", -1, 1 },
1468 { F_PCIE_PIOPARERR, "PCI PIO FIFO parity error", -1, 1 },
1469 { F_PCIE_WFPARERR, "PCI write FIFO parity error", -1, 1 },
1470 { F_PCIE_RFPARERR, "PCI read FIFO parity error", -1, 1 },
1471 { F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1 },
1472 { V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR),
1473 "PCI MSI-X table/PBA parity error", -1, 1 },
1474 { F_RETRYBUFPARERR, "PCI retry buffer parity error", -1, 1 },
1475 { F_RETRYLUTPARERR, "PCI retry LUT parity error", -1, 1 },
1476 { F_RXPARERR, "PCI Rx parity error", -1, 1 },
1477 { F_TXPARERR, "PCI Tx parity error", -1, 1 },
1478 { V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1 },
1479 { 0 }
1480 };
1481
1482 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
1483 CH_ALERT(adapter, "PEX error code 0x%x\n",
1484 t3_read_reg(adapter, A_PCIE_PEX_ERR));
1485
--- 8 unchanged lines hidden (view full) ---
1494static void tp_intr_handler(adapter_t *adapter)
1495{
1496 static struct intr_info tp_intr_info[] = {
1497 { 0xffffff, "TP parity error", -1, 1 },
1498 { 0x1000000, "TP out of Rx pages", -1, 1 },
1499 { 0x2000000, "TP out of Tx pages", -1, 1 },
1500 { 0 }
1501 };
1502 static struct intr_info tp_intr_info_t3c[] = {
1503 { 0x1fffffff, "TP parity error", -1, 1 },
1504 { F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1 },
1505 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
1506 { 0 }
1507 };
1508
1509 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff,
1510 adapter->params.rev < T3_REV_C ?
1511 tp_intr_info : tp_intr_info_t3c, NULL))
1512 t3_fatal_err(adapter);
1513}
1514
1515/*
1516 * CIM interrupt handler.
1517 */
1518static void cim_intr_handler(adapter_t *adapter)
1519{
--- 5 unchanged lines hidden (view full) ---
1525 { F_WRBLKFLASHINT, "CIM write to cached flash space", -1, 1 },
1526 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
1527 { F_BLKRDFLASHINT, "CIM block read from flash space", -1, 1 },
1528 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
1529 { F_BLKRDCTLINT, "CIM block read from CTL space", -1, 1 },
1530 { F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1 },
1531 { F_BLKRDPLINT, "CIM block read from PL space", -1, 1 },
1532 { F_BLKWRPLINT, "CIM block write to PL space", -1, 1 },
1533 { F_DRAMPARERR, "CIM DRAM parity error", -1, 1 },
1534 { F_ICACHEPARERR, "CIM icache parity error", -1, 1 },
1535 { F_DCACHEPARERR, "CIM dcache parity error", -1, 1 },
1536 { F_OBQSGEPARERR, "CIM OBQ SGE parity error", -1, 1 },
1537 { F_OBQULPHIPARERR, "CIM OBQ ULPHI parity error", -1, 1 },
1538 { F_OBQULPLOPARERR, "CIM OBQ ULPLO parity error", -1, 1 },
1539 { F_IBQSGELOPARERR, "CIM IBQ SGELO parity error", -1, 1 },
1540 { F_IBQSGEHIPARERR, "CIM IBQ SGEHI parity error", -1, 1 },
1541 { F_IBQULPPARERR, "CIM IBQ ULP parity error", -1, 1 },
1542 { F_IBQTPPARERR, "CIM IBQ TP parity error", -1, 1 },
1543 { F_ITAGPARERR, "CIM itag parity error", -1, 1 },
1544 { F_DTAGPARERR, "CIM dtag parity error", -1, 1 },
1545 { 0 }
1546 };
1547
1548 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, CIM_INTR_MASK,
1549 cim_intr_info, NULL))
1550 t3_fatal_err(adapter);
1551}
1552
1553/*
1554 * ULP RX interrupt handler.
1555 */
1556static void ulprx_intr_handler(adapter_t *adapter)
1557{
1558 static struct intr_info ulprx_intr_info[] = {
1559 { F_PARERRDATA, "ULP RX data parity error", -1, 1 },
1560 { F_PARERRPCMD, "ULP RX command parity error", -1, 1 },
1561 { F_ARBPF1PERR, "ULP RX ArbPF1 parity error", -1, 1 },
1562 { F_ARBPF0PERR, "ULP RX ArbPF0 parity error", -1, 1 },
1563 { F_ARBFPERR, "ULP RX ArbF parity error", -1, 1 },
1564 { F_PCMDMUXPERR, "ULP RX PCMDMUX parity error", -1, 1 },
1565 { F_DATASELFRAMEERR1, "ULP RX frame error", -1, 1 },
1566 { F_DATASELFRAMEERR0, "ULP RX frame error", -1, 1 },
1567 { 0 }
1568 };
1569
1570 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff,
1571 ulprx_intr_info, NULL))
1572 t3_fatal_err(adapter);
1573}
1574
1575/*
1576 * ULP TX interrupt handler.
1577 */
1578static void ulptx_intr_handler(adapter_t *adapter)
1579{
1580 static struct intr_info ulptx_intr_info[] = {
1581 { F_PBL_BOUND_ERR_CH0, "ULP TX channel 0 PBL out of bounds",
1582 STAT_ULP_CH0_PBL_OOB, 0 },
1583 { F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds",
1584 STAT_ULP_CH1_PBL_OOB, 0 },
1585 { 0xfc, "ULP TX parity error", -1, 1 },
1586 { 0 }
1587 };
1588
1589 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff,
1590 ulptx_intr_info, adapter->irq_stats))
1591 t3_fatal_err(adapter);
1592}
1593
--- 58 unchanged lines hidden (view full) ---
1652}
1653
1654/*
1655 * CPL switch interrupt handler.
1656 */
1657static void cplsw_intr_handler(adapter_t *adapter)
1658{
1659 static struct intr_info cplsw_intr_info[] = {
1660 { F_CIM_OP_MAP_PERR, "CPL switch CIM parity error", -1, 1 },
1661 { F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1 },
1662 { F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1 },
1663 { F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1 },
1664 { F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1 },
1665 { F_ZERO_SWITCH_ERROR, "CPL switch no-switch error", -1, 1 },
1666 { 0 }
1667 };
1668
1669 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff,
--- 117 unchanged lines hidden (view full) ---
1787 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1788
1789 for_each_port(adapter, i) {
1790 struct port_info *p = adap2pinfo(adapter, i);
1791
1792 mask = gpi - (gpi & (gpi - 1));
1793 gpi -= mask;
1794
1795 if (!(p->phy.caps & SUPPORTED_IRQ))
1796 continue;
1797
1798 if (cause & mask) {
1799 int phy_cause = p->phy.ops->intr_handler(&p->phy);
1800
1801 if (phy_cause & cphy_cause_link_change)
1802 t3_link_changed(adapter, i);
1803 if (phy_cause & cphy_cause_fifo_error)
--- 79 unchanged lines hidden (view full) ---
1883 { A_SG_INT_ENABLE, SGE_INTR_MASK },
1884 { A_MC7_INT_ENABLE, MC7_INTR_MASK },
1885 { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR,
1886 MC7_INTR_MASK },
1887 { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR,
1888 MC7_INTR_MASK },
1889 { A_MC5_DB_INT_ENABLE, MC5_INTR_MASK },
1890 { A_ULPRX_INT_ENABLE, ULPRX_INTR_MASK },
1891 { A_PM1_TX_INT_ENABLE, PMTX_INTR_MASK },
1892 { A_PM1_RX_INT_ENABLE, PMRX_INTR_MASK },
1893 { A_CIM_HOST_INT_ENABLE, CIM_INTR_MASK },
1894 { A_MPS_INT_ENABLE, MPS_INTR_MASK },
1895 };
1896
1897 adapter->slow_intr_mask = PL_INTR_MASK;
1898
1899 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
1900 t3_write_reg(adapter, A_TP_INT_ENABLE,
1901 adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff);
1902
1903 if (adapter->params.rev > 0) {
1904 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
1905 CPLSW_INTR_MASK | F_CIM_OVFL_ERROR);
1906 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1907 ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 |
1908 F_PBL_BOUND_ERR_CH1);
1909 } else {
--- 135 unchanged lines hidden (view full) ---
2045 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
2046 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
2047 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2048 V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id));
2049 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2050 0, SG_CONTEXT_CMD_ATTEMPTS, 1);
2051}
2052
2053static int clear_sge_ctxt(adapter_t *adap, unsigned int id, unsigned int type)
2054{
2055 t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0);
2056 t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0);
2057 t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0);
2058 t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0);
2059 return t3_sge_write_context(adap, id, type);
2060}
2061
2062/**
2063 * t3_sge_init_ecntxt - initialize an SGE egress context
2064 * @adapter: the adapter to configure
2065 * @id: the context id
2066 * @gts_enable: whether to enable GTS for the context
2067 * @type: the egress context type
2068 * @respq: associated response queue
2069 * @base_addr: base address of queue
--- 485 unchanged lines hidden (view full) ---
2555 unsigned int mask, unsigned int val)
2556{
2557 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2558 val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
2559 t3_write_reg(adap, A_TP_PIO_DATA, val);
2560}
2561
2562/**
2563 * pm_num_pages - calculate the number of pages of the payload memory
2564 * @mem_size: the size of the payload memory
2565 * @pg_size: the size of each payload memory page
2566 *
2567 * Calculate the number of pages, each of the given size, that fit in a
2568 * memory of the specified size, respecting the HW requirement that the
2569 * number of pages must be a multiple of 24.
2570 */
--- 88 unchanged lines hidden (view full) ---
2659 F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
2660 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2661 F_MTUENABLE | V_WINDOWSCALEMODE(1) |
2662 V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1));
2663 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2664 V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
2665 V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) |
2666 F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1));
2667 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
2668 F_IPV6ENABLE | F_NICMODE);
2669 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2670 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2671 t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
2672 adap->params.rev > 0 ? F_ENABLEESND :
2673 F_T3A_ENABLEESND);
2674 t3_set_reg_field(adap, A_TP_PC_CONFIG,
2675 F_ENABLEEPCMDAFULL,
2676 F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK |
2677 F_TXCONGESTIONMODE | F_RXCONGESTIONMODE);
2678 t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL,
2679 F_ENABLEIPV6RSS | F_ENABLENONOFDTNLSYN |
2680 F_ENABLEARPMISS | F_DISBLEDAPARBIT0);
2681 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2682 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2683
2684 if (adap->params.rev > 0) {
2685 tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
2686 t3_set_reg_field(adap, A_TP_PARA_REG3, 0,
2687 F_TXPACEAUTO | F_TXPACEAUTOSTRICT);
2688 t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2689 tp_wr_indirect(adap, A_TP_VLAN_PRI_MAP, 0xfa50);
2690 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP0, 0xfac688);
2691 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP1, 0xfac688);
2692 } else
2693 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2694
2695 if (adap->params.rev == T3_REV_C)
2696 t3_set_reg_field(adap, A_TP_PC_CONFIG,
2697 V_TABLELATENCYDELTA(M_TABLELATENCYDELTA),
2698 V_TABLELATENCYDELTA(4));
2699
2700 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2701 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2702 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2703 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2704
2705 if (adap->params.nports > 2) {
2706 t3_set_reg_field(adap, A_TP_PC_CONFIG2, 0,
2707 F_ENABLETXPORTFROMDA | F_ENABLERXPORTFROMADDR);
--- 422 unchanged lines hidden (view full) ---
3130 if (kbps > 0) {
3131 kbps *= 125; /* -> bytes */
3132 for (cpt = 1; cpt <= 255; cpt++) {
3133 tps = clk / cpt;
3134 bpt = (kbps + tps / 2) / tps;
3135 if (bpt > 0 && bpt <= 255) {
3136 v = bpt * tps;
3137 delta = v >= kbps ? v - kbps : kbps - v;
3138 if (delta < mindelta) {
3139 mindelta = delta;
3140 selected_cpt = cpt;
3141 selected_bpt = bpt;
3142 }
3143 } else if (selected_cpt)
3144 break;
3145 }
3146 if (!selected_cpt)
--- 394 unchanged lines hidden (view full) ---
3541 else
3542 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
3543 V_ACKLAT(acklat));
3544
3545 t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
3546 V_REPLAYLMT(rpllmt));
3547
3548 t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
3549 t3_set_reg_field(adap, A_PCIE_CFG, 0,
3550 F_PCIE_DMASTOPEN | F_PCIE_CLIDECEN);
3551}
3552
3553/**
3554 * t3_init_hw - initialize and configure T3 HW modules
3555 * @adapter: the adapter
3556 * @fw_params: initial parameters to pass to firmware (optional)
3557 *
3558 * Initialize and configure T3 HW modules. This performs the
3559 * initialization steps that need to be done once after a card is reset.
3560 * MAC and PHY initialization is handled separarely whenever a port is
3561 * enabled.
3562 *
3563 * @fw_params are passed to FW and their value is platform dependent.
3564 * Only the top 8 bits are available for use, the rest must be 0.
3565 */
3566int t3_init_hw(adapter_t *adapter, u32 fw_params)
3567{
3568 int err = -EIO, attempts, i;
3569 const struct vpd_params *vpd = &adapter->params.vpd;
3570
3571 if (adapter->params.rev > 0)
3572 calibrate_xgm_t3b(adapter);
3573 else if (calibrate_xgm(adapter))
3574 goto out_err;
3575
3576 if (adapter->params.nports > 2)
--- 4 unchanged lines hidden (view full) ---
3581
3582 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
3583 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
3584 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
3585 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
3586 adapter->params.mc5.nfilters,
3587 adapter->params.mc5.nroutes))
3588 goto out_err;
3589
3590 for (i = 0; i < 32; i++)
3591 if (clear_sge_ctxt(adapter, i, F_CQ))
3592 goto out_err;
3593 }
3594
3595 if (tp_init(adapter, &adapter->params.tp))
3596 goto out_err;
3597
3598#ifdef CONFIG_CHELSIO_T3_CORE
3599 t3_tp_set_coalescing_size(adapter,
3600 min(adapter->params.sge.max_pkt_size,
3601 MAX_RX_COALESCING_LEN), 1);
3602 t3_tp_set_max_rxsize(adapter,
3603 min(adapter->params.sge.max_pkt_size, 16384U));
3604 ulp_config(adapter, &adapter->params.tp);
3605#endif
3606 if (is_pcie(adapter))
3607 config_pcie(adapter);
3608 else
3609 t3_set_reg_field(adapter, A_PCIX_CFG, 0,
3610 F_DMASTOPEN | F_CLIDECEN);
3611
3612 if (adapter->params.rev == T3_REV_C)
3613 t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0,
3614 F_CFG_CQE_SOP_MASK);
3615
3616 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3617 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
3618 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
3619 chan_init_hw(adapter, adapter->params.chan_map);
3620 t3_sge_init(adapter, &adapter->params.sge);
3621
3622 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3623 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3624 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
3625 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3626
3627 attempts = 100;
3628 do { /* wait for uP to initialize */
3629 msleep(20);
3630 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3631 if (!attempts) {
3632 CH_ERR(adapter, "uP initialization timed out\n");
3633 goto out_err;
3634 }
3635
--- 134 unchanged lines hidden (view full) ---
3770 3 : 2);
3771
3772 mi1_init(adapter, ai);
3773 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
3774 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1));
3775 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
3776 ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL);
3777 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
3778 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff));
3779
3780 if (adapter->params.rev == 0 || !uses_xaui(adapter))
3781 val |= F_ENRGMII;
3782
3783 /* Enable MAC clocks so we can access the registers */
3784 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3785 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
3786
--- 34 unchanged lines hidden (view full) ---
3821 if (devid != 0x1425)
3822 return -1;
3823
3824 if (save_and_restore_pcie)
3825 t3_os_pci_restore_state(adapter);
3826 return 0;
3827}
3828
3829static int __devinit init_parity(adapter_t *adap)
3830{
3831 int i, err, addr;
3832
3833 if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
3834 return -EBUSY;
3835
3836 for (err = i = 0; !err && i < 16; i++)
3837 err = clear_sge_ctxt(adap, i, F_EGRESS);
3838 for (i = 0xfff0; !err && i <= 0xffff; i++)
3839 err = clear_sge_ctxt(adap, i, F_EGRESS);
3840 for (i = 0; !err && i < SGE_QSETS; i++)
3841 err = clear_sge_ctxt(adap, i, F_RESPONSEQ);
3842 if (err)
3843 return err;
3844
3845 t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0);
3846 for (i = 0; i < 4; i++)
3847 for (addr = 0; addr <= M_IBQDBGADDR; addr++) {
3848 t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN |
3849 F_IBQDBGWR | V_IBQDBGQID(i) |
3850 V_IBQDBGADDR(addr));
3851 err = t3_wait_op_done(adap, A_CIM_IBQ_DBG_CFG,
3852 F_IBQDBGBUSY, 0, 2, 1);
3853 if (err)
3854 return err;
3855 }
3856 return 0;
3857}
3858
3859/**
3860 * t3_prep_adapter - prepare SW and HW for operation
3861 * @adapter: the adapter
3862 * @ai: contains information about the adapter type and properties
3863 *
3864 * Initialize adapter SW state for the various HW modules, set initial
3865 * values for some adapter tunables, take PHYs out of reset, and
3866 * initialize the MDIO interface.
--- 65 unchanged lines hidden (view full) ---
3932
3933#ifdef CONFIG_CHELSIO_T3_CORE
3934 init_mtus(adapter->params.mtus);
3935 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3936#endif
3937 }
3938
3939 early_hw_init(adapter, ai);
3940 ret = init_parity(adapter);
3941 if (ret)
3942 return ret;
3943
3944 if (adapter->params.nports > 2 &&
3945 (ret = t3_vsc7323_init(adapter, adapter->params.nports)))
3946 return ret;
3947
3948 for_each_port(adapter, i) {
3949 u8 hw_addr[6];
3950 const struct port_type_info *pti;
3951 struct port_info *p = adap2pinfo(adapter, i);
3952
3953 while (!adapter->params.vpd.port_type[j])
3954 ++j;
3955
3956 pti = &port_types[adapter->params.vpd.port_type[j]];
3957 ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
3958 ai->mdio_ops);
3959 if (ret)
3960 return ret;
3961 mac_prep(&p->mac, adapter, j);
3962 ++j;
3963
3964 /*
3965 * The VPD EEPROM stores the base Ethernet address for the
3966 * card. A port's address is derived from the base by adding
3967 * the port's index to the base's low octet.
3968 */
3969 memcpy(hw_addr, adapter->params.vpd.eth_base, 5);
3970 hw_addr[5] = adapter->params.vpd.eth_base[5] + i;
3971
3972 t3_os_set_hw_addr(adapter, i, hw_addr);
3973 init_link_config(&p->link_config, p->phy.caps);
3974 p->phy.ops->power_down(&p->phy, 1);
3975 if (!(p->phy.caps & SUPPORTED_IRQ))
3976 adapter->params.linkpoll_period = 10;
3977 }
3978
3979 return 0;
3980}
3981
3982void t3_led_ready(adapter_t *adapter)
3983{
--- 24 unchanged lines hidden ---