1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
--- 14 unchanged lines hidden (view full) ---
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28***************************************************************************/
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_hw.c 171471 2007-07-17 06:50:35Z kmacy $");
32
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39
40#undef msleep
41#define msleep t3_os_sleep
42
43
44/**
45 * t3_wait_op_done_val - wait until an operation is completed
46 * @adapter: the adapter performing the operation
47 * @reg: the register to check for completion
48 * @mask: a single-bit field within @reg that indicates completion
49 * @polarity: the value of the field when the operation is completed
--- 300 unchanged lines hidden (view full) ---
350 return err;
351
352 do {
353 err = mdio_read(phy, mmd, MII_BMCR, &ctl);
354 if (err)
355 return err;
356 ctl &= BMCR_RESET;
357 if (ctl)
358 msleep(1);
359 } while (ctl && --wait);
360
361 return ctl ? -1 : 0;
362}
363
364/**
365 * t3_phy_advertise - set the PHY advertisement registers for autoneg
366 * @phy: the PHY to operate on
--- 110 unchanged lines hidden (view full) ---
477 return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
478}
479
480#define CAPS_1G (SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full | \
481 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII)
482#define CAPS_10G (SUPPORTED_10000baseT_Full | SUPPORTED_AUI)
483
484static struct port_type_info port_types[] = {
485 { NULL },
486 { t3_ael1002_phy_prep, CAPS_10G | SUPPORTED_FIBRE,
487 "10GBASE-XR" },
488 { t3_vsc8211_phy_prep, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
489 "10/100/1000BASE-T" },
490 { t3_mv88e1xxx_phy_prep, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
491 "10/100/1000BASE-T" },
492 { t3_xaui_direct_phy_prep, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4" },
493 { NULL, CAPS_10G, "10GBASE-KX4" },
--- 95 unchanged lines hidden (view full) ---
589 if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
590 return -EINVAL;
591
592 t3_os_pci_write_config_4(adapter, base + PCI_VPD_DATA,
593 cpu_to_le32(data));
594 t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR,
595 (u16)addr | PCI_VPD_ADDR_F);
596 do {
597 msleep(1);
598 t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val);
599 } while ((val & PCI_VPD_ADDR_F) && --attempts);
600
601 if (val & PCI_VPD_ADDR_F) {
602 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr);
603 return -EIO;
604 }
605 return 0;
--- 159 unchanged lines hidden (view full) ---
765 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 ||
766 (ret = sf1_read(adapter, 1, 0, &status)) != 0)
767 return ret;
768 if (!(status & 1))
769 return 0;
770 if (--attempts == 0)
771 return -EAGAIN;
772 if (delay)
773 msleep(delay);
774 }
775}
776
777/**
778 * t3_read_flash - read words from serial flash
779 * @adapter: the adapter
780 * @addr: the start address for the read
781 * @nwords: how many 32-bit words to read
--- 73 unchanged lines hidden (view full) ---
855 return ret;
856
857 if (memcmp(data - n, (u8 *)buf + offset, n))
858 return -EIO;
859 return 0;
860}
861
862/**
863 * t3_get_tp_version - read the tp sram version
864 * @adapter: the adapter
865 * @vers: where to place the version
866 *
867 * Reads the protocol sram version from sram.
868 */
869int t3_get_tp_version(adapter_t *adapter, u32 *vers)
870{
871 int ret;
872
873 /* Get version loaded in SRAM */
874 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
875 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
876 1, 1, 5, 1);
877 if (ret)
878 return ret;
879
880 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
881
882 return 0;
883}
884
885/**
886 * t3_check_tpsram_version - read the tp sram version
887 * @adapter: the adapter
888 *
889 */
890int t3_check_tpsram_version(adapter_t *adapter)
891{
892 int ret;
893 u32 vers;
894 unsigned int major, minor;
895
896 /* Get version loaded in SRAM */
--- 6 unchanged lines hidden (view full) ---
903 vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
904
905 major = G_TP_VERSION_MAJOR(vers);
906 minor = G_TP_VERSION_MINOR(vers);
907
908 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
909 return 0;
910
911 CH_ERR(adapter, "found wrong TP version (%u.%u), "
912 "driver needs version %d.%d\n", major, minor,
913 TP_VERSION_MAJOR, TP_VERSION_MINOR);
914 return -EINVAL;
915}
916
917/**
918 * t3_check_tpsram - check if provided protocol SRAM
919 * is compatible with this driver
920 * @adapter: the adapter
921 * @tp_sram: the firmware image to write
922 * @size: image size
923 *
924 * Checks if an adapter's tp sram is compatible with the driver.
925 * Returns 0 if the versions are compatible, a negative error otherwise.
926 */
927int t3_check_tpsram(adapter_t *adapter, const u8 *tp_sram, unsigned int size)
928{
929 u32 csum;
930 unsigned int i;
931 const u32 *p = (const u32 *)tp_sram;
932
933 /* Verify checksum */
934 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
935 csum += ntohl(p[i]);
--- 44 unchanged lines hidden (view full) ---
980 major = G_FW_VERSION_MAJOR(vers);
981 minor = G_FW_VERSION_MINOR(vers);
982
983 if (type == FW_VERSION_T3 && major == FW_VERSION_MAJOR &&
984 minor == FW_VERSION_MINOR)
985 return 0;
986
987 CH_ERR(adapter, "found wrong FW version (%u.%u), "
988 "driver needs version %d.%d\n", major, minor,
989 FW_VERSION_MAJOR, FW_VERSION_MINOR);
990 return -EINVAL;
991}
992
993/**
994 * t3_flash_erase_sectors - erase a range of flash sectors
995 * @adapter: the adapter
996 * @start: the first sector to erase
997 * @end: the last sector to erase
--- 1351 unchanged lines hidden (view full) ---
2349 */
2350void t3_tp_set_offload_mode(adapter_t *adap, int enable)
2351{
2352 if (is_offload(adap) || !enable)
2353 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
2354 V_NICMODE(!enable));
2355}
2356
2357static void tp_wr_bits_indirect(adapter_t *adap, unsigned int addr,
2358 unsigned int mask, unsigned int val)
2359{
2360 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2361 val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
2362 t3_write_reg(adap, A_TP_PIO_DATA, val);
2363}
2364
2365/**
2366 * t3_enable_filters - enable the HW filters
2367 * @adap: the adapter
2368 *
2369 * Enables the HW filters for NIC traffic.
2370 */
2371void t3_enable_filters(adapter_t *adap)
2372{
2373 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, 0);
2374 t3_set_reg_field(adap, A_MC5_DB_CONFIG, 0, F_FILTEREN);
2375 t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, 0, V_FIVETUPLELOOKUP(3));
2376 tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, 0, F_LOOKUPEVERYPKT);
2377}
2378
2379/**
2380 * pm_num_pages - calculate the number of pages of the payload memory
2381 * @mem_size: the size of the payload memory
2382 * @pg_size: the size of each payload memory page
2383 *
2384 * Calculate the number of pages, each of the given size, that fit in a
2385 * memory of the specified size, respecting the HW requirement that the
2386 * number of pages must be a multiple of 24.
2387 */
--- 76 unchanged lines hidden (view full) ---
2464}
2465
2466static inline void tp_wr_indirect(adapter_t *adap, unsigned int addr, u32 val)
2467{
2468 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2469 t3_write_reg(adap, A_TP_PIO_DATA, val);
2470}
2471
2472static void tp_config(adapter_t *adap, const struct tp_params *p)
2473{
2474 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2475 F_IPCHECKSUMOFFLOAD | F_UDPCHECKSUMOFFLOAD |
2476 F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
2477 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2478 F_MTUENABLE | V_WINDOWSCALEMODE(1) |
2479 V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1));
--- 13 unchanged lines hidden (view full) ---
2493 F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK |
2494 F_TXCONGESTIONMODE | F_RXCONGESTIONMODE);
2495 t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0);
2496 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2497 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2498
2499 if (adap->params.rev > 0) {
2500 tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
2501 t3_set_reg_field(adap, A_TP_PARA_REG3, 0,
2502 F_TXPACEAUTO | F_TXPACEAUTOSTRICT);
2503 t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2504 tp_wr_indirect(adap, A_TP_VLAN_PRI_MAP, 0xfa50);
2505 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP0, 0xfac688);
2506 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP1, 0xfac688);
2507 } else
2508 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2509
2510 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2511 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2512 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2513 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2514
--- 337 unchanged lines hidden (view full) ---
2852
2853/**
2854 * t3_set_proto_sram - set the contents of the protocol sram
2855 * @adapter: the adapter
2856 * @data: the protocol image
2857 *
2858 * Write the contents of the protocol SRAM.
2859 */
2860int t3_set_proto_sram(adapter_t *adap, const u8 *data)
2861{
2862 int i;
2863 u32 *buf = (u32 *)(uintptr_t)data;
2864
2865 for (i = 0; i < PROTO_SRAM_LINES; i++) {
2866 t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++));
2867 t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++));
2868 t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++));
2869 t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++));
2870 t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++));
2871
2872 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
2873 if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))
2874 return -EIO;
2875 }
2876 return 0;
2877}
2878#endif
--- 210 unchanged lines hidden (view full) ---
3089static int calibrate_xgm(adapter_t *adapter)
3090{
3091 if (uses_xaui(adapter)) {
3092 unsigned int v, i;
3093
3094 for (i = 0; i < 5; ++i) {
3095 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
3096 (void) t3_read_reg(adapter, A_XGM_XAUI_IMP);
3097 msleep(1);
3098 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
3099 if (!(v & (F_XGM_CALFAULT | F_CALBUSY))) {
3100 t3_write_reg(adapter, A_XGM_XAUI_IMP,
3101 V_XAUIIMP(G_CALIMP(v) >> 2));
3102 return 0;
3103 }
3104 }
3105 CH_ERR(adapter, "MAC calibration failed\n");
--- 70 unchanged lines hidden (view full) ---
3176
3177 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3178 slow = val & F_SLOW;
3179 width = G_WIDTH(val);
3180 density = G_DEN(val);
3181
3182 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3183 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3184 msleep(1);
3185
3186 if (!slow) {
3187 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3188 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3189 msleep(1);
3190 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3191 (F_BUSY | F_SGL_CAL_EN | F_CAL_FAULT)) {
3192 CH_ERR(adapter, "%s MC7 calibration timed out\n",
3193 mc7->name);
3194 goto out_fail;
3195 }
3196 }
3197
--- 49 unchanged lines hidden (view full) ---
3247 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
3248 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
3249 (mc7->size << width) - 1);
3250 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
3251 (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
3252
3253 attempts = 50;
3254 do {
3255 msleep(250);
3256 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
3257 } while ((val & F_BUSY) && --attempts);
3258 if (val & F_BUSY) {
3259 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
3260 goto out_fail;
3261 }
3262
3263 /* Enable normal memory accesses. */
--- 69 unchanged lines hidden (view full) ---
3333 int err = -EIO, attempts = 100;
3334 const struct vpd_params *vpd = &adapter->params.vpd;
3335
3336 if (adapter->params.rev > 0)
3337 calibrate_xgm_t3b(adapter);
3338 else if (calibrate_xgm(adapter))
3339 goto out_err;
3340
3341 if (adapter->params.nports > 2)
3342 t3_mac_reset(&adap2pinfo(adapter, 0)->mac);
3343
3344 if (vpd->mclk) {
3345 partition_mem(adapter, &adapter->params.tp);
3346
3347 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
3348 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
3349 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
3350 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
--- 23 unchanged lines hidden (view full) ---
3374 t3_sge_init(adapter, &adapter->params.sge);
3375
3376 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3377 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3378 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
3379 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3380
3381 do { /* wait for uP to initialize */
3382 msleep(20);
3383 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3384 if (!attempts) {
3385 CH_ERR(adapter, "uP initialization timed out\n");
3386 goto out_err;
3387 }
3388
3389 err = 0;
3390 out_err:
--- 95 unchanged lines hidden (view full) ---
3486 mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg);
3487 mc7->width = G_WIDTH(cfg);
3488}
3489
3490void mac_prep(struct cmac *mac, adapter_t *adapter, int index)
3491{
3492 mac->adapter = adapter;
3493 mac->multiport = adapter->params.nports > 2;
3494 if (mac->multiport) {
3495 mac->ext_port = (unsigned char)index;
3496 mac->nucast = 8;
3497 index = 0;
3498 } else
3499 mac->nucast = 1;
3500
3501 mac->offset = (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR) * index;
--- 46 unchanged lines hidden (view full) ---
3548 t3_os_pci_save_state(adapter);
3549 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
3550
3551 /*
3552 * Delay. Give Some time to device to reset fully.
3553 * XXX The delay time should be modified.
3554 */
3555 for (i = 0; i < 10; i++) {
3556 msleep(50);
3557 t3_os_pci_read_config_2(adapter, 0x00, &devid);
3558 if (devid == 0x1425)
3559 break;
3560 }
3561
3562 if (devid != 0x1425)
3563 return -1;
3564
--- 15 unchanged lines hidden (view full) ---
3580
3581 get_pci_mode(adapter, &adapter->params.pci);
3582
3583 adapter->params.info = ai;
3584 adapter->params.nports = ai->nports0 + ai->nports1;
3585 adapter->params.chan_map = !!ai->nports0 | (!!ai->nports1 << 1);
3586 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
3587 adapter->params.linkpoll_period = 0;
3588 if (adapter->params.nports > 2)
3589 adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS;
3590 else
3591 adapter->params.stats_update_period = is_10G(adapter) ?
3592 MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10);
3593 adapter->params.pci.vpd_cap_addr =
3594 t3_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
3595
3596 ret = get_vpd_params(adapter, &adapter->params.vpd);
3597 if (ret < 0)
3598 return ret;
3599
3600 if (reset && t3_reset_adapter(adapter))
3601 return -1;
3602
3603 t3_sge_prep(adapter, &adapter->params.sge);
3604
3605 if (adapter->params.vpd.mclk) {
3606 struct tp_params *p = &adapter->params.tp;
3607
--- 32 unchanged lines hidden (view full) ---
3640#ifdef CONFIG_CHELSIO_T3_CORE
3641 init_mtus(adapter->params.mtus);
3642 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3643#endif
3644 }
3645
3646 early_hw_init(adapter, ai);
3647
3648 if (adapter->params.nports > 2 &&
3649 (ret = t3_vsc7323_init(adapter, adapter->params.nports)))
3650 return ret;
3651
3652 for_each_port(adapter, i) {
3653 u8 hw_addr[6];
3654 struct port_info *p = adap2pinfo(adapter, i);
3655
3656 while (!adapter->params.vpd.port_type[j])
3657 ++j;
3658
3659 p->port_type = &port_types[adapter->params.vpd.port_type[j]];
3660 p->port_type->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
3661 ai->mdio_ops);
3662 mac_prep(&p->mac, adapter, j);
3663 ++j;
3664
3665 /*
3666 * The VPD EEPROM stores the base Ethernet address for the
3667 * card. A port's address is derived from the base by adding
--- 41 unchanged lines hidden ---
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
--- 14 unchanged lines hidden (view full) ---
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28***************************************************************************/
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_hw.c 171471 2007-07-17 06:50:35Z kmacy $");
32
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39
40#undef msleep
41#define msleep t3_os_sleep
42
43
44/**
45 * t3_wait_op_done_val - wait until an operation is completed
46 * @adapter: the adapter performing the operation
47 * @reg: the register to check for completion
48 * @mask: a single-bit field within @reg that indicates completion
49 * @polarity: the value of the field when the operation is completed
--- 300 unchanged lines hidden (view full) ---
350 return err;
351
352 do {
353 err = mdio_read(phy, mmd, MII_BMCR, &ctl);
354 if (err)
355 return err;
356 ctl &= BMCR_RESET;
357 if (ctl)
358 msleep(1);
359 } while (ctl && --wait);
360
361 return ctl ? -1 : 0;
362}
363
364/**
365 * t3_phy_advertise - set the PHY advertisement registers for autoneg
366 * @phy: the PHY to operate on
--- 110 unchanged lines hidden (view full) ---
477 return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
478}
479
480#define CAPS_1G (SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full | \
481 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII)
482#define CAPS_10G (SUPPORTED_10000baseT_Full | SUPPORTED_AUI)
483
484static struct port_type_info port_types[] = {
485 { NULL },
486 { t3_ael1002_phy_prep, CAPS_10G | SUPPORTED_FIBRE,
487 "10GBASE-XR" },
488 { t3_vsc8211_phy_prep, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
489 "10/100/1000BASE-T" },
490 { t3_mv88e1xxx_phy_prep, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
491 "10/100/1000BASE-T" },
492 { t3_xaui_direct_phy_prep, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4" },
493 { NULL, CAPS_10G, "10GBASE-KX4" },
--- 95 unchanged lines hidden (view full) ---
589 if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
590 return -EINVAL;
591
592 t3_os_pci_write_config_4(adapter, base + PCI_VPD_DATA,
593 cpu_to_le32(data));
594 t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR,
595 (u16)addr | PCI_VPD_ADDR_F);
596 do {
597 msleep(1);
598 t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val);
599 } while ((val & PCI_VPD_ADDR_F) && --attempts);
600
601 if (val & PCI_VPD_ADDR_F) {
602 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr);
603 return -EIO;
604 }
605 return 0;
--- 159 unchanged lines hidden (view full) ---
765 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 ||
766 (ret = sf1_read(adapter, 1, 0, &status)) != 0)
767 return ret;
768 if (!(status & 1))
769 return 0;
770 if (--attempts == 0)
771 return -EAGAIN;
772 if (delay)
773 msleep(delay);
774 }
775}
776
777/**
778 * t3_read_flash - read words from serial flash
779 * @adapter: the adapter
780 * @addr: the start address for the read
781 * @nwords: how many 32-bit words to read
--- 73 unchanged lines hidden (view full) ---
855 return ret;
856
857 if (memcmp(data - n, (u8 *)buf + offset, n))
858 return -EIO;
859 return 0;
860}
861
862/**
863 * t3_get_tp_version - read the tp sram version
864 * @adapter: the adapter
865 * @vers: where to place the version
866 *
867 * Reads the protocol sram version from sram.
868 */
869int t3_get_tp_version(adapter_t *adapter, u32 *vers)
870{
871 int ret;
872
873 /* Get version loaded in SRAM */
874 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
875 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
876 1, 1, 5, 1);
877 if (ret)
878 return ret;
879
880 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
881
882 return 0;
883}
884
885/**
886 * t3_check_tpsram_version - read the tp sram version
887 * @adapter: the adapter
888 *
889 */
890int t3_check_tpsram_version(adapter_t *adapter)
891{
892 int ret;
893 u32 vers;
894 unsigned int major, minor;
895
896 /* Get version loaded in SRAM */
--- 6 unchanged lines hidden (view full) ---
903 vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
904
905 major = G_TP_VERSION_MAJOR(vers);
906 minor = G_TP_VERSION_MINOR(vers);
907
908 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
909 return 0;
910
911 CH_ERR(adapter, "found wrong TP version (%u.%u), "
912 "driver needs version %d.%d\n", major, minor,
913 TP_VERSION_MAJOR, TP_VERSION_MINOR);
914 return -EINVAL;
915}
916
917/**
918 * t3_check_tpsram - check if provided protocol SRAM
919 * is compatible with this driver
920 * @adapter: the adapter
921 * @tp_sram: the firmware image to write
922 * @size: image size
923 *
924 * Checks if an adapter's tp sram is compatible with the driver.
925 * Returns 0 if the versions are compatible, a negative error otherwise.
926 */
927int t3_check_tpsram(adapter_t *adapter, const u8 *tp_sram, unsigned int size)
928{
929 u32 csum;
930 unsigned int i;
931 const u32 *p = (const u32 *)tp_sram;
932
933 /* Verify checksum */
934 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
935 csum += ntohl(p[i]);
--- 44 unchanged lines hidden (view full) ---
980 major = G_FW_VERSION_MAJOR(vers);
981 minor = G_FW_VERSION_MINOR(vers);
982
983 if (type == FW_VERSION_T3 && major == FW_VERSION_MAJOR &&
984 minor == FW_VERSION_MINOR)
985 return 0;
986
987 CH_ERR(adapter, "found wrong FW version (%u.%u), "
988 "driver needs version %d.%d\n", major, minor,
989 FW_VERSION_MAJOR, FW_VERSION_MINOR);
990 return -EINVAL;
991}
992
993/**
994 * t3_flash_erase_sectors - erase a range of flash sectors
995 * @adapter: the adapter
996 * @start: the first sector to erase
997 * @end: the last sector to erase
--- 1351 unchanged lines hidden (view full) ---
2349 */
2350void t3_tp_set_offload_mode(adapter_t *adap, int enable)
2351{
2352 if (is_offload(adap) || !enable)
2353 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
2354 V_NICMODE(!enable));
2355}
2356
2357static void tp_wr_bits_indirect(adapter_t *adap, unsigned int addr,
2358 unsigned int mask, unsigned int val)
2359{
2360 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2361 val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
2362 t3_write_reg(adap, A_TP_PIO_DATA, val);
2363}
2364
2365/**
2366 * t3_enable_filters - enable the HW filters
2367 * @adap: the adapter
2368 *
2369 * Enables the HW filters for NIC traffic.
2370 */
2371void t3_enable_filters(adapter_t *adap)
2372{
2373 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, 0);
2374 t3_set_reg_field(adap, A_MC5_DB_CONFIG, 0, F_FILTEREN);
2375 t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, 0, V_FIVETUPLELOOKUP(3));
2376 tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, 0, F_LOOKUPEVERYPKT);
2377}
2378
2379/**
2380 * pm_num_pages - calculate the number of pages of the payload memory
2381 * @mem_size: the size of the payload memory
2382 * @pg_size: the size of each payload memory page
2383 *
2384 * Calculate the number of pages, each of the given size, that fit in a
2385 * memory of the specified size, respecting the HW requirement that the
2386 * number of pages must be a multiple of 24.
2387 */
--- 76 unchanged lines hidden (view full) ---
2464}
2465
2466static inline void tp_wr_indirect(adapter_t *adap, unsigned int addr, u32 val)
2467{
2468 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2469 t3_write_reg(adap, A_TP_PIO_DATA, val);
2470}
2471
2472static void tp_config(adapter_t *adap, const struct tp_params *p)
2473{
2474 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2475 F_IPCHECKSUMOFFLOAD | F_UDPCHECKSUMOFFLOAD |
2476 F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
2477 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2478 F_MTUENABLE | V_WINDOWSCALEMODE(1) |
2479 V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1));
--- 13 unchanged lines hidden (view full) ---
2493 F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK |
2494 F_TXCONGESTIONMODE | F_RXCONGESTIONMODE);
2495 t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0);
2496 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2497 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2498
2499 if (adap->params.rev > 0) {
2500 tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
2501 t3_set_reg_field(adap, A_TP_PARA_REG3, 0,
2502 F_TXPACEAUTO | F_TXPACEAUTOSTRICT);
2503 t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2504 tp_wr_indirect(adap, A_TP_VLAN_PRI_MAP, 0xfa50);
2505 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP0, 0xfac688);
2506 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP1, 0xfac688);
2507 } else
2508 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2509
2510 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2511 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2512 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2513 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2514
--- 337 unchanged lines hidden (view full) ---
2852
2853/**
2854 * t3_set_proto_sram - set the contents of the protocol sram
2855 * @adapter: the adapter
2856 * @data: the protocol image
2857 *
2858 * Write the contents of the protocol SRAM.
2859 */
2860int t3_set_proto_sram(adapter_t *adap, const u8 *data)
2861{
2862 int i;
2863 u32 *buf = (u32 *)(uintptr_t)data;
2864
2865 for (i = 0; i < PROTO_SRAM_LINES; i++) {
2866 t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++));
2867 t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++));
2868 t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++));
2869 t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++));
2870 t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++));
2871
2872 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
2873 if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))
2874 return -EIO;
2875 }
2876 return 0;
2877}
2878#endif
--- 210 unchanged lines hidden (view full) ---
3089static int calibrate_xgm(adapter_t *adapter)
3090{
3091 if (uses_xaui(adapter)) {
3092 unsigned int v, i;
3093
3094 for (i = 0; i < 5; ++i) {
3095 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
3096 (void) t3_read_reg(adapter, A_XGM_XAUI_IMP);
3097 msleep(1);
3098 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
3099 if (!(v & (F_XGM_CALFAULT | F_CALBUSY))) {
3100 t3_write_reg(adapter, A_XGM_XAUI_IMP,
3101 V_XAUIIMP(G_CALIMP(v) >> 2));
3102 return 0;
3103 }
3104 }
3105 CH_ERR(adapter, "MAC calibration failed\n");
--- 70 unchanged lines hidden (view full) ---
3176
3177 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3178 slow = val & F_SLOW;
3179 width = G_WIDTH(val);
3180 density = G_DEN(val);
3181
3182 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3183 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3184 msleep(1);
3185
3186 if (!slow) {
3187 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3188 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3189 msleep(1);
3190 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3191 (F_BUSY | F_SGL_CAL_EN | F_CAL_FAULT)) {
3192 CH_ERR(adapter, "%s MC7 calibration timed out\n",
3193 mc7->name);
3194 goto out_fail;
3195 }
3196 }
3197
--- 49 unchanged lines hidden (view full) ---
3247 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
3248 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
3249 (mc7->size << width) - 1);
3250 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
3251 (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
3252
3253 attempts = 50;
3254 do {
3255 msleep(250);
3256 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
3257 } while ((val & F_BUSY) && --attempts);
3258 if (val & F_BUSY) {
3259 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
3260 goto out_fail;
3261 }
3262
3263 /* Enable normal memory accesses. */
--- 69 unchanged lines hidden (view full) ---
3333 int err = -EIO, attempts = 100;
3334 const struct vpd_params *vpd = &adapter->params.vpd;
3335
3336 if (adapter->params.rev > 0)
3337 calibrate_xgm_t3b(adapter);
3338 else if (calibrate_xgm(adapter))
3339 goto out_err;
3340
3341 if (adapter->params.nports > 2)
3342 t3_mac_reset(&adap2pinfo(adapter, 0)->mac);
3343
3344 if (vpd->mclk) {
3345 partition_mem(adapter, &adapter->params.tp);
3346
3347 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
3348 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
3349 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
3350 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
--- 23 unchanged lines hidden (view full) ---
3374 t3_sge_init(adapter, &adapter->params.sge);
3375
3376 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3377 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3378 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
3379 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3380
3381 do { /* wait for uP to initialize */
3382 msleep(20);
3383 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3384 if (!attempts) {
3385 CH_ERR(adapter, "uP initialization timed out\n");
3386 goto out_err;
3387 }
3388
3389 err = 0;
3390 out_err:
--- 95 unchanged lines hidden (view full) ---
3486 mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg);
3487 mc7->width = G_WIDTH(cfg);
3488}
3489
3490void mac_prep(struct cmac *mac, adapter_t *adapter, int index)
3491{
3492 mac->adapter = adapter;
3493 mac->multiport = adapter->params.nports > 2;
3494 if (mac->multiport) {
3495 mac->ext_port = (unsigned char)index;
3496 mac->nucast = 8;
3497 index = 0;
3498 } else
3499 mac->nucast = 1;
3500
3501 mac->offset = (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR) * index;
--- 46 unchanged lines hidden (view full) ---
3548 t3_os_pci_save_state(adapter);
3549 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
3550
3551 /*
3552 * Delay. Give Some time to device to reset fully.
3553 * XXX The delay time should be modified.
3554 */
3555 for (i = 0; i < 10; i++) {
3556 msleep(50);
3557 t3_os_pci_read_config_2(adapter, 0x00, &devid);
3558 if (devid == 0x1425)
3559 break;
3560 }
3561
3562 if (devid != 0x1425)
3563 return -1;
3564
--- 15 unchanged lines hidden (view full) ---
3580
3581 get_pci_mode(adapter, &adapter->params.pci);
3582
3583 adapter->params.info = ai;
3584 adapter->params.nports = ai->nports0 + ai->nports1;
3585 adapter->params.chan_map = !!ai->nports0 | (!!ai->nports1 << 1);
3586 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
3587 adapter->params.linkpoll_period = 0;
3588 if (adapter->params.nports > 2)
3589 adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS;
3590 else
3591 adapter->params.stats_update_period = is_10G(adapter) ?
3592 MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10);
3593 adapter->params.pci.vpd_cap_addr =
3594 t3_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
3595
3596 ret = get_vpd_params(adapter, &adapter->params.vpd);
3597 if (ret < 0)
3598 return ret;
3599
3600 if (reset && t3_reset_adapter(adapter))
3601 return -1;
3602
3603 t3_sge_prep(adapter, &adapter->params.sge);
3604
3605 if (adapter->params.vpd.mclk) {
3606 struct tp_params *p = &adapter->params.tp;
3607
--- 32 unchanged lines hidden (view full) ---
3640#ifdef CONFIG_CHELSIO_T3_CORE
3641 init_mtus(adapter->params.mtus);
3642 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3643#endif
3644 }
3645
3646 early_hw_init(adapter, ai);
3647
3648 if (adapter->params.nports > 2 &&
3649 (ret = t3_vsc7323_init(adapter, adapter->params.nports)))
3650 return ret;
3651
3652 for_each_port(adapter, i) {
3653 u8 hw_addr[6];
3654 struct port_info *p = adap2pinfo(adapter, i);
3655
3656 while (!adapter->params.vpd.port_type[j])
3657 ++j;
3658
3659 p->port_type = &port_types[adapter->params.vpd.port_type[j]];
3660 p->port_type->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
3661 ai->mdio_ops);
3662 mac_prep(&p->mac, adapter, j);
3663 ++j;
3664
3665 /*
3666 * The VPD EEPROM stores the base Ethernet address for the
3667 * card. A port's address is derived from the base by adding
--- 41 unchanged lines hidden ---