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cxgb_t3_cpl.h (176472) cxgb_t3_cpl.h (180583)
1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_cpl.h 176472 2008-02-23 01:06:17Z kmacy $
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_cpl.h 180583 2008-07-18 06:12:31Z kmacy $
29
30***************************************************************************/
31#ifndef T3_CPL_H
32#define T3_CPL_H
33
34enum CPL_opcode {
35 CPL_PASS_OPEN_REQ = 0x1,
36 CPL_PASS_ACCEPT_RPL = 0x2,

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98
99 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
100
101 CPL_TX_DMA_ACK = 0xA0,
102 CPL_RDMA_READ_REQ = 0xA1,
103 CPL_RDMA_TERMINATE = 0xA2,
104 CPL_TRACE_PKT = 0xA3,
105 CPL_RDMA_EC_STATUS = 0xA5,
29
30***************************************************************************/
31#ifndef T3_CPL_H
32#define T3_CPL_H
33
34enum CPL_opcode {
35 CPL_PASS_OPEN_REQ = 0x1,
36 CPL_PASS_ACCEPT_RPL = 0x2,

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98
99 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
100
101 CPL_TX_DMA_ACK = 0xA0,
102 CPL_RDMA_READ_REQ = 0xA1,
103 CPL_RDMA_TERMINATE = 0xA2,
104 CPL_TRACE_PKT = 0xA3,
105 CPL_RDMA_EC_STATUS = 0xA5,
106 CPL_SGE_EC_CR_RETURN = 0xA6,
106
107 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
108};
109
110enum CPL_error {
111 CPL_ERR_NONE = 0,
112 CPL_ERR_TCAM_PARITY = 1,
113 CPL_ERR_TCAM_FULL = 3,

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143
144enum {
145 ULP_CRC_HEADER = 1 << 0,
146 ULP_CRC_DATA = 1 << 1
147};
148
149enum {
150 CPL_PASS_OPEN_ACCEPT,
107
108 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
109};
110
111enum CPL_error {
112 CPL_ERR_NONE = 0,
113 CPL_ERR_TCAM_PARITY = 1,
114 CPL_ERR_TCAM_FULL = 3,

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144
145enum {
146 ULP_CRC_HEADER = 1 << 0,
147 ULP_CRC_DATA = 1 << 1
148};
149
150enum {
151 CPL_PASS_OPEN_ACCEPT,
151 CPL_PASS_OPEN_REJECT
152 CPL_PASS_OPEN_REJECT,
153 CPL_PASS_OPEN_ACCEPT_TNL
152};
153
154enum {
155 CPL_ABORT_SEND_RST = 0,
156 CPL_ABORT_NO_RST,
157 CPL_ABORT_POST_CLOSE_REQ = 2
158};
159

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902 RSS_HDR
903 union opcode_tid ot;
904 __be16 credits;
905 __be16 rsvd;
906 __be32 snd_nxt;
907 __be32 snd_una;
908};
909
154};
155
156enum {
157 CPL_ABORT_SEND_RST = 0,
158 CPL_ABORT_NO_RST,
159 CPL_ABORT_POST_CLOSE_REQ = 2
160};
161

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904 RSS_HDR
905 union opcode_tid ot;
906 __be16 credits;
907 __be16 rsvd;
908 __be32 snd_nxt;
909 __be32 snd_una;
910};
911
912struct cpl_sge_ec_cr_return {
913 RSS_HDR
914 union opcode_tid ot;
915 __be16 sge_ec_id;
916 __u8 cr;
917 __u8 rsvd;
918};
919
910struct cpl_rdma_ec_status {
911 RSS_HDR
912 union opcode_tid ot;
913 __u8 rsvd[3];
914 __u8 status;
915};
916
917struct mngt_pktsched_wr {

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954 __be16 rsvd;
955 __be16 len;
956 __be32 seq;
957 __be16 urg;
958#if defined(__LITTLE_ENDIAN_BITFIELD)
959 __u8 dack_mode:2;
960 __u8 psh:1;
961 __u8 heartbeat:1;
920struct cpl_rdma_ec_status {
921 RSS_HDR
922 union opcode_tid ot;
923 __u8 rsvd[3];
924 __u8 status;
925};
926
927struct mngt_pktsched_wr {

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964 __be16 rsvd;
965 __be16 len;
966 __be32 seq;
967 __be16 urg;
968#if defined(__LITTLE_ENDIAN_BITFIELD)
969 __u8 dack_mode:2;
970 __u8 psh:1;
971 __u8 heartbeat:1;
962 __u8 :4;
972 __u8 ddp_off:1;
973 __u8 :3;
963#else
974#else
964 __u8 :4;
975 __u8 :3;
976 __u8 ddp_off:1;
965 __u8 heartbeat:1;
966 __u8 psh:1;
967 __u8 dack_mode:2;
968#endif
969 __u8 status;
970};
971
972struct cpl_rx_data_ack {

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1124#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1125
1126struct cpl_tx_pkt {
1127 WR_HDR;
1128 __be32 cntrl;
1129 __be32 len;
1130};
1131
977 __u8 heartbeat:1;
978 __u8 psh:1;
979 __u8 dack_mode:2;
980#endif
981 __u8 status;
982};
983
984struct cpl_rx_data_ack {

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1136#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1137
1138struct cpl_tx_pkt {
1139 WR_HDR;
1140 __be32 cntrl;
1141 __be32 len;
1142};
1143
1144struct cpl_tx_pkt_coalesce {
1145 __be32 cntrl;
1146 __be32 len;
1147 __be64 addr;
1148};
1149
1150struct tx_pkt_coalesce_wr {
1151 WR_HDR;
1152 struct cpl_tx_pkt_coalesce cpl[0];
1153};
1154
1132struct cpl_tx_pkt_lso {
1133 WR_HDR;
1134 __be32 cntrl;
1135 __be32 len;
1136
1137 __be32 rsvd;
1138 __be32 lso_info;
1139};

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1260 __be16 vlan;
1261 __be16 len;
1262};
1263
1264struct cpl_l2t_write_req {
1265 WR_HDR;
1266 union opcode_tid ot;
1267 __be32 params;
1155struct cpl_tx_pkt_lso {
1156 WR_HDR;
1157 __be32 cntrl;
1158 __be32 len;
1159
1160 __be32 rsvd;
1161 __be32 lso_info;
1162};

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1283 __be16 vlan;
1284 __be16 len;
1285};
1286
1287struct cpl_l2t_write_req {
1288 WR_HDR;
1289 union opcode_tid ot;
1290 __be32 params;
1268 __u8 rsvd[2];
1291 __u8 rsvd;
1292 __u8 port_idx;
1269 __u8 dst_mac[6];
1270};
1271
1272/* cpl_l2t_write_req.params fields */
1273#define S_L2T_W_IDX 0
1274#define M_L2T_W_IDX 0x7FF
1275#define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1276#define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)

--- 293 unchanged lines hidden --- 		1293 __u8 dst_mac[6];
1294};
1295
1296/* cpl_l2t_write_req.params fields */
1297#define S_L2T_W_IDX 0
1298#define M_L2T_W_IDX 0x7FF
1299#define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1300#define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)

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