1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
--- 11 unchanged lines hidden (view full) ---
20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_cpl.h 170076 2007-05-28 22:57:27Z kmacy $
29
30***************************************************************************/
31#ifndef T3_CPL_H
32#define T3_CPL_H
33
34#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
35# include <asm/byteorder.h>
36#endif
37
38enum CPL_opcode {
39 CPL_PASS_OPEN_REQ = 0x1,
40 CPL_PASS_ACCEPT_RPL = 0x2,
41 CPL_ACT_OPEN_REQ = 0x3,
42 CPL_SET_TCB = 0x4,
43 CPL_SET_TCB_FIELD = 0x5,
44 CPL_GET_TCB = 0x6,
45 CPL_PCMD = 0x7,
--- 82 unchanged lines hidden (view full) ---
128 CPL_ERR_PERSIST_NEG_ADVICE = 36,
129 CPL_ERR_ABORT_FAILED = 42,
130 CPL_ERR_GENERAL = 99
131};
132
133enum {
134 CPL_CONN_POLICY_AUTO = 0,
135 CPL_CONN_POLICY_ASK = 1,
136 CPL_CONN_POLICY_DENY = 3
137};
138
139enum {
140 ULP_MODE_NONE = 0,
141 ULP_MODE_TCP_DDP = 1,
142 ULP_MODE_ISCSI = 2,
143 ULP_MODE_RDMA = 4,
--- 110 unchanged lines hidden (view full) ---
254#define S_WR_BCNTLFLT 16
255#define M_WR_BCNTLFLT 0xF
256#define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
257#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
258
259/* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before
260 * and after the BYPASS WR if the ATOMIC bit is set.
261 */
262#define S_WR_ATOMIC 16
263#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC)
264#define F_WR_ATOMIC V_WR_ATOMIC(1U)
265
266/* Applicable to BYPASS WRs only: the uP will flush buffered non abort
267 * related WRs.
268 */
269#define S_WR_FLUSH 17
270#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
271#define F_WR_FLUSH V_WR_FLUSH(1U)
272
273#define S_WR_DATATYPE 20
274#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
275#define F_WR_DATATYPE V_WR_DATATYPE(1U)
276
277#define S_WR_COMPL 21
278#define V_WR_COMPL(x) ((x) << S_WR_COMPL)
279#define F_WR_COMPL V_WR_COMPL(1U)
--- 130 unchanged lines hidden (view full) ---
410#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
411#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
412
413#define S_CPU_IDX 4
414#define M_CPU_IDX 0x3F
415#define V_CPU_IDX(x) ((x) << S_CPU_IDX)
416#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
417
418#define S_MAC_MATCH_VALID 18
419#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
420#define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
421
422#define S_CONN_POLICY 19
423#define M_CONN_POLICY 0x3
424#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
425#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
--- 377 unchanged lines hidden (view full) ---
803 __be32 wr_hi;
804 __be32 wr_lo;
805 __be32 len;
806 __be32 flags;
807 __be32 sndseq;
808 __be32 param;
809};
810
811/* tx_data_wr.param fields */
812#define S_TX_PORT 0
813#define M_TX_PORT 0x7
814#define V_TX_PORT(x) ((x) << S_TX_PORT)
815#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
816
817#define S_TX_MSS 4
818#define M_TX_MSS 0xF
--- 185 unchanged lines hidden (view full) ---
1004 RSS_HDR
1005 union opcode_tid ot;
1006 __be16 urg;
1007 __be16 len;
1008 __be32 seq;
1009 union {
1010 __be32 nxt_seq;
1011 __be32 ddp_report;
1012 } __U;
1013 __be32 ulp_crc;
1014 __be32 ddpvld_status;
1015};
1016
1017/* cpl_rx_data_ddp.ddpvld_status fields */
1018#define S_DDP_STATUS 0
1019#define M_DDP_STATUS 0xFF
1020#define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
--- 489 unchanged lines hidden (view full) ---
1510#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1511
1512struct ulp_mem_io {
1513 WR_HDR;
1514 __be32 cmd_lock_addr;
1515 __be32 len;
1516};
1517
1518 /* ulp_mem_io.cmd_lock_addr fields */
1519#define S_ULP_MEMIO_ADDR 0
1520#define M_ULP_MEMIO_ADDR 0x7FFFFFF
1521#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1522
1523#define S_ULP_MEMIO_LOCK 27
1524#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1525#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1526
1527 /* ulp_mem_io.len fields */
1528#define S_ULP_MEMIO_DATA_LEN 28
1529#define M_ULP_MEMIO_DATA_LEN 0xF
1530#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1531
1532struct ulp_txpkt {
1533 __be32 cmd_dest;
1534 __be32 len;
1535};
1536
1537 /* ulp_txpkt.cmd_dest fields */
1538#define S_ULP_TXPKT_DEST 24
1539#define M_ULP_TXPKT_DEST 0xF
1540#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
1541
1542#endif /* T3_CPL_H */
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
--- 11 unchanged lines hidden (view full) ---
20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_cpl.h 170076 2007-05-28 22:57:27Z kmacy $
29
30***************************************************************************/
31#ifndef T3_CPL_H
32#define T3_CPL_H
33
34#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
35# include <asm/byteorder.h>
36#endif
37
38enum CPL_opcode {
39 CPL_PASS_OPEN_REQ = 0x1,
40 CPL_PASS_ACCEPT_RPL = 0x2,
41 CPL_ACT_OPEN_REQ = 0x3,
42 CPL_SET_TCB = 0x4,
43 CPL_SET_TCB_FIELD = 0x5,
44 CPL_GET_TCB = 0x6,
45 CPL_PCMD = 0x7,
--- 82 unchanged lines hidden (view full) ---
128 CPL_ERR_PERSIST_NEG_ADVICE = 36,
129 CPL_ERR_ABORT_FAILED = 42,
130 CPL_ERR_GENERAL = 99
131};
132
133enum {
134 CPL_CONN_POLICY_AUTO = 0,
135 CPL_CONN_POLICY_ASK = 1,
136 CPL_CONN_POLICY_DENY = 3
137};
138
139enum {
140 ULP_MODE_NONE = 0,
141 ULP_MODE_TCP_DDP = 1,
142 ULP_MODE_ISCSI = 2,
143 ULP_MODE_RDMA = 4,
--- 110 unchanged lines hidden (view full) ---
254#define S_WR_BCNTLFLT 16
255#define M_WR_BCNTLFLT 0xF
256#define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
257#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
258
259/* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before
260 * and after the BYPASS WR if the ATOMIC bit is set.
261 */
262#define S_WR_ATOMIC 16
263#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC)
264#define F_WR_ATOMIC V_WR_ATOMIC(1U)
265
266/* Applicable to BYPASS WRs only: the uP will flush buffered non abort
267 * related WRs.
268 */
269#define S_WR_FLUSH 17
270#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
271#define F_WR_FLUSH V_WR_FLUSH(1U)
272
273#define S_WR_DATATYPE 20
274#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
275#define F_WR_DATATYPE V_WR_DATATYPE(1U)
276
277#define S_WR_COMPL 21
278#define V_WR_COMPL(x) ((x) << S_WR_COMPL)
279#define F_WR_COMPL V_WR_COMPL(1U)
--- 130 unchanged lines hidden (view full) ---
410#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
411#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
412
413#define S_CPU_IDX 4
414#define M_CPU_IDX 0x3F
415#define V_CPU_IDX(x) ((x) << S_CPU_IDX)
416#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
417
418#define S_MAC_MATCH_VALID 18
419#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
420#define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
421
422#define S_CONN_POLICY 19
423#define M_CONN_POLICY 0x3
424#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
425#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
--- 377 unchanged lines hidden (view full) ---
803 __be32 wr_hi;
804 __be32 wr_lo;
805 __be32 len;
806 __be32 flags;
807 __be32 sndseq;
808 __be32 param;
809};
810
811/* tx_data_wr.param fields */
812#define S_TX_PORT 0
813#define M_TX_PORT 0x7
814#define V_TX_PORT(x) ((x) << S_TX_PORT)
815#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
816
817#define S_TX_MSS 4
818#define M_TX_MSS 0xF
--- 185 unchanged lines hidden (view full) ---
1004 RSS_HDR
1005 union opcode_tid ot;
1006 __be16 urg;
1007 __be16 len;
1008 __be32 seq;
1009 union {
1010 __be32 nxt_seq;
1011 __be32 ddp_report;
1012 } __U;
1013 __be32 ulp_crc;
1014 __be32 ddpvld_status;
1015};
1016
1017/* cpl_rx_data_ddp.ddpvld_status fields */
1018#define S_DDP_STATUS 0
1019#define M_DDP_STATUS 0xFF
1020#define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
--- 489 unchanged lines hidden (view full) ---
1510#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1511
1512struct ulp_mem_io {
1513 WR_HDR;
1514 __be32 cmd_lock_addr;
1515 __be32 len;
1516};
1517
1518 /* ulp_mem_io.cmd_lock_addr fields */
1519#define S_ULP_MEMIO_ADDR 0
1520#define M_ULP_MEMIO_ADDR 0x7FFFFFF
1521#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1522
1523#define S_ULP_MEMIO_LOCK 27
1524#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1525#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1526
1527 /* ulp_mem_io.len fields */
1528#define S_ULP_MEMIO_DATA_LEN 28
1529#define M_ULP_MEMIO_DATA_LEN 0xF
1530#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1531
1532struct ulp_txpkt {
1533 __be32 cmd_dest;
1534 __be32 len;
1535};
1536
1537 /* ulp_txpkt.cmd_dest fields */
1538#define S_ULP_TXPKT_DEST 24
1539#define M_ULP_TXPKT_DEST 0xF
1540#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
1541
1542#endif /* T3_CPL_H */