| cxgb_regs.h (170076) | cxgb_regs.h (176472) |
|---|---|
| 1/************************************************************************** 2 3Copyright (c) 2007, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 --- 11 unchanged lines hidden (view full) --- 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 | 1/************************************************************************** 2 3Copyright (c) 2007, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 --- 11 unchanged lines hidden (view full) --- 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 |
| 28$FreeBSD: head/sys/dev/cxgb/common/cxgb_regs.h 170076 2007-05-28 22:57:27Z kmacy $ | 28$FreeBSD: head/sys/dev/cxgb/common/cxgb_regs.h 176472 2008-02-23 01:06:17Z kmacy $ |
| 29 30***************************************************************************/ 31/* This file is automatically generated --- do not edit */ 32 33/* registers for module SGE3 */ 34#define SGE3_BASE_ADDR 0x0 35 36#define A_SG_CONTROL 0x0 37 | 29 30***************************************************************************/ 31/* This file is automatically generated --- do not edit */ 32 33/* registers for module SGE3 */ 34#define SGE3_BASE_ADDR 0x0 35 36#define A_SG_CONTROL 0x0 37 |
| 38#define S_CONGMODE 29 39#define V_CONGMODE(x) ((x) << S_CONGMODE) 40#define F_CONGMODE V_CONGMODE(1U) 41 42#define S_TNLFLMODE 28 43#define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) 44#define F_TNLFLMODE V_TNLFLMODE(1U) 45 46#define S_FATLPERREN 27 47#define V_FATLPERREN(x) ((x) << S_FATLPERREN) 48#define F_FATLPERREN V_FATLPERREN(1U) 49 50#define S_URGTNL 26 51#define V_URGTNL(x) ((x) << S_URGTNL) 52#define F_URGTNL V_URGTNL(1U) 53 54#define S_NEWNOTIFY 25 55#define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY) 56#define F_NEWNOTIFY V_NEWNOTIFY(1U) 57 58#define S_AVOIDCQOVFL 24 59#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) 60#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) 61 62#define S_OPTONEINTMULTQ 23 63#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) 64#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) 65 66#define S_CQCRDTCTRL 22 67#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) 68#define F_CQCRDTCTRL V_CQCRDTCTRL(1U) 69 |
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| 38#define S_EGRENUPBP 21 39#define V_EGRENUPBP(x) ((x) << S_EGRENUPBP) 40#define F_EGRENUPBP V_EGRENUPBP(1U) 41 42#define S_DROPPKT 20 43#define V_DROPPKT(x) ((x) << S_DROPPKT) 44#define F_DROPPKT V_DROPPKT(1U) 45 --- 43 unchanged lines hidden (view full) --- 89#define S_ISCSICOALESCING 1 90#define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING) 91#define F_ISCSICOALESCING V_ISCSICOALESCING(1U) 92 93#define S_GLOBALENABLE 0 94#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) 95#define F_GLOBALENABLE V_GLOBALENABLE(1U) 96 | 70#define S_EGRENUPBP 21 71#define V_EGRENUPBP(x) ((x) << S_EGRENUPBP) 72#define F_EGRENUPBP V_EGRENUPBP(1U) 73 74#define S_DROPPKT 20 75#define V_DROPPKT(x) ((x) << S_DROPPKT) 76#define F_DROPPKT V_DROPPKT(1U) 77 --- 43 unchanged lines hidden (view full) --- 121#define S_ISCSICOALESCING 1 122#define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING) 123#define F_ISCSICOALESCING V_ISCSICOALESCING(1U) 124 125#define S_GLOBALENABLE 0 126#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) 127#define F_GLOBALENABLE V_GLOBALENABLE(1U) 128 |
| 97#define S_URGTNL 26 98#define V_URGTNL(x) ((x) << S_URGTNL) 99#define F_URGTNL V_URGTNL(1U) 100 101#define S_NEWNOTIFY 25 102#define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY) 103#define F_NEWNOTIFY V_NEWNOTIFY(1U) 104 105#define S_AVOIDCQOVFL 24 106#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) 107#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) 108 109#define S_OPTONEINTMULTQ 23 110#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) 111#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) 112 113#define S_CQCRDTCTRL 22 114#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) 115#define F_CQCRDTCTRL V_CQCRDTCTRL(1U) 116 | |
| 117#define A_SG_KDOORBELL 0x4 118 119#define S_SELEGRCNTX 31 120#define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX) 121#define F_SELEGRCNTX V_SELEGRCNTX(1U) 122 123#define S_EGRCNTX 0 124#define M_EGRCNTX 0xffff --- 236 unchanged lines hidden (view full) --- 361#define F_FL14EMPTY V_FL14EMPTY(1U) 362 363#define S_FL15EMPTY 31 364#define V_FL15EMPTY(x) ((x) << S_FL15EMPTY) 365#define F_FL15EMPTY V_FL15EMPTY(1U) 366 367#define A_SG_EGR_PRI_CNT 0x50 368 | 129#define A_SG_KDOORBELL 0x4 130 131#define S_SELEGRCNTX 31 132#define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX) 133#define F_SELEGRCNTX V_SELEGRCNTX(1U) 134 135#define S_EGRCNTX 0 136#define M_EGRCNTX 0xffff --- 236 unchanged lines hidden (view full) --- 373#define F_FL14EMPTY V_FL14EMPTY(1U) 374 375#define S_FL15EMPTY 31 376#define V_FL15EMPTY(x) ((x) << S_FL15EMPTY) 377#define F_FL15EMPTY V_FL15EMPTY(1U) 378 379#define A_SG_EGR_PRI_CNT 0x50 380 |
| 369#define S_EGRPRICNT 0 370#define M_EGRPRICNT 0x1f 371#define V_EGRPRICNT(x) ((x) << S_EGRPRICNT) 372#define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT) 373 | |
| 374#define S_EGRERROPCODE 24 375#define M_EGRERROPCODE 0xff 376#define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE) 377#define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE) 378 379#define S_EGRHIOPCODE 16 380#define M_EGRHIOPCODE 0xff 381#define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE) 382#define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE) 383 384#define S_EGRLOOPCODE 8 385#define M_EGRLOOPCODE 0xff 386#define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE) 387#define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE) 388 | 381#define S_EGRERROPCODE 24 382#define M_EGRERROPCODE 0xff 383#define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE) 384#define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE) 385 386#define S_EGRHIOPCODE 16 387#define M_EGRHIOPCODE 0xff 388#define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE) 389#define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE) 390 391#define S_EGRLOOPCODE 8 392#define M_EGRLOOPCODE 0xff 393#define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE) 394#define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE) 395 |
| 396#define S_EGRPRICNT 0 397#define M_EGRPRICNT 0x1f 398#define V_EGRPRICNT(x) ((x) << S_EGRPRICNT) 399#define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT) 400 |
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| 389#define A_SG_EGR_RCQ_DRB_THRSH 0x54 390 391#define S_HIRCQDRBTHRSH 16 392#define M_HIRCQDRBTHRSH 0x7ff 393#define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH) 394#define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH) 395 396#define S_LORCQDRBTHRSH 0 --- 5 unchanged lines hidden (view full) --- 402 403#define S_EGRCNTXBADDR 5 404#define M_EGRCNTXBADDR 0x7ffffff 405#define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR) 406#define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR) 407 408#define A_SG_INT_CAUSE 0x5c 409 | 401#define A_SG_EGR_RCQ_DRB_THRSH 0x54 402 403#define S_HIRCQDRBTHRSH 16 404#define M_HIRCQDRBTHRSH 0x7ff 405#define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH) 406#define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH) 407 408#define S_LORCQDRBTHRSH 0 --- 5 unchanged lines hidden (view full) --- 414 415#define S_EGRCNTXBADDR 5 416#define M_EGRCNTXBADDR 0x7ffffff 417#define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR) 418#define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR) 419 420#define A_SG_INT_CAUSE 0x5c 421 |
| 422#define S_HIRCQPARITYERROR 31 423#define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR) 424#define F_HIRCQPARITYERROR V_HIRCQPARITYERROR(1U) 425 426#define S_LORCQPARITYERROR 30 427#define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR) 428#define F_LORCQPARITYERROR V_LORCQPARITYERROR(1U) 429 430#define S_HIDRBPARITYERROR 29 431#define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR) 432#define F_HIDRBPARITYERROR V_HIDRBPARITYERROR(1U) 433 434#define S_LODRBPARITYERROR 28 435#define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR) 436#define F_LODRBPARITYERROR V_LODRBPARITYERROR(1U) 437 438#define S_FLPARITYERROR 22 439#define M_FLPARITYERROR 0x3f 440#define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR) 441#define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR) 442 443#define S_ITPARITYERROR 20 444#define M_ITPARITYERROR 0x3 445#define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR) 446#define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR) 447 448#define S_IRPARITYERROR 19 449#define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR) 450#define F_IRPARITYERROR V_IRPARITYERROR(1U) 451 452#define S_RCPARITYERROR 18 453#define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR) 454#define F_RCPARITYERROR V_RCPARITYERROR(1U) 455 456#define S_OCPARITYERROR 17 457#define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR) 458#define F_OCPARITYERROR V_OCPARITYERROR(1U) 459 460#define S_CPPARITYERROR 16 461#define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR) 462#define F_CPPARITYERROR V_CPPARITYERROR(1U) 463 464#define S_R_REQ_FRAMINGERROR 15 465#define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR) 466#define F_R_REQ_FRAMINGERROR V_R_REQ_FRAMINGERROR(1U) 467 468#define S_UC_REQ_FRAMINGERROR 14 469#define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR) 470#define F_UC_REQ_FRAMINGERROR V_UC_REQ_FRAMINGERROR(1U) 471 |
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| 410#define S_HICTLDRBDROPERR 13 411#define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR) 412#define F_HICTLDRBDROPERR V_HICTLDRBDROPERR(1U) 413 414#define S_LOCTLDRBDROPERR 12 415#define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR) 416#define F_LOCTLDRBDROPERR V_LOCTLDRBDROPERR(1U) 417 --- 159 unchanged lines hidden (view full) --- 577 578#define S_MSTDETPARERR 0 579#define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR) 580#define F_MSTDETPARERR V_MSTDETPARERR(1U) 581 582#define A_PCIX_INT_CAUSE 0x84 583#define A_PCIX_CFG 0x88 584 | 472#define S_HICTLDRBDROPERR 13 473#define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR) 474#define F_HICTLDRBDROPERR V_HICTLDRBDROPERR(1U) 475 476#define S_LOCTLDRBDROPERR 12 477#define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR) 478#define F_LOCTLDRBDROPERR V_LOCTLDRBDROPERR(1U) 479 --- 159 unchanged lines hidden (view full) --- 639 640#define S_MSTDETPARERR 0 641#define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR) 642#define F_MSTDETPARERR V_MSTDETPARERR(1U) 643 644#define A_PCIX_INT_CAUSE 0x84 645#define A_PCIX_CFG 0x88 646 |
| 647#define S_DMASTOPEN 19 648#define V_DMASTOPEN(x) ((x) << S_DMASTOPEN) 649#define F_DMASTOPEN V_DMASTOPEN(1U) 650 |
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| 585#define S_CLIDECEN 18 586#define V_CLIDECEN(x) ((x) << S_CLIDECEN) 587#define F_CLIDECEN V_CLIDECEN(1U) 588 589#define S_LATTMRDIS 17 590#define V_LATTMRDIS(x) ((x) << S_LATTMRDIS) 591#define F_LATTMRDIS V_LATTMRDIS(1U) 592 --- 123 unchanged lines hidden (view full) --- 716#define S_SLEEPMODE1 1 717#define V_SLEEPMODE1(x) ((x) << S_SLEEPMODE1) 718#define F_SLEEPMODE1 V_SLEEPMODE1(1U) 719 720#define S_SLEEPMODE0 0 721#define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0) 722#define F_SLEEPMODE0 V_SLEEPMODE0(1U) 723 | 651#define S_CLIDECEN 18 652#define V_CLIDECEN(x) ((x) << S_CLIDECEN) 653#define F_CLIDECEN V_CLIDECEN(1U) 654 655#define S_LATTMRDIS 17 656#define V_LATTMRDIS(x) ((x) << S_LATTMRDIS) 657#define F_LATTMRDIS V_LATTMRDIS(1U) 658 --- 123 unchanged lines hidden (view full) --- 782#define S_SLEEPMODE1 1 783#define V_SLEEPMODE1(x) ((x) << S_SLEEPMODE1) 784#define F_SLEEPMODE1 V_SLEEPMODE1(1U) 785 786#define S_SLEEPMODE0 0 787#define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0) 788#define F_SLEEPMODE0 V_SLEEPMODE0(1U) 789 |
| 790#define A_PCIX_STAT0 0x98 791 792#define S_PIOREQFIFOLEVEL 26 793#define M_PIOREQFIFOLEVEL 0x3f 794#define V_PIOREQFIFOLEVEL(x) ((x) << S_PIOREQFIFOLEVEL) 795#define G_PIOREQFIFOLEVEL(x) (((x) >> S_PIOREQFIFOLEVEL) & M_PIOREQFIFOLEVEL) 796 797#define S_RFINIST 24 798#define M_RFINIST 0x3 799#define V_RFINIST(x) ((x) << S_RFINIST) 800#define G_RFINIST(x) (((x) >> S_RFINIST) & M_RFINIST) 801 802#define S_RFRESPRDST 22 803#define M_RFRESPRDST 0x3 804#define V_RFRESPRDST(x) ((x) << S_RFRESPRDST) 805#define G_RFRESPRDST(x) (((x) >> S_RFRESPRDST) & M_RFRESPRDST) 806 807#define S_TARCST 19 808#define M_TARCST 0x7 809#define V_TARCST(x) ((x) << S_TARCST) 810#define G_TARCST(x) (((x) >> S_TARCST) & M_TARCST) 811 812#define S_TARXST 16 813#define M_TARXST 0x7 814#define V_TARXST(x) ((x) << S_TARXST) 815#define G_TARXST(x) (((x) >> S_TARXST) & M_TARXST) 816 817#define S_WFREQWRST 13 818#define M_WFREQWRST 0x7 819#define V_WFREQWRST(x) ((x) << S_WFREQWRST) 820#define G_WFREQWRST(x) (((x) >> S_WFREQWRST) & M_WFREQWRST) 821 822#define S_WFRESPFIFOEMPTY 12 823#define V_WFRESPFIFOEMPTY(x) ((x) << S_WFRESPFIFOEMPTY) 824#define F_WFRESPFIFOEMPTY V_WFRESPFIFOEMPTY(1U) 825 826#define S_WFREQFIFOEMPTY 11 827#define V_WFREQFIFOEMPTY(x) ((x) << S_WFREQFIFOEMPTY) 828#define F_WFREQFIFOEMPTY V_WFREQFIFOEMPTY(1U) 829 830#define S_RFRESPFIFOEMPTY 10 831#define V_RFRESPFIFOEMPTY(x) ((x) << S_RFRESPFIFOEMPTY) 832#define F_RFRESPFIFOEMPTY V_RFRESPFIFOEMPTY(1U) 833 834#define S_RFREQFIFOEMPTY 9 835#define V_RFREQFIFOEMPTY(x) ((x) << S_RFREQFIFOEMPTY) 836#define F_RFREQFIFOEMPTY V_RFREQFIFOEMPTY(1U) 837 838#define S_PIORESPFIFOLEVEL 7 839#define M_PIORESPFIFOLEVEL 0x3 840#define V_PIORESPFIFOLEVEL(x) ((x) << S_PIORESPFIFOLEVEL) 841#define G_PIORESPFIFOLEVEL(x) (((x) >> S_PIORESPFIFOLEVEL) & M_PIORESPFIFOLEVEL) 842 843#define S_CFRESPFIFOEMPTY 6 844#define V_CFRESPFIFOEMPTY(x) ((x) << S_CFRESPFIFOEMPTY) 845#define F_CFRESPFIFOEMPTY V_CFRESPFIFOEMPTY(1U) 846 847#define S_CFREQFIFOEMPTY 5 848#define V_CFREQFIFOEMPTY(x) ((x) << S_CFREQFIFOEMPTY) 849#define F_CFREQFIFOEMPTY V_CFREQFIFOEMPTY(1U) 850 851#define S_VPDRESPFIFOEMPTY 4 852#define V_VPDRESPFIFOEMPTY(x) ((x) << S_VPDRESPFIFOEMPTY) 853#define F_VPDRESPFIFOEMPTY V_VPDRESPFIFOEMPTY(1U) 854 855#define S_VPDREQFIFOEMPTY 3 856#define V_VPDREQFIFOEMPTY(x) ((x) << S_VPDREQFIFOEMPTY) 857#define F_VPDREQFIFOEMPTY V_VPDREQFIFOEMPTY(1U) 858 859#define S_PIO_RSPPND 2 860#define V_PIO_RSPPND(x) ((x) << S_PIO_RSPPND) 861#define F_PIO_RSPPND V_PIO_RSPPND(1U) 862 863#define S_DLYTRNPND 1 864#define V_DLYTRNPND(x) ((x) << S_DLYTRNPND) 865#define F_DLYTRNPND V_DLYTRNPND(1U) 866 867#define S_SPLTRNPND 0 868#define V_SPLTRNPND(x) ((x) << S_SPLTRNPND) 869#define F_SPLTRNPND V_SPLTRNPND(1U) 870 871#define A_PCIX_STAT1 0x9c 872 873#define S_WFINIST 26 874#define M_WFINIST 0xf 875#define V_WFINIST(x) ((x) << S_WFINIST) 876#define G_WFINIST(x) (((x) >> S_WFINIST) & M_WFINIST) 877 878#define S_ARBST 23 879#define M_ARBST 0x7 880#define V_ARBST(x) ((x) << S_ARBST) 881#define G_ARBST(x) (((x) >> S_ARBST) & M_ARBST) 882 883#define S_PMIST 21 884#define M_PMIST 0x3 885#define V_PMIST(x) ((x) << S_PMIST) 886#define G_PMIST(x) (((x) >> S_PMIST) & M_PMIST) 887 888#define S_CALST 19 889#define M_CALST 0x3 890#define V_CALST(x) ((x) << S_CALST) 891#define G_CALST(x) (((x) >> S_CALST) & M_CALST) 892 893#define S_CFREQRDST 17 894#define M_CFREQRDST 0x3 895#define V_CFREQRDST(x) ((x) << S_CFREQRDST) 896#define G_CFREQRDST(x) (((x) >> S_CFREQRDST) & M_CFREQRDST) 897 898#define S_CFINIST 15 899#define M_CFINIST 0x3 900#define V_CFINIST(x) ((x) << S_CFINIST) 901#define G_CFINIST(x) (((x) >> S_CFINIST) & M_CFINIST) 902 903#define S_CFRESPRDST 13 904#define M_CFRESPRDST 0x3 905#define V_CFRESPRDST(x) ((x) << S_CFRESPRDST) 906#define G_CFRESPRDST(x) (((x) >> S_CFRESPRDST) & M_CFRESPRDST) 907 908#define S_INICST 10 909#define M_INICST 0x7 910#define V_INICST(x) ((x) << S_INICST) 911#define G_INICST(x) (((x) >> S_INICST) & M_INICST) 912 913#define S_INIXST 7 914#define M_INIXST 0x7 915#define V_INIXST(x) ((x) << S_INIXST) 916#define G_INIXST(x) (((x) >> S_INIXST) & M_INIXST) 917 918#define S_INTST 4 919#define M_INTST 0x7 920#define V_INTST(x) ((x) << S_INTST) 921#define G_INTST(x) (((x) >> S_INTST) & M_INTST) 922 923#define S_PIOST 2 924#define M_PIOST 0x3 925#define V_PIOST(x) ((x) << S_PIOST) 926#define G_PIOST(x) (((x) >> S_PIOST) & M_PIOST) 927 928#define S_RFREQRDST 0 929#define M_RFREQRDST 0x3 930#define V_RFREQRDST(x) ((x) << S_RFREQRDST) 931#define G_RFREQRDST(x) (((x) >> S_RFREQRDST) & M_RFREQRDST) 932 |
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| 724/* registers for module PCIE0 */ 725#define PCIE0_BASE_ADDR 0x80 726 727#define A_PCIE_INT_ENABLE 0x80 728 | 933/* registers for module PCIE0 */ 934#define PCIE0_BASE_ADDR 0x80 935 936#define A_PCIE_INT_ENABLE 0x80 937 |
| 729#define S_BISTERR 15 | 938#define S_BISTERR 19 |
| 730#define M_BISTERR 0xff 731#define V_BISTERR(x) ((x) << S_BISTERR) 732#define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR) 733 | 939#define M_BISTERR 0xff 940#define V_BISTERR(x) ((x) << S_BISTERR) 941#define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR) 942 |
| 943#define S_TXPARERR 18 944#define V_TXPARERR(x) ((x) << S_TXPARERR) 945#define F_TXPARERR V_TXPARERR(1U) 946 947#define S_RXPARERR 17 948#define V_RXPARERR(x) ((x) << S_RXPARERR) 949#define F_RXPARERR V_RXPARERR(1U) 950 951#define S_RETRYLUTPARERR 16 952#define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR) 953#define F_RETRYLUTPARERR V_RETRYLUTPARERR(1U) 954 955#define S_RETRYBUFPARERR 15 956#define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR) 957#define F_RETRYBUFPARERR V_RETRYBUFPARERR(1U) 958 |
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| 734#define S_PCIE_MSIXPARERR 12 735#define M_PCIE_MSIXPARERR 0x7 736#define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR) 737#define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR) 738 739#define S_PCIE_CFPARERR 11 740#define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR) 741#define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U) --- 40 unchanged lines hidden (view full) --- 782 783#define S_PEXERR 0 784#define V_PEXERR(x) ((x) << S_PEXERR) 785#define F_PEXERR V_PEXERR(1U) 786 787#define A_PCIE_INT_CAUSE 0x84 788#define A_PCIE_CFG 0x88 789 | 959#define S_PCIE_MSIXPARERR 12 960#define M_PCIE_MSIXPARERR 0x7 961#define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR) 962#define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR) 963 964#define S_PCIE_CFPARERR 11 965#define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR) 966#define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U) --- 40 unchanged lines hidden (view full) --- 1007 1008#define S_PEXERR 0 1009#define V_PEXERR(x) ((x) << S_PEXERR) 1010#define F_PEXERR V_PEXERR(1U) 1011 1012#define A_PCIE_INT_CAUSE 0x84 1013#define A_PCIE_CFG 0x88 1014 |
| 1015#define S_PCIE_DMASTOPEN 24 1016#define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN) 1017#define F_PCIE_DMASTOPEN V_PCIE_DMASTOPEN(1U) 1018 1019#define S_PRIORITYINTA 23 1020#define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA) 1021#define F_PRIORITYINTA V_PRIORITYINTA(1U) 1022 1023#define S_INIFULLPKT 22 1024#define V_INIFULLPKT(x) ((x) << S_INIFULLPKT) 1025#define F_INIFULLPKT V_INIFULLPKT(1U) 1026 |
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| 790#define S_ENABLELINKDWNDRST 21 791#define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST) 792#define F_ENABLELINKDWNDRST V_ENABLELINKDWNDRST(1U) 793 794#define S_ENABLELINKDOWNRST 20 795#define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST) 796#define F_ENABLELINKDOWNRST V_ENABLELINKDOWNRST(1U) 797 --- 22 unchanged lines hidden (view full) --- 820#define M_PCIE_MAXSPLTRNR 0x3f 821#define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR) 822#define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR) 823 824#define S_CRSTWRMMODE 0 825#define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE) 826#define F_CRSTWRMMODE V_CRSTWRMMODE(1U) 827 | 1027#define S_ENABLELINKDWNDRST 21 1028#define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST) 1029#define F_ENABLELINKDWNDRST V_ENABLELINKDWNDRST(1U) 1030 1031#define S_ENABLELINKDOWNRST 20 1032#define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST) 1033#define F_ENABLELINKDOWNRST V_ENABLELINKDOWNRST(1U) 1034 --- 22 unchanged lines hidden (view full) --- 1057#define M_PCIE_MAXSPLTRNR 0x3f 1058#define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR) 1059#define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR) 1060 1061#define S_CRSTWRMMODE 0 1062#define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE) 1063#define F_CRSTWRMMODE V_CRSTWRMMODE(1U) 1064 |
| 828#define S_PRIORITYINTA 23 829#define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA) 830#define F_PRIORITYINTA V_PRIORITYINTA(1U) | 1065#define A_PCIE_MODE 0x8c |
| 831 | 1066 |
| 832#define S_INIFULLPKT 22 833#define V_INIFULLPKT(x) ((x) << S_INIFULLPKT) 834#define F_INIFULLPKT V_INIFULLPKT(1U) | 1067#define S_TAR_STATE 29 1068#define M_TAR_STATE 0x7 1069#define V_TAR_STATE(x) ((x) << S_TAR_STATE) 1070#define G_TAR_STATE(x) (((x) >> S_TAR_STATE) & M_TAR_STATE) |
| 835 | 1071 |
| 836#define A_PCIE_MODE 0x8c | 1072#define S_RF_STATEINI 26 1073#define M_RF_STATEINI 0x7 1074#define V_RF_STATEINI(x) ((x) << S_RF_STATEINI) 1075#define G_RF_STATEINI(x) (((x) >> S_RF_STATEINI) & M_RF_STATEINI) |
| 837 | 1076 |
| 1077#define S_CF_STATEINI 23 1078#define M_CF_STATEINI 0x7 1079#define V_CF_STATEINI(x) ((x) << S_CF_STATEINI) 1080#define G_CF_STATEINI(x) (((x) >> S_CF_STATEINI) & M_CF_STATEINI) 1081 1082#define S_PIO_STATEPL 20 1083#define M_PIO_STATEPL 0x7 1084#define V_PIO_STATEPL(x) ((x) << S_PIO_STATEPL) 1085#define G_PIO_STATEPL(x) (((x) >> S_PIO_STATEPL) & M_PIO_STATEPL) 1086 1087#define S_PIO_STATEISC 18 1088#define M_PIO_STATEISC 0x3 1089#define V_PIO_STATEISC(x) ((x) << S_PIO_STATEISC) 1090#define G_PIO_STATEISC(x) (((x) >> S_PIO_STATEISC) & M_PIO_STATEISC) 1091 1092#define S_NUMFSTTRNSEQRX 10 1093#define M_NUMFSTTRNSEQRX 0xff 1094#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) 1095#define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX) 1096 |
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| 838#define S_LNKCNTLSTATE 2 839#define M_LNKCNTLSTATE 0xff 840#define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE) 841#define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE) 842 843#define S_VC0UP 1 844#define V_VC0UP(x) ((x) << S_VC0UP) 845#define F_VC0UP V_VC0UP(1U) 846 847#define S_LNKINITIAL 0 848#define V_LNKINITIAL(x) ((x) << S_LNKINITIAL) 849#define F_LNKINITIAL V_LNKINITIAL(1U) 850 | 1097#define S_LNKCNTLSTATE 2 1098#define M_LNKCNTLSTATE 0xff 1099#define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE) 1100#define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE) 1101 1102#define S_VC0UP 1 1103#define V_VC0UP(x) ((x) << S_VC0UP) 1104#define F_VC0UP V_VC0UP(1U) 1105 1106#define S_LNKINITIAL 0 1107#define V_LNKINITIAL(x) ((x) << S_LNKINITIAL) 1108#define F_LNKINITIAL V_LNKINITIAL(1U) 1109 |
| 851#define S_NUMFSTTRNSEQRX 10 852#define M_NUMFSTTRNSEQRX 0xff 853#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) 854#define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX) | 1110#define A_PCIE_STAT 0x90 |
| 855 | 1111 |
| 1112#define S_INI_STATE 28 1113#define M_INI_STATE 0xf 1114#define V_INI_STATE(x) ((x) << S_INI_STATE) 1115#define G_INI_STATE(x) (((x) >> S_INI_STATE) & M_INI_STATE) 1116 1117#define S_WF_STATEINI 24 1118#define M_WF_STATEINI 0xf 1119#define V_WF_STATEINI(x) ((x) << S_WF_STATEINI) 1120#define G_WF_STATEINI(x) (((x) >> S_WF_STATEINI) & M_WF_STATEINI) 1121 1122#define S_PLM_REQFIFOCNT 22 1123#define M_PLM_REQFIFOCNT 0x3 1124#define V_PLM_REQFIFOCNT(x) ((x) << S_PLM_REQFIFOCNT) 1125#define G_PLM_REQFIFOCNT(x) (((x) >> S_PLM_REQFIFOCNT) & M_PLM_REQFIFOCNT) 1126 1127#define S_ER_REQFIFOEMPTY 21 1128#define V_ER_REQFIFOEMPTY(x) ((x) << S_ER_REQFIFOEMPTY) 1129#define F_ER_REQFIFOEMPTY V_ER_REQFIFOEMPTY(1U) 1130 1131#define S_WF_RSPFIFOEMPTY 20 1132#define V_WF_RSPFIFOEMPTY(x) ((x) << S_WF_RSPFIFOEMPTY) 1133#define F_WF_RSPFIFOEMPTY V_WF_RSPFIFOEMPTY(1U) 1134 1135#define S_WF_REQFIFOEMPTY 19 1136#define V_WF_REQFIFOEMPTY(x) ((x) << S_WF_REQFIFOEMPTY) 1137#define F_WF_REQFIFOEMPTY V_WF_REQFIFOEMPTY(1U) 1138 1139#define S_RF_RSPFIFOEMPTY 18 1140#define V_RF_RSPFIFOEMPTY(x) ((x) << S_RF_RSPFIFOEMPTY) 1141#define F_RF_RSPFIFOEMPTY V_RF_RSPFIFOEMPTY(1U) 1142 1143#define S_RF_REQFIFOEMPTY 17 1144#define V_RF_REQFIFOEMPTY(x) ((x) << S_RF_REQFIFOEMPTY) 1145#define F_RF_REQFIFOEMPTY V_RF_REQFIFOEMPTY(1U) 1146 1147#define S_RF_ACTEMPTY 16 1148#define V_RF_ACTEMPTY(x) ((x) << S_RF_ACTEMPTY) 1149#define F_RF_ACTEMPTY V_RF_ACTEMPTY(1U) 1150 1151#define S_PIO_RSPFIFOCNT 11 1152#define M_PIO_RSPFIFOCNT 0x1f 1153#define V_PIO_RSPFIFOCNT(x) ((x) << S_PIO_RSPFIFOCNT) 1154#define G_PIO_RSPFIFOCNT(x) (((x) >> S_PIO_RSPFIFOCNT) & M_PIO_RSPFIFOCNT) 1155 1156#define S_PIO_REQFIFOCNT 5 1157#define M_PIO_REQFIFOCNT 0x3f 1158#define V_PIO_REQFIFOCNT(x) ((x) << S_PIO_REQFIFOCNT) 1159#define G_PIO_REQFIFOCNT(x) (((x) >> S_PIO_REQFIFOCNT) & M_PIO_REQFIFOCNT) 1160 1161#define S_CF_RSPFIFOEMPTY 4 1162#define V_CF_RSPFIFOEMPTY(x) ((x) << S_CF_RSPFIFOEMPTY) 1163#define F_CF_RSPFIFOEMPTY V_CF_RSPFIFOEMPTY(1U) 1164 1165#define S_CF_REQFIFOEMPTY 3 1166#define V_CF_REQFIFOEMPTY(x) ((x) << S_CF_REQFIFOEMPTY) 1167#define F_CF_REQFIFOEMPTY V_CF_REQFIFOEMPTY(1U) 1168 1169#define S_CF_ACTEMPTY 2 1170#define V_CF_ACTEMPTY(x) ((x) << S_CF_ACTEMPTY) 1171#define F_CF_ACTEMPTY V_CF_ACTEMPTY(1U) 1172 1173#define S_VPD_RSPFIFOEMPTY 1 1174#define V_VPD_RSPFIFOEMPTY(x) ((x) << S_VPD_RSPFIFOEMPTY) 1175#define F_VPD_RSPFIFOEMPTY V_VPD_RSPFIFOEMPTY(1U) 1176 1177#define S_VPD_REQFIFOEMPTY 0 1178#define V_VPD_REQFIFOEMPTY(x) ((x) << S_VPD_REQFIFOEMPTY) 1179#define F_VPD_REQFIFOEMPTY V_VPD_REQFIFOEMPTY(1U) 1180 |
|
| 856#define A_PCIE_CAL 0x90 857 858#define S_CALBUSY 31 859#define V_CALBUSY(x) ((x) << S_CALBUSY) 860#define F_CALBUSY V_CALBUSY(1U) 861 862#define S_CALFAULT 30 863#define V_CALFAULT(x) ((x) << S_CALFAULT) --- 14 unchanged lines hidden (view full) --- 878#define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT) 879 880#define S_ZIN 0 881#define M_ZIN 0x7 882#define V_ZIN(x) ((x) << S_ZIN) 883#define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN) 884 885#define A_PCIE_WOL 0x94 | 1181#define A_PCIE_CAL 0x90 1182 1183#define S_CALBUSY 31 1184#define V_CALBUSY(x) ((x) << S_CALBUSY) 1185#define F_CALBUSY V_CALBUSY(1U) 1186 1187#define S_CALFAULT 30 1188#define V_CALFAULT(x) ((x) << S_CALFAULT) --- 14 unchanged lines hidden (view full) --- 1203#define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT) 1204 1205#define S_ZIN 0 1206#define M_ZIN 0x7 1207#define V_ZIN(x) ((x) << S_ZIN) 1208#define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN) 1209 1210#define A_PCIE_WOL 0x94 |
| 1211 1212#define S_CF_RSPSTATE 12 1213#define M_CF_RSPSTATE 0x3 1214#define V_CF_RSPSTATE(x) ((x) << S_CF_RSPSTATE) 1215#define G_CF_RSPSTATE(x) (((x) >> S_CF_RSPSTATE) & M_CF_RSPSTATE) 1216 1217#define S_RF_RSPSTATE 10 1218#define M_RF_RSPSTATE 0x3 1219#define V_RF_RSPSTATE(x) ((x) << S_RF_RSPSTATE) 1220#define G_RF_RSPSTATE(x) (((x) >> S_RF_RSPSTATE) & M_RF_RSPSTATE) 1221 1222#define S_PME_STATE 7 1223#define M_PME_STATE 0x7 1224#define V_PME_STATE(x) ((x) << S_PME_STATE) 1225#define G_PME_STATE(x) (((x) >> S_PME_STATE) & M_PME_STATE) 1226 1227#define S_INT_STATE 4 1228#define M_INT_STATE 0x7 1229#define V_INT_STATE(x) ((x) << S_INT_STATE) 1230#define G_INT_STATE(x) (((x) >> S_INT_STATE) & M_INT_STATE) 1231 |
|
| 886#define A_PCIE_PEX_CTRL0 0x98 887 | 1232#define A_PCIE_PEX_CTRL0 0x98 1233 |
| 1234#define S_CPLTIMEOUTRETRY 31 1235#define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY) 1236#define F_CPLTIMEOUTRETRY V_CPLTIMEOUTRETRY(1U) 1237 1238#define S_STRICTTSMN 30 1239#define V_STRICTTSMN(x) ((x) << S_STRICTTSMN) 1240#define F_STRICTTSMN V_STRICTTSMN(1U) 1241 |
|
| 888#define S_NUMFSTTRNSEQ 22 889#define M_NUMFSTTRNSEQ 0xff 890#define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ) 891#define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ) 892 893#define S_REPLAYLMT 2 894#define M_REPLAYLMT 0xfffff 895#define V_REPLAYLMT(x) ((x) << S_REPLAYLMT) 896#define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT) 897 898#define S_TXPNDCHKEN 1 899#define V_TXPNDCHKEN(x) ((x) << S_TXPNDCHKEN) 900#define F_TXPNDCHKEN V_TXPNDCHKEN(1U) 901 902#define S_CPLPNDCHKEN 0 903#define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN) 904#define F_CPLPNDCHKEN V_CPLPNDCHKEN(1U) 905 | 1242#define S_NUMFSTTRNSEQ 22 1243#define M_NUMFSTTRNSEQ 0xff 1244#define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ) 1245#define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ) 1246 1247#define S_REPLAYLMT 2 1248#define M_REPLAYLMT 0xfffff 1249#define V_REPLAYLMT(x) ((x) << S_REPLAYLMT) 1250#define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT) 1251 1252#define S_TXPNDCHKEN 1 1253#define V_TXPNDCHKEN(x) ((x) << S_TXPNDCHKEN) 1254#define F_TXPNDCHKEN V_TXPNDCHKEN(1U) 1255 1256#define S_CPLPNDCHKEN 0 1257#define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN) 1258#define F_CPLPNDCHKEN V_CPLPNDCHKEN(1U) 1259 |
| 906#define S_CPLTIMEOUTRETRY 31 907#define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY) 908#define F_CPLTIMEOUTRETRY V_CPLTIMEOUTRETRY(1U) 909 910#define S_STRICTTSMN 30 911#define V_STRICTTSMN(x) ((x) << S_STRICTTSMN) 912#define F_STRICTTSMN V_STRICTTSMN(1U) 913 | |
| 914#define A_PCIE_PEX_CTRL1 0x9c 915 | 1260#define A_PCIE_PEX_CTRL1 0x9c 1261 |
| 916#define S_T3A_DLLPTIMEOUTLMT 11 917#define M_T3A_DLLPTIMEOUTLMT 0xfffff 918#define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT) 919#define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT) 920 921#define S_T3A_ACKLAT 0 922#define M_T3A_ACKLAT 0x7ff 923#define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT) 924#define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT) 925 | |
| 926#define S_RXPHYERREN 31 927#define V_RXPHYERREN(x) ((x) << S_RXPHYERREN) 928#define F_RXPHYERREN V_RXPHYERREN(1U) 929 930#define S_DLLPTIMEOUTLMT 13 931#define M_DLLPTIMEOUTLMT 0x3ffff 932#define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT) 933#define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT) 934 935#define S_ACKLAT 0 936#define M_ACKLAT 0x1fff 937#define V_ACKLAT(x) ((x) << S_ACKLAT) 938#define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT) 939 | 1262#define S_RXPHYERREN 31 1263#define V_RXPHYERREN(x) ((x) << S_RXPHYERREN) 1264#define F_RXPHYERREN V_RXPHYERREN(1U) 1265 1266#define S_DLLPTIMEOUTLMT 13 1267#define M_DLLPTIMEOUTLMT 0x3ffff 1268#define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT) 1269#define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT) 1270 1271#define S_ACKLAT 0 1272#define M_ACKLAT 0x1fff 1273#define V_ACKLAT(x) ((x) << S_ACKLAT) 1274#define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT) 1275 |
| 1276#define S_T3A_DLLPTIMEOUTLMT 11 1277#define M_T3A_DLLPTIMEOUTLMT 0xfffff 1278#define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT) 1279#define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT) 1280 1281#define S_T3A_ACKLAT 0 1282#define M_T3A_ACKLAT 0x7ff 1283#define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT) 1284#define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT) 1285 |
|
| 940#define A_PCIE_PEX_CTRL2 0xa0 941 | 1286#define A_PCIE_PEX_CTRL2 0xa0 1287 |
| 942#define S_PMEXITL1REQ 29 | 1288#define S_LNKCNTLDETDIR 30 1289#define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR) 1290#define F_LNKCNTLDETDIR V_LNKCNTLDETDIR(1U) 1291 1292#define S_ENTERL1REN 29 1293#define V_ENTERL1REN(x) ((x) << S_ENTERL1REN) 1294#define F_ENTERL1REN V_ENTERL1REN(1U) 1295 1296#define S_PMEXITL1REQ 28 |
| 943#define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ) 944#define F_PMEXITL1REQ V_PMEXITL1REQ(1U) 945 | 1297#define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ) 1298#define F_PMEXITL1REQ V_PMEXITL1REQ(1U) 1299 |
| 946#define S_PMTXIDLE 28 | 1300#define S_PMTXIDLE 27 |
| 947#define V_PMTXIDLE(x) ((x) << S_PMTXIDLE) 948#define F_PMTXIDLE V_PMTXIDLE(1U) 949 | 1301#define V_PMTXIDLE(x) ((x) << S_PMTXIDLE) 1302#define F_PMTXIDLE V_PMTXIDLE(1U) 1303 |
| 950#define S_PCIMODELOOP 27 | 1304#define S_PCIMODELOOP 26 |
| 951#define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP) 952#define F_PCIMODELOOP V_PCIMODELOOP(1U) 953 | 1305#define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP) 1306#define F_PCIMODELOOP V_PCIMODELOOP(1U) 1307 |
| 954#define S_L1ASPMTXRXL0STIME 15 | 1308#define S_L1ASPMTXRXL0STIME 14 |
| 955#define M_L1ASPMTXRXL0STIME 0xfff 956#define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME) 957#define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME) 958 | 1309#define M_L1ASPMTXRXL0STIME 0xfff 1310#define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME) 1311#define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME) 1312 |
| 959#define S_L0SIDLETIME 4 | 1313#define S_L0SIDLETIME 3 |
| 960#define M_L0SIDLETIME 0x7ff 961#define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME) 962#define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME) 963 | 1314#define M_L0SIDLETIME 0x7ff 1315#define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME) 1316#define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME) 1317 |
| 964#define S_ENTERL23 3 965#define V_ENTERL23(x) ((x) << S_ENTERL23) 966#define F_ENTERL23 V_ENTERL23(1U) 967 | |
| 968#define S_ENTERL1ASPMEN 2 969#define V_ENTERL1ASPMEN(x) ((x) << S_ENTERL1ASPMEN) 970#define F_ENTERL1ASPMEN V_ENTERL1ASPMEN(1U) 971 972#define S_ENTERL1EN 1 973#define V_ENTERL1EN(x) ((x) << S_ENTERL1EN) 974#define F_ENTERL1EN V_ENTERL1EN(1U) 975 976#define S_ENTERL0SEN 0 977#define V_ENTERL0SEN(x) ((x) << S_ENTERL0SEN) 978#define F_ENTERL0SEN V_ENTERL0SEN(1U) 979 | 1318#define S_ENTERL1ASPMEN 2 1319#define V_ENTERL1ASPMEN(x) ((x) << S_ENTERL1ASPMEN) 1320#define F_ENTERL1ASPMEN V_ENTERL1ASPMEN(1U) 1321 1322#define S_ENTERL1EN 1 1323#define V_ENTERL1EN(x) ((x) << S_ENTERL1EN) 1324#define F_ENTERL1EN V_ENTERL1EN(1U) 1325 1326#define S_ENTERL0SEN 0 1327#define V_ENTERL0SEN(x) ((x) << S_ENTERL0SEN) 1328#define F_ENTERL0SEN V_ENTERL0SEN(1U) 1329 |
| 980#define S_LNKCNTLDETDIR 30 981#define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR) 982#define F_LNKCNTLDETDIR V_LNKCNTLDETDIR(1U) | 1330#define S_ENTERL23 3 1331#define V_ENTERL23(x) ((x) << S_ENTERL23) 1332#define F_ENTERL23 V_ENTERL23(1U) |
| 983 | 1333 |
| 984#define S_ENTERL1REN 29 985#define V_ENTERL1REN(x) ((x) << S_ENTERL1REN) 986#define F_ENTERL1REN V_ENTERL1REN(1U) 987 | |
| 988#define A_PCIE_PEX_ERR 0xa4 989 | 1334#define A_PCIE_PEX_ERR 0xa4 1335 |
| 1336#define S_CPLTIMEOUTID 18 1337#define M_CPLTIMEOUTID 0x7f 1338#define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID) 1339#define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID) 1340 |
|
| 990#define S_FLOWCTLOFLOWERR 17 991#define V_FLOWCTLOFLOWERR(x) ((x) << S_FLOWCTLOFLOWERR) 992#define F_FLOWCTLOFLOWERR V_FLOWCTLOFLOWERR(1U) 993 994#define S_REPLAYTIMEOUT 16 995#define V_REPLAYTIMEOUT(x) ((x) << S_REPLAYTIMEOUT) 996#define F_REPLAYTIMEOUT V_REPLAYTIMEOUT(1U) 997 --- 56 unchanged lines hidden (view full) --- 1054#define S_CPLABT 1 1055#define V_CPLABT(x) ((x) << S_CPLABT) 1056#define F_CPLABT V_CPLABT(1U) 1057 1058#define S_PSNCPL 0 1059#define V_PSNCPL(x) ((x) << S_PSNCPL) 1060#define F_PSNCPL V_PSNCPL(1U) 1061 | 1341#define S_FLOWCTLOFLOWERR 17 1342#define V_FLOWCTLOFLOWERR(x) ((x) << S_FLOWCTLOFLOWERR) 1343#define F_FLOWCTLOFLOWERR V_FLOWCTLOFLOWERR(1U) 1344 1345#define S_REPLAYTIMEOUT 16 1346#define V_REPLAYTIMEOUT(x) ((x) << S_REPLAYTIMEOUT) 1347#define F_REPLAYTIMEOUT V_REPLAYTIMEOUT(1U) 1348 --- 56 unchanged lines hidden (view full) --- 1405#define S_CPLABT 1 1406#define V_CPLABT(x) ((x) << S_CPLABT) 1407#define F_CPLABT V_CPLABT(1U) 1408 1409#define S_PSNCPL 0 1410#define V_PSNCPL(x) ((x) << S_PSNCPL) 1411#define F_PSNCPL V_PSNCPL(1U) 1412 |
| 1062#define S_CPLTIMEOUTID 18 1063#define M_CPLTIMEOUTID 0x7f 1064#define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID) 1065#define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID) | 1413#define A_PCIE_SERDES_CTRL 0xa8 |
| 1066 | 1414 |
| 1415#define S_PMASEL 3 1416#define V_PMASEL(x) ((x) << S_PMASEL) 1417#define F_PMASEL V_PMASEL(1U) 1418 1419#define S_LANE 0 1420#define M_LANE 0x7 1421#define V_LANE(x) ((x) << S_LANE) 1422#define G_LANE(x) (((x) >> S_LANE) & M_LANE) 1423 |
|
| 1067#define A_PCIE_PIPE_CTRL 0xa8 1068 1069#define S_RECDETUSEC 19 1070#define M_RECDETUSEC 0x7 1071#define V_RECDETUSEC(x) ((x) << S_RECDETUSEC) 1072#define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC) 1073 1074#define S_PLLLCKCYC 6 --- 13 unchanged lines hidden (view full) --- 1088#define S_PCLKREQINP1 1 1089#define V_PCLKREQINP1(x) ((x) << S_PCLKREQINP1) 1090#define F_PCLKREQINP1 V_PCLKREQINP1(1U) 1091 1092#define S_PCLKOFFINP1 0 1093#define V_PCLKOFFINP1(x) ((x) << S_PCLKOFFINP1) 1094#define F_PCLKOFFINP1 V_PCLKOFFINP1(1U) 1095 | 1424#define A_PCIE_PIPE_CTRL 0xa8 1425 1426#define S_RECDETUSEC 19 1427#define M_RECDETUSEC 0x7 1428#define V_RECDETUSEC(x) ((x) << S_RECDETUSEC) 1429#define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC) 1430 1431#define S_PLLLCKCYC 6 --- 13 unchanged lines hidden (view full) --- 1445#define S_PCLKREQINP1 1 1446#define V_PCLKREQINP1(x) ((x) << S_PCLKREQINP1) 1447#define F_PCLKREQINP1 V_PCLKREQINP1(1U) 1448 1449#define S_PCLKOFFINP1 0 1450#define V_PCLKOFFINP1(x) ((x) << S_PCLKOFFINP1) 1451#define F_PCLKOFFINP1 V_PCLKOFFINP1(1U) 1452 |
| 1096#define S_PMASEL 3 1097#define V_PMASEL(x) ((x) << S_PMASEL) 1098#define F_PMASEL V_PMASEL(1U) | 1453#define A_PCIE_SERDES_QUAD_CTRL0 0xac |
| 1099 | 1454 |
| 1100#define S_LANE 0 1101#define M_LANE 0x7 1102#define V_LANE(x) ((x) << S_LANE) 1103#define G_LANE(x) (((x) >> S_LANE) & M_LANE) | 1455#define S_TESTSIG 10 1456#define M_TESTSIG 0x7ffff 1457#define V_TESTSIG(x) ((x) << S_TESTSIG) 1458#define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG) |
| 1104 | 1459 |
| 1105#define A_PCIE_SERDES_CTRL 0xac | 1460#define S_OFFSET 2 1461#define M_OFFSET 0xff 1462#define V_OFFSET(x) ((x) << S_OFFSET) 1463#define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET) |
| 1106 | 1464 |
| 1465#define S_OFFSETEN 1 1466#define V_OFFSETEN(x) ((x) << S_OFFSETEN) 1467#define F_OFFSETEN V_OFFSETEN(1U) 1468 1469#define S_IDDQB 0 1470#define V_IDDQB(x) ((x) << S_IDDQB) 1471#define F_IDDQB V_IDDQB(1U) 1472 |
|
| 1107#define S_MANMODE 31 1108#define V_MANMODE(x) ((x) << S_MANMODE) 1109#define F_MANMODE V_MANMODE(1U) 1110 1111#define S_MANLPBKEN 29 1112#define M_MANLPBKEN 0x3 1113#define V_MANLPBKEN(x) ((x) << S_MANLPBKEN) 1114#define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN) --- 73 unchanged lines hidden (view full) --- 1188#define V_RXCOMADJ(x) ((x) << S_RXCOMADJ) 1189#define F_RXCOMADJ V_RXCOMADJ(1U) 1190 1191#define S_PREEMPH 0 1192#define M_PREEMPH 0x3 1193#define V_PREEMPH(x) ((x) << S_PREEMPH) 1194#define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH) 1195 | 1473#define S_MANMODE 31 1474#define V_MANMODE(x) ((x) << S_MANMODE) 1475#define F_MANMODE V_MANMODE(1U) 1476 1477#define S_MANLPBKEN 29 1478#define M_MANLPBKEN 0x3 1479#define V_MANLPBKEN(x) ((x) << S_MANLPBKEN) 1480#define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN) --- 73 unchanged lines hidden (view full) --- 1554#define V_RXCOMADJ(x) ((x) << S_RXCOMADJ) 1555#define F_RXCOMADJ V_RXCOMADJ(1U) 1556 1557#define S_PREEMPH 0 1558#define M_PREEMPH 0x3 1559#define V_PREEMPH(x) ((x) << S_PREEMPH) 1560#define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH) 1561 |
| 1196#define A_PCIE_SERDES_QUAD_CTRL0 0xac 1197 1198#define S_TESTSIG 10 1199#define M_TESTSIG 0x7ffff 1200#define V_TESTSIG(x) ((x) << S_TESTSIG) 1201#define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG) 1202 1203#define S_OFFSET 2 1204#define M_OFFSET 0xff 1205#define V_OFFSET(x) ((x) << S_OFFSET) 1206#define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET) 1207 1208#define S_OFFSETEN 1 1209#define V_OFFSETEN(x) ((x) << S_OFFSETEN) 1210#define F_OFFSETEN V_OFFSETEN(1U) 1211 1212#define S_IDDQB 0 1213#define V_IDDQB(x) ((x) << S_IDDQB) 1214#define F_IDDQB V_IDDQB(1U) 1215 1216#define A_PCIE_SERDES_STATUS0 0xb0 1217 1218#define S_RXERRLANE7 21 1219#define M_RXERRLANE7 0x7 1220#define V_RXERRLANE7(x) ((x) << S_RXERRLANE7) 1221#define G_RXERRLANE7(x) (((x) >> S_RXERRLANE7) & M_RXERRLANE7) 1222 1223#define S_RXERRLANE6 18 1224#define M_RXERRLANE6 0x7 1225#define V_RXERRLANE6(x) ((x) << S_RXERRLANE6) 1226#define G_RXERRLANE6(x) (((x) >> S_RXERRLANE6) & M_RXERRLANE6) 1227 1228#define S_RXERRLANE5 15 1229#define M_RXERRLANE5 0x7 1230#define V_RXERRLANE5(x) ((x) << S_RXERRLANE5) 1231#define G_RXERRLANE5(x) (((x) >> S_RXERRLANE5) & M_RXERRLANE5) 1232 1233#define S_RXERRLANE4 12 1234#define M_RXERRLANE4 0x7 1235#define V_RXERRLANE4(x) ((x) << S_RXERRLANE4) 1236#define G_RXERRLANE4(x) (((x) >> S_RXERRLANE4) & M_RXERRLANE4) 1237 1238#define S_PCIE_RXERRLANE3 9 1239#define M_PCIE_RXERRLANE3 0x7 1240#define V_PCIE_RXERRLANE3(x) ((x) << S_PCIE_RXERRLANE3) 1241#define G_PCIE_RXERRLANE3(x) (((x) >> S_PCIE_RXERRLANE3) & M_PCIE_RXERRLANE3) 1242 1243#define S_PCIE_RXERRLANE2 6 1244#define M_PCIE_RXERRLANE2 0x7 1245#define V_PCIE_RXERRLANE2(x) ((x) << S_PCIE_RXERRLANE2) 1246#define G_PCIE_RXERRLANE2(x) (((x) >> S_PCIE_RXERRLANE2) & M_PCIE_RXERRLANE2) 1247 1248#define S_PCIE_RXERRLANE1 3 1249#define M_PCIE_RXERRLANE1 0x7 1250#define V_PCIE_RXERRLANE1(x) ((x) << S_PCIE_RXERRLANE1) 1251#define G_PCIE_RXERRLANE1(x) (((x) >> S_PCIE_RXERRLANE1) & M_PCIE_RXERRLANE1) 1252 1253#define S_PCIE_RXERRLANE0 0 1254#define M_PCIE_RXERRLANE0 0x7 1255#define V_PCIE_RXERRLANE0(x) ((x) << S_PCIE_RXERRLANE0) 1256#define G_PCIE_RXERRLANE0(x) (((x) >> S_PCIE_RXERRLANE0) & M_PCIE_RXERRLANE0) 1257 | |
| 1258#define A_PCIE_SERDES_QUAD_CTRL1 0xb0 1259 1260#define S_FASTINIT 28 1261#define V_FASTINIT(x) ((x) << S_FASTINIT) 1262#define F_FASTINIT V_FASTINIT(1U) 1263 1264#define S_CTCDISABLE 27 1265#define V_CTCDISABLE(x) ((x) << S_CTCDISABLE) --- 68 unchanged lines hidden (view full) --- 1334#define S_PW 1 1335#define V_PW(x) ((x) << S_PW) 1336#define F_PW V_PW(1U) 1337 1338#define S_PCLKDETECT 0 1339#define V_PCLKDETECT(x) ((x) << S_PCLKDETECT) 1340#define F_PCLKDETECT V_PCLKDETECT(1U) 1341 | 1562#define A_PCIE_SERDES_QUAD_CTRL1 0xb0 1563 1564#define S_FASTINIT 28 1565#define V_FASTINIT(x) ((x) << S_FASTINIT) 1566#define F_FASTINIT V_FASTINIT(1U) 1567 1568#define S_CTCDISABLE 27 1569#define V_CTCDISABLE(x) ((x) << S_CTCDISABLE) --- 68 unchanged lines hidden (view full) --- 1638#define S_PW 1 1639#define V_PW(x) ((x) << S_PW) 1640#define F_PW V_PW(1U) 1641 1642#define S_PCLKDETECT 0 1643#define V_PCLKDETECT(x) ((x) << S_PCLKDETECT) 1644#define F_PCLKDETECT V_PCLKDETECT(1U) 1645 |
| 1646#define A_PCIE_SERDES_STATUS0 0xb0 1647 1648#define S_RXERRLANE7 21 1649#define M_RXERRLANE7 0x7 1650#define V_RXERRLANE7(x) ((x) << S_RXERRLANE7) 1651#define G_RXERRLANE7(x) (((x) >> S_RXERRLANE7) & M_RXERRLANE7) 1652 1653#define S_RXERRLANE6 18 1654#define M_RXERRLANE6 0x7 1655#define V_RXERRLANE6(x) ((x) << S_RXERRLANE6) 1656#define G_RXERRLANE6(x) (((x) >> S_RXERRLANE6) & M_RXERRLANE6) 1657 1658#define S_RXERRLANE5 15 1659#define M_RXERRLANE5 0x7 1660#define V_RXERRLANE5(x) ((x) << S_RXERRLANE5) 1661#define G_RXERRLANE5(x) (((x) >> S_RXERRLANE5) & M_RXERRLANE5) 1662 1663#define S_RXERRLANE4 12 1664#define M_RXERRLANE4 0x7 1665#define V_RXERRLANE4(x) ((x) << S_RXERRLANE4) 1666#define G_RXERRLANE4(x) (((x) >> S_RXERRLANE4) & M_RXERRLANE4) 1667 1668#define S_PCIE_RXERRLANE3 9 1669#define M_PCIE_RXERRLANE3 0x7 1670#define V_PCIE_RXERRLANE3(x) ((x) << S_PCIE_RXERRLANE3) 1671#define G_PCIE_RXERRLANE3(x) (((x) >> S_PCIE_RXERRLANE3) & M_PCIE_RXERRLANE3) 1672 1673#define S_PCIE_RXERRLANE2 6 1674#define M_PCIE_RXERRLANE2 0x7 1675#define V_PCIE_RXERRLANE2(x) ((x) << S_PCIE_RXERRLANE2) 1676#define G_PCIE_RXERRLANE2(x) (((x) >> S_PCIE_RXERRLANE2) & M_PCIE_RXERRLANE2) 1677 1678#define S_PCIE_RXERRLANE1 3 1679#define M_PCIE_RXERRLANE1 0x7 1680#define V_PCIE_RXERRLANE1(x) ((x) << S_PCIE_RXERRLANE1) 1681#define G_PCIE_RXERRLANE1(x) (((x) >> S_PCIE_RXERRLANE1) & M_PCIE_RXERRLANE1) 1682 1683#define S_PCIE_RXERRLANE0 0 1684#define M_PCIE_RXERRLANE0 0x7 1685#define V_PCIE_RXERRLANE0(x) ((x) << S_PCIE_RXERRLANE0) 1686#define G_PCIE_RXERRLANE0(x) (((x) >> S_PCIE_RXERRLANE0) & M_PCIE_RXERRLANE0) 1687 1688#define A_PCIE_SERDES_LANE_CTRL 0xb4 1689 1690#define S_EXTBISTCHKERRCLR 22 1691#define V_EXTBISTCHKERRCLR(x) ((x) << S_EXTBISTCHKERRCLR) 1692#define F_EXTBISTCHKERRCLR V_EXTBISTCHKERRCLR(1U) 1693 1694#define S_EXTBISTCHKEN 21 1695#define V_EXTBISTCHKEN(x) ((x) << S_EXTBISTCHKEN) 1696#define F_EXTBISTCHKEN V_EXTBISTCHKEN(1U) 1697 1698#define S_EXTBISTGENEN 20 1699#define V_EXTBISTGENEN(x) ((x) << S_EXTBISTGENEN) 1700#define F_EXTBISTGENEN V_EXTBISTGENEN(1U) 1701 1702#define S_EXTBISTPAT 17 1703#define M_EXTBISTPAT 0x7 1704#define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT) 1705#define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT) 1706 1707#define S_EXTPARRESET 16 1708#define V_EXTPARRESET(x) ((x) << S_EXTPARRESET) 1709#define F_EXTPARRESET V_EXTPARRESET(1U) 1710 1711#define S_EXTPARLPBK 15 1712#define V_EXTPARLPBK(x) ((x) << S_EXTPARLPBK) 1713#define F_EXTPARLPBK V_EXTPARLPBK(1U) 1714 1715#define S_MANRXTERMEN 14 1716#define V_MANRXTERMEN(x) ((x) << S_MANRXTERMEN) 1717#define F_MANRXTERMEN V_MANRXTERMEN(1U) 1718 1719#define S_MANBEACONTXEN 13 1720#define V_MANBEACONTXEN(x) ((x) << S_MANBEACONTXEN) 1721#define F_MANBEACONTXEN V_MANBEACONTXEN(1U) 1722 1723#define S_MANRXDETECTEN 12 1724#define V_MANRXDETECTEN(x) ((x) << S_MANRXDETECTEN) 1725#define F_MANRXDETECTEN V_MANRXDETECTEN(1U) 1726 1727#define S_MANTXIDLEEN 11 1728#define V_MANTXIDLEEN(x) ((x) << S_MANTXIDLEEN) 1729#define F_MANTXIDLEEN V_MANTXIDLEEN(1U) 1730 1731#define S_MANRXIDLEEN 10 1732#define V_MANRXIDLEEN(x) ((x) << S_MANRXIDLEEN) 1733#define F_MANRXIDLEEN V_MANRXIDLEEN(1U) 1734 1735#define S_MANL1PWRDN 9 1736#define V_MANL1PWRDN(x) ((x) << S_MANL1PWRDN) 1737#define F_MANL1PWRDN V_MANL1PWRDN(1U) 1738 1739#define S_MANRESET 8 1740#define V_MANRESET(x) ((x) << S_MANRESET) 1741#define F_MANRESET V_MANRESET(1U) 1742 1743#define S_MANFMOFFSET 3 1744#define M_MANFMOFFSET 0x1f 1745#define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET) 1746#define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET) 1747 1748#define S_MANFMOFFSETEN 2 1749#define V_MANFMOFFSETEN(x) ((x) << S_MANFMOFFSETEN) 1750#define F_MANFMOFFSETEN V_MANFMOFFSETEN(1U) 1751 1752#define S_MANLANEEN 1 1753#define V_MANLANEEN(x) ((x) << S_MANLANEEN) 1754#define F_MANLANEEN V_MANLANEEN(1U) 1755 1756#define S_INTSERLPBK 0 1757#define V_INTSERLPBK(x) ((x) << S_INTSERLPBK) 1758#define F_INTSERLPBK V_INTSERLPBK(1U) 1759 |
|
| 1342#define A_PCIE_SERDES_STATUS1 0xb4 1343 1344#define S_CMULOCK 31 1345#define V_CMULOCK(x) ((x) << S_CMULOCK) 1346#define F_CMULOCK V_CMULOCK(1U) 1347 1348#define S_RXKLOCKLANE7 23 1349#define V_RXKLOCKLANE7(x) ((x) << S_RXKLOCKLANE7) --- 86 unchanged lines hidden (view full) --- 1436#define S_PCIE_RXOFLOWLANE1 1 1437#define V_PCIE_RXOFLOWLANE1(x) ((x) << S_PCIE_RXOFLOWLANE1) 1438#define F_PCIE_RXOFLOWLANE1 V_PCIE_RXOFLOWLANE1(1U) 1439 1440#define S_PCIE_RXOFLOWLANE0 0 1441#define V_PCIE_RXOFLOWLANE0(x) ((x) << S_PCIE_RXOFLOWLANE0) 1442#define F_PCIE_RXOFLOWLANE0 V_PCIE_RXOFLOWLANE0(1U) 1443 | 1760#define A_PCIE_SERDES_STATUS1 0xb4 1761 1762#define S_CMULOCK 31 1763#define V_CMULOCK(x) ((x) << S_CMULOCK) 1764#define F_CMULOCK V_CMULOCK(1U) 1765 1766#define S_RXKLOCKLANE7 23 1767#define V_RXKLOCKLANE7(x) ((x) << S_RXKLOCKLANE7) --- 86 unchanged lines hidden (view full) --- 1854#define S_PCIE_RXOFLOWLANE1 1 1855#define V_PCIE_RXOFLOWLANE1(x) ((x) << S_PCIE_RXOFLOWLANE1) 1856#define F_PCIE_RXOFLOWLANE1 V_PCIE_RXOFLOWLANE1(1U) 1857 1858#define S_PCIE_RXOFLOWLANE0 0 1859#define V_PCIE_RXOFLOWLANE0(x) ((x) << S_PCIE_RXOFLOWLANE0) 1860#define F_PCIE_RXOFLOWLANE0 V_PCIE_RXOFLOWLANE0(1U) 1861 |
| 1444#define A_PCIE_SERDES_LANE_CTRL 0xb4 | 1862#define A_PCIE_SERDES_LANE_STAT 0xb8 |
| 1445 | 1863 |
| 1446#define S_EXTBISTCHKERRCLR 22 1447#define V_EXTBISTCHKERRCLR(x) ((x) << S_EXTBISTCHKERRCLR) 1448#define F_EXTBISTCHKERRCLR V_EXTBISTCHKERRCLR(1U) | 1864#define S_EXTBISTCHKERRCNT 8 1865#define M_EXTBISTCHKERRCNT 0xffffff 1866#define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT) 1867#define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT) |
| 1449 | 1868 |
| 1450#define S_EXTBISTCHKEN 21 1451#define V_EXTBISTCHKEN(x) ((x) << S_EXTBISTCHKEN) 1452#define F_EXTBISTCHKEN V_EXTBISTCHKEN(1U) | 1869#define S_EXTBISTCHKFMD 7 1870#define V_EXTBISTCHKFMD(x) ((x) << S_EXTBISTCHKFMD) 1871#define F_EXTBISTCHKFMD V_EXTBISTCHKFMD(1U) |
| 1453 | 1872 |
| 1454#define S_EXTBISTGENEN 20 1455#define V_EXTBISTGENEN(x) ((x) << S_EXTBISTGENEN) 1456#define F_EXTBISTGENEN V_EXTBISTGENEN(1U) | 1873#define S_BEACONDETECTCHG 6 1874#define V_BEACONDETECTCHG(x) ((x) << S_BEACONDETECTCHG) 1875#define F_BEACONDETECTCHG V_BEACONDETECTCHG(1U) |
| 1457 | 1876 |
| 1458#define S_EXTBISTPAT 17 1459#define M_EXTBISTPAT 0x7 1460#define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT) 1461#define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT) | 1877#define S_RXDETECTCHG 5 1878#define V_RXDETECTCHG(x) ((x) << S_RXDETECTCHG) 1879#define F_RXDETECTCHG V_RXDETECTCHG(1U) |
| 1462 | 1880 |
| 1463#define S_EXTPARRESET 16 1464#define V_EXTPARRESET(x) ((x) << S_EXTPARRESET) 1465#define F_EXTPARRESET V_EXTPARRESET(1U) | 1881#define S_TXIDLEDETECTCHG 4 1882#define V_TXIDLEDETECTCHG(x) ((x) << S_TXIDLEDETECTCHG) 1883#define F_TXIDLEDETECTCHG V_TXIDLEDETECTCHG(1U) |
| 1466 | 1884 |
| 1467#define S_EXTPARLPBK 15 1468#define V_EXTPARLPBK(x) ((x) << S_EXTPARLPBK) 1469#define F_EXTPARLPBK V_EXTPARLPBK(1U) | 1885#define S_BEACONDETECT 2 1886#define V_BEACONDETECT(x) ((x) << S_BEACONDETECT) 1887#define F_BEACONDETECT V_BEACONDETECT(1U) |
| 1470 | 1888 |
| 1471#define S_MANRXTERMEN 14 1472#define V_MANRXTERMEN(x) ((x) << S_MANRXTERMEN) 1473#define F_MANRXTERMEN V_MANRXTERMEN(1U) | 1889#define S_RXDETECT 1 1890#define V_RXDETECT(x) ((x) << S_RXDETECT) 1891#define F_RXDETECT V_RXDETECT(1U) |
| 1474 | 1892 |
| 1475#define S_MANBEACONTXEN 13 1476#define V_MANBEACONTXEN(x) ((x) << S_MANBEACONTXEN) 1477#define F_MANBEACONTXEN V_MANBEACONTXEN(1U) | 1893#define S_TXIDLEDETECT 0 1894#define V_TXIDLEDETECT(x) ((x) << S_TXIDLEDETECT) 1895#define F_TXIDLEDETECT V_TXIDLEDETECT(1U) |
| 1478 | 1896 |
| 1479#define S_MANRXDETECTEN 12 1480#define V_MANRXDETECTEN(x) ((x) << S_MANRXDETECTEN) 1481#define F_MANRXDETECTEN V_MANRXDETECTEN(1U) 1482 1483#define S_MANTXIDLEEN 11 1484#define V_MANTXIDLEEN(x) ((x) << S_MANTXIDLEEN) 1485#define F_MANTXIDLEEN V_MANTXIDLEEN(1U) 1486 1487#define S_MANRXIDLEEN 10 1488#define V_MANRXIDLEEN(x) ((x) << S_MANRXIDLEEN) 1489#define F_MANRXIDLEEN V_MANRXIDLEEN(1U) 1490 1491#define S_MANL1PWRDN 9 1492#define V_MANL1PWRDN(x) ((x) << S_MANL1PWRDN) 1493#define F_MANL1PWRDN V_MANL1PWRDN(1U) 1494 1495#define S_MANRESET 8 1496#define V_MANRESET(x) ((x) << S_MANRESET) 1497#define F_MANRESET V_MANRESET(1U) 1498 1499#define S_MANFMOFFSET 3 1500#define M_MANFMOFFSET 0x1f 1501#define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET) 1502#define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET) 1503 1504#define S_MANFMOFFSETEN 2 1505#define V_MANFMOFFSETEN(x) ((x) << S_MANFMOFFSETEN) 1506#define F_MANFMOFFSETEN V_MANFMOFFSETEN(1U) 1507 1508#define S_MANLANEEN 1 1509#define V_MANLANEEN(x) ((x) << S_MANLANEEN) 1510#define F_MANLANEEN V_MANLANEEN(1U) 1511 1512#define S_INTSERLPBK 0 1513#define V_INTSERLPBK(x) ((x) << S_INTSERLPBK) 1514#define F_INTSERLPBK V_INTSERLPBK(1U) 1515 | |
| 1516#define A_PCIE_SERDES_STATUS2 0xb8 1517 1518#define S_TXRECDETLANE7 31 1519#define V_TXRECDETLANE7(x) ((x) << S_TXRECDETLANE7) 1520#define F_TXRECDETLANE7 V_TXRECDETLANE7(1U) 1521 1522#define S_TXRECDETLANE6 30 1523#define V_TXRECDETLANE6(x) ((x) << S_TXRECDETLANE6) --- 114 unchanged lines hidden (view full) --- 1638#define S_PCIE_RXADDSKIPLANE1 1 1639#define V_PCIE_RXADDSKIPLANE1(x) ((x) << S_PCIE_RXADDSKIPLANE1) 1640#define F_PCIE_RXADDSKIPLANE1 V_PCIE_RXADDSKIPLANE1(1U) 1641 1642#define S_PCIE_RXADDSKIPLANE0 0 1643#define V_PCIE_RXADDSKIPLANE0(x) ((x) << S_PCIE_RXADDSKIPLANE0) 1644#define F_PCIE_RXADDSKIPLANE0 V_PCIE_RXADDSKIPLANE0(1U) 1645 | 1897#define A_PCIE_SERDES_STATUS2 0xb8 1898 1899#define S_TXRECDETLANE7 31 1900#define V_TXRECDETLANE7(x) ((x) << S_TXRECDETLANE7) 1901#define F_TXRECDETLANE7 V_TXRECDETLANE7(1U) 1902 1903#define S_TXRECDETLANE6 30 1904#define V_TXRECDETLANE6(x) ((x) << S_TXRECDETLANE6) --- 114 unchanged lines hidden (view full) --- 2019#define S_PCIE_RXADDSKIPLANE1 1 2020#define V_PCIE_RXADDSKIPLANE1(x) ((x) << S_PCIE_RXADDSKIPLANE1) 2021#define F_PCIE_RXADDSKIPLANE1 V_PCIE_RXADDSKIPLANE1(1U) 2022 2023#define S_PCIE_RXADDSKIPLANE0 0 2024#define V_PCIE_RXADDSKIPLANE0(x) ((x) << S_PCIE_RXADDSKIPLANE0) 2025#define F_PCIE_RXADDSKIPLANE0 V_PCIE_RXADDSKIPLANE0(1U) 2026 |
| 1646#define A_PCIE_SERDES_LANE_STAT 0xb8 | 2027#define A_PCIE_PEX_WMARK 0xbc |
| 1647 | 2028 |
| 1648#define S_EXTBISTCHKERRCNT 8 1649#define M_EXTBISTCHKERRCNT 0xffffff 1650#define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT) 1651#define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT) | 2029#define S_P_WMARK 18 2030#define M_P_WMARK 0x7ff 2031#define V_P_WMARK(x) ((x) << S_P_WMARK) 2032#define G_P_WMARK(x) (((x) >> S_P_WMARK) & M_P_WMARK) |
| 1652 | 2033 |
| 1653#define S_EXTBISTCHKFMD 7 1654#define V_EXTBISTCHKFMD(x) ((x) << S_EXTBISTCHKFMD) 1655#define F_EXTBISTCHKFMD V_EXTBISTCHKFMD(1U) | 2034#define S_NP_WMARK 11 2035#define M_NP_WMARK 0x7f 2036#define V_NP_WMARK(x) ((x) << S_NP_WMARK) 2037#define G_NP_WMARK(x) (((x) >> S_NP_WMARK) & M_NP_WMARK) |
| 1656 | 2038 |
| 1657#define S_BEACONDETECTCHG 6 1658#define V_BEACONDETECTCHG(x) ((x) << S_BEACONDETECTCHG) 1659#define F_BEACONDETECTCHG V_BEACONDETECTCHG(1U) | 2039#define S_CPL_WMARK 0 2040#define M_CPL_WMARK 0x7ff 2041#define V_CPL_WMARK(x) ((x) << S_CPL_WMARK) 2042#define G_CPL_WMARK(x) (((x) >> S_CPL_WMARK) & M_CPL_WMARK) |
| 1660 | 2043 |
| 1661#define S_RXDETECTCHG 5 1662#define V_RXDETECTCHG(x) ((x) << S_RXDETECTCHG) 1663#define F_RXDETECTCHG V_RXDETECTCHG(1U) 1664 1665#define S_TXIDLEDETECTCHG 4 1666#define V_TXIDLEDETECTCHG(x) ((x) << S_TXIDLEDETECTCHG) 1667#define F_TXIDLEDETECTCHG V_TXIDLEDETECTCHG(1U) 1668 1669#define S_BEACONDETECT 2 1670#define V_BEACONDETECT(x) ((x) << S_BEACONDETECT) 1671#define F_BEACONDETECT V_BEACONDETECT(1U) 1672 1673#define S_RXDETECT 1 1674#define V_RXDETECT(x) ((x) << S_RXDETECT) 1675#define F_RXDETECT V_RXDETECT(1U) 1676 1677#define S_TXIDLEDETECT 0 1678#define V_TXIDLEDETECT(x) ((x) << S_TXIDLEDETECT) 1679#define F_TXIDLEDETECT V_TXIDLEDETECT(1U) 1680 | |
| 1681#define A_PCIE_SERDES_BIST 0xbc 1682 1683#define S_PCIE_BISTDONE 24 1684#define M_PCIE_BISTDONE 0xff 1685#define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE) 1686#define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE) 1687 1688#define S_PCIE_BISTCYCLETHRESH 3 --- 137 unchanged lines hidden (view full) --- 1826#define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U) 1827 1828#define S_GPIO0_OUT_VAL 0 1829#define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL) 1830#define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U) 1831 1832#define A_T3DBG_GPIO_IN 0xd4 1833 | 2044#define A_PCIE_SERDES_BIST 0xbc 2045 2046#define S_PCIE_BISTDONE 24 2047#define M_PCIE_BISTDONE 0xff 2048#define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE) 2049#define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE) 2050 2051#define S_PCIE_BISTCYCLETHRESH 3 --- 137 unchanged lines hidden (view full) --- 2189#define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U) 2190 2191#define S_GPIO0_OUT_VAL 0 2192#define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL) 2193#define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U) 2194 2195#define A_T3DBG_GPIO_IN 0xd4 2196 |
| 1834#define S_GPIO11_IN 11 1835#define V_GPIO11_IN(x) ((x) << S_GPIO11_IN) 1836#define F_GPIO11_IN V_GPIO11_IN(1U) 1837 1838#define S_GPIO10_IN 10 1839#define V_GPIO10_IN(x) ((x) << S_GPIO10_IN) 1840#define F_GPIO10_IN V_GPIO10_IN(1U) 1841 1842#define S_GPIO9_IN 9 1843#define V_GPIO9_IN(x) ((x) << S_GPIO9_IN) 1844#define F_GPIO9_IN V_GPIO9_IN(1U) 1845 1846#define S_GPIO8_IN 8 1847#define V_GPIO8_IN(x) ((x) << S_GPIO8_IN) 1848#define F_GPIO8_IN V_GPIO8_IN(1U) 1849 1850#define S_GPIO7_IN 7 1851#define V_GPIO7_IN(x) ((x) << S_GPIO7_IN) 1852#define F_GPIO7_IN V_GPIO7_IN(1U) 1853 1854#define S_GPIO6_IN 6 1855#define V_GPIO6_IN(x) ((x) << S_GPIO6_IN) 1856#define F_GPIO6_IN V_GPIO6_IN(1U) 1857 1858#define S_GPIO5_IN 5 1859#define V_GPIO5_IN(x) ((x) << S_GPIO5_IN) 1860#define F_GPIO5_IN V_GPIO5_IN(1U) 1861 1862#define S_GPIO4_IN 4 1863#define V_GPIO4_IN(x) ((x) << S_GPIO4_IN) 1864#define F_GPIO4_IN V_GPIO4_IN(1U) 1865 1866#define S_GPIO3_IN 3 1867#define V_GPIO3_IN(x) ((x) << S_GPIO3_IN) 1868#define F_GPIO3_IN V_GPIO3_IN(1U) 1869 1870#define S_GPIO2_IN 2 1871#define V_GPIO2_IN(x) ((x) << S_GPIO2_IN) 1872#define F_GPIO2_IN V_GPIO2_IN(1U) 1873 1874#define S_GPIO1_IN 1 1875#define V_GPIO1_IN(x) ((x) << S_GPIO1_IN) 1876#define F_GPIO1_IN V_GPIO1_IN(1U) 1877 1878#define S_GPIO0_IN 0 1879#define V_GPIO0_IN(x) ((x) << S_GPIO0_IN) 1880#define F_GPIO0_IN V_GPIO0_IN(1U) 1881 | |
| 1882#define S_GPIO11_CHG_DET 27 1883#define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET) 1884#define F_GPIO11_CHG_DET V_GPIO11_CHG_DET(1U) 1885 1886#define S_GPIO10_CHG_DET 26 1887#define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET) 1888#define F_GPIO10_CHG_DET V_GPIO10_CHG_DET(1U) 1889 --- 32 unchanged lines hidden (view full) --- 1922#define S_GPIO1_CHG_DET 17 1923#define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET) 1924#define F_GPIO1_CHG_DET V_GPIO1_CHG_DET(1U) 1925 1926#define S_GPIO0_CHG_DET 16 1927#define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET) 1928#define F_GPIO0_CHG_DET V_GPIO0_CHG_DET(1U) 1929 | 2197#define S_GPIO11_CHG_DET 27 2198#define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET) 2199#define F_GPIO11_CHG_DET V_GPIO11_CHG_DET(1U) 2200 2201#define S_GPIO10_CHG_DET 26 2202#define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET) 2203#define F_GPIO10_CHG_DET V_GPIO10_CHG_DET(1U) 2204 --- 32 unchanged lines hidden (view full) --- 2237#define S_GPIO1_CHG_DET 17 2238#define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET) 2239#define F_GPIO1_CHG_DET V_GPIO1_CHG_DET(1U) 2240 2241#define S_GPIO0_CHG_DET 16 2242#define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET) 2243#define F_GPIO0_CHG_DET V_GPIO0_CHG_DET(1U) 2244 |
| 2245#define S_GPIO11_IN 11 2246#define V_GPIO11_IN(x) ((x) << S_GPIO11_IN) 2247#define F_GPIO11_IN V_GPIO11_IN(1U) 2248 2249#define S_GPIO10_IN 10 2250#define V_GPIO10_IN(x) ((x) << S_GPIO10_IN) 2251#define F_GPIO10_IN V_GPIO10_IN(1U) 2252 2253#define S_GPIO9_IN 9 2254#define V_GPIO9_IN(x) ((x) << S_GPIO9_IN) 2255#define F_GPIO9_IN V_GPIO9_IN(1U) 2256 2257#define S_GPIO8_IN 8 2258#define V_GPIO8_IN(x) ((x) << S_GPIO8_IN) 2259#define F_GPIO8_IN V_GPIO8_IN(1U) 2260 2261#define S_GPIO7_IN 7 2262#define V_GPIO7_IN(x) ((x) << S_GPIO7_IN) 2263#define F_GPIO7_IN V_GPIO7_IN(1U) 2264 2265#define S_GPIO6_IN 6 2266#define V_GPIO6_IN(x) ((x) << S_GPIO6_IN) 2267#define F_GPIO6_IN V_GPIO6_IN(1U) 2268 2269#define S_GPIO5_IN 5 2270#define V_GPIO5_IN(x) ((x) << S_GPIO5_IN) 2271#define F_GPIO5_IN V_GPIO5_IN(1U) 2272 2273#define S_GPIO4_IN 4 2274#define V_GPIO4_IN(x) ((x) << S_GPIO4_IN) 2275#define F_GPIO4_IN V_GPIO4_IN(1U) 2276 2277#define S_GPIO3_IN 3 2278#define V_GPIO3_IN(x) ((x) << S_GPIO3_IN) 2279#define F_GPIO3_IN V_GPIO3_IN(1U) 2280 2281#define S_GPIO2_IN 2 2282#define V_GPIO2_IN(x) ((x) << S_GPIO2_IN) 2283#define F_GPIO2_IN V_GPIO2_IN(1U) 2284 2285#define S_GPIO1_IN 1 2286#define V_GPIO1_IN(x) ((x) << S_GPIO1_IN) 2287#define F_GPIO1_IN V_GPIO1_IN(1U) 2288 2289#define S_GPIO0_IN 0 2290#define V_GPIO0_IN(x) ((x) << S_GPIO0_IN) 2291#define F_GPIO0_IN V_GPIO0_IN(1U) 2292 |
|
| 1930#define A_T3DBG_INT_ENABLE 0xd8 1931 1932#define S_C_LOCK 21 1933#define V_C_LOCK(x) ((x) << S_C_LOCK) 1934#define F_C_LOCK V_C_LOCK(1U) 1935 1936#define S_M_LOCK 20 1937#define V_M_LOCK(x) ((x) << S_M_LOCK) --- 6 unchanged lines hidden (view full) --- 1944#define S_R_LOCK 18 1945#define V_R_LOCK(x) ((x) << S_R_LOCK) 1946#define F_R_LOCK V_R_LOCK(1U) 1947 1948#define S_PX_LOCK 17 1949#define V_PX_LOCK(x) ((x) << S_PX_LOCK) 1950#define F_PX_LOCK V_PX_LOCK(1U) 1951 | 2293#define A_T3DBG_INT_ENABLE 0xd8 2294 2295#define S_C_LOCK 21 2296#define V_C_LOCK(x) ((x) << S_C_LOCK) 2297#define F_C_LOCK V_C_LOCK(1U) 2298 2299#define S_M_LOCK 20 2300#define V_M_LOCK(x) ((x) << S_M_LOCK) --- 6 unchanged lines hidden (view full) --- 2307#define S_R_LOCK 18 2308#define V_R_LOCK(x) ((x) << S_R_LOCK) 2309#define F_R_LOCK V_R_LOCK(1U) 2310 2311#define S_PX_LOCK 17 2312#define V_PX_LOCK(x) ((x) << S_PX_LOCK) 2313#define F_PX_LOCK V_PX_LOCK(1U) 2314 |
| 1952#define S_PE_LOCK 16 1953#define V_PE_LOCK(x) ((x) << S_PE_LOCK) 1954#define F_PE_LOCK V_PE_LOCK(1U) 1955 | |
| 1956#define S_GPIO11 11 1957#define V_GPIO11(x) ((x) << S_GPIO11) 1958#define F_GPIO11 V_GPIO11(1U) 1959 1960#define S_GPIO10 10 1961#define V_GPIO10(x) ((x) << S_GPIO10) 1962#define F_GPIO10 V_GPIO10(1U) 1963 --- 32 unchanged lines hidden (view full) --- 1996#define S_GPIO1 1 1997#define V_GPIO1(x) ((x) << S_GPIO1) 1998#define F_GPIO1 V_GPIO1(1U) 1999 2000#define S_GPIO0 0 2001#define V_GPIO0(x) ((x) << S_GPIO0) 2002#define F_GPIO0 V_GPIO0(1U) 2003 | 2315#define S_GPIO11 11 2316#define V_GPIO11(x) ((x) << S_GPIO11) 2317#define F_GPIO11 V_GPIO11(1U) 2318 2319#define S_GPIO10 10 2320#define V_GPIO10(x) ((x) << S_GPIO10) 2321#define F_GPIO10 V_GPIO10(1U) 2322 --- 32 unchanged lines hidden (view full) --- 2355#define S_GPIO1 1 2356#define V_GPIO1(x) ((x) << S_GPIO1) 2357#define F_GPIO1 V_GPIO1(1U) 2358 2359#define S_GPIO0 0 2360#define V_GPIO0(x) ((x) << S_GPIO0) 2361#define F_GPIO0 V_GPIO0(1U) 2362 |
| 2363#define S_PE_LOCK 16 2364#define V_PE_LOCK(x) ((x) << S_PE_LOCK) 2365#define F_PE_LOCK V_PE_LOCK(1U) 2366 |
|
| 2004#define A_T3DBG_INT_CAUSE 0xdc 2005#define A_T3DBG_DBG0_RST_VALUE 0xe0 2006 2007#define S_DEBUGDATA 0 | 2367#define A_T3DBG_INT_CAUSE 0xdc 2368#define A_T3DBG_DBG0_RST_VALUE 0xe0 2369 2370#define S_DEBUGDATA 0 |
| 2371#define M_DEBUGDATA 0xff |
|
| 2008#define V_DEBUGDATA(x) ((x) << S_DEBUGDATA) | 2372#define V_DEBUGDATA(x) ((x) << S_DEBUGDATA) |
| 2009#define F_DEBUGDATA V_DEBUGDATA(1U) | 2373#define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA) |
| 2010 2011#define A_T3DBG_PLL_OCLK_PAD_EN 0xe4 2012 2013#define S_PCIE_OCLK_EN 20 2014#define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN) 2015#define F_PCIE_OCLK_EN V_PCIE_OCLK_EN(1U) 2016 | 2374 2375#define A_T3DBG_PLL_OCLK_PAD_EN 0xe4 2376 2377#define S_PCIE_OCLK_EN 20 2378#define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN) 2379#define F_PCIE_OCLK_EN V_PCIE_OCLK_EN(1U) 2380 |
| 2381#define S_PCLKTREE_DBG_EN 17 2382#define V_PCLKTREE_DBG_EN(x) ((x) << S_PCLKTREE_DBG_EN) 2383#define F_PCLKTREE_DBG_EN V_PCLKTREE_DBG_EN(1U) 2384 |
|
| 2017#define S_PCIX_OCLK_EN 16 2018#define V_PCIX_OCLK_EN(x) ((x) << S_PCIX_OCLK_EN) 2019#define F_PCIX_OCLK_EN V_PCIX_OCLK_EN(1U) 2020 2021#define S_U_OCLK_EN 12 2022#define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN) 2023#define F_U_OCLK_EN V_U_OCLK_EN(1U) 2024 --- 4 unchanged lines hidden (view full) --- 2029#define S_M_OCLK_EN 4 2030#define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN) 2031#define F_M_OCLK_EN V_M_OCLK_EN(1U) 2032 2033#define S_C_OCLK_EN 0 2034#define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN) 2035#define F_C_OCLK_EN V_C_OCLK_EN(1U) 2036 | 2385#define S_PCIX_OCLK_EN 16 2386#define V_PCIX_OCLK_EN(x) ((x) << S_PCIX_OCLK_EN) 2387#define F_PCIX_OCLK_EN V_PCIX_OCLK_EN(1U) 2388 2389#define S_U_OCLK_EN 12 2390#define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN) 2391#define F_U_OCLK_EN V_U_OCLK_EN(1U) 2392 --- 4 unchanged lines hidden (view full) --- 2397#define S_M_OCLK_EN 4 2398#define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN) 2399#define F_M_OCLK_EN V_M_OCLK_EN(1U) 2400 2401#define S_C_OCLK_EN 0 2402#define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN) 2403#define F_C_OCLK_EN V_C_OCLK_EN(1U) 2404 |
| 2037#define S_PCLKTREE_DBG_EN 17 2038#define V_PCLKTREE_DBG_EN(x) ((x) << S_PCLKTREE_DBG_EN) 2039#define F_PCLKTREE_DBG_EN V_PCLKTREE_DBG_EN(1U) 2040 | |
| 2041#define A_T3DBG_PLL_LOCK 0xe8 2042 | 2405#define A_T3DBG_PLL_LOCK 0xe8 2406 |
| 2043#define S_PCIE_LOCK 20 2044#define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK) 2045#define F_PCIE_LOCK V_PCIE_LOCK(1U) 2046 | |
| 2047#define S_PCIX_LOCK 16 2048#define V_PCIX_LOCK(x) ((x) << S_PCIX_LOCK) 2049#define F_PCIX_LOCK V_PCIX_LOCK(1U) 2050 2051#define S_PLL_U_LOCK 12 2052#define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK) 2053#define F_PLL_U_LOCK V_PLL_U_LOCK(1U) 2054 --- 4 unchanged lines hidden (view full) --- 2059#define S_PLL_M_LOCK 4 2060#define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK) 2061#define F_PLL_M_LOCK V_PLL_M_LOCK(1U) 2062 2063#define S_PLL_C_LOCK 0 2064#define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK) 2065#define F_PLL_C_LOCK V_PLL_C_LOCK(1U) 2066 | 2407#define S_PCIX_LOCK 16 2408#define V_PCIX_LOCK(x) ((x) << S_PCIX_LOCK) 2409#define F_PCIX_LOCK V_PCIX_LOCK(1U) 2410 2411#define S_PLL_U_LOCK 12 2412#define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK) 2413#define F_PLL_U_LOCK V_PLL_U_LOCK(1U) 2414 --- 4 unchanged lines hidden (view full) --- 2419#define S_PLL_M_LOCK 4 2420#define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK) 2421#define F_PLL_M_LOCK V_PLL_M_LOCK(1U) 2422 2423#define S_PLL_C_LOCK 0 2424#define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK) 2425#define F_PLL_C_LOCK V_PLL_C_LOCK(1U) 2426 |
| 2427#define S_PCIE_LOCK 20 2428#define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK) 2429#define F_PCIE_LOCK V_PCIE_LOCK(1U) 2430 |
|
| 2067#define A_T3DBG_SERDES_RBC_CFG 0xec 2068 2069#define S_X_RBC_LANE_SEL 16 | 2431#define A_T3DBG_SERDES_RBC_CFG 0xec 2432 2433#define S_X_RBC_LANE_SEL 16 |
| 2434#define M_X_RBC_LANE_SEL 0x3 |
|
| 2070#define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL) | 2435#define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL) |
| 2071#define F_X_RBC_LANE_SEL V_X_RBC_LANE_SEL(1U) | 2436#define G_X_RBC_LANE_SEL(x) (((x) >> S_X_RBC_LANE_SEL) & M_X_RBC_LANE_SEL) |
| 2072 2073#define S_X_RBC_DBG_EN 12 2074#define V_X_RBC_DBG_EN(x) ((x) << S_X_RBC_DBG_EN) 2075#define F_X_RBC_DBG_EN V_X_RBC_DBG_EN(1U) 2076 2077#define S_X_SERDES_SEL 8 2078#define V_X_SERDES_SEL(x) ((x) << S_X_SERDES_SEL) 2079#define F_X_SERDES_SEL V_X_SERDES_SEL(1U) 2080 2081#define S_PE_RBC_LANE_SEL 4 | 2437 2438#define S_X_RBC_DBG_EN 12 2439#define V_X_RBC_DBG_EN(x) ((x) << S_X_RBC_DBG_EN) 2440#define F_X_RBC_DBG_EN V_X_RBC_DBG_EN(1U) 2441 2442#define S_X_SERDES_SEL 8 2443#define V_X_SERDES_SEL(x) ((x) << S_X_SERDES_SEL) 2444#define F_X_SERDES_SEL V_X_SERDES_SEL(1U) 2445 2446#define S_PE_RBC_LANE_SEL 4 |
| 2447#define M_PE_RBC_LANE_SEL 0x7 |
|
| 2082#define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL) | 2448#define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL) |
| 2083#define F_PE_RBC_LANE_SEL V_PE_RBC_LANE_SEL(1U) | 2449#define G_PE_RBC_LANE_SEL(x) (((x) >> S_PE_RBC_LANE_SEL) & M_PE_RBC_LANE_SEL) |
| 2084 2085#define S_PE_RBC_DBG_EN 0 2086#define V_PE_RBC_DBG_EN(x) ((x) << S_PE_RBC_DBG_EN) 2087#define F_PE_RBC_DBG_EN V_PE_RBC_DBG_EN(1U) 2088 2089#define A_T3DBG_GPIO_ACT_LOW 0xf0 2090 2091#define S_C_LOCK_ACT_LOW 21 --- 11 unchanged lines hidden (view full) --- 2103#define S_R_LOCK_ACT_LOW 18 2104#define V_R_LOCK_ACT_LOW(x) ((x) << S_R_LOCK_ACT_LOW) 2105#define F_R_LOCK_ACT_LOW V_R_LOCK_ACT_LOW(1U) 2106 2107#define S_PX_LOCK_ACT_LOW 17 2108#define V_PX_LOCK_ACT_LOW(x) ((x) << S_PX_LOCK_ACT_LOW) 2109#define F_PX_LOCK_ACT_LOW V_PX_LOCK_ACT_LOW(1U) 2110 | 2450 2451#define S_PE_RBC_DBG_EN 0 2452#define V_PE_RBC_DBG_EN(x) ((x) << S_PE_RBC_DBG_EN) 2453#define F_PE_RBC_DBG_EN V_PE_RBC_DBG_EN(1U) 2454 2455#define A_T3DBG_GPIO_ACT_LOW 0xf0 2456 2457#define S_C_LOCK_ACT_LOW 21 --- 11 unchanged lines hidden (view full) --- 2469#define S_R_LOCK_ACT_LOW 18 2470#define V_R_LOCK_ACT_LOW(x) ((x) << S_R_LOCK_ACT_LOW) 2471#define F_R_LOCK_ACT_LOW V_R_LOCK_ACT_LOW(1U) 2472 2473#define S_PX_LOCK_ACT_LOW 17 2474#define V_PX_LOCK_ACT_LOW(x) ((x) << S_PX_LOCK_ACT_LOW) 2475#define F_PX_LOCK_ACT_LOW V_PX_LOCK_ACT_LOW(1U) 2476 |
| 2111#define S_PE_LOCK_ACT_LOW 16 2112#define V_PE_LOCK_ACT_LOW(x) ((x) << S_PE_LOCK_ACT_LOW) 2113#define F_PE_LOCK_ACT_LOW V_PE_LOCK_ACT_LOW(1U) 2114 | |
| 2115#define S_GPIO11_ACT_LOW 11 2116#define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW) 2117#define F_GPIO11_ACT_LOW V_GPIO11_ACT_LOW(1U) 2118 2119#define S_GPIO10_ACT_LOW 10 2120#define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW) 2121#define F_GPIO10_ACT_LOW V_GPIO10_ACT_LOW(1U) 2122 --- 32 unchanged lines hidden (view full) --- 2155#define S_GPIO1_ACT_LOW 1 2156#define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW) 2157#define F_GPIO1_ACT_LOW V_GPIO1_ACT_LOW(1U) 2158 2159#define S_GPIO0_ACT_LOW 0 2160#define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW) 2161#define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U) 2162 | 2477#define S_GPIO11_ACT_LOW 11 2478#define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW) 2479#define F_GPIO11_ACT_LOW V_GPIO11_ACT_LOW(1U) 2480 2481#define S_GPIO10_ACT_LOW 10 2482#define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW) 2483#define F_GPIO10_ACT_LOW V_GPIO10_ACT_LOW(1U) 2484 --- 32 unchanged lines hidden (view full) --- 2517#define S_GPIO1_ACT_LOW 1 2518#define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW) 2519#define F_GPIO1_ACT_LOW V_GPIO1_ACT_LOW(1U) 2520 2521#define S_GPIO0_ACT_LOW 0 2522#define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW) 2523#define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U) 2524 |
| 2525#define S_PE_LOCK_ACT_LOW 16 2526#define V_PE_LOCK_ACT_LOW(x) ((x) << S_PE_LOCK_ACT_LOW) 2527#define F_PE_LOCK_ACT_LOW V_PE_LOCK_ACT_LOW(1U) 2528 |
|
| 2163#define A_T3DBG_PMON_CFG 0xf4 2164 2165#define S_PMON_DONE 29 2166#define V_PMON_DONE(x) ((x) << S_PMON_DONE) 2167#define F_PMON_DONE V_PMON_DONE(1U) 2168 2169#define S_PMON_FAIL 28 2170#define V_PMON_FAIL(x) ((x) << S_PMON_FAIL) 2171#define F_PMON_FAIL V_PMON_FAIL(1U) 2172 2173#define S_PMON_FDEL_AUTO 22 | 2529#define A_T3DBG_PMON_CFG 0xf4 2530 2531#define S_PMON_DONE 29 2532#define V_PMON_DONE(x) ((x) << S_PMON_DONE) 2533#define F_PMON_DONE V_PMON_DONE(1U) 2534 2535#define S_PMON_FAIL 28 2536#define V_PMON_FAIL(x) ((x) << S_PMON_FAIL) 2537#define F_PMON_FAIL V_PMON_FAIL(1U) 2538 2539#define S_PMON_FDEL_AUTO 22 |
| 2540#define M_PMON_FDEL_AUTO 0x3f |
|
| 2174#define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO) | 2541#define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO) |
| 2175#define F_PMON_FDEL_AUTO V_PMON_FDEL_AUTO(1U) | 2542#define G_PMON_FDEL_AUTO(x) (((x) >> S_PMON_FDEL_AUTO) & M_PMON_FDEL_AUTO) |
| 2176 2177#define S_PMON_CDEL_AUTO 16 | 2543 2544#define S_PMON_CDEL_AUTO 16 |
| 2545#define M_PMON_CDEL_AUTO 0x3f |
|
| 2178#define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO) | 2546#define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO) |
| 2179#define F_PMON_CDEL_AUTO V_PMON_CDEL_AUTO(1U) | 2547#define G_PMON_CDEL_AUTO(x) (((x) >> S_PMON_CDEL_AUTO) & M_PMON_CDEL_AUTO) |
| 2180 2181#define S_PMON_FDEL_MANUAL 10 | 2548 2549#define S_PMON_FDEL_MANUAL 10 |
| 2550#define M_PMON_FDEL_MANUAL 0x3f |
|
| 2182#define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL) | 2551#define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL) |
| 2183#define F_PMON_FDEL_MANUAL V_PMON_FDEL_MANUAL(1U) | 2552#define G_PMON_FDEL_MANUAL(x) (((x) >> S_PMON_FDEL_MANUAL) & M_PMON_FDEL_MANUAL) |
| 2184 2185#define S_PMON_CDEL_MANUAL 4 | 2553 2554#define S_PMON_CDEL_MANUAL 4 |
| 2555#define M_PMON_CDEL_MANUAL 0x3f |
|
| 2186#define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL) | 2556#define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL) |
| 2187#define F_PMON_CDEL_MANUAL V_PMON_CDEL_MANUAL(1U) | 2557#define G_PMON_CDEL_MANUAL(x) (((x) >> S_PMON_CDEL_MANUAL) & M_PMON_CDEL_MANUAL) |
| 2188 2189#define S_PMON_MANUAL 1 2190#define V_PMON_MANUAL(x) ((x) << S_PMON_MANUAL) 2191#define F_PMON_MANUAL V_PMON_MANUAL(1U) 2192 2193#define S_PMON_AUTO 0 2194#define V_PMON_AUTO(x) ((x) << S_PMON_AUTO) 2195#define F_PMON_AUTO V_PMON_AUTO(1U) --- 539 unchanged lines hidden (view full) --- 2735 2736#define S_UPSPAREINT 0 2737#define M_UPSPAREINT 0x7 2738#define V_UPSPAREINT(x) ((x) << S_UPSPAREINT) 2739#define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT) 2740 2741#define A_CIM_HOST_INT_ENABLE 0x298 2742 | 2558 2559#define S_PMON_MANUAL 1 2560#define V_PMON_MANUAL(x) ((x) << S_PMON_MANUAL) 2561#define F_PMON_MANUAL V_PMON_MANUAL(1U) 2562 2563#define S_PMON_AUTO 0 2564#define V_PMON_AUTO(x) ((x) << S_PMON_AUTO) 2565#define F_PMON_AUTO V_PMON_AUTO(1U) --- 539 unchanged lines hidden (view full) --- 3105 3106#define S_UPSPAREINT 0 3107#define M_UPSPAREINT 0x7 3108#define V_UPSPAREINT(x) ((x) << S_UPSPAREINT) 3109#define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT) 3110 3111#define A_CIM_HOST_INT_ENABLE 0x298 3112 |
| 3113#define S_DTAGPARERR 28 3114#define V_DTAGPARERR(x) ((x) << S_DTAGPARERR) 3115#define F_DTAGPARERR V_DTAGPARERR(1U) 3116 3117#define S_ITAGPARERR 27 3118#define V_ITAGPARERR(x) ((x) << S_ITAGPARERR) 3119#define F_ITAGPARERR V_ITAGPARERR(1U) 3120 3121#define S_IBQTPPARERR 26 3122#define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR) 3123#define F_IBQTPPARERR V_IBQTPPARERR(1U) 3124 3125#define S_IBQULPPARERR 25 3126#define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR) 3127#define F_IBQULPPARERR V_IBQULPPARERR(1U) 3128 3129#define S_IBQSGEHIPARERR 24 3130#define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR) 3131#define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U) 3132 3133#define S_IBQSGELOPARERR 23 3134#define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR) 3135#define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U) 3136 3137#define S_OBQULPLOPARERR 22 3138#define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR) 3139#define F_OBQULPLOPARERR V_OBQULPLOPARERR(1U) 3140 3141#define S_OBQULPHIPARERR 21 3142#define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR) 3143#define F_OBQULPHIPARERR V_OBQULPHIPARERR(1U) 3144 3145#define S_OBQSGEPARERR 20 3146#define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR) 3147#define F_OBQSGEPARERR V_OBQSGEPARERR(1U) 3148 3149#define S_DCACHEPARERR 19 3150#define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR) 3151#define F_DCACHEPARERR V_DCACHEPARERR(1U) 3152 3153#define S_ICACHEPARERR 18 3154#define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR) 3155#define F_ICACHEPARERR V_ICACHEPARERR(1U) 3156 3157#define S_DRAMPARERR 17 3158#define V_DRAMPARERR(x) ((x) << S_DRAMPARERR) 3159#define F_DRAMPARERR V_DRAMPARERR(1U) 3160 |
|
| 2743#define S_TIMER1INTEN 15 2744#define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN) 2745#define F_TIMER1INTEN V_TIMER1INTEN(1U) 2746 2747#define S_TIMER0INTEN 14 2748#define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN) 2749#define F_TIMER0INTEN V_TIMER0INTEN(1U) 2750 --- 287 unchanged lines hidden (view full) --- 3038#define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO) 3039#define F_TXFBARBPRIO V_TXFBARBPRIO(1U) 3040 3041#define S_DBMAXOPCNT 16 3042#define M_DBMAXOPCNT 0xff 3043#define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT) 3044#define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT) 3045 | 3161#define S_TIMER1INTEN 15 3162#define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN) 3163#define F_TIMER1INTEN V_TIMER1INTEN(1U) 3164 3165#define S_TIMER0INTEN 14 3166#define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN) 3167#define F_TIMER0INTEN V_TIMER0INTEN(1U) 3168 --- 287 unchanged lines hidden (view full) --- 3456#define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO) 3457#define F_TXFBARBPRIO V_TXFBARBPRIO(1U) 3458 3459#define S_DBMAXOPCNT 16 3460#define M_DBMAXOPCNT 0xff 3461#define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT) 3462#define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT) 3463 |
| 3464#define S_IPV6ENABLE 15 3465#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE) 3466#define F_IPV6ENABLE V_IPV6ENABLE(1U) 3467 |
|
| 3046#define S_NICMODE 14 3047#define V_NICMODE(x) ((x) << S_NICMODE) 3048#define F_NICMODE V_NICMODE(1U) 3049 3050#define S_ECHECKSUMCHECKTCP 13 3051#define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP) 3052#define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U) 3053 --- 28 unchanged lines hidden (view full) --- 3082#define S_CETHERNET 1 3083#define V_CETHERNET(x) ((x) << S_CETHERNET) 3084#define F_CETHERNET V_CETHERNET(1U) 3085 3086#define S_CTUNNEL 0 3087#define V_CTUNNEL(x) ((x) << S_CTUNNEL) 3088#define F_CTUNNEL V_CTUNNEL(1U) 3089 | 3468#define S_NICMODE 14 3469#define V_NICMODE(x) ((x) << S_NICMODE) 3470#define F_NICMODE V_NICMODE(1U) 3471 3472#define S_ECHECKSUMCHECKTCP 13 3473#define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP) 3474#define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U) 3475 --- 28 unchanged lines hidden (view full) --- 3504#define S_CETHERNET 1 3505#define V_CETHERNET(x) ((x) << S_CETHERNET) 3506#define F_CETHERNET V_CETHERNET(1U) 3507 3508#define S_CTUNNEL 0 3509#define V_CTUNNEL(x) ((x) << S_CTUNNEL) 3510#define F_CTUNNEL V_CTUNNEL(1U) 3511 |
| 3090#define S_IPV6ENABLE 15 3091#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE) 3092#define F_IPV6ENABLE V_IPV6ENABLE(1U) 3093 | |
| 3094#define A_TP_OUT_CONFIG 0x304 3095 | 3512#define A_TP_OUT_CONFIG 0x304 3513 |
| 3514#define S_IPIDSPLITMODE 16 3515#define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE) 3516#define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U) 3517 3518#define S_VLANEXTRACTIONENABLE2NDPORT 13 3519#define V_VLANEXTRACTIONENABLE2NDPORT(x) ((x) << S_VLANEXTRACTIONENABLE2NDPORT) 3520#define F_VLANEXTRACTIONENABLE2NDPORT V_VLANEXTRACTIONENABLE2NDPORT(1U) 3521 |
|
| 3096#define S_VLANEXTRACTIONENABLE 12 3097#define V_VLANEXTRACTIONENABLE(x) ((x) << S_VLANEXTRACTIONENABLE) 3098#define F_VLANEXTRACTIONENABLE V_VLANEXTRACTIONENABLE(1U) 3099 3100#define S_ECHECKSUMGENERATETCP 11 3101#define V_ECHECKSUMGENERATETCP(x) ((x) << S_ECHECKSUMGENERATETCP) 3102#define F_ECHECKSUMGENERATETCP V_ECHECKSUMGENERATETCP(1U) 3103 --- 20 unchanged lines hidden (view full) --- 3124#define S_OUT_CCPL 2 3125#define V_OUT_CCPL(x) ((x) << S_OUT_CCPL) 3126#define F_OUT_CCPL V_OUT_CCPL(1U) 3127 3128#define S_OUT_CETHERNET 0 3129#define V_OUT_CETHERNET(x) ((x) << S_OUT_CETHERNET) 3130#define F_OUT_CETHERNET V_OUT_CETHERNET(1U) 3131 | 3522#define S_VLANEXTRACTIONENABLE 12 3523#define V_VLANEXTRACTIONENABLE(x) ((x) << S_VLANEXTRACTIONENABLE) 3524#define F_VLANEXTRACTIONENABLE V_VLANEXTRACTIONENABLE(1U) 3525 3526#define S_ECHECKSUMGENERATETCP 11 3527#define V_ECHECKSUMGENERATETCP(x) ((x) << S_ECHECKSUMGENERATETCP) 3528#define F_ECHECKSUMGENERATETCP V_ECHECKSUMGENERATETCP(1U) 3529 --- 20 unchanged lines hidden (view full) --- 3550#define S_OUT_CCPL 2 3551#define V_OUT_CCPL(x) ((x) << S_OUT_CCPL) 3552#define F_OUT_CCPL V_OUT_CCPL(1U) 3553 3554#define S_OUT_CETHERNET 0 3555#define V_OUT_CETHERNET(x) ((x) << S_OUT_CETHERNET) 3556#define F_OUT_CETHERNET V_OUT_CETHERNET(1U) 3557 |
| 3132#define S_IPIDSPLITMODE 16 3133#define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE) 3134#define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U) 3135 3136#define S_VLANEXTRACTIONENABLE2NDPORT 13 3137#define V_VLANEXTRACTIONENABLE2NDPORT(x) ((x) << S_VLANEXTRACTIONENABLE2NDPORT) 3138#define F_VLANEXTRACTIONENABLE2NDPORT V_VLANEXTRACTIONENABLE2NDPORT(1U) 3139 | |
| 3140#define A_TP_GLOBAL_CONFIG 0x308 3141 | 3558#define A_TP_GLOBAL_CONFIG 0x308 3559 |
| 3560#define S_SYNCOOKIEPARAMS 26 3561#define M_SYNCOOKIEPARAMS 0x3f 3562#define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS) 3563#define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS) 3564 |
|
| 3142#define S_RXFLOWCONTROLDISABLE 25 3143#define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE) 3144#define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U) 3145 3146#define S_TXPACINGENABLE 24 3147#define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE) 3148#define F_TXPACINGENABLE V_TXPACINGENABLE(1U) 3149 --- 51 unchanged lines hidden (view full) --- 3201#define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE) 3202#define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE) 3203 3204#define S_IPTTL 0 3205#define M_IPTTL 0xff 3206#define V_IPTTL(x) ((x) << S_IPTTL) 3207#define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL) 3208 | 3565#define S_RXFLOWCONTROLDISABLE 25 3566#define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE) 3567#define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U) 3568 3569#define S_TXPACINGENABLE 24 3570#define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE) 3571#define F_TXPACINGENABLE V_TXPACINGENABLE(1U) 3572 --- 51 unchanged lines hidden (view full) --- 3624#define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE) 3625#define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE) 3626 3627#define S_IPTTL 0 3628#define M_IPTTL 0xff 3629#define V_IPTTL(x) ((x) << S_IPTTL) 3630#define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL) 3631 |
| 3209#define S_SYNCOOKIEPARAMS 26 3210#define M_SYNCOOKIEPARAMS 0x3f 3211#define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS) 3212#define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS) 3213 | |
| 3214#define A_TP_GLOBAL_RX_CREDIT 0x30c 3215#define A_TP_CMM_SIZE 0x310 3216 3217#define S_CMMEMMGRSIZE 0 3218#define M_CMMEMMGRSIZE 0xfffffff 3219#define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE) 3220#define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE) 3221 3222#define A_TP_CMM_MM_BASE 0x314 3223 3224#define S_CMMEMMGRBASE 0 3225#define M_CMMEMMGRBASE 0xfffffff 3226#define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE) 3227#define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE) 3228 3229#define A_TP_CMM_TIMER_BASE 0x318 3230 | 3632#define A_TP_GLOBAL_RX_CREDIT 0x30c 3633#define A_TP_CMM_SIZE 0x310 3634 3635#define S_CMMEMMGRSIZE 0 3636#define M_CMMEMMGRSIZE 0xfffffff 3637#define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE) 3638#define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE) 3639 3640#define A_TP_CMM_MM_BASE 0x314 3641 3642#define S_CMMEMMGRBASE 0 3643#define M_CMMEMMGRBASE 0xfffffff 3644#define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE) 3645#define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE) 3646 3647#define A_TP_CMM_TIMER_BASE 0x318 3648 |
| 3231#define S_CMTIMERBASE 0 3232#define M_CMTIMERBASE 0xfffffff 3233#define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE) 3234#define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE) 3235 | |
| 3236#define S_CMTIMERMAXNUM 28 3237#define M_CMTIMERMAXNUM 0x3 3238#define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM) 3239#define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM) 3240 | 3649#define S_CMTIMERMAXNUM 28 3650#define M_CMTIMERMAXNUM 0x3 3651#define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM) 3652#define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM) 3653 |
| 3654#define S_CMTIMERBASE 0 3655#define M_CMTIMERBASE 0xfffffff 3656#define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE) 3657#define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE) 3658 |
|
| 3241#define A_TP_PMM_SIZE 0x31c 3242 3243#define S_PMSIZE 0 3244#define M_PMSIZE 0xfffffff 3245#define V_PMSIZE(x) ((x) << S_PMSIZE) 3246#define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE) 3247 3248#define A_TP_PMM_TX_BASE 0x320 --- 85 unchanged lines hidden (view full) --- 3334#define F_AUTOENABLE V_AUTOENABLE(1U) 3335 3336#define S_DACK_MODE 0 3337#define V_DACK_MODE(x) ((x) << S_DACK_MODE) 3338#define F_DACK_MODE V_DACK_MODE(1U) 3339 3340#define A_TP_PC_CONFIG 0x348 3341 | 3659#define A_TP_PMM_SIZE 0x31c 3660 3661#define S_PMSIZE 0 3662#define M_PMSIZE 0xfffffff 3663#define V_PMSIZE(x) ((x) << S_PMSIZE) 3664#define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE) 3665 3666#define A_TP_PMM_TX_BASE 0x320 --- 85 unchanged lines hidden (view full) --- 3752#define F_AUTOENABLE V_AUTOENABLE(1U) 3753 3754#define S_DACK_MODE 0 3755#define V_DACK_MODE(x) ((x) << S_DACK_MODE) 3756#define F_DACK_MODE V_DACK_MODE(1U) 3757 3758#define A_TP_PC_CONFIG 0x348 3759 |
| 3760#define S_CMCACHEDISABLE 31 3761#define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE) 3762#define F_CMCACHEDISABLE V_CMCACHEDISABLE(1U) 3763 3764#define S_ENABLEOCSPIFULL 30 3765#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL) 3766#define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U) 3767 3768#define S_ENABLEFLMERRORDDP 29 3769#define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP) 3770#define F_ENABLEFLMERRORDDP V_ENABLEFLMERRORDDP(1U) 3771 3772#define S_LOCKTID 28 3773#define V_LOCKTID(x) ((x) << S_LOCKTID) 3774#define F_LOCKTID V_LOCKTID(1U) 3775 3776#define S_FIXRCVWND 27 3777#define V_FIXRCVWND(x) ((x) << S_FIXRCVWND) 3778#define F_FIXRCVWND V_FIXRCVWND(1U) 3779 |
|
| 3342#define S_TXTOSQUEUEMAPMODE 26 3343#define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE) 3344#define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U) 3345 3346#define S_RDDPCONGEN 25 3347#define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN) 3348#define F_RDDPCONGEN V_RDDPCONGEN(1U) 3349 --- 81 unchanged lines hidden (view full) --- 3431#define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN) 3432#define F_DISABLEHELDFIN V_DISABLEHELDFIN(1U) 3433 3434#define S_TABLELATENCYDELTA 0 3435#define M_TABLELATENCYDELTA 0xf 3436#define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA) 3437#define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) 3438 | 3780#define S_TXTOSQUEUEMAPMODE 26 3781#define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE) 3782#define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U) 3783 3784#define S_RDDPCONGEN 25 3785#define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN) 3786#define F_RDDPCONGEN V_RDDPCONGEN(1U) 3787 --- 81 unchanged lines hidden (view full) --- 3869#define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN) 3870#define F_DISABLEHELDFIN V_DISABLEHELDFIN(1U) 3871 3872#define S_TABLELATENCYDELTA 0 3873#define M_TABLELATENCYDELTA 0xf 3874#define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA) 3875#define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) 3876 |
| 3439#define S_CMCACHEDISABLE 31 3440#define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE) 3441#define F_CMCACHEDISABLE V_CMCACHEDISABLE(1U) | 3877#define A_TP_PC_CONFIG2 0x34c |
| 3442 | 3878 |
| 3443#define S_ENABLEOCSPIFULL 30 3444#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL) 3445#define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U) | 3879#define S_DISBLEDAPARBIT0 15 3880#define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0) 3881#define F_DISBLEDAPARBIT0 V_DISBLEDAPARBIT0(1U) |
| 3446 | 3882 |
| 3447#define S_ENABLEFLMERRORDDP 29 3448#define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP) 3449#define F_ENABLEFLMERRORDDP V_ENABLEFLMERRORDDP(1U) | 3883#define S_ENABLEARPMISS 13 3884#define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS) 3885#define F_ENABLEARPMISS V_ENABLEARPMISS(1U) |
| 3450 | 3886 |
| 3451#define S_LOCKTID 28 3452#define V_LOCKTID(x) ((x) << S_LOCKTID) 3453#define F_LOCKTID V_LOCKTID(1U) | 3887#define S_ENABLENONOFDTNLSYN 12 3888#define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN) 3889#define F_ENABLENONOFDTNLSYN V_ENABLENONOFDTNLSYN(1U) |
| 3454 | 3890 |
| 3455#define S_FIXRCVWND 27 3456#define V_FIXRCVWND(x) ((x) << S_FIXRCVWND) 3457#define F_FIXRCVWND V_FIXRCVWND(1U) | 3891#define S_ENABLEIPV6RSS 11 3892#define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS) 3893#define F_ENABLEIPV6RSS V_ENABLEIPV6RSS(1U) |
| 3458 | 3894 |
| 3459#define A_TP_PC_CONFIG2 0x34c 3460 | |
| 3461#define S_ENABLEDROPRQEMPTYPKT 10 3462#define V_ENABLEDROPRQEMPTYPKT(x) ((x) << S_ENABLEDROPRQEMPTYPKT) 3463#define F_ENABLEDROPRQEMPTYPKT V_ENABLEDROPRQEMPTYPKT(1U) 3464 3465#define S_ENABLETXPORTFROMDA2 9 3466#define V_ENABLETXPORTFROMDA2(x) ((x) << S_ENABLETXPORTFROMDA2) 3467#define F_ENABLETXPORTFROMDA2 V_ENABLETXPORTFROMDA2(1U) 3468 --- 8 unchanged lines hidden (view full) --- 3477#define S_ENABLERXPORTFROMADDR 6 3478#define V_ENABLERXPORTFROMADDR(x) ((x) << S_ENABLERXPORTFROMADDR) 3479#define F_ENABLERXPORTFROMADDR V_ENABLERXPORTFROMADDR(1U) 3480 3481#define S_ENABLETXPORTFROMDA 5 3482#define V_ENABLETXPORTFROMDA(x) ((x) << S_ENABLETXPORTFROMDA) 3483#define F_ENABLETXPORTFROMDA V_ENABLETXPORTFROMDA(1U) 3484 | 3895#define S_ENABLEDROPRQEMPTYPKT 10 3896#define V_ENABLEDROPRQEMPTYPKT(x) ((x) << S_ENABLEDROPRQEMPTYPKT) 3897#define F_ENABLEDROPRQEMPTYPKT V_ENABLEDROPRQEMPTYPKT(1U) 3898 3899#define S_ENABLETXPORTFROMDA2 9 3900#define V_ENABLETXPORTFROMDA2(x) ((x) << S_ENABLETXPORTFROMDA2) 3901#define F_ENABLETXPORTFROMDA2 V_ENABLETXPORTFROMDA2(1U) 3902 --- 8 unchanged lines hidden (view full) --- 3911#define S_ENABLERXPORTFROMADDR 6 3912#define V_ENABLERXPORTFROMADDR(x) ((x) << S_ENABLERXPORTFROMADDR) 3913#define F_ENABLERXPORTFROMADDR V_ENABLERXPORTFROMADDR(1U) 3914 3915#define S_ENABLETXPORTFROMDA 5 3916#define V_ENABLETXPORTFROMDA(x) ((x) << S_ENABLETXPORTFROMDA) 3917#define F_ENABLETXPORTFROMDA V_ENABLETXPORTFROMDA(1U) 3918 |
| 3485#define S_CHDRAFULL 4 3486#define V_CHDRAFULL(x) ((x) << S_CHDRAFULL) 3487#define F_CHDRAFULL V_CHDRAFULL(1U) | 3919#define S_ENABLECHDRAFULL 4 3920#define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL) 3921#define F_ENABLECHDRAFULL V_ENABLECHDRAFULL(1U) |
| 3488 3489#define S_ENABLENONOFDSCBBIT 3 3490#define V_ENABLENONOFDSCBBIT(x) ((x) << S_ENABLENONOFDSCBBIT) 3491#define F_ENABLENONOFDSCBBIT V_ENABLENONOFDSCBBIT(1U) 3492 3493#define S_ENABLENONOFDTIDRSS 2 3494#define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS) 3495#define F_ENABLENONOFDTIDRSS V_ENABLENONOFDTIDRSS(1U) 3496 3497#define S_ENABLENONOFDTCBRSS 1 3498#define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS) 3499#define F_ENABLENONOFDTCBRSS V_ENABLENONOFDTCBRSS(1U) 3500 3501#define S_ENABLEOLDRXFORWARD 0 3502#define V_ENABLEOLDRXFORWARD(x) ((x) << S_ENABLEOLDRXFORWARD) 3503#define F_ENABLEOLDRXFORWARD V_ENABLEOLDRXFORWARD(1U) 3504 | 3922 3923#define S_ENABLENONOFDSCBBIT 3 3924#define V_ENABLENONOFDSCBBIT(x) ((x) << S_ENABLENONOFDSCBBIT) 3925#define F_ENABLENONOFDSCBBIT V_ENABLENONOFDSCBBIT(1U) 3926 3927#define S_ENABLENONOFDTIDRSS 2 3928#define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS) 3929#define F_ENABLENONOFDTIDRSS V_ENABLENONOFDTIDRSS(1U) 3930 3931#define S_ENABLENONOFDTCBRSS 1 3932#define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS) 3933#define F_ENABLENONOFDTCBRSS V_ENABLENONOFDTCBRSS(1U) 3934 3935#define S_ENABLEOLDRXFORWARD 0 3936#define V_ENABLEOLDRXFORWARD(x) ((x) << S_ENABLEOLDRXFORWARD) 3937#define F_ENABLEOLDRXFORWARD V_ENABLEOLDRXFORWARD(1U) 3938 |
| 3939#define S_CHDRAFULL 4 3940#define V_CHDRAFULL(x) ((x) << S_CHDRAFULL) 3941#define F_CHDRAFULL V_CHDRAFULL(1U) 3942 |
|
| 3505#define A_TP_TCP_BACKOFF_REG0 0x350 3506 3507#define S_TIMERBACKOFFINDEX3 24 3508#define M_TIMERBACKOFFINDEX3 0xff 3509#define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3) 3510#define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3) 3511 3512#define S_TIMERBACKOFFINDEX2 16 --- 144 unchanged lines hidden (view full) --- 3657#define S_TXPACEFIXED 9 3658#define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED) 3659#define F_TXPACEFIXED V_TXPACEFIXED(1U) 3660 3661#define S_TXPACEAUTO 8 3662#define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO) 3663#define F_TXPACEAUTO V_TXPACEAUTO(1U) 3664 | 3943#define A_TP_TCP_BACKOFF_REG0 0x350 3944 3945#define S_TIMERBACKOFFINDEX3 24 3946#define M_TIMERBACKOFFINDEX3 0xff 3947#define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3) 3948#define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3) 3949 3950#define S_TIMERBACKOFFINDEX2 16 --- 144 unchanged lines hidden (view full) --- 4095#define S_TXPACEFIXED 9 4096#define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED) 4097#define F_TXPACEFIXED V_TXPACEFIXED(1U) 4098 4099#define S_TXPACEAUTO 8 4100#define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO) 4101#define F_TXPACEAUTO V_TXPACEAUTO(1U) 4102 |
| 4103#define S_RXURGTUNNEL 6 4104#define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL) 4105#define F_RXURGTUNNEL V_RXURGTUNNEL(1U) 4106 |
|
| 3665#define S_RXURGMODE 5 3666#define V_RXURGMODE(x) ((x) << S_RXURGMODE) 3667#define F_RXURGMODE V_RXURGMODE(1U) 3668 3669#define S_TXURGMODE 4 3670#define V_TXURGMODE(x) ((x) << S_TXURGMODE) 3671#define F_TXURGMODE V_TXURGMODE(1U) 3672 --- 5 unchanged lines hidden (view full) --- 3678#define S_RXCOALESCEENABLE 1 3679#define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE) 3680#define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U) 3681 3682#define S_RXCOALESCEPSHEN 0 3683#define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN) 3684#define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U) 3685 | 4107#define S_RXURGMODE 5 4108#define V_RXURGMODE(x) ((x) << S_RXURGMODE) 4109#define F_RXURGMODE V_RXURGMODE(1U) 4110 4111#define S_TXURGMODE 4 4112#define V_TXURGMODE(x) ((x) << S_TXURGMODE) 4113#define F_TXURGMODE V_TXURGMODE(1U) 4114 --- 5 unchanged lines hidden (view full) --- 4120#define S_RXCOALESCEENABLE 1 4121#define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE) 4122#define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U) 4123 4124#define S_RXCOALESCEPSHEN 0 4125#define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN) 4126#define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U) 4127 |
| 3686#define S_RXURGTUNNEL 6 3687#define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL) 3688#define F_RXURGTUNNEL V_RXURGTUNNEL(1U) 3689 | |
| 3690#define A_TP_PARA_REG4 0x370 3691 3692#define S_HIGHSPEEDCFG 24 3693#define M_HIGHSPEEDCFG 0xff 3694#define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG) 3695#define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG) 3696 3697#define S_NEWRENOCFG 16 --- 17 unchanged lines hidden (view full) --- 3715#define M_INDICATESIZE 0xffff 3716#define V_INDICATESIZE(x) ((x) << S_INDICATESIZE) 3717#define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE) 3718 3719#define S_SCHDENABLE 8 3720#define V_SCHDENABLE(x) ((x) << S_SCHDENABLE) 3721#define F_SCHDENABLE V_SCHDENABLE(1U) 3722 | 4128#define A_TP_PARA_REG4 0x370 4129 4130#define S_HIGHSPEEDCFG 24 4131#define M_HIGHSPEEDCFG 0xff 4132#define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG) 4133#define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG) 4134 4135#define S_NEWRENOCFG 16 --- 17 unchanged lines hidden (view full) --- 4153#define M_INDICATESIZE 0xffff 4154#define V_INDICATESIZE(x) ((x) << S_INDICATESIZE) 4155#define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE) 4156 4157#define S_SCHDENABLE 8 4158#define V_SCHDENABLE(x) ((x) << S_SCHDENABLE) 4159#define F_SCHDENABLE V_SCHDENABLE(1U) 4160 |
| 4161#define S_RXDDPOFFINIT 3 4162#define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT) 4163#define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U) 4164 |
|
| 3723#define S_ONFLYDDPENABLE 2 3724#define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE) 3725#define F_ONFLYDDPENABLE V_ONFLYDDPENABLE(1U) 3726 3727#define S_DACKTIMERSPIN 1 3728#define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN) 3729#define F_DACKTIMERSPIN V_DACKTIMERSPIN(1U) 3730 3731#define S_PUSHTIMERENABLE 0 3732#define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE) 3733#define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U) 3734 3735#define A_TP_PARA_REG6 0x378 3736 3737#define S_TXPDUSIZEADJ 16 3738#define M_TXPDUSIZEADJ 0xff 3739#define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ) 3740#define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ) 3741 | 4165#define S_ONFLYDDPENABLE 2 4166#define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE) 4167#define F_ONFLYDDPENABLE V_ONFLYDDPENABLE(1U) 4168 4169#define S_DACKTIMERSPIN 1 4170#define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN) 4171#define F_DACKTIMERSPIN V_DACKTIMERSPIN(1U) 4172 4173#define S_PUSHTIMERENABLE 0 4174#define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE) 4175#define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U) 4176 4177#define A_TP_PARA_REG6 0x378 4178 4179#define S_TXPDUSIZEADJ 16 4180#define M_TXPDUSIZEADJ 0xff 4181#define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ) 4182#define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ) 4183 |
| 3742#define S_ENABLEEPDU 14 3743#define V_ENABLEEPDU(x) ((x) << S_ENABLEEPDU) 3744#define F_ENABLEEPDU V_ENABLEEPDU(1U) | 4184#define S_ENABLEDEFERACK 12 4185#define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK) 4186#define F_ENABLEDEFERACK V_ENABLEDEFERACK(1U) |
| 3745 | 4187 |
| 3746#define S_T3A_ENABLEESND 13 3747#define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND) 3748#define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U) | 4188#define S_ENABLEESND 11 4189#define V_ENABLEESND(x) ((x) << S_ENABLEESND) 4190#define F_ENABLEESND V_ENABLEESND(1U) |
| 3749 | 4191 |
| 3750#define S_T3A_ENABLECSND 12 3751#define V_T3A_ENABLECSND(x) ((x) << S_T3A_ENABLECSND) 3752#define F_T3A_ENABLECSND V_T3A_ENABLECSND(1U) | 4192#define S_ENABLECSND 10 4193#define V_ENABLECSND(x) ((x) << S_ENABLECSND) 4194#define F_ENABLECSND V_ENABLECSND(1U) |
| 3753 | 4195 |
| 3754#define S_T3A_ENABLEDEFERACK 9 3755#define V_T3A_ENABLEDEFERACK(x) ((x) << S_T3A_ENABLEDEFERACK) 3756#define F_T3A_ENABLEDEFERACK V_T3A_ENABLEDEFERACK(1U) | 4196#define S_ENABLEPDUE 9 4197#define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE) 4198#define F_ENABLEPDUE V_ENABLEPDUE(1U) |
| 3757 3758#define S_ENABLEPDUC 8 3759#define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC) 3760#define F_ENABLEPDUC V_ENABLEPDUC(1U) 3761 | 4199 4200#define S_ENABLEPDUC 8 4201#define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC) 4202#define F_ENABLEPDUC V_ENABLEPDUC(1U) 4203 |
| 3762#define S_ENABLEPDUI 7 3763#define V_ENABLEPDUI(x) ((x) << S_ENABLEPDUI) 3764#define F_ENABLEPDUI V_ENABLEPDUI(1U) | 4204#define S_ENABLEBUFI 7 4205#define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI) 4206#define F_ENABLEBUFI V_ENABLEBUFI(1U) |
| 3765 | 4207 |
| 3766#define S_T3A_ENABLEPDUE 6 3767#define V_T3A_ENABLEPDUE(x) ((x) << S_T3A_ENABLEPDUE) 3768#define F_T3A_ENABLEPDUE V_T3A_ENABLEPDUE(1U) | 4208#define S_ENABLEBUFE 6 4209#define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE) 4210#define F_ENABLEBUFE V_ENABLEBUFE(1U) |
| 3769 3770#define S_ENABLEDEFER 5 3771#define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER) 3772#define F_ENABLEDEFER V_ENABLEDEFER(1U) 3773 3774#define S_ENABLECLEARRXMTOOS 4 3775#define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS) 3776#define F_ENABLECLEARRXMTOOS V_ENABLECLEARRXMTOOS(1U) --- 9 unchanged lines hidden (view full) --- 3786#define S_DISABLEPDURXMT 1 3787#define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT) 3788#define F_DISABLEPDURXMT V_DISABLEPDURXMT(1U) 3789 3790#define S_DISABLEPDUXMT 0 3791#define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT) 3792#define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U) 3793 | 4211 4212#define S_ENABLEDEFER 5 4213#define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER) 4214#define F_ENABLEDEFER V_ENABLEDEFER(1U) 4215 4216#define S_ENABLECLEARRXMTOOS 4 4217#define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS) 4218#define F_ENABLECLEARRXMTOOS V_ENABLECLEARRXMTOOS(1U) --- 9 unchanged lines hidden (view full) --- 4228#define S_DISABLEPDURXMT 1 4229#define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT) 4230#define F_DISABLEPDURXMT V_DISABLEPDURXMT(1U) 4231 4232#define S_DISABLEPDUXMT 0 4233#define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT) 4234#define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U) 4235 |
| 3794#define S_ENABLEDEFERACK 12 3795#define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK) 3796#define F_ENABLEDEFERACK V_ENABLEDEFERACK(1U) | 4236#define S_ENABLEEPDU 14 4237#define V_ENABLEEPDU(x) ((x) << S_ENABLEEPDU) 4238#define F_ENABLEEPDU V_ENABLEEPDU(1U) |
| 3797 | 4239 |
| 3798#define S_ENABLEESND 11 3799#define V_ENABLEESND(x) ((x) << S_ENABLEESND) 3800#define F_ENABLEESND V_ENABLEESND(1U) | 4240#define S_T3A_ENABLEESND 13 4241#define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND) 4242#define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U) |
| 3801 | 4243 |
| 3802#define S_ENABLECSND 10 3803#define V_ENABLECSND(x) ((x) << S_ENABLECSND) 3804#define F_ENABLECSND V_ENABLECSND(1U) | 4244#define S_T3A_ENABLECSND 12 4245#define V_T3A_ENABLECSND(x) ((x) << S_T3A_ENABLECSND) 4246#define F_T3A_ENABLECSND V_T3A_ENABLECSND(1U) |
| 3805 | 4247 |
| 3806#define S_ENABLEPDUE 9 3807#define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE) 3808#define F_ENABLEPDUE V_ENABLEPDUE(1U) | 4248#define S_T3A_ENABLEDEFERACK 9 4249#define V_T3A_ENABLEDEFERACK(x) ((x) << S_T3A_ENABLEDEFERACK) 4250#define F_T3A_ENABLEDEFERACK V_T3A_ENABLEDEFERACK(1U) |
| 3809 | 4251 |
| 3810#define S_ENABLEBUFI 7 3811#define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI) 3812#define F_ENABLEBUFI V_ENABLEBUFI(1U) | 4252#define S_ENABLEPDUI 7 4253#define V_ENABLEPDUI(x) ((x) << S_ENABLEPDUI) 4254#define F_ENABLEPDUI V_ENABLEPDUI(1U) |
| 3813 | 4255 |
| 3814#define S_ENABLEBUFE 6 3815#define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE) 3816#define F_ENABLEBUFE V_ENABLEBUFE(1U) | 4256#define S_T3A_ENABLEPDUE 6 4257#define V_T3A_ENABLEPDUE(x) ((x) << S_T3A_ENABLEPDUE) 4258#define F_T3A_ENABLEPDUE V_T3A_ENABLEPDUE(1U) |
| 3817 3818#define A_TP_PARA_REG7 0x37c 3819 3820#define S_PMMAXXFERLEN1 16 3821#define M_PMMAXXFERLEN1 0xffff 3822#define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1) 3823#define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1) 3824 --- 472 unchanged lines hidden (view full) --- 4297#define A_TP_CMM_MM_MAX_PSTRUCT 0x46c 4298 4299#define S_CMMAXPSTRUCT 0 4300#define M_CMMAXPSTRUCT 0x1fffff 4301#define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT) 4302#define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT) 4303 4304#define A_TP_INT_ENABLE 0x470 | 4259 4260#define A_TP_PARA_REG7 0x37c 4261 4262#define S_PMMAXXFERLEN1 16 4263#define M_PMMAXXFERLEN1 0xffff 4264#define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1) 4265#define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1) 4266 --- 472 unchanged lines hidden (view full) --- 4739#define A_TP_CMM_MM_MAX_PSTRUCT 0x46c 4740 4741#define S_CMMAXPSTRUCT 0 4742#define M_CMMAXPSTRUCT 0x1fffff 4743#define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT) 4744#define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT) 4745 4746#define A_TP_INT_ENABLE 0x470 |
| 4747 4748#define S_FLMTXFLSTEMPTY 30 4749#define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY) 4750#define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U) 4751 4752#define S_FLMRXFLSTEMPTY 29 4753#define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY) 4754#define F_FLMRXFLSTEMPTY V_FLMRXFLSTEMPTY(1U) 4755 4756#define S_FLMPERRSET 28 4757#define V_FLMPERRSET(x) ((x) << S_FLMPERRSET) 4758#define F_FLMPERRSET V_FLMPERRSET(1U) 4759 4760#define S_PROTOCOLSRAMPERR 27 4761#define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR) 4762#define F_PROTOCOLSRAMPERR V_PROTOCOLSRAMPERR(1U) 4763 4764#define S_ARPLUTPERR 26 4765#define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR) 4766#define F_ARPLUTPERR V_ARPLUTPERR(1U) 4767 4768#define S_CMRCFOPPERR 25 4769#define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR) 4770#define F_CMRCFOPPERR V_CMRCFOPPERR(1U) 4771 4772#define S_CMCACHEPERR 24 4773#define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR) 4774#define F_CMCACHEPERR V_CMCACHEPERR(1U) 4775 4776#define S_CMRCFDATAPERR 23 4777#define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR) 4778#define F_CMRCFDATAPERR V_CMRCFDATAPERR(1U) 4779 4780#define S_DBL2TLUTPERR 22 4781#define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR) 4782#define F_DBL2TLUTPERR V_DBL2TLUTPERR(1U) 4783 4784#define S_DBTXTIDPERR 21 4785#define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR) 4786#define F_DBTXTIDPERR V_DBTXTIDPERR(1U) 4787 4788#define S_DBEXTPERR 20 4789#define V_DBEXTPERR(x) ((x) << S_DBEXTPERR) 4790#define F_DBEXTPERR V_DBEXTPERR(1U) 4791 4792#define S_DBOPPERR 19 4793#define V_DBOPPERR(x) ((x) << S_DBOPPERR) 4794#define F_DBOPPERR V_DBOPPERR(1U) 4795 4796#define S_TMCACHEPERR 18 4797#define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR) 4798#define F_TMCACHEPERR V_TMCACHEPERR(1U) 4799 4800#define S_ETPOUTCPLFIFOPERR 17 4801#define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR) 4802#define F_ETPOUTCPLFIFOPERR V_ETPOUTCPLFIFOPERR(1U) 4803 4804#define S_ETPOUTTCPFIFOPERR 16 4805#define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR) 4806#define F_ETPOUTTCPFIFOPERR V_ETPOUTTCPFIFOPERR(1U) 4807 4808#define S_ETPOUTIPFIFOPERR 15 4809#define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR) 4810#define F_ETPOUTIPFIFOPERR V_ETPOUTIPFIFOPERR(1U) 4811 4812#define S_ETPOUTETHFIFOPERR 14 4813#define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR) 4814#define F_ETPOUTETHFIFOPERR V_ETPOUTETHFIFOPERR(1U) 4815 4816#define S_ETPINCPLFIFOPERR 13 4817#define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR) 4818#define F_ETPINCPLFIFOPERR V_ETPINCPLFIFOPERR(1U) 4819 4820#define S_ETPINTCPOPTFIFOPERR 12 4821#define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR) 4822#define F_ETPINTCPOPTFIFOPERR V_ETPINTCPOPTFIFOPERR(1U) 4823 4824#define S_ETPINTCPFIFOPERR 11 4825#define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR) 4826#define F_ETPINTCPFIFOPERR V_ETPINTCPFIFOPERR(1U) 4827 4828#define S_ETPINIPFIFOPERR 10 4829#define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR) 4830#define F_ETPINIPFIFOPERR V_ETPINIPFIFOPERR(1U) 4831 4832#define S_ETPINETHFIFOPERR 9 4833#define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR) 4834#define F_ETPINETHFIFOPERR V_ETPINETHFIFOPERR(1U) 4835 4836#define S_CTPOUTCPLFIFOPERR 8 4837#define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR) 4838#define F_CTPOUTCPLFIFOPERR V_CTPOUTCPLFIFOPERR(1U) 4839 4840#define S_CTPOUTTCPFIFOPERR 7 4841#define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR) 4842#define F_CTPOUTTCPFIFOPERR V_CTPOUTTCPFIFOPERR(1U) 4843 4844#define S_CTPOUTIPFIFOPERR 6 4845#define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR) 4846#define F_CTPOUTIPFIFOPERR V_CTPOUTIPFIFOPERR(1U) 4847 4848#define S_CTPOUTETHFIFOPERR 5 4849#define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR) 4850#define F_CTPOUTETHFIFOPERR V_CTPOUTETHFIFOPERR(1U) 4851 4852#define S_CTPINCPLFIFOPERR 4 4853#define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR) 4854#define F_CTPINCPLFIFOPERR V_CTPINCPLFIFOPERR(1U) 4855 4856#define S_CTPINTCPOPFIFOPERR 3 4857#define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR) 4858#define F_CTPINTCPOPFIFOPERR V_CTPINTCPOPFIFOPERR(1U) 4859 4860#define S_CTPINTCPFIFOPERR 2 4861#define V_CTPINTCPFIFOPERR(x) ((x) << S_CTPINTCPFIFOPERR) 4862#define F_CTPINTCPFIFOPERR V_CTPINTCPFIFOPERR(1U) 4863 4864#define S_CTPINIPFIFOPERR 1 4865#define V_CTPINIPFIFOPERR(x) ((x) << S_CTPINIPFIFOPERR) 4866#define F_CTPINIPFIFOPERR V_CTPINIPFIFOPERR(1U) 4867 4868#define S_CTPINETHFIFOPERR 0 4869#define V_CTPINETHFIFOPERR(x) ((x) << S_CTPINETHFIFOPERR) 4870#define F_CTPINETHFIFOPERR V_CTPINETHFIFOPERR(1U) 4871 |
|
| 4305#define A_TP_INT_CAUSE 0x474 4306#define A_TP_FLM_FREE_PS_CNT 0x480 4307 4308#define S_FREEPSTRUCTCOUNT 0 4309#define M_FREEPSTRUCTCOUNT 0x1fffff 4310#define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT) 4311#define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT) 4312 --- 16 unchanged lines hidden (view full) --- 4329#define A_TP_TM_DACK_PUSH_CNT 0x494 4330#define A_TP_TM_DACK_POP_CNT 0x498 4331#define A_TP_TM_MOD_PUSH_CNT 0x49c 4332#define A_TP_MOD_POP_CNT 0x4a0 4333#define A_TP_TIMER_SEPARATOR 0x4a4 4334#define A_TP_DEBUG_SEL 0x4a8 4335#define A_TP_DEBUG_FLAGS 0x4ac 4336 | 4872#define A_TP_INT_CAUSE 0x474 4873#define A_TP_FLM_FREE_PS_CNT 0x480 4874 4875#define S_FREEPSTRUCTCOUNT 0 4876#define M_FREEPSTRUCTCOUNT 0x1fffff 4877#define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT) 4878#define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT) 4879 --- 16 unchanged lines hidden (view full) --- 4896#define A_TP_TM_DACK_PUSH_CNT 0x494 4897#define A_TP_TM_DACK_POP_CNT 0x498 4898#define A_TP_TM_MOD_PUSH_CNT 0x49c 4899#define A_TP_MOD_POP_CNT 0x4a0 4900#define A_TP_TIMER_SEPARATOR 0x4a4 4901#define A_TP_DEBUG_SEL 0x4a8 4902#define A_TP_DEBUG_FLAGS 0x4ac 4903 |
| 4337#define S_RXDEBUGFLAGS 16 4338#define M_RXDEBUGFLAGS 0xffff 4339#define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS) 4340#define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS) 4341 4342#define S_TXDEBUGFLAGS 0 4343#define M_TXDEBUGFLAGS 0xffff 4344#define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS) 4345#define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS) 4346 | |
| 4347#define S_RXTIMERDACKFIRST 26 4348#define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST) 4349#define F_RXTIMERDACKFIRST V_RXTIMERDACKFIRST(1U) 4350 4351#define S_RXTIMERDACK 25 4352#define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK) 4353#define F_RXTIMERDACK V_RXTIMERDACK(1U) 4354 --- 76 unchanged lines hidden (view full) --- 4431#define S_TXRCVADVZERO 1 4432#define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO) 4433#define F_TXRCVADVZERO V_TXRCVADVZERO(1U) 4434 4435#define S_TXRCVADVLTMSS 0 4436#define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS) 4437#define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U) 4438 | 4904#define S_RXTIMERDACKFIRST 26 4905#define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST) 4906#define F_RXTIMERDACKFIRST V_RXTIMERDACKFIRST(1U) 4907 4908#define S_RXTIMERDACK 25 4909#define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK) 4910#define F_RXTIMERDACK V_RXTIMERDACK(1U) 4911 --- 76 unchanged lines hidden (view full) --- 4988#define S_TXRCVADVZERO 1 4989#define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO) 4990#define F_TXRCVADVZERO V_TXRCVADVZERO(1U) 4991 4992#define S_TXRCVADVLTMSS 0 4993#define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS) 4994#define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U) 4995 |
| 4996#define S_RXDEBUGFLAGS 16 4997#define M_RXDEBUGFLAGS 0xffff 4998#define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS) 4999#define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS) 5000 5001#define S_TXDEBUGFLAGS 0 5002#define M_TXDEBUGFLAGS 0xffff 5003#define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS) 5004#define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS) 5005 5006#define A_TP_PROXY_FLOW_CNTL 0x4b0 |
|
| 4439#define A_TP_CM_FLOW_CNTL_MODE 0x4b0 4440 4441#define S_CMFLOWCACHEDISABLE 0 4442#define V_CMFLOWCACHEDISABLE(x) ((x) << S_CMFLOWCACHEDISABLE) 4443#define F_CMFLOWCACHEDISABLE V_CMFLOWCACHEDISABLE(1U) 4444 | 5007#define A_TP_CM_FLOW_CNTL_MODE 0x4b0 5008 5009#define S_CMFLOWCACHEDISABLE 0 5010#define V_CMFLOWCACHEDISABLE(x) ((x) << S_CMFLOWCACHEDISABLE) 5011#define F_CMFLOWCACHEDISABLE V_CMFLOWCACHEDISABLE(1U) 5012 |
| 4445#define A_TP_PROXY_FLOW_CNTL 0x4b0 | |
| 4446#define A_TP_PC_CONGESTION_CNTL 0x4b4 4447 4448#define S_EDROPTUNNEL 19 4449#define V_EDROPTUNNEL(x) ((x) << S_EDROPTUNNEL) 4450#define F_EDROPTUNNEL V_EDROPTUNNEL(1U) 4451 4452#define S_CDROPTUNNEL 18 4453#define V_CDROPTUNNEL(x) ((x) << S_CDROPTUNNEL) --- 352 unchanged lines hidden (view full) --- 4806#define F_ISCSITAGTCB V_ISCSITAGTCB(1U) 4807 4808#define S_TDDPTAGTCB 0 4809#define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB) 4810#define F_TDDPTAGTCB V_TDDPTAGTCB(1U) 4811 4812#define A_ULPRX_INT_ENABLE 0x504 4813 | 5013#define A_TP_PC_CONGESTION_CNTL 0x4b4 5014 5015#define S_EDROPTUNNEL 19 5016#define V_EDROPTUNNEL(x) ((x) << S_EDROPTUNNEL) 5017#define F_EDROPTUNNEL V_EDROPTUNNEL(1U) 5018 5019#define S_CDROPTUNNEL 18 5020#define V_CDROPTUNNEL(x) ((x) << S_CDROPTUNNEL) --- 352 unchanged lines hidden (view full) --- 5373#define F_ISCSITAGTCB V_ISCSITAGTCB(1U) 5374 5375#define S_TDDPTAGTCB 0 5376#define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB) 5377#define F_TDDPTAGTCB V_TDDPTAGTCB(1U) 5378 5379#define A_ULPRX_INT_ENABLE 0x504 5380 |
| 5381#define S_DATASELFRAMEERR0 7 5382#define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0) 5383#define F_DATASELFRAMEERR0 V_DATASELFRAMEERR0(1U) 5384 5385#define S_DATASELFRAMEERR1 6 5386#define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1) 5387#define F_DATASELFRAMEERR1 V_DATASELFRAMEERR1(1U) 5388 5389#define S_PCMDMUXPERR 5 5390#define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR) 5391#define F_PCMDMUXPERR V_PCMDMUXPERR(1U) 5392 5393#define S_ARBFPERR 4 5394#define V_ARBFPERR(x) ((x) << S_ARBFPERR) 5395#define F_ARBFPERR V_ARBFPERR(1U) 5396 5397#define S_ARBPF0PERR 3 5398#define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR) 5399#define F_ARBPF0PERR V_ARBPF0PERR(1U) 5400 5401#define S_ARBPF1PERR 2 5402#define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR) 5403#define F_ARBPF1PERR V_ARBPF1PERR(1U) 5404 5405#define S_PARERRPCMD 1 5406#define V_PARERRPCMD(x) ((x) << S_PARERRPCMD) 5407#define F_PARERRPCMD V_PARERRPCMD(1U) 5408 5409#define S_PARERRDATA 0 5410#define V_PARERRDATA(x) ((x) << S_PARERRDATA) 5411#define F_PARERRDATA V_PARERRDATA(1U) 5412 |
|
| 4814#define S_PARERR 0 4815#define V_PARERR(x) ((x) << S_PARERR) 4816#define F_PARERR V_PARERR(1U) 4817 4818#define A_ULPRX_INT_CAUSE 0x508 4819#define A_ULPRX_ISCSI_LLIMIT 0x50c 4820 4821#define S_ISCSILLIMIT 6 --- 66 unchanged lines hidden (view full) --- 4888#define A_ULPRX_PBL_LLIMIT 0x53c 4889#define A_ULPRX_PBL_ULIMIT 0x540 4890 4891/* registers for module ULP2_TX */ 4892#define ULP2_TX_BASE_ADDR 0x580 4893 4894#define A_ULPTX_CONFIG 0x580 4895 | 5413#define S_PARERR 0 5414#define V_PARERR(x) ((x) << S_PARERR) 5415#define F_PARERR V_PARERR(1U) 5416 5417#define A_ULPRX_INT_CAUSE 0x508 5418#define A_ULPRX_ISCSI_LLIMIT 0x50c 5419 5420#define S_ISCSILLIMIT 6 --- 66 unchanged lines hidden (view full) --- 5487#define A_ULPRX_PBL_LLIMIT 0x53c 5488#define A_ULPRX_PBL_ULIMIT 0x540 5489 5490/* registers for module ULP2_TX */ 5491#define ULP2_TX_BASE_ADDR 0x580 5492 5493#define A_ULPTX_CONFIG 0x580 5494 |
| 5495#define S_CFG_CQE_SOP_MASK 1 5496#define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK) 5497#define F_CFG_CQE_SOP_MASK V_CFG_CQE_SOP_MASK(1U) 5498 |
|
| 4896#define S_CFG_RR_ARB 0 4897#define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB) 4898#define F_CFG_RR_ARB V_CFG_RR_ARB(1U) 4899 4900#define A_ULPTX_INT_ENABLE 0x584 4901 | 5499#define S_CFG_RR_ARB 0 5500#define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB) 5501#define F_CFG_RR_ARB V_CFG_RR_ARB(1U) 5502 5503#define A_ULPTX_INT_ENABLE 0x584 5504 |
| 5505#define S_CMD_FIFO_PERR_SET1 7 5506#define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1) 5507#define F_CMD_FIFO_PERR_SET1 V_CMD_FIFO_PERR_SET1(1U) 5508 5509#define S_CMD_FIFO_PERR_SET0 6 5510#define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0) 5511#define F_CMD_FIFO_PERR_SET0 V_CMD_FIFO_PERR_SET0(1U) 5512 5513#define S_LSO_HDR_SRAM_PERR_SET1 5 5514#define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1) 5515#define F_LSO_HDR_SRAM_PERR_SET1 V_LSO_HDR_SRAM_PERR_SET1(1U) 5516 5517#define S_LSO_HDR_SRAM_PERR_SET0 4 5518#define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0) 5519#define F_LSO_HDR_SRAM_PERR_SET0 V_LSO_HDR_SRAM_PERR_SET0(1U) 5520 5521#define S_IMM_DATA_PERR_SET_CH1 3 5522#define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1) 5523#define F_IMM_DATA_PERR_SET_CH1 V_IMM_DATA_PERR_SET_CH1(1U) 5524 5525#define S_IMM_DATA_PERR_SET_CH0 2 5526#define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0) 5527#define F_IMM_DATA_PERR_SET_CH0 V_IMM_DATA_PERR_SET_CH0(1U) 5528 |
|
| 4902#define S_PBL_BOUND_ERR_CH1 1 4903#define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1) 4904#define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U) 4905 4906#define S_PBL_BOUND_ERR_CH0 0 4907#define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0) 4908#define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U) 4909 --- 203 unchanged lines hidden (view full) --- 5113 5114#define A_PM1_TX_INT_CAUSE 0x5fc 5115 5116/* registers for module MPS0 */ 5117#define MPS0_BASE_ADDR 0x600 5118 5119#define A_MPS_CFG 0x600 5120 | 5529#define S_PBL_BOUND_ERR_CH1 1 5530#define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1) 5531#define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U) 5532 5533#define S_PBL_BOUND_ERR_CH0 0 5534#define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0) 5535#define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U) 5536 --- 203 unchanged lines hidden (view full) --- 5740 5741#define A_PM1_TX_INT_CAUSE 0x5fc 5742 5743/* registers for module MPS0 */ 5744#define MPS0_BASE_ADDR 0x600 5745 5746#define A_MPS_CFG 0x600 5747 |
| 5748#define S_ENFORCEPKT 11 5749#define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT) 5750#define F_ENFORCEPKT V_ENFORCEPKT(1U) 5751 |
|
| 5121#define S_SGETPQID 8 5122#define M_SGETPQID 0x7 5123#define V_SGETPQID(x) ((x) << S_SGETPQID) 5124#define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID) 5125 5126#define S_TPRXPORTSIZE 7 5127#define V_TPRXPORTSIZE(x) ((x) << S_TPRXPORTSIZE) 5128#define F_TPRXPORTSIZE V_TPRXPORTSIZE(1U) --- 21 unchanged lines hidden (view full) --- 5150#define S_PORT1ACTIVE 1 5151#define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE) 5152#define F_PORT1ACTIVE V_PORT1ACTIVE(1U) 5153 5154#define S_PORT0ACTIVE 0 5155#define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE) 5156#define F_PORT0ACTIVE V_PORT0ACTIVE(1U) 5157 | 5752#define S_SGETPQID 8 5753#define M_SGETPQID 0x7 5754#define V_SGETPQID(x) ((x) << S_SGETPQID) 5755#define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID) 5756 5757#define S_TPRXPORTSIZE 7 5758#define V_TPRXPORTSIZE(x) ((x) << S_TPRXPORTSIZE) 5759#define F_TPRXPORTSIZE V_TPRXPORTSIZE(1U) --- 21 unchanged lines hidden (view full) --- 5781#define S_PORT1ACTIVE 1 5782#define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE) 5783#define F_PORT1ACTIVE V_PORT1ACTIVE(1U) 5784 5785#define S_PORT0ACTIVE 0 5786#define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE) 5787#define F_PORT0ACTIVE V_PORT0ACTIVE(1U) 5788 |
| 5158#define S_ENFORCEPKT 11 5159#define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT) 5160#define F_ENFORCEPKT V_ENFORCEPKT(1U) 5161 | |
| 5162#define A_MPS_DRR_CFG1 0x604 5163 5164#define S_RLDWTTPD1 11 5165#define M_RLDWTTPD1 0x7ff 5166#define V_RLDWTTPD1(x) ((x) << S_RLDWTTPD1) 5167#define G_RLDWTTPD1(x) (((x) >> S_RLDWTTPD1) & M_RLDWTTPD1) 5168 5169#define S_RLDWTTPD0 0 --- 105 unchanged lines hidden (view full) --- 5275 5276#define A_CPL_SWITCH_CNTRL 0x640 5277 5278#define S_CPL_PKT_TID 8 5279#define M_CPL_PKT_TID 0xffffff 5280#define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID) 5281#define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID) 5282 | 5789#define A_MPS_DRR_CFG1 0x604 5790 5791#define S_RLDWTTPD1 11 5792#define M_RLDWTTPD1 0x7ff 5793#define V_RLDWTTPD1(x) ((x) << S_RLDWTTPD1) 5794#define G_RLDWTTPD1(x) (((x) >> S_RLDWTTPD1) & M_RLDWTTPD1) 5795 5796#define S_RLDWTTPD0 0 --- 105 unchanged lines hidden (view full) --- 5902 5903#define A_CPL_SWITCH_CNTRL 0x640 5904 5905#define S_CPL_PKT_TID 8 5906#define M_CPL_PKT_TID 0xffffff 5907#define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID) 5908#define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID) 5909 |
| 5910#define S_CIM_TO_UP_FULL_SIZE 4 5911#define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE) 5912#define F_CIM_TO_UP_FULL_SIZE V_CIM_TO_UP_FULL_SIZE(1U) 5913 |
|
| 5283#define S_CPU_NO_3F_CIM_ENABLE 3 5284#define V_CPU_NO_3F_CIM_ENABLE(x) ((x) << S_CPU_NO_3F_CIM_ENABLE) 5285#define F_CPU_NO_3F_CIM_ENABLE V_CPU_NO_3F_CIM_ENABLE(1U) 5286 5287#define S_SWITCH_TABLE_ENABLE 2 5288#define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE) 5289#define F_SWITCH_TABLE_ENABLE V_SWITCH_TABLE_ENABLE(1U) 5290 --- 17 unchanged lines hidden (view full) --- 5308 5309#define S_ZERO_CMD 0 5310#define M_ZERO_CMD 0xff 5311#define V_ZERO_CMD(x) ((x) << S_ZERO_CMD) 5312#define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD) 5313 5314#define A_CPL_INTR_ENABLE 0x650 5315 | 5914#define S_CPU_NO_3F_CIM_ENABLE 3 5915#define V_CPU_NO_3F_CIM_ENABLE(x) ((x) << S_CPU_NO_3F_CIM_ENABLE) 5916#define F_CPU_NO_3F_CIM_ENABLE V_CPU_NO_3F_CIM_ENABLE(1U) 5917 5918#define S_SWITCH_TABLE_ENABLE 2 5919#define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE) 5920#define F_SWITCH_TABLE_ENABLE V_SWITCH_TABLE_ENABLE(1U) 5921 --- 17 unchanged lines hidden (view full) --- 5939 5940#define S_ZERO_CMD 0 5941#define M_ZERO_CMD 0xff 5942#define V_ZERO_CMD(x) ((x) << S_ZERO_CMD) 5943#define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD) 5944 5945#define A_CPL_INTR_ENABLE 0x650 5946 |
| 5947#define S_CIM_OP_MAP_PERR 5 5948#define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR) 5949#define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U) 5950 |
|
| 5316#define S_CIM_OVFL_ERROR 4 5317#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR) 5318#define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U) 5319 5320#define S_TP_FRAMING_ERROR 3 5321#define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR) 5322#define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U) 5323 --- 375 unchanged lines hidden (view full) --- 5699#define V_BYTECNT(x) ((x) << S_BYTECNT) 5700#define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT) 5701 5702/* registers for module PL3 */ 5703#define PL3_BASE_ADDR 0x6e0 5704 5705#define A_PL_INT_ENABLE0 0x6e0 5706 | 5951#define S_CIM_OVFL_ERROR 4 5952#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR) 5953#define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U) 5954 5955#define S_TP_FRAMING_ERROR 3 5956#define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR) 5957#define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U) 5958 --- 375 unchanged lines hidden (view full) --- 6334#define V_BYTECNT(x) ((x) << S_BYTECNT) 6335#define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT) 6336 6337/* registers for module PL3 */ 6338#define PL3_BASE_ADDR 0x6e0 6339 6340#define A_PL_INT_ENABLE0 0x6e0 6341 |
| 6342#define S_SW 25 6343#define V_SW(x) ((x) << S_SW) 6344#define F_SW V_SW(1U) 6345 |
|
| 5707#define S_EXT 24 5708#define V_EXT(x) ((x) << S_EXT) 5709#define F_EXT V_EXT(1U) 5710 5711#define S_T3DBG 23 5712#define V_T3DBG(x) ((x) << S_T3DBG) 5713#define F_T3DBG V_T3DBG(1U) 5714 --- 72 unchanged lines hidden (view full) --- 5787#define S_PCIM0 1 5788#define V_PCIM0(x) ((x) << S_PCIM0) 5789#define F_PCIM0 V_PCIM0(1U) 5790 5791#define S_SGE3 0 5792#define V_SGE3(x) ((x) << S_SGE3) 5793#define F_SGE3 V_SGE3(1U) 5794 | 6346#define S_EXT 24 6347#define V_EXT(x) ((x) << S_EXT) 6348#define F_EXT V_EXT(1U) 6349 6350#define S_T3DBG 23 6351#define V_T3DBG(x) ((x) << S_T3DBG) 6352#define F_T3DBG V_T3DBG(1U) 6353 --- 72 unchanged lines hidden (view full) --- 6426#define S_PCIM0 1 6427#define V_PCIM0(x) ((x) << S_PCIM0) 6428#define F_PCIM0 V_PCIM0(1U) 6429 6430#define S_SGE3 0 6431#define V_SGE3(x) ((x) << S_SGE3) 6432#define F_SGE3 V_SGE3(1U) 6433 |
| 5795#define S_SW 25 5796#define V_SW(x) ((x) << S_SW) 5797#define F_SW V_SW(1U) 5798 | |
| 5799#define A_PL_INT_CAUSE0 0x6e4 5800#define A_PL_INT_ENABLE1 0x6e8 5801#define A_PL_INT_CAUSE1 0x6ec 5802#define A_PL_RST 0x6f0 5803 | 6434#define A_PL_INT_CAUSE0 0x6e4 6435#define A_PL_INT_ENABLE1 0x6e8 6436#define A_PL_INT_CAUSE1 0x6ec 6437#define A_PL_RST 0x6f0 6438 |
| 5804#define S_CRSTWRM 1 5805#define V_CRSTWRM(x) ((x) << S_CRSTWRM) 5806#define F_CRSTWRM V_CRSTWRM(1U) | 6439#define S_FATALPERREN 4 6440#define V_FATALPERREN(x) ((x) << S_FATALPERREN) 6441#define F_FATALPERREN V_FATALPERREN(1U) |
| 5807 5808#define S_SWINT1 3 5809#define V_SWINT1(x) ((x) << S_SWINT1) 5810#define F_SWINT1 V_SWINT1(1U) 5811 5812#define S_SWINT0 2 5813#define V_SWINT0(x) ((x) << S_SWINT0) 5814#define F_SWINT0 V_SWINT0(1U) 5815 | 6442 6443#define S_SWINT1 3 6444#define V_SWINT1(x) ((x) << S_SWINT1) 6445#define F_SWINT1 V_SWINT1(1U) 6446 6447#define S_SWINT0 2 6448#define V_SWINT0(x) ((x) << S_SWINT0) 6449#define F_SWINT0 V_SWINT0(1U) 6450 |
| 6451#define S_CRSTWRM 1 6452#define V_CRSTWRM(x) ((x) << S_CRSTWRM) 6453#define F_CRSTWRM V_CRSTWRM(1U) 6454 |
|
| 5816#define A_PL_REV 0x6f4 5817 5818#define S_REV 0 5819#define M_REV 0xf 5820#define V_REV(x) ((x) << S_REV) 5821#define G_REV(x) (((x) >> S_REV) & M_REV) 5822 5823#define A_PL_CLI 0x6f8 --- 32 unchanged lines hidden (view full) --- 5856#define S_GDDRI 26 5857#define V_GDDRI(x) ((x) << S_GDDRI) 5858#define F_GDDRI V_GDDRI(1U) 5859 5860#define S_READ 25 5861#define V_READ(x) ((x) << S_READ) 5862#define F_READ V_READ(1U) 5863 | 6455#define A_PL_REV 0x6f4 6456 6457#define S_REV 0 6458#define M_REV 0xf 6459#define V_REV(x) ((x) << S_REV) 6460#define G_REV(x) (((x) >> S_REV) & M_REV) 6461 6462#define A_PL_CLI 0x6f8 --- 32 unchanged lines hidden (view full) --- 6495#define S_GDDRI 26 6496#define V_GDDRI(x) ((x) << S_GDDRI) 6497#define F_GDDRI V_GDDRI(1U) 6498 6499#define S_READ 25 6500#define V_READ(x) ((x) << S_READ) 6501#define F_READ V_READ(1U) 6502 |
| 5864#define S_CAL_IMP_UPD 23 5865#define V_CAL_IMP_UPD(x) ((x) << S_CAL_IMP_UPD) 5866#define F_CAL_IMP_UPD V_CAL_IMP_UPD(1U) | 6503#define S_IMP_SET_UPDATE 24 6504#define V_IMP_SET_UPDATE(x) ((x) << S_IMP_SET_UPDATE) 6505#define F_IMP_SET_UPDATE V_IMP_SET_UPDATE(1U) |
| 5867 | 6506 |
| 6507#define S_CAL_UPDATE 23 6508#define V_CAL_UPDATE(x) ((x) << S_CAL_UPDATE) 6509#define F_CAL_UPDATE V_CAL_UPDATE(1U) 6510 |
|
| 5868#define S_CAL_BUSY 22 5869#define V_CAL_BUSY(x) ((x) << S_CAL_BUSY) 5870#define F_CAL_BUSY V_CAL_BUSY(1U) 5871 5872#define S_CAL_ERROR 21 5873#define V_CAL_ERROR(x) ((x) << S_CAL_ERROR) 5874#define F_CAL_ERROR V_CAL_ERROR(1U) 5875 --- 34 unchanged lines hidden (view full) --- 5910#define V_SET_PU(x) ((x) << S_SET_PU) 5911#define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU) 5912 5913#define S_SET_PD 0 5914#define M_SET_PD 0x7 5915#define V_SET_PD(x) ((x) << S_SET_PD) 5916#define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD) 5917 | 6511#define S_CAL_BUSY 22 6512#define V_CAL_BUSY(x) ((x) << S_CAL_BUSY) 6513#define F_CAL_BUSY V_CAL_BUSY(1U) 6514 6515#define S_CAL_ERROR 21 6516#define V_CAL_ERROR(x) ((x) << S_CAL_ERROR) 6517#define F_CAL_ERROR V_CAL_ERROR(1U) 6518 --- 34 unchanged lines hidden (view full) --- 6553#define V_SET_PU(x) ((x) << S_SET_PU) 6554#define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU) 6555 6556#define S_SET_PD 0 6557#define M_SET_PD 0x7 6558#define V_SET_PD(x) ((x) << S_SET_PD) 6559#define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD) 6560 |
| 5918#define S_IMP_SET_UPDATE 24 5919#define V_IMP_SET_UPDATE(x) ((x) << S_IMP_SET_UPDATE) 5920#define F_IMP_SET_UPDATE V_IMP_SET_UPDATE(1U) | 6561#define S_CAL_IMP_UPD 23 6562#define V_CAL_IMP_UPD(x) ((x) << S_CAL_IMP_UPD) 6563#define F_CAL_IMP_UPD V_CAL_IMP_UPD(1U) |
| 5921 | 6564 |
| 5922#define S_CAL_UPDATE 23 5923#define V_CAL_UPDATE(x) ((x) << S_CAL_UPDATE) 5924#define F_CAL_UPDATE V_CAL_UPDATE(1U) 5925 | |
| 5926#define A_MC5_DB_CONFIG 0x704 5927 5928#define S_TMCFGWRLOCK 31 5929#define V_TMCFGWRLOCK(x) ((x) << S_TMCFGWRLOCK) 5930#define F_TMCFGWRLOCK V_TMCFGWRLOCK(1U) 5931 5932#define S_TMTYPEHI 30 5933#define V_TMTYPEHI(x) ((x) << S_TMTYPEHI) --- 22 unchanged lines hidden (view full) --- 5956#define S_COMPEN 17 5957#define V_COMPEN(x) ((x) << S_COMPEN) 5958#define F_COMPEN V_COMPEN(1U) 5959 5960#define S_BUILD 16 5961#define V_BUILD(x) ((x) << S_BUILD) 5962#define F_BUILD V_BUILD(1U) 5963 | 6565#define A_MC5_DB_CONFIG 0x704 6566 6567#define S_TMCFGWRLOCK 31 6568#define V_TMCFGWRLOCK(x) ((x) << S_TMCFGWRLOCK) 6569#define F_TMCFGWRLOCK V_TMCFGWRLOCK(1U) 6570 6571#define S_TMTYPEHI 30 6572#define V_TMTYPEHI(x) ((x) << S_TMTYPEHI) --- 22 unchanged lines hidden (view full) --- 6595#define S_COMPEN 17 6596#define V_COMPEN(x) ((x) << S_COMPEN) 6597#define F_COMPEN V_COMPEN(1U) 6598 6599#define S_BUILD 16 6600#define V_BUILD(x) ((x) << S_BUILD) 6601#define F_BUILD V_BUILD(1U) 6602 |
| 6603#define S_FILTEREN 11 6604#define V_FILTEREN(x) ((x) << S_FILTEREN) 6605#define F_FILTEREN V_FILTEREN(1U) 6606 6607#define S_CLIPUPDATE 10 6608#define V_CLIPUPDATE(x) ((x) << S_CLIPUPDATE) 6609#define F_CLIPUPDATE V_CLIPUPDATE(1U) 6610 |
|
| 5964#define S_TM_IO_PDOWN 9 5965#define V_TM_IO_PDOWN(x) ((x) << S_TM_IO_PDOWN) 5966#define F_TM_IO_PDOWN V_TM_IO_PDOWN(1U) 5967 5968#define S_SYNMODE 7 5969#define M_SYNMODE 0x3 5970#define V_SYNMODE(x) ((x) << S_SYNMODE) 5971#define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE) --- 5 unchanged lines hidden (view full) --- 5977#define S_MBUSEN 5 5978#define V_MBUSEN(x) ((x) << S_MBUSEN) 5979#define F_MBUSEN V_MBUSEN(1U) 5980 5981#define S_DBGIEN 4 5982#define V_DBGIEN(x) ((x) << S_DBGIEN) 5983#define F_DBGIEN V_DBGIEN(1U) 5984 | 6611#define S_TM_IO_PDOWN 9 6612#define V_TM_IO_PDOWN(x) ((x) << S_TM_IO_PDOWN) 6613#define F_TM_IO_PDOWN V_TM_IO_PDOWN(1U) 6614 6615#define S_SYNMODE 7 6616#define M_SYNMODE 0x3 6617#define V_SYNMODE(x) ((x) << S_SYNMODE) 6618#define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE) --- 5 unchanged lines hidden (view full) --- 6624#define S_MBUSEN 5 6625#define V_MBUSEN(x) ((x) << S_MBUSEN) 6626#define F_MBUSEN V_MBUSEN(1U) 6627 6628#define S_DBGIEN 4 6629#define V_DBGIEN(x) ((x) << S_DBGIEN) 6630#define F_DBGIEN V_DBGIEN(1U) 6631 |
| 6632#define S_TCMCFGOVR 3 6633#define V_TCMCFGOVR(x) ((x) << S_TCMCFGOVR) 6634#define F_TCMCFGOVR V_TCMCFGOVR(1U) 6635 |
|
| 5985#define S_TMRDY 2 5986#define V_TMRDY(x) ((x) << S_TMRDY) 5987#define F_TMRDY V_TMRDY(1U) 5988 5989#define S_TMRST 1 5990#define V_TMRST(x) ((x) << S_TMRST) 5991#define F_TMRST V_TMRST(1U) 5992 5993#define S_TMMODE 0 5994#define V_TMMODE(x) ((x) << S_TMMODE) 5995#define F_TMMODE V_TMMODE(1U) 5996 | 6636#define S_TMRDY 2 6637#define V_TMRDY(x) ((x) << S_TMRDY) 6638#define F_TMRDY V_TMRDY(1U) 6639 6640#define S_TMRST 1 6641#define V_TMRST(x) ((x) << S_TMRST) 6642#define F_TMRST V_TMRST(1U) 6643 6644#define S_TMMODE 0 6645#define V_TMMODE(x) ((x) << S_TMMODE) 6646#define F_TMMODE V_TMMODE(1U) 6647 |
| 5997#define S_FILTEREN 11 5998#define V_FILTEREN(x) ((x) << S_FILTEREN) 5999#define F_FILTEREN V_FILTEREN(1U) 6000 6001#define S_CLIPUPDATE 10 6002#define V_CLIPUPDATE(x) ((x) << S_CLIPUPDATE) 6003#define F_CLIPUPDATE V_CLIPUPDATE(1U) 6004 6005#define S_TCMCFGOVR 3 6006#define V_TCMCFGOVR(x) ((x) << S_TCMCFGOVR) 6007#define F_TCMCFGOVR V_TCMCFGOVR(1U) 6008 | |
| 6009#define A_MC5_MISC 0x708 6010 6011#define S_LIP_CMP_UNAVAILABLE 0 6012#define M_LIP_CMP_UNAVAILABLE 0xf 6013#define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE) 6014#define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE) 6015 6016#define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c 6017 6018#define S_RTINDX 0 6019#define M_RTINDX 0x3fffff 6020#define V_RTINDX(x) ((x) << S_RTINDX) 6021#define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX) 6022 6023#define A_MC5_DB_FILTER_TABLE 0x710 | 6648#define A_MC5_MISC 0x708 6649 6650#define S_LIP_CMP_UNAVAILABLE 0 6651#define M_LIP_CMP_UNAVAILABLE 0xf 6652#define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE) 6653#define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE) 6654 6655#define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c 6656 6657#define S_RTINDX 0 6658#define M_RTINDX 0x3fffff 6659#define V_RTINDX(x) ((x) << S_RTINDX) 6660#define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX) 6661 6662#define A_MC5_DB_FILTER_TABLE 0x710 |
| 6024#define A_MC5_DB_SERVER_INDEX 0x714 | |
| 6025 6026#define S_SRINDX 0 6027#define M_SRINDX 0x3fffff 6028#define V_SRINDX(x) ((x) << S_SRINDX) 6029#define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX) 6030 | 6663 6664#define S_SRINDX 0 6665#define M_SRINDX 0x3fffff 6666#define V_SRINDX(x) ((x) << S_SRINDX) 6667#define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX) 6668 |
| 6669#define A_MC5_DB_SERVER_INDEX 0x714 |
|
| 6031#define A_MC5_DB_LIP_RAM_ADDR 0x718 6032 6033#define S_RAMWR 8 6034#define V_RAMWR(x) ((x) << S_RAMWR) 6035#define F_RAMWR V_RAMWR(1U) 6036 6037#define S_RAMADDR 0 6038#define M_RAMADDR 0x3f --- 71 unchanged lines hidden (view full) --- 6110#define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL) 6111#define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL) 6112 6113#define S_CLIPMAPADDR 0 6114#define M_CLIPMAPADDR 0x3f 6115#define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR) 6116#define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR) 6117 | 6670#define A_MC5_DB_LIP_RAM_ADDR 0x718 6671 6672#define S_RAMWR 8 6673#define V_RAMWR(x) ((x) << S_RAMWR) 6674#define F_RAMWR V_RAMWR(1U) 6675 6676#define S_RAMADDR 0 6677#define M_RAMADDR 0x3f --- 71 unchanged lines hidden (view full) --- 6749#define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL) 6750#define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL) 6751 6752#define S_CLIPMAPADDR 0 6753#define M_CLIPMAPADDR 0x3f 6754#define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR) 6755#define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR) 6756 |
| 6757#define A_MC5_DB_SIZE 0x73c |
|
| 6118#define A_MC5_DB_INT_ENABLE 0x740 6119 6120#define S_MSGSEL 28 6121#define M_MSGSEL 0xf 6122#define V_MSGSEL(x) ((x) << S_MSGSEL) 6123#define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL) 6124 6125#define S_DELACTEMPTY 18 --- 499 unchanged lines hidden (view full) --- 6625#define F_INCRSTATS V_INCRSTATS(1U) 6626 6627#define S_ENTESTMODEWR 0 6628#define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR) 6629#define F_ENTESTMODEWR V_ENTESTMODEWR(1U) 6630 6631#define A_XGM_RXFIFO_CFG 0x884 6632 | 6758#define A_MC5_DB_INT_ENABLE 0x740 6759 6760#define S_MSGSEL 28 6761#define M_MSGSEL 0xf 6762#define V_MSGSEL(x) ((x) << S_MSGSEL) 6763#define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL) 6764 6765#define S_DELACTEMPTY 18 --- 499 unchanged lines hidden (view full) --- 7265#define F_INCRSTATS V_INCRSTATS(1U) 7266 7267#define S_ENTESTMODEWR 0 7268#define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR) 7269#define F_ENTESTMODEWR V_ENTESTMODEWR(1U) 7270 7271#define A_XGM_RXFIFO_CFG 0x884 7272 |
| 7273#define S_RXFIFO_EMPTY 31 7274#define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY) 7275#define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U) 7276 7277#define S_RXFIFO_FULL 30 7278#define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL) 7279#define F_RXFIFO_FULL V_RXFIFO_FULL(1U) 7280 |
|
| 6633#define S_RXFIFOPAUSEHWM 17 6634#define M_RXFIFOPAUSEHWM 0xfff 6635#define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM) 6636#define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM) 6637 6638#define S_RXFIFOPAUSELWM 5 6639#define M_RXFIFOPAUSELWM 0xfff 6640#define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM) --- 16 unchanged lines hidden (view full) --- 6657#define F_RXSTRFRWRD V_RXSTRFRWRD(1U) 6658 6659#define S_DISERRFRAMES 0 6660#define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES) 6661#define F_DISERRFRAMES V_DISERRFRAMES(1U) 6662 6663#define A_XGM_TXFIFO_CFG 0x888 6664 | 7281#define S_RXFIFOPAUSEHWM 17 7282#define M_RXFIFOPAUSEHWM 0xfff 7283#define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM) 7284#define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM) 7285 7286#define S_RXFIFOPAUSELWM 5 7287#define M_RXFIFOPAUSELWM 0xfff 7288#define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM) --- 16 unchanged lines hidden (view full) --- 7305#define F_RXSTRFRWRD V_RXSTRFRWRD(1U) 7306 7307#define S_DISERRFRAMES 0 7308#define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES) 7309#define F_DISERRFRAMES V_DISERRFRAMES(1U) 7310 7311#define A_XGM_TXFIFO_CFG 0x888 7312 |
| 7313#define S_TXFIFO_EMPTY 31 7314#define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY) 7315#define F_TXFIFO_EMPTY V_TXFIFO_EMPTY(1U) 7316 7317#define S_TXFIFO_FULL 30 7318#define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL) 7319#define F_TXFIFO_FULL V_TXFIFO_FULL(1U) 7320 7321#define S_UNDERUNFIX 22 7322#define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX) 7323#define F_UNDERUNFIX V_UNDERUNFIX(1U) 7324 7325#define S_ENDROPPKT 21 7326#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT) 7327#define F_ENDROPPKT V_ENDROPPKT(1U) 7328 |
|
| 6665#define S_TXIPG 13 6666#define M_TXIPG 0xff 6667#define V_TXIPG(x) ((x) << S_TXIPG) 6668#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG) 6669 6670#define S_TXFIFOTHRESH 4 6671#define M_TXFIFOTHRESH 0x1ff 6672#define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH) --- 10 unchanged lines hidden (view full) --- 6683#define S_DISCRC 1 6684#define V_DISCRC(x) ((x) << S_DISCRC) 6685#define F_DISCRC V_DISCRC(1U) 6686 6687#define S_DISPREAMBLE 0 6688#define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE) 6689#define F_DISPREAMBLE V_DISPREAMBLE(1U) 6690 | 7329#define S_TXIPG 13 7330#define M_TXIPG 0xff 7331#define V_TXIPG(x) ((x) << S_TXIPG) 7332#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG) 7333 7334#define S_TXFIFOTHRESH 4 7335#define M_TXFIFOTHRESH 0x1ff 7336#define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH) --- 10 unchanged lines hidden (view full) --- 7347#define S_DISCRC 1 7348#define V_DISCRC(x) ((x) << S_DISCRC) 7349#define F_DISCRC V_DISCRC(1U) 7350 7351#define S_DISPREAMBLE 0 7352#define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE) 7353#define F_DISPREAMBLE V_DISPREAMBLE(1U) 7354 |
| 6691#define S_ENDROPPKT 21 6692#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT) 6693#define F_ENDROPPKT V_ENDROPPKT(1U) 6694 | |
| 6695#define A_XGM_SLOW_TIMER 0x88c 6696 6697#define S_PAUSESLOWTIMEREN 31 6698#define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN) 6699#define F_PAUSESLOWTIMEREN V_PAUSESLOWTIMEREN(1U) 6700 6701#define S_PAUSESLOWTIMER 0 6702#define M_PAUSESLOWTIMER 0xfffff 6703#define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER) 6704#define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER) 6705 | 7355#define A_XGM_SLOW_TIMER 0x88c 7356 7357#define S_PAUSESLOWTIMEREN 31 7358#define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN) 7359#define F_PAUSESLOWTIMEREN V_PAUSESLOWTIMEREN(1U) 7360 7361#define S_PAUSESLOWTIMER 0 7362#define M_PAUSESLOWTIMER 0xfffff 7363#define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER) 7364#define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER) 7365 |
| 7366#define A_XGM_PAUSE_TIMER 0x890 7367 7368#define S_PAUSETIMER 0 7369#define M_PAUSETIMER 0xfffff 7370#define V_PAUSETIMER(x) ((x) << S_PAUSETIMER) 7371#define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER) 7372 |
|
| 6706#define A_XGM_SERDES_CTRL 0x890 6707 6708#define S_SERDESEN 25 6709#define V_SERDESEN(x) ((x) << S_SERDESEN) 6710#define F_SERDESEN V_SERDESEN(1U) 6711 6712#define S_SERDESRESET_ 24 6713#define V_SERDESRESET_(x) ((x) << S_SERDESRESET_) --- 42 unchanged lines hidden (view full) --- 6756#define S_RXENABLE 4 6757#define V_RXENABLE(x) ((x) << S_RXENABLE) 6758#define F_RXENABLE V_RXENABLE(1U) 6759 6760#define S_TXENABLE 3 6761#define V_TXENABLE(x) ((x) << S_TXENABLE) 6762#define F_TXENABLE V_TXENABLE(1U) 6763 | 7373#define A_XGM_SERDES_CTRL 0x890 7374 7375#define S_SERDESEN 25 7376#define V_SERDESEN(x) ((x) << S_SERDESEN) 7377#define F_SERDESEN V_SERDESEN(1U) 7378 7379#define S_SERDESRESET_ 24 7380#define V_SERDESRESET_(x) ((x) << S_SERDESRESET_) --- 42 unchanged lines hidden (view full) --- 7423#define S_RXENABLE 4 7424#define V_RXENABLE(x) ((x) << S_RXENABLE) 7425#define F_RXENABLE V_RXENABLE(1U) 7426 7427#define S_TXENABLE 3 7428#define V_TXENABLE(x) ((x) << S_TXENABLE) 7429#define F_TXENABLE V_TXENABLE(1U) 7430 |
| 6764#define A_XGM_PAUSE_TIMER 0x890 6765 6766#define S_PAUSETIMER 0 6767#define M_PAUSETIMER 0xfffff 6768#define V_PAUSETIMER(x) ((x) << S_PAUSETIMER) 6769#define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER) 6770 | |
| 6771#define A_XGM_XAUI_PCS_TEST 0x894 6772 6773#define S_TESTPATTERN 1 6774#define M_TESTPATTERN 0x3 6775#define V_TESTPATTERN(x) ((x) << S_TESTPATTERN) 6776#define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN) 6777 6778#define S_ENTEST 0 --- 8 unchanged lines hidden (view full) --- 6787#define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH) 6788 6789#define S_TXCLK90SHIFT 0 6790#define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT) 6791#define F_TXCLK90SHIFT V_TXCLK90SHIFT(1U) 6792 6793#define A_XGM_RGMII_IMP 0x89c 6794 | 7431#define A_XGM_XAUI_PCS_TEST 0x894 7432 7433#define S_TESTPATTERN 1 7434#define M_TESTPATTERN 0x3 7435#define V_TESTPATTERN(x) ((x) << S_TESTPATTERN) 7436#define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN) 7437 7438#define S_ENTEST 0 --- 8 unchanged lines hidden (view full) --- 7447#define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH) 7448 7449#define S_TXCLK90SHIFT 0 7450#define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT) 7451#define F_TXCLK90SHIFT V_TXCLK90SHIFT(1U) 7452 7453#define A_XGM_RGMII_IMP 0x89c 7454 |
| 7455#define S_CALRESET 8 7456#define V_CALRESET(x) ((x) << S_CALRESET) 7457#define F_CALRESET V_CALRESET(1U) 7458 7459#define S_CALUPDATE 7 7460#define V_CALUPDATE(x) ((x) << S_CALUPDATE) 7461#define F_CALUPDATE V_CALUPDATE(1U) 7462 |
|
| 6795#define S_XGM_IMPSETUPDATE 6 6796#define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE) 6797#define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U) 6798 6799#define S_RGMIIIMPPD 3 6800#define M_RGMIIIMPPD 0x7 6801#define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD) 6802#define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD) 6803 6804#define S_RGMIIIMPPU 0 6805#define M_RGMIIIMPPU 0x7 6806#define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU) 6807#define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU) 6808 | 7463#define S_XGM_IMPSETUPDATE 6 7464#define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE) 7465#define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U) 7466 7467#define S_RGMIIIMPPD 3 7468#define M_RGMIIIMPPD 0x7 7469#define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD) 7470#define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD) 7471 7472#define S_RGMIIIMPPU 0 7473#define M_RGMIIIMPPU 0x7 7474#define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU) 7475#define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU) 7476 |
| 6809#define S_CALRESET 8 6810#define V_CALRESET(x) ((x) << S_CALRESET) 6811#define F_CALRESET V_CALRESET(1U) 6812 6813#define S_CALUPDATE 7 6814#define V_CALUPDATE(x) ((x) << S_CALUPDATE) 6815#define F_CALUPDATE V_CALUPDATE(1U) 6816 | |
| 6817#define A_XGM_XAUI_IMP 0x8a0 6818 6819#define S_XGM_CALFAULT 29 6820#define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT) 6821#define F_XGM_CALFAULT V_XGM_CALFAULT(1U) 6822 6823#define S_CALIMP 24 6824#define M_CALIMP 0x1f --- 14 unchanged lines hidden (view full) --- 6839 6840#define S_BISTCYCLETHRESH 3 6841#define M_BISTCYCLETHRESH 0x1ffff 6842#define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH) 6843#define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH) 6844 6845#define A_XGM_RX_MAX_PKT_SIZE 0x8a8 6846 | 7477#define A_XGM_XAUI_IMP 0x8a0 7478 7479#define S_XGM_CALFAULT 29 7480#define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT) 7481#define F_XGM_CALFAULT V_XGM_CALFAULT(1U) 7482 7483#define S_CALIMP 24 7484#define M_CALIMP 0x1f --- 14 unchanged lines hidden (view full) --- 7499 7500#define S_BISTCYCLETHRESH 3 7501#define M_BISTCYCLETHRESH 0x1ffff 7502#define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH) 7503#define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH) 7504 7505#define A_XGM_RX_MAX_PKT_SIZE 0x8a8 7506 |
| 7507#define S_RXMAXFRAMERSIZE 17 7508#define M_RXMAXFRAMERSIZE 0x3fff 7509#define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE) 7510#define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE) 7511 7512#define S_RXENERRORGATHER 16 7513#define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER) 7514#define F_RXENERRORGATHER V_RXENERRORGATHER(1U) 7515 7516#define S_RXENSINGLEFLIT 15 7517#define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT) 7518#define F_RXENSINGLEFLIT V_RXENSINGLEFLIT(1U) 7519 7520#define S_RXENFRAMER 14 7521#define V_RXENFRAMER(x) ((x) << S_RXENFRAMER) 7522#define F_RXENFRAMER V_RXENFRAMER(1U) 7523 |
|
| 6847#define S_RXMAXPKTSIZE 0 6848#define M_RXMAXPKTSIZE 0x3fff 6849#define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE) 6850#define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE) 6851 6852#define A_XGM_RESET_CTRL 0x8ac 6853 | 7524#define S_RXMAXPKTSIZE 0 7525#define M_RXMAXPKTSIZE 0x3fff 7526#define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE) 7527#define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE) 7528 7529#define A_XGM_RESET_CTRL 0x8ac 7530 |
| 7531#define S_XGMAC_STOP_EN 4 7532#define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN) 7533#define F_XGMAC_STOP_EN V_XGMAC_STOP_EN(1U) 7534 |
|
| 6854#define S_XG2G_RESET_ 3 6855#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_) 6856#define F_XG2G_RESET_ V_XG2G_RESET_(1U) 6857 6858#define S_RGMII_RESET_ 2 6859#define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_) 6860#define F_RGMII_RESET_ V_RGMII_RESET_(1U) 6861 --- 63 unchanged lines hidden (view full) --- 6925 6926#define S_PIO_ADDRESS 0 6927#define M_PIO_ADDRESS 0xff 6928#define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS) 6929#define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS) 6930 6931#define A_XGM_INT_ENABLE 0x8d4 6932 | 7535#define S_XG2G_RESET_ 3 7536#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_) 7537#define F_XG2G_RESET_ V_XG2G_RESET_(1U) 7538 7539#define S_RGMII_RESET_ 2 7540#define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_) 7541#define F_RGMII_RESET_ V_RGMII_RESET_(1U) 7542 --- 63 unchanged lines hidden (view full) --- 7606 7607#define S_PIO_ADDRESS 0 7608#define M_PIO_ADDRESS 0xff 7609#define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS) 7610#define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS) 7611 7612#define A_XGM_INT_ENABLE 0x8d4 7613 |
| 6933#define S_SERDESCMULOCK_LOSS 24 6934#define V_SERDESCMULOCK_LOSS(x) ((x) << S_SERDESCMULOCK_LOSS) 6935#define F_SERDESCMULOCK_LOSS V_SERDESCMULOCK_LOSS(1U) | 7614#define S_XAUIPCSDECERR 24 7615#define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR) 7616#define F_XAUIPCSDECERR V_XAUIPCSDECERR(1U) |
| 6936 6937#define S_RGMIIRXFIFOOVERFLOW 23 6938#define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW) 6939#define F_RGMIIRXFIFOOVERFLOW V_RGMIIRXFIFOOVERFLOW(1U) 6940 6941#define S_RGMIIRXFIFOUNDERFLOW 22 6942#define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW) 6943#define F_RGMIIRXFIFOUNDERFLOW V_RGMIIRXFIFOUNDERFLOW(1U) --- 19 unchanged lines hidden (view full) --- 6963#define S_TXFIFO_UNDERRUN 13 6964#define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN) 6965#define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U) 6966 6967#define S_RXFIFO_OVERFLOW 12 6968#define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW) 6969#define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U) 6970 | 7617 7618#define S_RGMIIRXFIFOOVERFLOW 23 7619#define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW) 7620#define F_RGMIIRXFIFOOVERFLOW V_RGMIIRXFIFOOVERFLOW(1U) 7621 7622#define S_RGMIIRXFIFOUNDERFLOW 22 7623#define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW) 7624#define F_RGMIIRXFIFOUNDERFLOW V_RGMIIRXFIFOUNDERFLOW(1U) --- 19 unchanged lines hidden (view full) --- 7644#define S_TXFIFO_UNDERRUN 13 7645#define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN) 7646#define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U) 7647 7648#define S_RXFIFO_OVERFLOW 12 7649#define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW) 7650#define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U) 7651 |
| 6971#define S_SERDESBIST_ERR 8 6972#define M_SERDESBIST_ERR 0xf 6973#define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR) 6974#define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR) | 7652#define S_SERDESBISTERR 8 7653#define M_SERDESBISTERR 0xf 7654#define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR) 7655#define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR) |
| 6975 | 7656 |
| 6976#define S_SERDES_LOS 4 6977#define M_SERDES_LOS 0xf 6978#define V_SERDES_LOS(x) ((x) << S_SERDES_LOS) 6979#define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS) | 7657#define S_SERDESLOWSIGCHANGE 4 7658#define M_SERDESLOWSIGCHANGE 0xf 7659#define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE) 7660#define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE) |
| 6980 6981#define S_XAUIPCSCTCERR 3 6982#define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR) 6983#define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U) 6984 6985#define S_XAUIPCSALIGNCHANGE 2 6986#define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE) 6987#define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U) 6988 6989#define S_RGMIILINKSTSCHANGE 1 6990#define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE) 6991#define F_RGMIILINKSTSCHANGE V_RGMIILINKSTSCHANGE(1U) 6992 6993#define S_XGM_INT 0 6994#define V_XGM_INT(x) ((x) << S_XGM_INT) 6995#define F_XGM_INT V_XGM_INT(1U) 6996 | 7661 7662#define S_XAUIPCSCTCERR 3 7663#define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR) 7664#define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U) 7665 7666#define S_XAUIPCSALIGNCHANGE 2 7667#define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE) 7668#define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U) 7669 7670#define S_RGMIILINKSTSCHANGE 1 7671#define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE) 7672#define F_RGMIILINKSTSCHANGE V_RGMIILINKSTSCHANGE(1U) 7673 7674#define S_XGM_INT 0 7675#define V_XGM_INT(x) ((x) << S_XGM_INT) 7676#define F_XGM_INT V_XGM_INT(1U) 7677 |
| 6997#define S_SERDESBISTERR 8 6998#define M_SERDESBISTERR 0xf 6999#define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR) 7000#define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR) | 7678#define S_SERDESCMULOCK_LOSS 24 7679#define V_SERDESCMULOCK_LOSS(x) ((x) << S_SERDESCMULOCK_LOSS) 7680#define F_SERDESCMULOCK_LOSS V_SERDESCMULOCK_LOSS(1U) |
| 7001 | 7681 |
| 7002#define S_SERDESLOWSIGCHANGE 4 7003#define M_SERDESLOWSIGCHANGE 0xf 7004#define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE) 7005#define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE) | 7682#define S_SERDESBIST_ERR 8 7683#define M_SERDESBIST_ERR 0xf 7684#define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR) 7685#define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR) |
| 7006 | 7686 |
| 7687#define S_SERDES_LOS 4 7688#define M_SERDES_LOS 0xf 7689#define V_SERDES_LOS(x) ((x) << S_SERDES_LOS) 7690#define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS) 7691 |
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| 7007#define A_XGM_INT_CAUSE 0x8d8 7008#define A_XGM_XAUI_ACT_CTRL 0x8dc 7009 7010#define S_TXACTENABLE 1 7011#define V_TXACTENABLE(x) ((x) << S_TXACTENABLE) 7012#define F_TXACTENABLE V_TXACTENABLE(1U) 7013 7014#define A_XGM_SERDES_CTRL0 0x8e0 --- 278 unchanged lines hidden (view full) --- 7293#define M_EXTBISTCHKERRCNT0 0xffffff 7294#define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0) 7295#define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0) 7296 7297#define S_EXTBISTCHKFMD0 3 7298#define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0) 7299#define F_EXTBISTCHKFMD0 V_EXTBISTCHKFMD0(1U) 7300 | 7692#define A_XGM_INT_CAUSE 0x8d8 7693#define A_XGM_XAUI_ACT_CTRL 0x8dc 7694 7695#define S_TXACTENABLE 1 7696#define V_TXACTENABLE(x) ((x) << S_TXACTENABLE) 7697#define F_TXACTENABLE V_TXACTENABLE(1U) 7698 7699#define A_XGM_SERDES_CTRL0 0x8e0 --- 278 unchanged lines hidden (view full) --- 7978#define M_EXTBISTCHKERRCNT0 0xffffff 7979#define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0) 7980#define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0) 7981 7982#define S_EXTBISTCHKFMD0 3 7983#define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0) 7984#define F_EXTBISTCHKFMD0 V_EXTBISTCHKFMD0(1U) 7985 |
| 7986#define S_LOWSIGFORCEEN0 2 7987#define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0) 7988#define F_LOWSIGFORCEEN0 V_LOWSIGFORCEEN0(1U) 7989 7990#define S_LOWSIGFORCEVALUE0 1 7991#define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0) 7992#define F_LOWSIGFORCEVALUE0 V_LOWSIGFORCEVALUE0(1U) 7993 |
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| 7301#define S_LOWSIG0 0 7302#define V_LOWSIG0(x) ((x) << S_LOWSIG0) 7303#define F_LOWSIG0 V_LOWSIG0(1U) 7304 7305#define A_XGM_SERDES_STAT1 0x8f4 7306 7307#define S_EXTBISTCHKERRCNT1 4 7308#define M_EXTBISTCHKERRCNT1 0xffffff 7309#define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1) 7310#define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1) 7311 7312#define S_EXTBISTCHKFMD1 3 7313#define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1) 7314#define F_EXTBISTCHKFMD1 V_EXTBISTCHKFMD1(1U) 7315 | 7994#define S_LOWSIG0 0 7995#define V_LOWSIG0(x) ((x) << S_LOWSIG0) 7996#define F_LOWSIG0 V_LOWSIG0(1U) 7997 7998#define A_XGM_SERDES_STAT1 0x8f4 7999 8000#define S_EXTBISTCHKERRCNT1 4 8001#define M_EXTBISTCHKERRCNT1 0xffffff 8002#define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1) 8003#define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1) 8004 8005#define S_EXTBISTCHKFMD1 3 8006#define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1) 8007#define F_EXTBISTCHKFMD1 V_EXTBISTCHKFMD1(1U) 8008 |
| 8009#define S_LOWSIGFORCEEN1 2 8010#define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1) 8011#define F_LOWSIGFORCEEN1 V_LOWSIGFORCEEN1(1U) 8012 8013#define S_LOWSIGFORCEVALUE1 1 8014#define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1) 8015#define F_LOWSIGFORCEVALUE1 V_LOWSIGFORCEVALUE1(1U) 8016 |
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| 7316#define S_LOWSIG1 0 7317#define V_LOWSIG1(x) ((x) << S_LOWSIG1) 7318#define F_LOWSIG1 V_LOWSIG1(1U) 7319 7320#define A_XGM_SERDES_STAT2 0x8f8 7321 7322#define S_EXTBISTCHKERRCNT2 4 7323#define M_EXTBISTCHKERRCNT2 0xffffff 7324#define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2) 7325#define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2) 7326 7327#define S_EXTBISTCHKFMD2 3 7328#define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2) 7329#define F_EXTBISTCHKFMD2 V_EXTBISTCHKFMD2(1U) 7330 | 8017#define S_LOWSIG1 0 8018#define V_LOWSIG1(x) ((x) << S_LOWSIG1) 8019#define F_LOWSIG1 V_LOWSIG1(1U) 8020 8021#define A_XGM_SERDES_STAT2 0x8f8 8022 8023#define S_EXTBISTCHKERRCNT2 4 8024#define M_EXTBISTCHKERRCNT2 0xffffff 8025#define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2) 8026#define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2) 8027 8028#define S_EXTBISTCHKFMD2 3 8029#define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2) 8030#define F_EXTBISTCHKFMD2 V_EXTBISTCHKFMD2(1U) 8031 |
| 8032#define S_LOWSIGFORCEEN2 2 8033#define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2) 8034#define F_LOWSIGFORCEEN2 V_LOWSIGFORCEEN2(1U) 8035 8036#define S_LOWSIGFORCEVALUE2 1 8037#define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2) 8038#define F_LOWSIGFORCEVALUE2 V_LOWSIGFORCEVALUE2(1U) 8039 |
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| 7331#define S_LOWSIG2 0 7332#define V_LOWSIG2(x) ((x) << S_LOWSIG2) 7333#define F_LOWSIG2 V_LOWSIG2(1U) 7334 7335#define A_XGM_SERDES_STAT3 0x8fc 7336 7337#define S_EXTBISTCHKERRCNT3 4 7338#define M_EXTBISTCHKERRCNT3 0xffffff 7339#define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3) 7340#define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3) 7341 7342#define S_EXTBISTCHKFMD3 3 7343#define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3) 7344#define F_EXTBISTCHKFMD3 V_EXTBISTCHKFMD3(1U) 7345 | 8040#define S_LOWSIG2 0 8041#define V_LOWSIG2(x) ((x) << S_LOWSIG2) 8042#define F_LOWSIG2 V_LOWSIG2(1U) 8043 8044#define A_XGM_SERDES_STAT3 0x8fc 8045 8046#define S_EXTBISTCHKERRCNT3 4 8047#define M_EXTBISTCHKERRCNT3 0xffffff 8048#define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3) 8049#define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3) 8050 8051#define S_EXTBISTCHKFMD3 3 8052#define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3) 8053#define F_EXTBISTCHKFMD3 V_EXTBISTCHKFMD3(1U) 8054 |
| 8055#define S_LOWSIGFORCEEN3 2 8056#define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3) 8057#define F_LOWSIGFORCEEN3 V_LOWSIGFORCEEN3(1U) 8058 8059#define S_LOWSIGFORCEVALUE3 1 8060#define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3) 8061#define F_LOWSIGFORCEVALUE3 V_LOWSIGFORCEVALUE3(1U) 8062 |
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| 7346#define S_LOWSIG3 0 7347#define V_LOWSIG3(x) ((x) << S_LOWSIG3) 7348#define F_LOWSIG3 V_LOWSIG3(1U) 7349 7350#define A_XGM_STAT_TX_BYTE_LOW 0x900 7351#define A_XGM_STAT_TX_BYTE_HIGH 0x904 7352 7353#define S_TXBYTES_HIGH 0 --- 288 unchanged lines hidden --- | 8063#define S_LOWSIG3 0 8064#define V_LOWSIG3(x) ((x) << S_LOWSIG3) 8065#define F_LOWSIG3 V_LOWSIG3(1U) 8066 8067#define A_XGM_STAT_TX_BYTE_LOW 0x900 8068#define A_XGM_STAT_TX_BYTE_HIGH 0x904 8069 8070#define S_TXBYTES_HIGH 0 --- 288 unchanged lines hidden --- |