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cxgb_common.h (170654) cxgb_common.h (171471)
1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_common.h 170654 2007-06-13 05:36:00Z kmacy $
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_common.h 171471 2007-07-17 06:50:35Z kmacy $
29
30***************************************************************************/
31#ifndef __CHELSIO_COMMON_H
32#define __CHELSIO_COMMON_H
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_osdep.h>
36#else
37#include <dev/cxgb/cxgb_osdep.h>
38#endif
39
40enum {
29
30***************************************************************************/
31#ifndef __CHELSIO_COMMON_H
32#define __CHELSIO_COMMON_H
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_osdep.h>
36#else
37#include <dev/cxgb/cxgb_osdep.h>
38#endif
39
40enum {
41 MAX_NPORTS = 4,
42 TP_TMR_RES = 200, /* TP timer resolution in usec */
43 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
44 EEPROMSIZE = 8192, /* Serial EEPROM size */
45 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
46 TCB_SIZE = 128, /* TCB size */
47 NMTUS = 16, /* size of MTU table */
48 NCCTRL_WIN = 32, /* # of congestion control windows */
49 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
50 PROTO_SRAM_LINES = 128, /* size of protocol sram */
41 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
42 EEPROMSIZE = 8192, /* Serial EEPROM size */
43 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
44 TCB_SIZE = 128, /* TCB size */
45 NMTUS = 16, /* size of MTU table */
46 NCCTRL_WIN = 32, /* # of congestion control windows */
47 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
48 PROTO_SRAM_LINES = 128, /* size of protocol sram */
49 MAX_NPORTS = 4,
50 TP_TMR_RES = 200,
51 TP_SRAM_OFFSET = 4096, /* TP SRAM content offset in eeprom */
52 TP_SRAM_LEN = 2112, /* TP SRAM content offset in eeprom */
51};
52
53#define MAX_RX_COALESCING_LEN 12288U
54
55enum {
56 PAUSE_RX = 1 << 0,
57 PAUSE_TX = 1 << 1,
58 PAUSE_AUTONEG = 1 << 2

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67 STAT_ULP_CH1_PBL_OOB,
68 STAT_PCI_CORR_ECC,
69
70 IRQ_NUM_STATS /* keep last */
71};
72
73enum {
74 TP_VERSION_MAJOR = 1,
53};
54
55#define MAX_RX_COALESCING_LEN 12288U
56
57enum {
58 PAUSE_RX = 1 << 0,
59 PAUSE_TX = 1 << 1,
60 PAUSE_AUTONEG = 1 << 2

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69 STAT_ULP_CH1_PBL_OOB,
70 STAT_PCI_CORR_ECC,
71
72 IRQ_NUM_STATS /* keep last */
73};
74
75enum {
76 TP_VERSION_MAJOR = 1,
75 TP_VERSION_MINOR = 0,
76 TP_VERSION_MICRO = 44
77 TP_VERSION_MINOR = 1,
78 TP_VERSION_MICRO = 0
77};
78
79#define S_TP_VERSION_MAJOR 16
80#define M_TP_VERSION_MAJOR 0xFF
81#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
82#define G_TP_VERSION_MAJOR(x) \
83 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
84

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91#define S_TP_VERSION_MICRO 0
92#define M_TP_VERSION_MICRO 0xFF
93#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
94#define G_TP_VERSION_MICRO(x) \
95 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
96
97enum {
98 FW_VERSION_MAJOR = 4,
79};
80
81#define S_TP_VERSION_MAJOR 16
82#define M_TP_VERSION_MAJOR 0xFF
83#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
84#define G_TP_VERSION_MAJOR(x) \
85 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
86

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93#define S_TP_VERSION_MICRO 0
94#define M_TP_VERSION_MICRO 0xFF
95#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
96#define G_TP_VERSION_MICRO(x) \
97 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
98
99enum {
100 FW_VERSION_MAJOR = 4,
99 FW_VERSION_MINOR = 1,
101 FW_VERSION_MINOR = 5,
100 FW_VERSION_MICRO = 0
101};
102
103enum {
104 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
105 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
106 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
107};

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388 unsigned int rev; /* chip revision */
389 unsigned int offload;
390};
391
392enum { /* chip revisions */
393 T3_REV_A = 0,
394 T3_REV_B = 2,
395 T3_REV_B2 = 3,
102 FW_VERSION_MICRO = 0
103};
104
105enum {
106 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
107 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
108 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
109};

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390 unsigned int rev; /* chip revision */
391 unsigned int offload;
392};
393
394enum { /* chip revisions */
395 T3_REV_A = 0,
396 T3_REV_B = 2,
397 T3_REV_B2 = 3,
398 T3_REV_C = 4,
396};
397
398struct trace_params {
399 u32 sip;
400 u32 sip_mask;
401 u32 dip;
402 u32 dip_mask;
403 u16 sport;

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462 unsigned char nucast; /* # of address filters for unicast MACs */
463 unsigned char multiport; /* multiple ports connected to this MAC */
464 unsigned char ext_port; /* external MAC port */
465 unsigned char promisc_map; /* which external ports are promiscuous */
466 unsigned int tx_tcnt;
467 unsigned int tx_xcnt;
468 u64 tx_mcnt;
469 unsigned int rx_xcnt;
399};
400
401struct trace_params {
402 u32 sip;
403 u32 sip_mask;
404 u32 dip;
405 u32 dip_mask;
406 u16 sport;

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465 unsigned char nucast; /* # of address filters for unicast MACs */
466 unsigned char multiport; /* multiple ports connected to this MAC */
467 unsigned char ext_port; /* external MAC port */
468 unsigned char promisc_map; /* which external ports are promiscuous */
469 unsigned int tx_tcnt;
470 unsigned int tx_xcnt;
471 u64 tx_mcnt;
472 unsigned int rx_xcnt;
473 unsigned int rx_ocnt;
470 u64 rx_mcnt;
471 unsigned int toggle_cnt;
472 unsigned int txen;
473 struct mac_stats stats;
474};
475
476enum {
477 MAC_DIRECTION_RX = 1,

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557 phy->mdio_read = mdio_ops->read;
558 phy->mdio_write = mdio_ops->write;
559 }
560}
561
562/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
563#define MAC_STATS_ACCUM_SECS 180
564
474 u64 rx_mcnt;
475 unsigned int toggle_cnt;
476 unsigned int txen;
477 struct mac_stats stats;
478};
479
480enum {
481 MAC_DIRECTION_RX = 1,

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561 phy->mdio_read = mdio_ops->read;
562 phy->mdio_write = mdio_ops->write;
563 }
564}
565
566/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
567#define MAC_STATS_ACCUM_SECS 180
568
569/* The external MAC needs accumulation every 30 seconds */
570#define VSC_STATS_ACCUM_SECS 30
571
565#define XGM_REG(reg_addr, idx) \
566 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
567
568struct addr_val_pair {
569 unsigned int reg_addr;
570 unsigned int val;
571};
572

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651void t3_link_changed(adapter_t *adapter, int port_id);
652int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
653const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
654int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
655int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
656int t3_seeprom_wp(adapter_t *adapter, int enable);
657int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
658 u32 *data, int byte_oriented);
572#define XGM_REG(reg_addr, idx) \
573 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
574
575struct addr_val_pair {
576 unsigned int reg_addr;
577 unsigned int val;
578};
579

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658void t3_link_changed(adapter_t *adapter, int port_id);
659int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
660const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
661int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
662int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
663int t3_seeprom_wp(adapter_t *adapter, int enable);
664int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
665 u32 *data, int byte_oriented);
666int t3_get_tp_version(adapter_t *adapter, u32 *vers);
659int t3_check_tpsram_version(adapter_t *adapter);
667int t3_check_tpsram_version(adapter_t *adapter);
660int t3_check_tpsram(adapter_t *adapter, u8 *tp_ram, unsigned int size);
661int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
668int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
669int t3_load_fw(adapter_t *adapter, const const u8 *fw_data, unsigned int size);
662int t3_get_fw_version(adapter_t *adapter, u32 *vers);
663int t3_check_fw_version(adapter_t *adapter);
664int t3_init_hw(adapter_t *adapter, u32 fw_params);
665void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
666void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
667int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
668void t3_led_ready(adapter_t *adapter);
669void t3_fatal_err(adapter_t *adapter);
670void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
670int t3_get_fw_version(adapter_t *adapter, u32 *vers);
671int t3_check_fw_version(adapter_t *adapter);
672int t3_init_hw(adapter_t *adapter, u32 fw_params);
673void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
674void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
675int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
676void t3_led_ready(adapter_t *adapter);
677void t3_fatal_err(adapter_t *adapter);
678void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
679void t3_enable_filters(adapter_t *adap);
671void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
672 const u16 *rspq);
673int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
680void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
681 const u16 *rspq);
682int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
674int t3_set_proto_sram(adapter_t *adap, u8 *data);
683int t3_set_proto_sram(adapter_t *adap, const u8 *data);
675int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
676void t3_port_failover(adapter_t *adapter, int port);
677void t3_failover_done(adapter_t *adapter, int port);
678void t3_failover_clear(adapter_t *adapter);
679int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
680 unsigned int *valp);
681int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
682 u64 *buf);

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748int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
749int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
750 unsigned int credits);
751
752int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
753int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
754int t3_vsc7323_init(adapter_t *adap, int nports);
755int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
684int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
685void t3_port_failover(adapter_t *adapter, int port);
686void t3_failover_done(adapter_t *adapter, int port);
687void t3_failover_clear(adapter_t *adapter);
688int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
689 unsigned int *valp);
690int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
691 u64 *buf);

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757int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
758int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
759 unsigned int credits);
760
761int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
762int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
763int t3_vsc7323_init(adapter_t *adap, int nports);
764int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
756int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
757int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
765int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
766int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
758int t3_vsc7323_enable(adapter_t *adap, int port, int which);
759int t3_vsc7323_disable(adapter_t *adap, int port, int which);
760const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
761
762void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
763 const struct mdio_ops *mdio_ops);
764void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
765 const struct mdio_ops *mdio_ops);
766void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
767 const struct mdio_ops *mdio_ops);
768void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
769 const struct mdio_ops *mdio_ops);
770void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
771 const struct mdio_ops *mdio_ops);
772void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
773 const struct mdio_ops *mdio_ops);
774#endif /* __CHELSIO_COMMON_H */
767int t3_vsc7323_enable(adapter_t *adap, int port, int which);
768int t3_vsc7323_disable(adapter_t *adap, int port, int which);
769const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
770
771void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
772 const struct mdio_ops *mdio_ops);
773void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
774 const struct mdio_ops *mdio_ops);
775void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
776 const struct mdio_ops *mdio_ops);
777void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
778 const struct mdio_ops *mdio_ops);
779void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
780 const struct mdio_ops *mdio_ops);
781void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
782 const struct mdio_ops *mdio_ops);
783#endif /* __CHELSIO_COMMON_H */