1/*- 2 * Copyright (c) 2004-2005 Nate Lawson (SDG) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h>
| 1/*- 2 * Copyright (c) 2004-2005 Nate Lawson (SDG) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h>
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28__FBSDID("$FreeBSD: head/sys/dev/cpufreq/ichss.c 142156 2005-02-20 23:41:20Z njl $");
| 28__FBSDID("$FreeBSD: head/sys/dev/cpufreq/ichss.c 142203 2005-02-22 06:31:45Z njl $");
|
29 30#include <sys/param.h> 31#include <sys/bus.h> 32#include <sys/cpu.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36#include <sys/pcpu.h> 37#include <sys/sysctl.h> 38#include <sys/systm.h> 39 40#include <dev/pci/pcivar.h> 41#include <machine/bus.h> 42#include <machine/clock.h> 43#include <machine/resource.h> 44#include <sys/rman.h> 45 46#include "cpufreq_if.h" 47 48/* 49 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency 50 * transition available on the ICH2M, 3M, and 4M. It is different from 51 * the newer Pentium-M SpeedStep feature. It offers only two levels of 52 * frequency/voltage. Often, the BIOS will select one of the levels via 53 * SMM code during the power-on process (i.e., choose a lower level if the 54 * system is off AC power.) 55 */ 56 57struct ichss_softc { 58 device_t dev; 59 int bm_rid; /* Bus-mastering control (PM2REG). */ 60 struct resource *bm_reg; 61 int ctrl_rid; /* Control/status register. */ 62 struct resource *ctrl_reg; 63 struct cf_setting sets[2]; /* Only two settings. */ 64}; 65 66/* Supported PCI IDs. */ 67#define PCI_VENDOR_INTEL 0x8086 68#define PCI_DEV_82801BA 0x244c /* ICH2M */ 69#define PCI_DEV_82801CA 0x248c /* ICH3M */ 70#define PCI_DEV_82801DB 0x24cc /* ICH4M */ 71#define PCI_DEV_82815BA 0x1130 /* Unsupported/buggy part */ 72 73/* PCI config registers for finding PMBASE and enabling SpeedStep. */ 74#define ICHSS_PMBASE_OFFSET 0x40 75#define ICHSS_PMCFG_OFFSET 0xa0 76 77/* Values and masks. */ 78#define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */ 79#define ICHSS_IO_REG 0x1 /* Access register via I/O space. */ 80#define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */ 81#define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */ 82#define ICHSS_BM_DISABLE 0x1 83 84/* Offsets from PMBASE for various registers. */ 85#define ICHSS_BM_OFFSET 0x20 86#define ICHSS_CTRL_OFFSET 0x50 87 88#define ICH_GET_REG(reg) \ 89 (bus_space_read_1(rman_get_bustag((reg)), \ 90 rman_get_bushandle((reg)), 0)) 91#define ICH_SET_REG(reg, val) \ 92 (bus_space_write_1(rman_get_bustag((reg)), \ 93 rman_get_bushandle((reg)), 0, (val))) 94 95static int ichss_pci_probe(device_t dev); 96static int ichss_probe(device_t dev); 97static int ichss_attach(device_t dev); 98static int ichss_detach(device_t dev); 99static int ichss_settings(device_t dev, struct cf_setting *sets, 100 int *count); 101static int ichss_set(device_t dev, const struct cf_setting *set); 102static int ichss_get(device_t dev, struct cf_setting *set); 103static int ichss_type(device_t dev, int *type); 104 105static device_method_t ichss_methods[] = { 106 /* Device interface */ 107 DEVMETHOD(device_probe, ichss_probe), 108 DEVMETHOD(device_attach, ichss_attach), 109 DEVMETHOD(device_detach, ichss_detach), 110 111 /* cpufreq interface */ 112 DEVMETHOD(cpufreq_drv_set, ichss_set), 113 DEVMETHOD(cpufreq_drv_get, ichss_get), 114 DEVMETHOD(cpufreq_drv_type, ichss_type), 115 DEVMETHOD(cpufreq_drv_settings, ichss_settings), 116 {0, 0} 117}; 118static driver_t ichss_driver = { 119 "ichss", ichss_methods, sizeof(struct ichss_softc) 120}; 121static devclass_t ichss_devclass; 122DRIVER_MODULE(ichss, cpu, ichss_driver, ichss_devclass, 0, 0); 123 124static device_method_t ichss_pci_methods[] = { 125 DEVMETHOD(device_probe, ichss_pci_probe), 126 {0, 0} 127}; 128static driver_t ichss_pci_driver = { 129 "ichss_pci", ichss_pci_methods, 0 130}; 131static devclass_t ichss_pci_devclass; 132DRIVER_MODULE(ichss_pci, pci, ichss_pci_driver, ichss_pci_devclass, 0, 0); 133 134#if 0 135#define DPRINT(x...) printf(x) 136#else 137#define DPRINT(x...) 138#endif 139 140/* 141 * We detect the chipset by looking for its LPC bus ID during the PCI 142 * scan and reading its config registers during the probe. However, 143 * we add the ichss child under the cpu device since even though the 144 * chipset provides the control, it really affects the cpu only. 145 * 146 * XXX This approach does not work if the module is loaded after boot. 147 */ 148static int 149ichss_pci_probe(device_t dev) 150{ 151 device_t child, parent; 152 uint32_t pmbase; 153 uint16_t ss_en; 154 155 /* 156 * TODO: add a quirk to disable if we see the 82815_MC along 157 * with the 82801BA and revision < 5. 158 */ 159 if (pci_get_vendor(dev) != PCI_VENDOR_INTEL || 160 (pci_get_device(dev) != PCI_DEV_82801BA && 161 pci_get_device(dev) != PCI_DEV_82801CA && 162 pci_get_device(dev) != PCI_DEV_82801DB)) 163 return (ENXIO); 164 165 /* Only one CPU is supported for this hardware. */ 166 if (devclass_get_device(ichss_devclass, 0)) 167 return (ENXIO); 168 169 /* Add a child under the CPU parent. */ 170 parent = devclass_get_device(devclass_find("cpu"), 0); 171 KASSERT(parent != NULL, ("cpu parent is NULL")); 172 child = BUS_ADD_CHILD(parent, 0, "ichss", 0); 173 if (child == NULL) { 174 device_printf(parent, "add SpeedStep child failed\n"); 175 return (ENXIO); 176 } 177 178 /* Find the PMBASE register from our PCI config header. */ 179 pmbase = pci_read_config(dev, ICHSS_PMBASE_OFFSET, sizeof(pmbase)); 180 if ((pmbase & ICHSS_IO_REG) == 0) { 181 printf("ichss: invalid PMBASE memory type\n"); 182 return (ENXIO); 183 } 184 pmbase &= ICHSS_PMBASE_MASK; 185 if (pmbase == 0) { 186 printf("ichss: invalid zero PMBASE address\n"); 187 return (ENXIO); 188 } 189 DPRINT("ichss: PMBASE is %#x\n", pmbase); 190 191 /* Add the bus master arbitration and control registers. */ 192 bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET, 193 1); 194 bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET, 195 1); 196 197 /* Activate SpeedStep control if not already enabled. */ 198 ss_en = pci_read_config(dev, ICHSS_PMCFG_OFFSET, sizeof(ss_en)); 199 if ((ss_en & ICHSS_ENABLE) == 0) { 200 printf("ichss: enabling SpeedStep support\n"); 201 pci_write_config(dev, ICHSS_PMCFG_OFFSET, 202 ss_en | ICHSS_ENABLE, sizeof(ss_en)); 203 } 204 205 /* Attach the new CPU child now. */ 206 device_probe_and_attach(child); 207 208 return (ENXIO); 209} 210 211static int 212ichss_probe(device_t dev) 213{ 214 device_t est_dev, perf_dev; 215 int error, type; 216
| 29 30#include <sys/param.h> 31#include <sys/bus.h> 32#include <sys/cpu.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36#include <sys/pcpu.h> 37#include <sys/sysctl.h> 38#include <sys/systm.h> 39 40#include <dev/pci/pcivar.h> 41#include <machine/bus.h> 42#include <machine/clock.h> 43#include <machine/resource.h> 44#include <sys/rman.h> 45 46#include "cpufreq_if.h" 47 48/* 49 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency 50 * transition available on the ICH2M, 3M, and 4M. It is different from 51 * the newer Pentium-M SpeedStep feature. It offers only two levels of 52 * frequency/voltage. Often, the BIOS will select one of the levels via 53 * SMM code during the power-on process (i.e., choose a lower level if the 54 * system is off AC power.) 55 */ 56 57struct ichss_softc { 58 device_t dev; 59 int bm_rid; /* Bus-mastering control (PM2REG). */ 60 struct resource *bm_reg; 61 int ctrl_rid; /* Control/status register. */ 62 struct resource *ctrl_reg; 63 struct cf_setting sets[2]; /* Only two settings. */ 64}; 65 66/* Supported PCI IDs. */ 67#define PCI_VENDOR_INTEL 0x8086 68#define PCI_DEV_82801BA 0x244c /* ICH2M */ 69#define PCI_DEV_82801CA 0x248c /* ICH3M */ 70#define PCI_DEV_82801DB 0x24cc /* ICH4M */ 71#define PCI_DEV_82815BA 0x1130 /* Unsupported/buggy part */ 72 73/* PCI config registers for finding PMBASE and enabling SpeedStep. */ 74#define ICHSS_PMBASE_OFFSET 0x40 75#define ICHSS_PMCFG_OFFSET 0xa0 76 77/* Values and masks. */ 78#define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */ 79#define ICHSS_IO_REG 0x1 /* Access register via I/O space. */ 80#define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */ 81#define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */ 82#define ICHSS_BM_DISABLE 0x1 83 84/* Offsets from PMBASE for various registers. */ 85#define ICHSS_BM_OFFSET 0x20 86#define ICHSS_CTRL_OFFSET 0x50 87 88#define ICH_GET_REG(reg) \ 89 (bus_space_read_1(rman_get_bustag((reg)), \ 90 rman_get_bushandle((reg)), 0)) 91#define ICH_SET_REG(reg, val) \ 92 (bus_space_write_1(rman_get_bustag((reg)), \ 93 rman_get_bushandle((reg)), 0, (val))) 94 95static int ichss_pci_probe(device_t dev); 96static int ichss_probe(device_t dev); 97static int ichss_attach(device_t dev); 98static int ichss_detach(device_t dev); 99static int ichss_settings(device_t dev, struct cf_setting *sets, 100 int *count); 101static int ichss_set(device_t dev, const struct cf_setting *set); 102static int ichss_get(device_t dev, struct cf_setting *set); 103static int ichss_type(device_t dev, int *type); 104 105static device_method_t ichss_methods[] = { 106 /* Device interface */ 107 DEVMETHOD(device_probe, ichss_probe), 108 DEVMETHOD(device_attach, ichss_attach), 109 DEVMETHOD(device_detach, ichss_detach), 110 111 /* cpufreq interface */ 112 DEVMETHOD(cpufreq_drv_set, ichss_set), 113 DEVMETHOD(cpufreq_drv_get, ichss_get), 114 DEVMETHOD(cpufreq_drv_type, ichss_type), 115 DEVMETHOD(cpufreq_drv_settings, ichss_settings), 116 {0, 0} 117}; 118static driver_t ichss_driver = { 119 "ichss", ichss_methods, sizeof(struct ichss_softc) 120}; 121static devclass_t ichss_devclass; 122DRIVER_MODULE(ichss, cpu, ichss_driver, ichss_devclass, 0, 0); 123 124static device_method_t ichss_pci_methods[] = { 125 DEVMETHOD(device_probe, ichss_pci_probe), 126 {0, 0} 127}; 128static driver_t ichss_pci_driver = { 129 "ichss_pci", ichss_pci_methods, 0 130}; 131static devclass_t ichss_pci_devclass; 132DRIVER_MODULE(ichss_pci, pci, ichss_pci_driver, ichss_pci_devclass, 0, 0); 133 134#if 0 135#define DPRINT(x...) printf(x) 136#else 137#define DPRINT(x...) 138#endif 139 140/* 141 * We detect the chipset by looking for its LPC bus ID during the PCI 142 * scan and reading its config registers during the probe. However, 143 * we add the ichss child under the cpu device since even though the 144 * chipset provides the control, it really affects the cpu only. 145 * 146 * XXX This approach does not work if the module is loaded after boot. 147 */ 148static int 149ichss_pci_probe(device_t dev) 150{ 151 device_t child, parent; 152 uint32_t pmbase; 153 uint16_t ss_en; 154 155 /* 156 * TODO: add a quirk to disable if we see the 82815_MC along 157 * with the 82801BA and revision < 5. 158 */ 159 if (pci_get_vendor(dev) != PCI_VENDOR_INTEL || 160 (pci_get_device(dev) != PCI_DEV_82801BA && 161 pci_get_device(dev) != PCI_DEV_82801CA && 162 pci_get_device(dev) != PCI_DEV_82801DB)) 163 return (ENXIO); 164 165 /* Only one CPU is supported for this hardware. */ 166 if (devclass_get_device(ichss_devclass, 0)) 167 return (ENXIO); 168 169 /* Add a child under the CPU parent. */ 170 parent = devclass_get_device(devclass_find("cpu"), 0); 171 KASSERT(parent != NULL, ("cpu parent is NULL")); 172 child = BUS_ADD_CHILD(parent, 0, "ichss", 0); 173 if (child == NULL) { 174 device_printf(parent, "add SpeedStep child failed\n"); 175 return (ENXIO); 176 } 177 178 /* Find the PMBASE register from our PCI config header. */ 179 pmbase = pci_read_config(dev, ICHSS_PMBASE_OFFSET, sizeof(pmbase)); 180 if ((pmbase & ICHSS_IO_REG) == 0) { 181 printf("ichss: invalid PMBASE memory type\n"); 182 return (ENXIO); 183 } 184 pmbase &= ICHSS_PMBASE_MASK; 185 if (pmbase == 0) { 186 printf("ichss: invalid zero PMBASE address\n"); 187 return (ENXIO); 188 } 189 DPRINT("ichss: PMBASE is %#x\n", pmbase); 190 191 /* Add the bus master arbitration and control registers. */ 192 bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET, 193 1); 194 bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET, 195 1); 196 197 /* Activate SpeedStep control if not already enabled. */ 198 ss_en = pci_read_config(dev, ICHSS_PMCFG_OFFSET, sizeof(ss_en)); 199 if ((ss_en & ICHSS_ENABLE) == 0) { 200 printf("ichss: enabling SpeedStep support\n"); 201 pci_write_config(dev, ICHSS_PMCFG_OFFSET, 202 ss_en | ICHSS_ENABLE, sizeof(ss_en)); 203 } 204 205 /* Attach the new CPU child now. */ 206 device_probe_and_attach(child); 207 208 return (ENXIO); 209} 210 211static int 212ichss_probe(device_t dev) 213{ 214 device_t est_dev, perf_dev; 215 int error, type; 216
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| 217 if (resource_disabled("ichss", 0)) 218 return (ENXIO); 219
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217 /* 218 * If the ACPI perf driver has attached and is not just offering 219 * info, let it manage things. Also, if Enhanced SpeedStep is 220 * available, don't attach. 221 */ 222 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 223 if (perf_dev && device_is_attached(perf_dev)) { 224 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 225 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 226 return (ENXIO); 227 } 228 est_dev = device_find_child(device_get_parent(dev), "est", -1); 229 if (est_dev && device_is_attached(est_dev)) 230 return (ENXIO); 231 232 device_set_desc(dev, "SpeedStep ICH"); 233 return (-1000); 234} 235 236static int 237ichss_attach(device_t dev) 238{ 239 struct ichss_softc *sc; 240 241 sc = device_get_softc(dev); 242 sc->dev = dev; 243 244 sc->bm_rid = 0; 245 sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid, 246 RF_ACTIVE); 247 if (sc->bm_reg == NULL) { 248 device_printf(dev, "failed to alloc BM arb register\n"); 249 return (ENXIO); 250 } 251 sc->ctrl_rid = 1; 252 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 253 &sc->ctrl_rid, RF_ACTIVE); 254 if (sc->ctrl_reg == NULL) { 255 device_printf(dev, "failed to alloc control register\n"); 256 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid, 257 sc->bm_reg); 258 return (ENXIO); 259 } 260 261 /* Setup some defaults for our exported settings. */ 262 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; 263 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; 264 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; 265 sc->sets[0].lat = 1000; 266 sc->sets[0].dev = dev; 267 sc->sets[1] = sc->sets[0]; 268 cpufreq_register(dev); 269 270 return (0); 271} 272 273static int 274ichss_detach(device_t dev) 275{ 276 /* TODO: teardown BM and CTRL registers. */ 277 return (ENXIO); 278} 279 280static int 281ichss_settings(device_t dev, struct cf_setting *sets, int *count) 282{ 283 struct ichss_softc *sc; 284 struct cf_setting set; 285 int first, i; 286 287 if (sets == NULL || count == NULL) 288 return (EINVAL); 289 if (*count < 2) { 290 *count = 2; 291 return (E2BIG); 292 } 293 sc = device_get_softc(dev); 294 295 /* 296 * Estimate frequencies for both levels, temporarily switching to 297 * the other one if we haven't calibrated it yet. 298 */ 299 ichss_get(dev, &set); 300 for (i = 0; i < 2; i++) { 301 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) { 302 first = (i == 0) ? 1 : 0; 303 ichss_set(dev, &sc->sets[i]); 304 ichss_set(dev, &sc->sets[first]); 305 } 306 } 307 308 bcopy(sc->sets, sets, sizeof(sc->sets)); 309 *count = 2; 310 311 return (0); 312} 313 314static int 315ichss_set(device_t dev, const struct cf_setting *set) 316{ 317 struct ichss_softc *sc; 318 uint8_t bmval, new_val, old_val, req_val; 319 uint64_t rate; 320 register_t regs; 321 322 /* Look up appropriate bit value based on frequency. */ 323 sc = device_get_softc(dev); 324 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq)) 325 req_val = 0; 326 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq)) 327 req_val = ICHSS_CTRL_BIT; 328 else 329 return (EINVAL); 330 DPRINT("ichss: requested setting %d\n", req_val); 331 332 /* Disable interrupts and get the other register contents. */ 333 regs = intr_disable(); 334 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT; 335 336 /* 337 * Disable bus master arbitration, write the new value to the control 338 * register, and then re-enable bus master arbitration. 339 */ 340 bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE; 341 ICH_SET_REG(sc->bm_reg, bmval); 342 ICH_SET_REG(sc->ctrl_reg, old_val | req_val); 343 ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE); 344 345 /* Get the new value and re-enable interrupts. */ 346 new_val = ICH_GET_REG(sc->ctrl_reg); 347 intr_restore(regs); 348 349 /* Check if the desired state was indeed selected. */ 350 if (req_val != (new_val & ICHSS_CTRL_BIT)) { 351 device_printf(sc->dev, "transition to %d failed\n", req_val); 352 return (ENXIO); 353 } 354 355 /* Re-initialize our cycle counter if we don't know this new state. */ 356 if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) { 357 cpu_est_clockrate(0, &rate); 358 sc->sets[req_val].freq = rate / 1000000; 359 DPRINT("ichss: set calibrated new rate of %d\n", 360 sc->sets[req_val].freq); 361 } 362 363 return (0); 364} 365 366static int 367ichss_get(device_t dev, struct cf_setting *set) 368{ 369 struct ichss_softc *sc; 370 uint64_t rate; 371 uint8_t state; 372 373 sc = device_get_softc(dev); 374 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT; 375 376 /* If we haven't changed settings yet, estimate the current value. */ 377 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) { 378 cpu_est_clockrate(0, &rate); 379 sc->sets[state].freq = rate / 1000000; 380 DPRINT("ichss: get calibrated new rate of %d\n", 381 sc->sets[state].freq); 382 } 383 *set = sc->sets[state]; 384 385 return (0); 386} 387 388static int 389ichss_type(device_t dev, int *type) 390{ 391 392 if (type == NULL) 393 return (EINVAL); 394 395 *type = CPUFREQ_TYPE_ABSOLUTE; 396 return (0); 397}
| 220 /* 221 * If the ACPI perf driver has attached and is not just offering 222 * info, let it manage things. Also, if Enhanced SpeedStep is 223 * available, don't attach. 224 */ 225 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 226 if (perf_dev && device_is_attached(perf_dev)) { 227 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 228 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 229 return (ENXIO); 230 } 231 est_dev = device_find_child(device_get_parent(dev), "est", -1); 232 if (est_dev && device_is_attached(est_dev)) 233 return (ENXIO); 234 235 device_set_desc(dev, "SpeedStep ICH"); 236 return (-1000); 237} 238 239static int 240ichss_attach(device_t dev) 241{ 242 struct ichss_softc *sc; 243 244 sc = device_get_softc(dev); 245 sc->dev = dev; 246 247 sc->bm_rid = 0; 248 sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid, 249 RF_ACTIVE); 250 if (sc->bm_reg == NULL) { 251 device_printf(dev, "failed to alloc BM arb register\n"); 252 return (ENXIO); 253 } 254 sc->ctrl_rid = 1; 255 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 256 &sc->ctrl_rid, RF_ACTIVE); 257 if (sc->ctrl_reg == NULL) { 258 device_printf(dev, "failed to alloc control register\n"); 259 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid, 260 sc->bm_reg); 261 return (ENXIO); 262 } 263 264 /* Setup some defaults for our exported settings. */ 265 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; 266 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; 267 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; 268 sc->sets[0].lat = 1000; 269 sc->sets[0].dev = dev; 270 sc->sets[1] = sc->sets[0]; 271 cpufreq_register(dev); 272 273 return (0); 274} 275 276static int 277ichss_detach(device_t dev) 278{ 279 /* TODO: teardown BM and CTRL registers. */ 280 return (ENXIO); 281} 282 283static int 284ichss_settings(device_t dev, struct cf_setting *sets, int *count) 285{ 286 struct ichss_softc *sc; 287 struct cf_setting set; 288 int first, i; 289 290 if (sets == NULL || count == NULL) 291 return (EINVAL); 292 if (*count < 2) { 293 *count = 2; 294 return (E2BIG); 295 } 296 sc = device_get_softc(dev); 297 298 /* 299 * Estimate frequencies for both levels, temporarily switching to 300 * the other one if we haven't calibrated it yet. 301 */ 302 ichss_get(dev, &set); 303 for (i = 0; i < 2; i++) { 304 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) { 305 first = (i == 0) ? 1 : 0; 306 ichss_set(dev, &sc->sets[i]); 307 ichss_set(dev, &sc->sets[first]); 308 } 309 } 310 311 bcopy(sc->sets, sets, sizeof(sc->sets)); 312 *count = 2; 313 314 return (0); 315} 316 317static int 318ichss_set(device_t dev, const struct cf_setting *set) 319{ 320 struct ichss_softc *sc; 321 uint8_t bmval, new_val, old_val, req_val; 322 uint64_t rate; 323 register_t regs; 324 325 /* Look up appropriate bit value based on frequency. */ 326 sc = device_get_softc(dev); 327 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq)) 328 req_val = 0; 329 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq)) 330 req_val = ICHSS_CTRL_BIT; 331 else 332 return (EINVAL); 333 DPRINT("ichss: requested setting %d\n", req_val); 334 335 /* Disable interrupts and get the other register contents. */ 336 regs = intr_disable(); 337 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT; 338 339 /* 340 * Disable bus master arbitration, write the new value to the control 341 * register, and then re-enable bus master arbitration. 342 */ 343 bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE; 344 ICH_SET_REG(sc->bm_reg, bmval); 345 ICH_SET_REG(sc->ctrl_reg, old_val | req_val); 346 ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE); 347 348 /* Get the new value and re-enable interrupts. */ 349 new_val = ICH_GET_REG(sc->ctrl_reg); 350 intr_restore(regs); 351 352 /* Check if the desired state was indeed selected. */ 353 if (req_val != (new_val & ICHSS_CTRL_BIT)) { 354 device_printf(sc->dev, "transition to %d failed\n", req_val); 355 return (ENXIO); 356 } 357 358 /* Re-initialize our cycle counter if we don't know this new state. */ 359 if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) { 360 cpu_est_clockrate(0, &rate); 361 sc->sets[req_val].freq = rate / 1000000; 362 DPRINT("ichss: set calibrated new rate of %d\n", 363 sc->sets[req_val].freq); 364 } 365 366 return (0); 367} 368 369static int 370ichss_get(device_t dev, struct cf_setting *set) 371{ 372 struct ichss_softc *sc; 373 uint64_t rate; 374 uint8_t state; 375 376 sc = device_get_softc(dev); 377 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT; 378 379 /* If we haven't changed settings yet, estimate the current value. */ 380 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) { 381 cpu_est_clockrate(0, &rate); 382 sc->sets[state].freq = rate / 1000000; 383 DPRINT("ichss: get calibrated new rate of %d\n", 384 sc->sets[state].freq); 385 } 386 *set = sc->sets[state]; 387 388 return (0); 389} 390 391static int 392ichss_type(device_t dev, int *type) 393{ 394 395 if (type == NULL) 396 return (EINVAL); 397 398 *type = CPUFREQ_TYPE_ABSOLUTE; 399 return (0); 400}
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