| if_bgereg.h (241388) | if_bgereg.h (241436) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 16 unchanged lines hidden (view full) --- 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * | 1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 16 unchanged lines hidden (view full) --- 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * |
| 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 241388 2012-10-10 01:24:02Z yongari $ | 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 241436 2012-10-11 05:48:04Z yongari $ |
| 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and --- 383 unchanged lines hidden (view full) --- 425 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 426 * register is set. 427 */ 428#define BGE_PCISTATE_FORCE_RESET 0x00000001 429#define BGE_PCISTATE_INTR_STATE 0x00000002 430#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 431#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 432#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ | 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and --- 383 unchanged lines hidden (view full) --- 425 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 426 * register is set. 427 */ 428#define BGE_PCISTATE_FORCE_RESET 0x00000001 429#define BGE_PCISTATE_INTR_STATE 0x00000002 430#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 431#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 432#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ |
| 433#define BGE_PCISTATE_WANT_EXPROM 0x00000020 434#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 | 433#define BGE_PCISTATE_ROM_ENABLE 0x00000020 434#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 |
| 435#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 436#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 | 435#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 436#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 |
| 437#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 |
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| 437 438/* 439 * PCI Clock Control register -- note, this register is read only 440 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 441 * register is set. 442 */ 443#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 444#define BGE_PCICLOCKCTL_M66EN 0x00000080 --- 2439 unchanged lines hidden --- | 438 439/* 440 * PCI Clock Control register -- note, this register is read only 441 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 442 * register is set. 443 */ 444#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 445#define BGE_PCICLOCKCTL_M66EN 0x00000080 --- 2439 unchanged lines hidden --- |