1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 16 unchanged lines hidden (view full) --- 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * |
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 153437 2005-12-15 05:48:49Z yongari $ |
34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and --- 160 unchanged lines hidden (view full) --- 202#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 203#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 204#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 205#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 206#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 207#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 208#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 209 |
210#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 211#if BYTE_ORDER == LITTLE_ENDIAN 212#define BGE_DMA_SWAP_OPTIONS \ 213 BGE_MODECTL_WORDSWAP_NONFRAME| \ 214 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 215#else 216#define BGE_DMA_SWAP_OPTIONS \ 217 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 218 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 219#endif |
220 |
221#define BGE_INIT \ 222 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 223 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) |
224 225#define BGE_CHIPID_TIGON_I 0x40000000 226#define BGE_CHIPID_TIGON_II 0x60000000 227#define BGE_CHIPID_BCM5700_B0 0x71000000 228#define BGE_CHIPID_BCM5700_B1 0x71020000 229#define BGE_CHIPID_BCM5700_B2 0x71030000 230#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 231#define BGE_CHIPID_BCM5700_C0 0x72000000 --- 1536 unchanged lines hidden (view full) --- 1768 ((u_int64_t) (y) >> 32) 1769 1770/* Ring control block structure */ 1771struct bge_rcb { 1772 bge_hostaddr bge_hostaddr; 1773 u_int32_t bge_maxlen_flags; 1774 u_int32_t bge_nicaddr; 1775}; |
1776 1777#define RCB_WRITE_4(sc, rcb, offset, val) \ 1778 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1779 rcb + offsetof(struct bge_rcb, offset), val) |
1780#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1781 1782#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1783#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1784 1785struct bge_tx_bd { 1786 bge_hostaddr bge_addr; |
1787#if BYTE_ORDER == LITTLE_ENDIAN |
1788 u_int16_t bge_flags; 1789 u_int16_t bge_len; 1790 u_int16_t bge_vlan_tag; 1791 u_int16_t bge_rsvd; |
1792#else 1793 u_int16_t bge_len; 1794 u_int16_t bge_flags; 1795 u_int16_t bge_rsvd; 1796 u_int16_t bge_vlan_tag; 1797#endif |
1798}; 1799 1800#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1801#define BGE_TXBDFLAG_IP_CSUM 0x0002 1802#define BGE_TXBDFLAG_END 0x0004 1803#define BGE_TXBDFLAG_IP_FRAG 0x0008 1804#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1805#define BGE_TXBDFLAG_VLAN_TAG 0x0040 --- 5 unchanged lines hidden (view full) --- 1811#define BGE_TXBDFLAG_NO_CRC 0x8000 1812 1813#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1814 BGE_SEND_RING_1_TO_4 + \ 1815 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1816 1817struct bge_rx_bd { 1818 bge_hostaddr bge_addr; |
1819#if BYTE_ORDER == LITTLE_ENDIAN |
1820 u_int16_t bge_len; 1821 u_int16_t bge_idx; 1822 u_int16_t bge_flags; 1823 u_int16_t bge_type; 1824 u_int16_t bge_tcp_udp_csum; 1825 u_int16_t bge_ip_csum; 1826 u_int16_t bge_vlan_tag; 1827 u_int16_t bge_error_flag; |
1828#else 1829 u_int16_t bge_idx; 1830 u_int16_t bge_len; 1831 u_int16_t bge_type; 1832 u_int16_t bge_flags; 1833 u_int16_t bge_ip_csum; 1834 u_int16_t bge_tcp_udp_csum; 1835 u_int16_t bge_error_flag; 1836 u_int16_t bge_vlan_tag; 1837#endif |
1838 u_int32_t bge_rsvd; 1839 u_int32_t bge_opaque; 1840}; 1841 1842struct bge_extrx_bd { 1843 bge_hostaddr bge_addr1; 1844 bge_hostaddr bge_addr2; 1845 bge_hostaddr bge_addr3; |
1846#if BYTE_ORDER == LITTLE_ENDIAN |
1847 u_int16_t bge_len2; 1848 u_int16_t bge_len1; 1849 u_int16_t bge_rsvd1; 1850 u_int16_t bge_len3; |
1851#else 1852 u_int16_t bge_len1; 1853 u_int16_t bge_len2; 1854 u_int16_t bge_len3; 1855 u_int16_t bge_rsvd1; 1856#endif |
1857 bge_hostaddr bge_addr0; |
1858#if BYTE_ORDER == LITTLE_ENDIAN |
1859 u_int16_t bge_len0; 1860 u_int16_t bge_idx; 1861 u_int16_t bge_flags; 1862 u_int16_t bge_type; 1863 u_int16_t bge_tcp_udp_csum; 1864 u_int16_t bge_ip_csum; 1865 u_int16_t bge_vlan_tag; 1866 u_int16_t bge_error_flag; |
1867#else 1868 u_int16_t bge_idx; 1869 u_int16_t bge_len0; 1870 u_int16_t bge_type; 1871 u_int16_t bge_flags; 1872 u_int16_t bge_ip_csum; 1873 u_int16_t bge_tcp_udp_csum; 1874 u_int16_t bge_error_flag; 1875 u_int16_t bge_vlan_tag; 1876#endif |
1877 u_int32_t bge_rsvd0; 1878 u_int32_t bge_opaque; 1879}; 1880 1881#define BGE_RXBDFLAG_END 0x0004 1882#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1883#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1884#define BGE_RXBDFLAG_ERROR 0x0400 --- 7 unchanged lines hidden (view full) --- 1892#define BGE_RXERRFLAG_LINK_LOST 0x0004 1893#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1894#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1895#define BGE_RXERRFLAG_RUNT 0x0020 1896#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1897#define BGE_RXERRFLAG_GIANT 0x0080 1898 1899struct bge_sts_idx { |
1900#if BYTE_ORDER == LITTLE_ENDIAN |
1901 u_int16_t bge_rx_prod_idx; 1902 u_int16_t bge_tx_cons_idx; |
1903#else 1904 u_int16_t bge_tx_cons_idx; 1905 u_int16_t bge_rx_prod_idx; 1906#endif |
1907}; 1908 1909struct bge_status_block { 1910 u_int32_t bge_status; 1911 u_int32_t bge_rsvd0; |
1912#if BYTE_ORDER == LITTLE_ENDIAN |
1913 u_int16_t bge_rx_jumbo_cons_idx; 1914 u_int16_t bge_rx_std_cons_idx; 1915 u_int16_t bge_rx_mini_cons_idx; 1916 u_int16_t bge_rsvd1; |
1917#else 1918 u_int16_t bge_rx_std_cons_idx; 1919 u_int16_t bge_rx_jumbo_cons_idx; 1920 u_int16_t bge_rsvd1; 1921 u_int16_t bge_rx_mini_cons_idx; 1922#endif |
1923 struct bge_sts_idx bge_idx[16]; 1924}; 1925 1926#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1927#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1928 1929#define BGE_STATFLAG_UPDATED 0x00000001 1930#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 --- 455 unchanged lines hidden (view full) --- 2386}; 2387 2388struct bge_softc { 2389 struct ifnet *bge_ifp; /* interface info */ 2390 device_t bge_dev; 2391 struct mtx bge_mtx; 2392 device_t bge_miibus; 2393 bus_space_handle_t bge_bhandle; |
2394 bus_space_tag_t bge_btag; 2395 void *bge_intrhand; 2396 struct resource *bge_irq; 2397 struct resource *bge_res; 2398 struct ifmedia bge_ifmedia; /* TBI media info */ 2399 u_int8_t bge_unit; /* interface number */ 2400 u_int8_t bge_extram; /* has external SSRAM */ 2401 u_int8_t bge_tbi; --- 37 unchanged lines hidden --- |