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1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *	1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 210152 2010-07-15 23:34:58Z yongari $	33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 211596 2010-08-22 01:39:09Z yongari $
34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81#define BGE_UNMAPPED 0x00001000 82#define BGE_UNMAPPED_END 0x00001FFF 83#define BGE_DMA_DESCRIPTORS 0x00002000 84#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85#define BGE_SEND_RING_1_TO_4 0x00004000 86#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 87 88/ Firmware interface / 89#define BGE_FW_DRV_ALIVE 0x00000001 90#define BGE_FW_PAUSE 0x00000002 91 92/ Mappings for internal memory configuration / 93#define BGE_STD_RX_RINGS 0x00006000 94#define BGE_STD_RX_RINGS_END 0x00006FFF 95#define BGE_JUMBO_RX_RINGS 0x00007000 96#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97#define BGE_BUFFPOOL_1 0x00008000 98#define BGE_BUFFPOOL_1_END 0x0000FFFF 99#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 100#define BGE_BUFFPOOL_2_END 0x00017FFF 101#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 102#define BGE_BUFFPOOL_3_END 0x0001FFFF 103* 104/* Mappings for external SSRAM configurations / 105#define BGE_SEND_RING_5_TO_6 0x00006000 106#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107#define BGE_SEND_RING_7_TO_8 0x00007000 108#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109#define BGE_SEND_RING_9_TO_16 0x00008000 110#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111#define BGE_EXT_STD_RX_RINGS 0x0000C000 112#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115#define BGE_MINI_RX_RINGS 0x0000E000 116#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 118#define BGE_AVAIL_REGION1_END 0x00017FFF 119#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 120#define BGE_AVAIL_REGION2_END 0x0001FFFF 121#define BGE_EXT_SSRAM 0x00020000 122#define BGE_EXT_SSRAM_END 0x000FFFFF 123* 124 125/* 126 * BCM570x register offsets. These are memory mapped registers 127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 128 * Each register must be accessed using 32 bit operations. 129 * 130 * All registers are accessed through a 32K shared memory block. 131 * The first group of registers are actually copies of the PCI 132 * configuration space registers. 133 / 134* 135/* 136 * PCI registers defined in the PCI 2.2 spec. 137 / 138#define BGE_PCI_VID 0x00 139#define BGE_PCI_DID 0x02 140#define BGE_PCI_CMD 0x04 141#define BGE_PCI_STS 0x06 142#define BGE_PCI_REV 0x08 143#define BGE_PCI_CLASS 0x09 144#define BGE_PCI_CACHESZ 0x0C 145#define BGE_PCI_LATTIMER 0x0D 146#define BGE_PCI_HDRTYPE 0x0E 147#define BGE_PCI_BIST 0x0F 148#define BGE_PCI_BAR0 0x10 149#define BGE_PCI_BAR1 0x14 150#define BGE_PCI_SUBSYS 0x2C 151#define BGE_PCI_SUBVID 0x2E 152#define BGE_PCI_ROMBASE 0x30 153#define BGE_PCI_CAPPTR 0x34 154#define BGE_PCI_INTLINE 0x3C 155#define BGE_PCI_INTPIN 0x3D 156#define BGE_PCI_MINGNT 0x3E 157#define BGE_PCI_MAXLAT 0x3F 158#define BGE_PCI_PCIXCAP 0x40 159#define BGE_PCI_NEXTPTR_PM 0x41 160#define BGE_PCI_PCIX_CMD 0x42 161#define BGE_PCI_PCIX_STS 0x44 162#define BGE_PCI_PWRMGMT_CAPID 0x48 163#define BGE_PCI_NEXTPTR_VPD 0x49 164#define BGE_PCI_PWRMGMT_CAPS 0x4A 165#define BGE_PCI_PWRMGMT_CMD 0x4C 166#define BGE_PCI_PWRMGMT_STS 0x4D 167#define BGE_PCI_PWRMGMT_DATA 0x4F 168#define BGE_PCI_VPD_CAPID 0x50 169#define BGE_PCI_NEXTPTR_MSI 0x51 170#define BGE_PCI_VPD_ADDR 0x52 171#define BGE_PCI_VPD_DATA 0x54 172#define BGE_PCI_MSI_CAPID 0x58 173#define BGE_PCI_NEXTPTR_NONE 0x59 174#define BGE_PCI_MSI_CTL 0x5A 175#define BGE_PCI_MSI_ADDR_HI 0x5C 176#define BGE_PCI_MSI_ADDR_LO 0x60 177#define BGE_PCI_MSI_DATA 0x64 178* 179/* 180 * PCI Express definitions 181 * According to 182 * PCI Express base specification, REV. 1.0a 183 / 184* 185/* PCI Express device control, 16bits / 186#define BGE_PCIE_DEVCTL 0x08 187#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 188#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 189#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 190#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 191#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 192#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 193#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 194* 195/* PCI MSI. ??? / 196#define BGE_PCIE_CAPID_REG 0xD0 197#define BGE_PCIE_CAPID 0x10 198* 199/* 200 * PCI registers specific to the BCM570x family. 201 / 202#define BGE_PCI_MISC_CTL 0x68 203#define BGE_PCI_DMA_RW_CTL 0x6C 204#define BGE_PCI_PCISTATE 0x70 205#define BGE_PCI_CLKCTL 0x74 206#define BGE_PCI_REG_BASEADDR 0x78 207#define BGE_PCI_MEMWIN_BASEADDR 0x7C 208#define BGE_PCI_REG_DATA 0x80 209#define BGE_PCI_MEMWIN_DATA 0x84 210#define BGE_PCI_MODECTL 0x88 211#define BGE_PCI_MISC_CFG 0x8C 212#define BGE_PCI_MISC_LOCALCTL 0x90 213#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 214#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219#define BGE_PCI_ISR_MBX_HI 0xB0 220#define BGE_PCI_ISR_MBX_LO 0xB4 221#define BGE_PCI_PRODID_ASICREV 0xBC 222* 223/* PCI Misc. Host control register / 224#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 225#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 226#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 227#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 228#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 229#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 230#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 231#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 232#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 233#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 234* 235#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 236#if BYTE_ORDER == LITTLE_ENDIAN 237#define BGE_DMA_SWAP_OPTIONS \ 238 BGE_MODECTL_WORDSWAP_NONFRAME\| \ 239 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 240#else 241#define BGE_DMA_SWAP_OPTIONS \ 242 BGE_MODECTL_WORDSWAP_NONFRAME\|BGE_MODECTL_BYTESWAP_NONFRAME\| \ 243 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 244#endif 245 246#define BGE_INIT \ 247 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 248 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 249 250#define BGE_CHIPID_TIGON_I 0x4000 251#define BGE_CHIPID_TIGON_II 0x6000 252#define BGE_CHIPID_BCM5700_A0 0x7000 253#define BGE_CHIPID_BCM5700_A1 0x7001 254#define BGE_CHIPID_BCM5700_B0 0x7100 255#define BGE_CHIPID_BCM5700_B1 0x7101 256#define BGE_CHIPID_BCM5700_B2 0x7102 257#define BGE_CHIPID_BCM5700_B3 0x7103 258#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 259#define BGE_CHIPID_BCM5700_C0 0x7200 260#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr / 261#define BGE_CHIPID_BCM5701_B0 0x0100 262#define BGE_CHIPID_BCM5701_B2 0x0102 263#define BGE_CHIPID_BCM5701_B5 0x0105 264#define BGE_CHIPID_BCM5703_A0 0x1000 265#define BGE_CHIPID_BCM5703_A1 0x1001 266#define BGE_CHIPID_BCM5703_A2 0x1002 267#define BGE_CHIPID_BCM5703_A3 0x1003 268#define BGE_CHIPID_BCM5703_B0 0x1100 269#define BGE_CHIPID_BCM5704_A0 0x2000 270#define BGE_CHIPID_BCM5704_A1 0x2001 271#define BGE_CHIPID_BCM5704_A2 0x2002 272#define BGE_CHIPID_BCM5704_A3 0x2003 273#define BGE_CHIPID_BCM5704_B0 0x2100 274#define BGE_CHIPID_BCM5705_A0 0x3000 275#define BGE_CHIPID_BCM5705_A1 0x3001 276#define BGE_CHIPID_BCM5705_A2 0x3002 277#define BGE_CHIPID_BCM5705_A3 0x3003 278#define BGE_CHIPID_BCM5750_A0 0x4000 279#define BGE_CHIPID_BCM5750_A1 0x4001 280#define BGE_CHIPID_BCM5750_A3 0x4000 281#define BGE_CHIPID_BCM5750_B0 0x4100 282#define BGE_CHIPID_BCM5750_B1 0x4101 283#define BGE_CHIPID_BCM5750_C0 0x4200 284#define BGE_CHIPID_BCM5750_C1 0x4201 285#define BGE_CHIPID_BCM5750_C2 0x4202 286#define BGE_CHIPID_BCM5714_A0 0x5000 287#define BGE_CHIPID_BCM5752_A0 0x6000 288#define BGE_CHIPID_BCM5752_A1 0x6001 289#define BGE_CHIPID_BCM5752_A2 0x6002 290#define BGE_CHIPID_BCM5714_B0 0x8000 291#define BGE_CHIPID_BCM5714_B3 0x8003 292#define BGE_CHIPID_BCM5715_A0 0x9000 293#define BGE_CHIPID_BCM5715_A1 0x9001 294#define BGE_CHIPID_BCM5715_A3 0x9003 295#define BGE_CHIPID_BCM5755_A0 0xa000 296#define BGE_CHIPID_BCM5755_A1 0xa001 297#define BGE_CHIPID_BCM5755_A2 0xa002 298#define BGE_CHIPID_BCM5722_A0 0xa200 299#define BGE_CHIPID_BCM5754_A0 0xb000 300#define BGE_CHIPID_BCM5754_A1 0xb001 301#define BGE_CHIPID_BCM5754_A2 0xb002 302#define BGE_CHIPID_BCM5761_A0 0x5761000 303#define BGE_CHIPID_BCM5761_A1 0x5761100 304#define BGE_CHIPID_BCM5784_A0 0x5784000 305#define BGE_CHIPID_BCM5784_A1 0x5784100 306#define BGE_CHIPID_BCM5787_A0 0xb000 307#define BGE_CHIPID_BCM5787_A1 0xb001 308#define BGE_CHIPID_BCM5787_A2 0xb002 309#define BGE_CHIPID_BCM5906_A1 0xc001 310#define BGE_CHIPID_BCM5906_A2 0xc002 311#define BGE_CHIPID_BCM57780_A0 0x57780000 312#define BGE_CHIPID_BCM57780_A1 0x57780001 313* 314/* shorthand one / 315#define BGE_ASICREV(x) ((x) >> 12) 316#define BGE_ASICREV_BCM5701 0x00 317#define BGE_ASICREV_BCM5703 0x01 318#define BGE_ASICREV_BCM5704 0x02 319#define BGE_ASICREV_BCM5705 0x03 320#define BGE_ASICREV_BCM5750 0x04 321#define BGE_ASICREV_BCM5714_A0 0x05 322#define BGE_ASICREV_BCM5752 0x06 323#define BGE_ASICREV_BCM5700 0x07 324#define BGE_ASICREV_BCM5780 0x08 325#define BGE_ASICREV_BCM5714 0x09 326#define BGE_ASICREV_BCM5755 0x0a 327#define BGE_ASICREV_BCM5754 0x0b 328#define BGE_ASICREV_BCM5787 0x0b 329#define BGE_ASICREV_BCM5906 0x0c 330/ Should consult BGE_PCI_PRODID_ASICREV for ChipID / 331#define BGE_ASICREV_USE_PRODID_REG 0x0f 332/ BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. / 333#define BGE_ASICREV_BCM5761 0x5761 334#define BGE_ASICREV_BCM5784 0x5784 335#define BGE_ASICREV_BCM5785 0x5785 336#define BGE_ASICREV_BCM57780 0x57780 337* 338/* chip revisions / 339#define BGE_CHIPREV(x) ((x) >> 8) 340#define BGE_CHIPREV_5700_AX 0x70 341#define BGE_CHIPREV_5700_BX 0x71 342#define BGE_CHIPREV_5700_CX 0x72 343#define BGE_CHIPREV_5701_AX 0x00 344#define BGE_CHIPREV_5703_AX 0x10 345#define BGE_CHIPREV_5704_AX 0x20 346#define BGE_CHIPREV_5704_BX 0x21 347#define BGE_CHIPREV_5750_AX 0x40 348#define BGE_CHIPREV_5750_BX 0x41 349/ BGE_PCI_PRODID_ASICREV chip rev. identifiers. / 350#define BGE_CHIPREV_5761_AX 0x57611 351#define BGE_CHIPREV_5784_AX 0x57841 352* 353/* PCI DMA Read/Write Control register / 354#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 355#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 356#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 357#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 358#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 359#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 360#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 361#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 362#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 363#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 364#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 365#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 366* 367#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 368#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 369#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 370#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 371 372#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 373#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 374#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 375#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 376#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 377#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 378#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 379#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 380 381#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 382#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 383#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 384#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 385#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 386#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 387#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 388#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 389 390/* 391 * PCI state register -- note, this register is read only 392 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 393 * register is set. 394 / 395#define BGE_PCISTATE_FORCE_RESET 0x00000001 396#define BGE_PCISTATE_INTR_STATE 0x00000002 397#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 398#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 66/133, 0 = 33/66 / 399#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 400#define BGE_PCISTATE_WANT_EXPROM 0x00000020 401#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 402#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 403#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 404* 405/* 406 * PCI Clock Control register -- note, this register is read only 407 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 408 * register is set. 409 / 410#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 411#define BGE_PCICLOCKCTL_M66EN 0x00000080 412#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 413#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 414#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 415#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 416#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 417#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 418#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 419#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 420* 421 422#ifndef PCIM_CMD_MWIEN 423#define PCIM_CMD_MWIEN 0x0010 424#endif 425#ifndef PCIM_CMD_INTxDIS 426#define PCIM_CMD_INTxDIS 0x0400 427#endif 428 429/* 430 * High priority mailbox registers 431 * Each mailbox is 64-bits wide, though we only use the 432 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 433 * first. The NIC will load the mailbox after the lower 32 bit word 434 * has been updated. 435 / 436#define BGE_MBX_IRQ0_HI 0x0200 437#define BGE_MBX_IRQ0_LO 0x0204 438#define BGE_MBX_IRQ1_HI 0x0208 439#define BGE_MBX_IRQ1_LO 0x020C 440#define BGE_MBX_IRQ2_HI 0x0210 441#define BGE_MBX_IRQ2_LO 0x0214 442#define BGE_MBX_IRQ3_HI 0x0218 443#define BGE_MBX_IRQ3_LO 0x021C 444#define BGE_MBX_GEN0_HI 0x0220 445#define BGE_MBX_GEN0_LO 0x0224 446#define BGE_MBX_GEN1_HI 0x0228 447#define BGE_MBX_GEN1_LO 0x022C 448#define BGE_MBX_GEN2_HI 0x0230 449#define BGE_MBX_GEN2_LO 0x0234 450#define BGE_MBX_GEN3_HI 0x0228 451#define BGE_MBX_GEN3_LO 0x022C 452#define BGE_MBX_GEN4_HI 0x0240 453#define BGE_MBX_GEN4_LO 0x0244 454#define BGE_MBX_GEN5_HI 0x0248 455#define BGE_MBX_GEN5_LO 0x024C 456#define BGE_MBX_GEN6_HI 0x0250 457#define BGE_MBX_GEN6_LO 0x0254 458#define BGE_MBX_GEN7_HI 0x0258 459#define BGE_MBX_GEN7_LO 0x025C 460#define BGE_MBX_RELOAD_STATS_HI 0x0260 461#define BGE_MBX_RELOAD_STATS_LO 0x0264 462#define BGE_MBX_RX_STD_PROD_HI 0x0268 463#define BGE_MBX_RX_STD_PROD_LO 0x026C 464#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 465#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 466#define BGE_MBX_RX_MINI_PROD_HI 0x0278 467#define BGE_MBX_RX_MINI_PROD_LO 0x027C 468#define BGE_MBX_RX_CONS0_HI 0x0280 469#define BGE_MBX_RX_CONS0_LO 0x0284 470#define BGE_MBX_RX_CONS1_HI 0x0288 471#define BGE_MBX_RX_CONS1_LO 0x028C 472#define BGE_MBX_RX_CONS2_HI 0x0290 473#define BGE_MBX_RX_CONS2_LO 0x0294 474#define BGE_MBX_RX_CONS3_HI 0x0298 475#define BGE_MBX_RX_CONS3_LO 0x029C 476#define BGE_MBX_RX_CONS4_HI 0x02A0 477#define BGE_MBX_RX_CONS4_LO 0x02A4 478#define BGE_MBX_RX_CONS5_HI 0x02A8 479#define BGE_MBX_RX_CONS5_LO 0x02AC 480#define BGE_MBX_RX_CONS6_HI 0x02B0 481#define BGE_MBX_RX_CONS6_LO 0x02B4 482#define BGE_MBX_RX_CONS7_HI 0x02B8 483#define BGE_MBX_RX_CONS7_LO 0x02BC 484#define BGE_MBX_RX_CONS8_HI 0x02C0 485#define BGE_MBX_RX_CONS8_LO 0x02C4 486#define BGE_MBX_RX_CONS9_HI 0x02C8 487#define BGE_MBX_RX_CONS9_LO 0x02CC 488#define BGE_MBX_RX_CONS10_HI 0x02D0 489#define BGE_MBX_RX_CONS10_LO 0x02D4 490#define BGE_MBX_RX_CONS11_HI 0x02D8 491#define BGE_MBX_RX_CONS11_LO 0x02DC 492#define BGE_MBX_RX_CONS12_HI 0x02E0 493#define BGE_MBX_RX_CONS12_LO 0x02E4 494#define BGE_MBX_RX_CONS13_HI 0x02E8 495#define BGE_MBX_RX_CONS13_LO 0x02EC 496#define BGE_MBX_RX_CONS14_HI 0x02F0 497#define BGE_MBX_RX_CONS14_LO 0x02F4 498#define BGE_MBX_RX_CONS15_HI 0x02F8 499#define BGE_MBX_RX_CONS15_LO 0x02FC 500#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 501#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 502#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 503#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 504#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 505#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 506#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 507#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 508#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 509#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 510#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 511#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 512#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 513#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 514#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 515#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 516#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 517#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 518#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 519#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 520#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 521#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 522#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 523#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 524#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 525#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 526#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 527#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 528#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 529#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 530#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 531#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 532#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 533#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 534#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 535#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 536#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 537#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 538#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 539#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 540#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 541#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 542#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 543#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 544#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 545#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 546#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 547#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 548#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 549#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 550#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 551#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 552#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 553#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 554#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 555#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 556#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 557#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 558#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 559#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 560#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 561#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 562#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 563#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 564* 565#define BGE_TX_RINGS_MAX 4 566#define BGE_TX_RINGS_EXTSSRAM_MAX 16 567#define BGE_RX_RINGS_MAX 16 568 569/* Ethernet MAC control registers / 570#define BGE_MAC_MODE 0x0400 571#define BGE_MAC_STS 0x0404 572#define BGE_MAC_EVT_ENB 0x0408 573#define BGE_MAC_LED_CTL 0x040C 574#define BGE_MAC_ADDR1_LO 0x0410 575#define BGE_MAC_ADDR1_HI 0x0414 576#define BGE_MAC_ADDR2_LO 0x0418 577#define BGE_MAC_ADDR2_HI 0x041C 578#define BGE_MAC_ADDR3_LO 0x0420 579#define BGE_MAC_ADDR3_HI 0x0424 580#define BGE_MAC_ADDR4_LO 0x0428 581#define BGE_MAC_ADDR4_HI 0x042C 582#define BGE_WOL_PATPTR 0x0430 583#define BGE_WOL_PATCFG 0x0434 584#define BGE_TX_RANDOM_BACKOFF 0x0438 585#define BGE_RX_MTU 0x043C 586#define BGE_GBIT_PCS_TEST 0x0440 587#define BGE_TX_TBI_AUTONEG 0x0444 588#define BGE_RX_TBI_AUTONEG 0x0448 589#define BGE_MI_COMM 0x044C 590#define BGE_MI_STS 0x0450 591#define BGE_MI_MODE 0x0454 592#define BGE_AUTOPOLL_STS 0x0458 593#define BGE_TX_MODE 0x045C 594#define BGE_TX_STS 0x0460 595#define BGE_TX_LENGTHS 0x0464 596#define BGE_RX_MODE 0x0468 597#define BGE_RX_STS 0x046C 598#define BGE_MAR0 0x0470 599#define BGE_MAR1 0x0474 600#define BGE_MAR2 0x0478 601#define BGE_MAR3 0x047C 602#define BGE_RX_BD_RULES_CTL0 0x0480 603#define BGE_RX_BD_RULES_MASKVAL0 0x0484 604#define BGE_RX_BD_RULES_CTL1 0x0488 605#define BGE_RX_BD_RULES_MASKVAL1 0x048C 606#define BGE_RX_BD_RULES_CTL2 0x0490 607#define BGE_RX_BD_RULES_MASKVAL2 0x0494 608#define BGE_RX_BD_RULES_CTL3 0x0498 609#define BGE_RX_BD_RULES_MASKVAL3 0x049C 610#define BGE_RX_BD_RULES_CTL4 0x04A0 611#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 612#define BGE_RX_BD_RULES_CTL5 0x04A8 613#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 614#define BGE_RX_BD_RULES_CTL6 0x04B0 615#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 616#define BGE_RX_BD_RULES_CTL7 0x04B8 617#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 618#define BGE_RX_BD_RULES_CTL8 0x04C0 619#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 620#define BGE_RX_BD_RULES_CTL9 0x04C8 621#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 622#define BGE_RX_BD_RULES_CTL10 0x04D0 623#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 624#define BGE_RX_BD_RULES_CTL11 0x04D8 625#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 626#define BGE_RX_BD_RULES_CTL12 0x04E0 627#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 628#define BGE_RX_BD_RULES_CTL13 0x04E8 629#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 630#define BGE_RX_BD_RULES_CTL14 0x04F0 631#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 632#define BGE_RX_BD_RULES_CTL15 0x04F8 633#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 634#define BGE_RX_RULES_CFG 0x0500 635#define BGE_SERDES_CFG 0x0590 636#define BGE_SERDES_STS 0x0594 637#define BGE_SGDIG_CFG 0x05B0 638#define BGE_SGDIG_STS 0x05B4 639#define BGE_MAC_STATS 0x0800 640* 641/* Ethernet MAC Mode register / 642#define BGE_MACMODE_RESET 0x00000001 643#define BGE_MACMODE_HALF_DUPLEX 0x00000002 644#define BGE_MACMODE_PORTMODE 0x0000000C 645#define BGE_MACMODE_LOOPBACK 0x00000010 646#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 647#define BGE_MACMODE_TX_BURST_ENB 0x00000100 648#define BGE_MACMODE_MAX_DEFER 0x00000200 649#define BGE_MACMODE_LINK_POLARITY 0x00000400 650#define BGE_MACMODE_RX_STATS_ENB 0x00000800 651#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 652#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 653#define BGE_MACMODE_TX_STATS_ENB 0x00004000 654#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 655#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 656#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 657#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 658#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 659#define BGE_MACMODE_MIP_ENB 0x00100000 660#define BGE_MACMODE_TXDMA_ENB 0x00200000 661#define BGE_MACMODE_RXDMA_ENB 0x00400000 662#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 663* 664#define BGE_PORTMODE_NONE 0x00000000 665#define BGE_PORTMODE_MII 0x00000004 666#define BGE_PORTMODE_GMII 0x00000008 667#define BGE_PORTMODE_TBI 0x0000000C 668 669/* MAC Status register / 670#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 671#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 672#define BGE_MACSTAT_RX_CFG 0x00000004 673#define BGE_MACSTAT_CFG_CHANGED 0x00000008 674#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 675#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 676#define BGE_MACSTAT_LINK_CHANGED 0x00001000 677#define BGE_MACSTAT_MI_COMPLETE 0x00400000 678#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 679#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 680#define BGE_MACSTAT_ODI_ERROR 0x02000000 681#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 682#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 683* 684/* MAC Event Enable Register / 685#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 686#define BGE_EVTENB_LINK_CHANGED 0x00001000 687#define BGE_EVTENB_MI_COMPLETE 0x00400000 688#define BGE_EVTENB_MI_INTERRUPT 0x00800000 689#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 690#define BGE_EVTENB_ODI_ERROR 0x02000000 691#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 692#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 693* 694/* LED Control Register / 695#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 696#define BGE_LEDCTL_1000MBPS_LED 0x00000002 697#define BGE_LEDCTL_100MBPS_LED 0x00000004 698#define BGE_LEDCTL_10MBPS_LED 0x00000008 699#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 700#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 701#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 702#define BGE_LEDCTL_1000MBPS_STS 0x00000080 703#define BGE_LEDCTL_100MBPS_STS 0x00000100 704#define BGE_LEDCTL_10MBPS_STS 0x00000200 705#define BGE_LEDCTL_TRADLED_STS 0x00000400 706#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 707#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 708* 709/* TX backoff seed register / 710#define BGE_TX_BACKOFF_SEED_MASK 0x3F 711* 712/* Autopoll status register / 713#define BGE_AUTOPOLLSTS_ERROR 0x00000001 714* 715/* Transmit MAC mode register / 716#define BGE_TXMODE_RESET 0x00000001 717#define BGE_TXMODE_ENABLE 0x00000002 718#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 719#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 720#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 721* 722/* Transmit MAC status register / 723#define BGE_TXSTAT_RX_XOFFED 0x00000001 724#define BGE_TXSTAT_SENT_XOFF 0x00000002 725#define BGE_TXSTAT_SENT_XON 0x00000004 726#define BGE_TXSTAT_LINK_UP 0x00000008 727#define BGE_TXSTAT_ODI_UFLOW 0x00000010 728#define BGE_TXSTAT_ODI_OFLOW 0x00000020 729* 730/* Transmit MAC lengths register / 731#define BGE_TXLEN_SLOTTIME 0x000000FF 732#define BGE_TXLEN_IPG 0x00000F00 733#define BGE_TXLEN_CRS 0x00003000 734* 735/* Receive MAC mode register / 736#define BGE_RXMODE_RESET 0x00000001 737#define BGE_RXMODE_ENABLE 0x00000002 738#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 739#define BGE_RXMODE_RX_GIANTS 0x00000020 740#define BGE_RXMODE_RX_RUNTS 0x00000040 741#define BGE_RXMODE_8022_LENCHECK 0x00000080 742#define BGE_RXMODE_RX_PROMISC 0x00000100 743#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 744#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 745* 746/* Receive MAC status register / 747#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 748#define BGE_RXSTAT_RCVD_XOFF 0x00000002 749#define BGE_RXSTAT_RCVD_XON 0x00000004 750* 751/* Receive Rules Control register / 752#define BGE_RXRULECTL_OFFSET 0x000000FF 753#define BGE_RXRULECTL_CLASS 0x00001F00 754#define BGE_RXRULECTL_HDRTYPE 0x0000E000 755#define BGE_RXRULECTL_COMPARE_OP 0x00030000 756#define BGE_RXRULECTL_MAP 0x01000000 757#define BGE_RXRULECTL_DISCARD 0x02000000 758#define BGE_RXRULECTL_MASK 0x04000000 759#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 760#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 761#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 762#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 763* 764/* Receive Rules Mask register / 765#define BGE_RXRULEMASK_VALUE 0x0000FFFF 766#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 767* 768/* SERDES configuration register / 769#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 770#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 771#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 772#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 773#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 774#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 775#define BGE_SERDESCFG_TXMODE 0x00001000 776#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 777#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 778#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 779#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 780#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 781#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 782#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 783#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 784#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 785* 786/* SERDES status register / 787#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 788#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 789* 790/* SGDIG config (not documented) / 791#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 792#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 793#define BGE_SGDIGCFG_SEND 0x40000000 794#define BGE_SGDIGCFG_AUTO 0x80000000 795* 796/* SGDIG status (not documented) / 797#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 798#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 799#define BGE_SGDIGSTS_DONE 0x00000002 800* 801 802/* MI communication register / 803#define BGE_MICOMM_DATA 0x0000FFFF 804#define BGE_MICOMM_REG 0x001F0000 805#define BGE_MICOMM_PHY 0x03E00000 806#define BGE_MICOMM_CMD 0x0C000000 807#define BGE_MICOMM_READFAIL 0x10000000 808#define BGE_MICOMM_BUSY 0x20000000 809* 810#define BGE_MIREG(x) ((x & 0x1F) << 16) 811#define BGE_MIPHY(x) ((x & 0x1F) << 21) 812#define BGE_MICMD_WRITE 0x04000000 813#define BGE_MICMD_READ 0x08000000 814 815/* MI status register / 816#define BGE_MISTS_LINK 0x00000001 817#define BGE_MISTS_10MBPS 0x00000002 818* 819#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 820#define BGE_MIMODE_AUTOPOLL 0x00000010 821#define BGE_MIMODE_CLKCNT 0x001F0000 822 823 824/* 825 * Send data initiator control registers. 826 / 827#define BGE_SDI_MODE 0x0C00 828#define BGE_SDI_STATUS 0x0C04 829#define BGE_SDI_STATS_CTL 0x0C08 830#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 831#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 832#define BGE_LOCSTATS_COS0 0x0C80 833#define BGE_LOCSTATS_COS1 0x0C84 834#define BGE_LOCSTATS_COS2 0x0C88 835#define BGE_LOCSTATS_COS3 0x0C8C 836#define BGE_LOCSTATS_COS4 0x0C90 837#define BGE_LOCSTATS_COS5 0x0C84 838#define BGE_LOCSTATS_COS6 0x0C98 839#define BGE_LOCSTATS_COS7 0x0C9C 840#define BGE_LOCSTATS_COS8 0x0CA0 841#define BGE_LOCSTATS_COS9 0x0CA4 842#define BGE_LOCSTATS_COS10 0x0CA8 843#define BGE_LOCSTATS_COS11 0x0CAC 844#define BGE_LOCSTATS_COS12 0x0CB0 845#define BGE_LOCSTATS_COS13 0x0CB4 846#define BGE_LOCSTATS_COS14 0x0CB8 847#define BGE_LOCSTATS_COS15 0x0CBC 848#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 849#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 850#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 851#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 852#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 853#define BGE_LOCSTATS_IRQS 0x0CD4 854#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 855#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 856* 857/* Send Data Initiator mode register / 858#define BGE_SDIMODE_RESET 0x00000001 859#define BGE_SDIMODE_ENABLE 0x00000002 860#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 861* 862/* Send Data Initiator stats register / 863#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 864* 865/* Send Data Initiator stats control register / 866#define BGE_SDISTATSCTL_ENABLE 0x00000001 867#define BGE_SDISTATSCTL_FASTER 0x00000002 868#define BGE_SDISTATSCTL_CLEAR 0x00000004 869#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 870#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 871* 872/* 873 * Send Data Completion Control registers 874 / 875#define BGE_SDC_MODE 0x1000 876#define BGE_SDC_STATUS 0x1004 877* 878/* Send Data completion mode register / 879#define BGE_SDCMODE_RESET 0x00000001 880#define BGE_SDCMODE_ENABLE 0x00000002 881#define BGE_SDCMODE_ATTN 0x00000004 882#define BGE_SDCMODE_CDELAY 0x00000010 883* 884/* Send Data completion status register / 885#define BGE_SDCSTAT_ATTN 0x00000004 886* 887/* 888 * Send BD Ring Selector Control registers 889 / 890#define BGE_SRS_MODE 0x1400 891#define BGE_SRS_STATUS 0x1404 892#define BGE_SRS_HWDIAG 0x1408 893#define BGE_SRS_LOC_NIC_CONS0 0x1440 894#define BGE_SRS_LOC_NIC_CONS1 0x1444 895#define BGE_SRS_LOC_NIC_CONS2 0x1448 896#define BGE_SRS_LOC_NIC_CONS3 0x144C 897#define BGE_SRS_LOC_NIC_CONS4 0x1450 898#define BGE_SRS_LOC_NIC_CONS5 0x1454 899#define BGE_SRS_LOC_NIC_CONS6 0x1458 900#define BGE_SRS_LOC_NIC_CONS7 0x145C 901#define BGE_SRS_LOC_NIC_CONS8 0x1460 902#define BGE_SRS_LOC_NIC_CONS9 0x1464 903#define BGE_SRS_LOC_NIC_CONS10 0x1468 904#define BGE_SRS_LOC_NIC_CONS11 0x146C 905#define BGE_SRS_LOC_NIC_CONS12 0x1470 906#define BGE_SRS_LOC_NIC_CONS13 0x1474 907#define BGE_SRS_LOC_NIC_CONS14 0x1478 908#define BGE_SRS_LOC_NIC_CONS15 0x147C 909* 910/* Send BD Ring Selector Mode register / 911#define BGE_SRSMODE_RESET 0x00000001 912#define BGE_SRSMODE_ENABLE 0x00000002 913#define BGE_SRSMODE_ATTN 0x00000004 914* 915/* Send BD Ring Selector Status register / 916#define BGE_SRSSTAT_ERROR 0x00000004 917* 918/* Send BD Ring Selector HW Diagnostics register / 919#define BGE_SRSHWDIAG_STATE 0x0000000F 920#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 921#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 922#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 923* 924/* 925 * Send BD Initiator Selector Control registers 926 / 927#define BGE_SBDI_MODE 0x1800 928#define BGE_SBDI_STATUS 0x1804 929#define BGE_SBDI_LOC_NIC_PROD0 0x1808 930#define BGE_SBDI_LOC_NIC_PROD1 0x180C 931#define BGE_SBDI_LOC_NIC_PROD2 0x1810 932#define BGE_SBDI_LOC_NIC_PROD3 0x1814 933#define BGE_SBDI_LOC_NIC_PROD4 0x1818 934#define BGE_SBDI_LOC_NIC_PROD5 0x181C 935#define BGE_SBDI_LOC_NIC_PROD6 0x1820 936#define BGE_SBDI_LOC_NIC_PROD7 0x1824 937#define BGE_SBDI_LOC_NIC_PROD8 0x1828 938#define BGE_SBDI_LOC_NIC_PROD9 0x182C 939#define BGE_SBDI_LOC_NIC_PROD10 0x1830 940#define BGE_SBDI_LOC_NIC_PROD11 0x1834 941#define BGE_SBDI_LOC_NIC_PROD12 0x1838 942#define BGE_SBDI_LOC_NIC_PROD13 0x183C 943#define BGE_SBDI_LOC_NIC_PROD14 0x1840 944#define BGE_SBDI_LOC_NIC_PROD15 0x1844 945* 946/* Send BD Initiator Mode register / 947#define BGE_SBDIMODE_RESET 0x00000001 948#define BGE_SBDIMODE_ENABLE 0x00000002 949#define BGE_SBDIMODE_ATTN 0x00000004 950* 951/* Send BD Initiator Status register / 952#define BGE_SBDISTAT_ERROR 0x00000004 953* 954/* 955 * Send BD Completion Control registers 956 / 957#define BGE_SBDC_MODE 0x1C00 958#define BGE_SBDC_STATUS 0x1C04 959* 960/* Send BD Completion Control Mode register / 961#define BGE_SBDCMODE_RESET 0x00000001 962#define BGE_SBDCMODE_ENABLE 0x00000002 963#define BGE_SBDCMODE_ATTN 0x00000004 964* 965/* Send BD Completion Control Status register / 966#define BGE_SBDCSTAT_ATTN 0x00000004 967* 968/* 969 * Receive List Placement Control registers 970 / 971#define BGE_RXLP_MODE 0x2000 972#define BGE_RXLP_STATUS 0x2004 973#define BGE_RXLP_SEL_LIST_LOCK 0x2008 974#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 975#define BGE_RXLP_CFG 0x2010 976#define BGE_RXLP_STATS_CTL 0x2014 977#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 978#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 979#define BGE_RXLP_HEAD0 0x2100 980#define BGE_RXLP_TAIL0 0x2104 981#define BGE_RXLP_COUNT0 0x2108 982#define BGE_RXLP_HEAD1 0x2110 983#define BGE_RXLP_TAIL1 0x2114 984#define BGE_RXLP_COUNT1 0x2118 985#define BGE_RXLP_HEAD2 0x2120 986#define BGE_RXLP_TAIL2 0x2124 987#define BGE_RXLP_COUNT2 0x2128 988#define BGE_RXLP_HEAD3 0x2130 989#define BGE_RXLP_TAIL3 0x2134 990#define BGE_RXLP_COUNT3 0x2138 991#define BGE_RXLP_HEAD4 0x2140 992#define BGE_RXLP_TAIL4 0x2144 993#define BGE_RXLP_COUNT4 0x2148 994#define BGE_RXLP_HEAD5 0x2150 995#define BGE_RXLP_TAIL5 0x2154 996#define BGE_RXLP_COUNT5 0x2158 997#define BGE_RXLP_HEAD6 0x2160 998#define BGE_RXLP_TAIL6 0x2164 999#define BGE_RXLP_COUNT6 0x2168 1000#define BGE_RXLP_HEAD7 0x2170 1001#define BGE_RXLP_TAIL7 0x2174 1002#define BGE_RXLP_COUNT7 0x2178 1003#define BGE_RXLP_HEAD8 0x2180 1004#define BGE_RXLP_TAIL8 0x2184 1005#define BGE_RXLP_COUNT8 0x2188 1006#define BGE_RXLP_HEAD9 0x2190 1007#define BGE_RXLP_TAIL9 0x2194 1008#define BGE_RXLP_COUNT9 0x2198 1009#define BGE_RXLP_HEAD10 0x21A0 1010#define BGE_RXLP_TAIL10 0x21A4 1011#define BGE_RXLP_COUNT10 0x21A8 1012#define BGE_RXLP_HEAD11 0x21B0 1013#define BGE_RXLP_TAIL11 0x21B4 1014#define BGE_RXLP_COUNT11 0x21B8 1015#define BGE_RXLP_HEAD12 0x21C0 1016#define BGE_RXLP_TAIL12 0x21C4 1017#define BGE_RXLP_COUNT12 0x21C8 1018#define BGE_RXLP_HEAD13 0x21D0 1019#define BGE_RXLP_TAIL13 0x21D4 1020#define BGE_RXLP_COUNT13 0x21D8 1021#define BGE_RXLP_HEAD14 0x21E0 1022#define BGE_RXLP_TAIL14 0x21E4 1023#define BGE_RXLP_COUNT14 0x21E8 1024#define BGE_RXLP_HEAD15 0x21F0 1025#define BGE_RXLP_TAIL15 0x21F4 1026#define BGE_RXLP_COUNT15 0x21F8 1027#define BGE_RXLP_LOCSTAT_COS0 0x2200 1028#define BGE_RXLP_LOCSTAT_COS1 0x2204 1029#define BGE_RXLP_LOCSTAT_COS2 0x2208 1030#define BGE_RXLP_LOCSTAT_COS3 0x220C 1031#define BGE_RXLP_LOCSTAT_COS4 0x2210 1032#define BGE_RXLP_LOCSTAT_COS5 0x2214 1033#define BGE_RXLP_LOCSTAT_COS6 0x2218 1034#define BGE_RXLP_LOCSTAT_COS7 0x221C 1035#define BGE_RXLP_LOCSTAT_COS8 0x2220 1036#define BGE_RXLP_LOCSTAT_COS9 0x2224 1037#define BGE_RXLP_LOCSTAT_COS10 0x2228 1038#define BGE_RXLP_LOCSTAT_COS11 0x222C 1039#define BGE_RXLP_LOCSTAT_COS12 0x2230 1040#define BGE_RXLP_LOCSTAT_COS13 0x2234 1041#define BGE_RXLP_LOCSTAT_COS14 0x2238 1042#define BGE_RXLP_LOCSTAT_COS15 0x223C 1043#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1044#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1045#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1046#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1047#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1048#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1049#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1050* 1051 1052/* Receive List Placement mode register / 1053#define BGE_RXLPMODE_RESET 0x00000001 1054#define BGE_RXLPMODE_ENABLE 0x00000002 1055#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1056#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1057#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1058* 1059/* Receive List Placement Status register / 1060#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1061#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1062#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1063* 1064/* 1065 * Receive Data and Receive BD Initiator Control Registers 1066 / 1067#define BGE_RDBDI_MODE 0x2400 1068#define BGE_RDBDI_STATUS 0x2404 1069#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1070#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1071#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1072#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1073#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1074#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1075#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1076#define BGE_RX_STD_RCB_NICADDR 0x245C 1077#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1078#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1079#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1080#define BGE_RX_MINI_RCB_NICADDR 0x246C 1081#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1082#define BGE_RDBDI_STD_RX_CONS 0x2474 1083#define BGE_RDBDI_MINI_RX_CONS 0x2478 1084#define BGE_RDBDI_RETURN_PROD0 0x2480 1085#define BGE_RDBDI_RETURN_PROD1 0x2484 1086#define BGE_RDBDI_RETURN_PROD2 0x2488 1087#define BGE_RDBDI_RETURN_PROD3 0x248C 1088#define BGE_RDBDI_RETURN_PROD4 0x2490 1089#define BGE_RDBDI_RETURN_PROD5 0x2494 1090#define BGE_RDBDI_RETURN_PROD6 0x2498 1091#define BGE_RDBDI_RETURN_PROD7 0x249C 1092#define BGE_RDBDI_RETURN_PROD8 0x24A0 1093#define BGE_RDBDI_RETURN_PROD9 0x24A4 1094#define BGE_RDBDI_RETURN_PROD10 0x24A8 1095#define BGE_RDBDI_RETURN_PROD11 0x24AC 1096#define BGE_RDBDI_RETURN_PROD12 0x24B0 1097#define BGE_RDBDI_RETURN_PROD13 0x24B4 1098#define BGE_RDBDI_RETURN_PROD14 0x24B8 1099#define BGE_RDBDI_RETURN_PROD15 0x24BC 1100#define BGE_RDBDI_HWDIAG 0x24C0 1101* 1102 1103/* Receive Data and Receive BD Initiator Mode register / 1104#define BGE_RDBDIMODE_RESET 0x00000001 1105#define BGE_RDBDIMODE_ENABLE 0x00000002 1106#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1107#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1108#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1109* 1110/* Receive Data and Receive BD Initiator Status register / 1111#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1112#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1113#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1114* 1115 1116/* 1117 * Receive Data Completion Control registers 1118 / 1119#define BGE_RDC_MODE 0x2800 1120* 1121/* Receive Data Completion Mode register / 1122#define BGE_RDCMODE_RESET 0x00000001 1123#define BGE_RDCMODE_ENABLE 0x00000002 1124#define BGE_RDCMODE_ATTN 0x00000004 1125* 1126/* 1127 * Receive BD Initiator Control registers 1128 / 1129#define BGE_RBDI_MODE 0x2C00 1130#define BGE_RBDI_STATUS 0x2C04 1131#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1132#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1133#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1134#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1135#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1136#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1137* 1138/* Receive BD Initiator Mode register / 1139#define BGE_RBDIMODE_RESET 0x00000001 1140#define BGE_RBDIMODE_ENABLE 0x00000002 1141#define BGE_RBDIMODE_ATTN 0x00000004 1142* 1143/* Receive BD Initiator Status register / 1144#define BGE_RBDISTAT_ATTN 0x00000004 1145* 1146/* 1147 * Receive BD Completion Control registers 1148 / 1149#define BGE_RBDC_MODE 0x3000 1150#define BGE_RBDC_STATUS 0x3004 1151#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1152#define BGE_RBDC_STD_BD_PROD 0x300C 1153#define BGE_RBDC_MINI_BD_PROD 0x3010 1154* 1155/* Receive BD completion mode register / 1156#define BGE_RBDCMODE_RESET 0x00000001 1157#define BGE_RBDCMODE_ENABLE 0x00000002 1158#define BGE_RBDCMODE_ATTN 0x00000004 1159* 1160/* Receive BD completion status register / 1161#define BGE_RBDCSTAT_ERROR 0x00000004 1162* 1163/* 1164 * Receive List Selector Control registers 1165 / 1166#define BGE_RXLS_MODE 0x3400 1167#define BGE_RXLS_STATUS 0x3404 1168* 1169/* Receive List Selector Mode register / 1170#define BGE_RXLSMODE_RESET 0x00000001 1171#define BGE_RXLSMODE_ENABLE 0x00000002 1172#define BGE_RXLSMODE_ATTN 0x00000004 1173* 1174/* Receive List Selector Status register / 1175#define BGE_RXLSSTAT_ERROR 0x00000004 1176* 1177/* 1178 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1179 / 1180#define BGE_MBCF_MODE 0x3800 1181#define BGE_MBCF_STATUS 0x3804 1182* 1183/* Mbuf Cluster Free mode register / 1184#define BGE_MBCFMODE_RESET 0x00000001 1185#define BGE_MBCFMODE_ENABLE 0x00000002 1186#define BGE_MBCFMODE_ATTN 0x00000004 1187* 1188/* Mbuf Cluster Free status register / 1189#define BGE_MBCFSTAT_ERROR 0x00000004 1190* 1191/* 1192 * Host Coalescing Control registers 1193 / 1194#define BGE_HCC_MODE 0x3C00 1195#define BGE_HCC_STATUS 0x3C04 1196#define BGE_HCC_RX_COAL_TICKS 0x3C08 1197#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1198#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1199#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1200#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1201#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1202#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1203#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1204#define BGE_HCC_STATS_TICKS 0x3C28 1205#define BGE_HCC_STATS_ADDR_HI 0x3C30 1206#define BGE_HCC_STATS_ADDR_LO 0x3C34 1207#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1208#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1209#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1210#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1211#define BGE_FLOW_ATTN 0x3C48 1212#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1213#define BGE_HCC_STD_BD_CONS 0x3C54 1214#define BGE_HCC_MINI_BD_CONS 0x3C58 1215#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1216#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1217#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1218#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1219#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1220#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1221#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1222#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1223#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1224#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1225#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1226#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1227#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1228#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1229#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1230#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1231#define BGE_HCC_TX_BD_CONS0 0x3CC0 1232#define BGE_HCC_TX_BD_CONS1 0x3CC4 1233#define BGE_HCC_TX_BD_CONS2 0x3CC8 1234#define BGE_HCC_TX_BD_CONS3 0x3CCC 1235#define BGE_HCC_TX_BD_CONS4 0x3CD0 1236#define BGE_HCC_TX_BD_CONS5 0x3CD4 1237#define BGE_HCC_TX_BD_CONS6 0x3CD8 1238#define BGE_HCC_TX_BD_CONS7 0x3CDC 1239#define BGE_HCC_TX_BD_CONS8 0x3CE0 1240#define BGE_HCC_TX_BD_CONS9 0x3CE4 1241#define BGE_HCC_TX_BD_CONS10 0x3CE8 1242#define BGE_HCC_TX_BD_CONS11 0x3CEC 1243#define BGE_HCC_TX_BD_CONS12 0x3CF0 1244#define BGE_HCC_TX_BD_CONS13 0x3CF4 1245#define BGE_HCC_TX_BD_CONS14 0x3CF8 1246#define BGE_HCC_TX_BD_CONS15 0x3CFC 1247* 1248 1249/* Host coalescing mode register / 1250#define BGE_HCCMODE_RESET 0x00000001 1251#define BGE_HCCMODE_ENABLE 0x00000002 1252#define BGE_HCCMODE_ATTN 0x00000004 1253#define BGE_HCCMODE_COAL_NOW 0x00000008 1254#define BGE_HCCMODE_MSI_BITS 0x00000070 1255#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1256* 1257#define BGE_STATBLKSZ_FULL 0x00000000 1258#define BGE_STATBLKSZ_64BYTE 0x00000080 1259#define BGE_STATBLKSZ_32BYTE 0x00000100 1260 1261/* Host coalescing status register / 1262#define BGE_HCCSTAT_ERROR 0x00000004 1263* 1264/* Flow attention register / 1265#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1266#define BGE_FLOWATTN_MEMARB 0x00000080 1267#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1268#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1269#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1270#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1271#define BGE_FLOWATTN_RDBDI 0x00080000 1272#define BGE_FLOWATTN_RXLS 0x00100000 1273#define BGE_FLOWATTN_RXLP 0x00200000 1274#define BGE_FLOWATTN_RBDC 0x00400000 1275#define BGE_FLOWATTN_RBDI 0x00800000 1276#define BGE_FLOWATTN_SDC 0x08000000 1277#define BGE_FLOWATTN_SDI 0x10000000 1278#define BGE_FLOWATTN_SRS 0x20000000 1279#define BGE_FLOWATTN_SBDC 0x40000000 1280#define BGE_FLOWATTN_SBDI 0x80000000 1281* 1282/* 1283 * Memory arbiter registers 1284 / 1285#define BGE_MARB_MODE 0x4000 1286#define BGE_MARB_STATUS 0x4004 1287#define BGE_MARB_TRAPADDR_HI 0x4008 1288#define BGE_MARB_TRAPADDR_LO 0x400C 1289* 1290/* Memory arbiter mode register / 1291#define BGE_MARBMODE_RESET 0x00000001 1292#define BGE_MARBMODE_ENABLE 0x00000002 1293#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1294#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1295#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1296#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1297#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1298#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1299#define BGE_MARBMODE_PCI_TRAP 0x00000100 1300#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1301#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1302#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1303#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1304#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1305#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1306#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1307#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1308#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1309#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1310#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1311#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1312#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1313#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1314#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1315#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1316#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1317* 1318/* Memory arbiter status register / 1319#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1320#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1321#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1322#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1323#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1324#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1325#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1326#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1327#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1328#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1329#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1330#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1331#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1332#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1333#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1334#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1335#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1336#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1337#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1338#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1339#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1340#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1341#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1342#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1343* 1344/* 1345 * Buffer manager control registers 1346 / 1347#define BGE_BMAN_MODE 0x4400 1348#define BGE_BMAN_STATUS 0x4404 1349#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1350#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1351#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1352#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1353#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1354#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1355#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1356#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1357#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1358#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1359#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1360#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1361#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1362#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1363#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1364#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1365#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1366#define BGE_BMAN_HWDIAG_1 0x444C 1367#define BGE_BMAN_HWDIAG_2 0x4450 1368#define BGE_BMAN_HWDIAG_3 0x4454 1369* 1370/* Buffer manager mode register / 1371#define BGE_BMANMODE_RESET 0x00000001 1372#define BGE_BMANMODE_ENABLE 0x00000002 1373#define BGE_BMANMODE_ATTN 0x00000004 1374#define BGE_BMANMODE_TESTMODE 0x00000008 1375#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1376* 1377/* Buffer manager status register / 1378#define BGE_BMANSTAT_ERRO 0x00000004 1379#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1380* 1381 1382/* 1383 * Read DMA Control registers 1384 / 1385#define BGE_RDMA_MODE 0x4800 1386#define BGE_RDMA_STATUS 0x4804 1387* 1388/* Read DMA mode register / 1389#define BGE_RDMAMODE_RESET 0x00000001 1390#define BGE_RDMAMODE_ENABLE 0x00000002 1391#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1392#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1393#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1394#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1395#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1396#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1397#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1398#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1399#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1400#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1401#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1402#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1403#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1404#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1405#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1406#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1407* 1408/* Read DMA status register / 1409#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1410#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1411#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1412#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1413#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1414#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1415#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1416#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1417* 1418/* 1419 * Write DMA control registers 1420 / 1421#define BGE_WDMA_MODE 0x4C00 1422#define BGE_WDMA_STATUS 0x4C04 1423* 1424/* Write DMA mode register / 1425#define BGE_WDMAMODE_RESET 0x00000001 1426#define BGE_WDMAMODE_ENABLE 0x00000002 1427#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1428#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1429#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1430#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1431#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1432#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1433#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1434#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1435#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1436#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1437* 1438/* Write DMA status register / 1439#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1440#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1441#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1442#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1443#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1444#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1445#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1446#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1447* 1448 1449/* 1450 * RX CPU registers 1451 / 1452#define BGE_RXCPU_MODE 0x5000 1453#define BGE_RXCPU_STATUS 0x5004 1454#define BGE_RXCPU_PC 0x501C 1455* 1456/* RX CPU mode register / 1457#define BGE_RXCPUMODE_RESET 0x00000001 1458#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1459#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1460#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1461#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1462#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1463#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1464#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1465#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1466#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1467#define BGE_RXCPUMODE_HALTCPU 0x00000400 1468#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1469#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1470#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1471* 1472/* RX CPU status register / 1473#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1474#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1475#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1476#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1477#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1478#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1479#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1480#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1481#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1482#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1483#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1484#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1485#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1486#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1487#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1488#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1489#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1490* 1491/* 1492 * V? CPU registers 1493 / 1494#define BGE_VCPU_STATUS 0x5100 1495#define BGE_VCPU_EXT_CTRL 0x6890 1496* 1497#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1498#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1499 1500#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1501#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1502 1503/* 1504 * TX CPU registers 1505 / 1506#define BGE_TXCPU_MODE 0x5400 1507#define BGE_TXCPU_STATUS 0x5404 1508#define BGE_TXCPU_PC 0x541C 1509* 1510/* TX CPU mode register / 1511#define BGE_TXCPUMODE_RESET 0x00000001 1512#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1513#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1514#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1515#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1516#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1517#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1518#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1519#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1520#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1521#define BGE_TXCPUMODE_HALTCPU 0x00000400 1522#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1523#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1524* 1525/* TX CPU status register / 1526#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1527#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1528#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1529#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1530#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1531#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1532#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1533#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1534#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1535#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1536#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1537#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1538#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1539#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1540#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1541#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1542#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1543* 1544 1545/* 1546 * Low priority mailbox registers 1547 / 1548#define BGE_LPMBX_IRQ0_HI 0x5800 1549#define BGE_LPMBX_IRQ0_LO 0x5804 1550#define BGE_LPMBX_IRQ1_HI 0x5808 1551#define BGE_LPMBX_IRQ1_LO 0x580C 1552#define BGE_LPMBX_IRQ2_HI 0x5810 1553#define BGE_LPMBX_IRQ2_LO 0x5814 1554#define BGE_LPMBX_IRQ3_HI 0x5818 1555#define BGE_LPMBX_IRQ3_LO 0x581C 1556#define BGE_LPMBX_GEN0_HI 0x5820 1557#define BGE_LPMBX_GEN0_LO 0x5824 1558#define BGE_LPMBX_GEN1_HI 0x5828 1559#define BGE_LPMBX_GEN1_LO 0x582C 1560#define BGE_LPMBX_GEN2_HI 0x5830 1561#define BGE_LPMBX_GEN2_LO 0x5834 1562#define BGE_LPMBX_GEN3_HI 0x5828 1563#define BGE_LPMBX_GEN3_LO 0x582C 1564#define BGE_LPMBX_GEN4_HI 0x5840 1565#define BGE_LPMBX_GEN4_LO 0x5844 1566#define BGE_LPMBX_GEN5_HI 0x5848 1567#define BGE_LPMBX_GEN5_LO 0x584C 1568#define BGE_LPMBX_GEN6_HI 0x5850 1569#define BGE_LPMBX_GEN6_LO 0x5854 1570#define BGE_LPMBX_GEN7_HI 0x5858 1571#define BGE_LPMBX_GEN7_LO 0x585C 1572#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1573#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1574#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1575#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1576#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1577#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1578#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1579#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1580#define BGE_LPMBX_RX_CONS0_HI 0x5880 1581#define BGE_LPMBX_RX_CONS0_LO 0x5884 1582#define BGE_LPMBX_RX_CONS1_HI 0x5888 1583#define BGE_LPMBX_RX_CONS1_LO 0x588C 1584#define BGE_LPMBX_RX_CONS2_HI 0x5890 1585#define BGE_LPMBX_RX_CONS2_LO 0x5894 1586#define BGE_LPMBX_RX_CONS3_HI 0x5898 1587#define BGE_LPMBX_RX_CONS3_LO 0x589C 1588#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1589#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1590#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1591#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1592#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1593#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1594#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1595#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1596#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1597#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1598#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1599#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1600#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1601#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1602#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1603#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1604#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1605#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1606#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1607#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1608#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1609#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1610#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1611#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1612#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1613#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1614#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1615#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1616#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1617#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1618#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1619#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1620#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1621#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1622#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1623#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1624#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1625#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1626#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1627#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1628#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1629#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1630#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1631#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1632#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1633#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1634#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1635#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1636#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1637#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1638#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1639#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1640#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1641#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1642#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1643#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1644#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1645#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1646#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1647#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1648#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1649#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1650#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1651#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1652#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1653#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1654#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1655#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1656#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1657#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1658#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1659#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1660#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1661#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1662#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1663#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1664#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1665#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1666#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1667#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1668#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1669#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1670#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1671#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1672#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1673#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1674#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1675#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1676* 1677/* 1678 * Flow throw Queue reset register 1679 / 1680#define BGE_FTQ_RESET 0x5C00 1681* 1682#define BGE_FTQRESET_DMAREAD 0x00000002 1683#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1684#define BGE_FTQRESET_DMADONE 0x00000010 1685#define BGE_FTQRESET_SBDC 0x00000020 1686#define BGE_FTQRESET_SDI 0x00000040 1687#define BGE_FTQRESET_WDMA 0x00000080 1688#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1689#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1690#define BGE_FTQRESET_SDC 0x00000400 1691#define BGE_FTQRESET_HCC 0x00000800 1692#define BGE_FTQRESET_TXFIFO 0x00001000 1693#define BGE_FTQRESET_MBC 0x00002000 1694#define BGE_FTQRESET_RBDC 0x00004000 1695#define BGE_FTQRESET_RXLP 0x00008000 1696#define BGE_FTQRESET_RDBDI 0x00010000 1697#define BGE_FTQRESET_RDC 0x00020000 1698#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1699 1700/* 1701 * Message Signaled Interrupt registers 1702 / 1703#define BGE_MSI_MODE 0x6000 1704#define BGE_MSI_STATUS 0x6004 1705#define BGE_MSI_FIFOACCESS 0x6008 1706* 1707/* MSI mode register / 1708#define BGE_MSIMODE_RESET 0x00000001 1709#define BGE_MSIMODE_ENABLE 0x00000002 1710#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1711#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1712* 1713/* MSI status register / 1714#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1715#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1716#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1717#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1718#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1719* 1720 1721/* 1722 * DMA Completion registers 1723 / 1724#define BGE_DMAC_MODE 0x6400 1725* 1726/* DMA Completion mode register / 1727#define BGE_DMACMODE_RESET 0x00000001 1728#define BGE_DMACMODE_ENABLE 0x00000002 1729* 1730 1731/* 1732 * General control registers. 1733 / 1734#define BGE_MODE_CTL 0x6800 1735#define BGE_MISC_CFG 0x6804 1736#define BGE_MISC_LOCAL_CTL 0x6808 1737#define BGE_CPU_EVENT 0x6810 1738#define BGE_EE_ADDR 0x6838 1739#define BGE_EE_DATA 0x683C 1740#define BGE_EE_CTL 0x6840 1741#define BGE_MDI_CTL 0x6844 1742#define BGE_EE_DELAY 0x6848 1743#define BGE_FASTBOOT_PC 0x6894 1744* 1745/* 1746 * NVRAM Control registers 1747 / 1748#define BGE_NVRAM_CMD 0x7000 1749#define BGE_NVRAM_STAT 0x7004 1750#define BGE_NVRAM_WRDATA 0x7008 1751#define BGE_NVRAM_ADDR 0x700c 1752#define BGE_NVRAM_RDDATA 0x7010 1753#define BGE_NVRAM_CFG1 0x7014 1754#define BGE_NVRAM_CFG2 0x7018 1755#define BGE_NVRAM_CFG3 0x701c 1756#define BGE_NVRAM_SWARB 0x7020 1757#define BGE_NVRAM_ACCESS 0x7024 1758#define BGE_NVRAM_WRITE1 0x7028 1759* 1760#define BGE_NVRAMCMD_RESET 0x00000001 1761#define BGE_NVRAMCMD_DONE 0x00000008 1762#define BGE_NVRAMCMD_START 0x00000010 1763#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd / 1764#define BGE_NVRAMCMD_ERASE 0x00000040 1765#define BGE_NVRAMCMD_FIRST 0x00000080 1766#define BGE_NVRAMCMD_LAST 0x00000100 1767* 1768#define BGE_NVRAM_READCMD \ 1769 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1770 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE) 1771#define BGE_NVRAM_WRITECMD \ 1772 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1773 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE\|BGE_NVRAMCMD_WR) 1774 1775#define BGE_NVRAMSWARB_SET0 0x00000001 1776#define BGE_NVRAMSWARB_SET1 0x00000002 1777#define BGE_NVRAMSWARB_SET2 0x00000003 1778#define BGE_NVRAMSWARB_SET3 0x00000004 1779#define BGE_NVRAMSWARB_CLR0 0x00000010 1780#define BGE_NVRAMSWARB_CLR1 0x00000020 1781#define BGE_NVRAMSWARB_CLR2 0x00000040 1782#define BGE_NVRAMSWARB_CLR3 0x00000080 1783#define BGE_NVRAMSWARB_GNT0 0x00000100 1784#define BGE_NVRAMSWARB_GNT1 0x00000200 1785#define BGE_NVRAMSWARB_GNT2 0x00000400 1786#define BGE_NVRAMSWARB_GNT3 0x00000800 1787#define BGE_NVRAMSWARB_REQ0 0x00001000 1788#define BGE_NVRAMSWARB_REQ1 0x00002000 1789#define BGE_NVRAMSWARB_REQ2 0x00004000 1790#define BGE_NVRAMSWARB_REQ3 0x00008000 1791 1792#define BGE_NVRAMACC_ENABLE 0x00000001 1793#define BGE_NVRAMACC_WRENABLE 0x00000002 1794 1795/* Mode control register / 1796#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1797#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1798#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1799#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1800#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1801#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1802#define BGE_MODECTL_NO_RX_CRC 0x00000400 1803#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1804#define BGE_MODECTL_NO_TX_INTR 0x00002000 1805#define BGE_MODECTL_NO_RX_INTR 0x00004000 1806#define BGE_MODECTL_FORCE_PCI32 0x00008000 1807#define BGE_MODECTL_STACKUP 0x00010000 1808#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1809#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1810#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1811#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1812#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1813#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1814#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1815#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1816#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1817#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1818* 1819/* Misc. config register / 1820#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1821#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1822#define BGE_MISCCFG_BOARD_ID 0x0001E000 1823#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1824#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1825#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1826#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1827* 1828#define BGE_32BITTIME_66MHZ (0x41 << 1) 1829 1830/* Misc. Local Control / 1831#define BGE_MLC_INTR_STATE 0x00000001 1832#define BGE_MLC_INTR_CLR 0x00000002 1833#define BGE_MLC_INTR_SET 0x00000004 1834#define BGE_MLC_INTR_ONATTN 0x00000008 1835#define BGE_MLC_MISCIO_IN0 0x00000100 1836#define BGE_MLC_MISCIO_IN1 0x00000200 1837#define BGE_MLC_MISCIO_IN2 0x00000400 1838#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1839#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1840#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1841#define BGE_MLC_MISCIO_OUT0 0x00004000 1842#define BGE_MLC_MISCIO_OUT1 0x00008000 1843#define BGE_MLC_MISCIO_OUT2 0x00010000 1844#define BGE_MLC_EXTRAM_ENB 0x00020000 1845#define BGE_MLC_SRAM_SIZE 0x001C0000 1846#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 1847#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 1848#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1849#define BGE_MLC_AUTO_EEPROM 0x01000000 1850* 1851#define BGE_SSRAMSIZE_256KB 0x00000000 1852#define BGE_SSRAMSIZE_512KB 0x00040000 1853#define BGE_SSRAMSIZE_1MB 0x00080000 1854#define BGE_SSRAMSIZE_2MB 0x000C0000 1855#define BGE_SSRAMSIZE_4MB 0x00100000 1856#define BGE_SSRAMSIZE_8MB 0x00140000 1857#define BGE_SSRAMSIZE_16M 0x00180000 1858 1859/* EEPROM address register / 1860#define BGE_EEADDR_ADDRESS 0x0000FFFC 1861#define BGE_EEADDR_HALFCLK 0x01FF0000 1862#define BGE_EEADDR_START 0x02000000 1863#define BGE_EEADDR_DEVID 0x1C000000 1864#define BGE_EEADDR_RESET 0x20000000 1865#define BGE_EEADDR_DONE 0x40000000 1866#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 1867* 1868#define BGE_EEDEVID(x) ((x & 7) << 26) 1869#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1870#define BGE_HALFCLK_384SCL 0x60 1871#define BGE_EE_READCMD \ 1872 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1873 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 1874#define BGE_EE_WRCMD \ 1875 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1876 BGE_EEADDR_START\|BGE_EEADDR_DONE) 1877 1878/* EEPROM Control register / 1879#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1880#define BGE_EECTL_CLKOUT 0x00000002 1881#define BGE_EECTL_CLKIN 0x00000004 1882#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1883#define BGE_EECTL_DATAOUT 0x00000010 1884#define BGE_EECTL_DATAIN 0x00000020 1885* 1886/* MDI (MII/GMII) access register / 1887#define BGE_MDI_DATA 0x00000001 1888#define BGE_MDI_DIR 0x00000002 1889#define BGE_MDI_SEL 0x00000004 1890#define BGE_MDI_CLK 0x00000008 1891* 1892#define BGE_MEMWIN_START 0x00008000 1893#define BGE_MEMWIN_END 0x0000FFFF 1894 1895 1896#define BGE_MEMWIN_READ(sc, x, val) \ 1897 do { \ 1898 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1899 (0xFFFF0000 & x), 4); \ 1900 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1901 } while(0) 1902 1903#define BGE_MEMWIN_WRITE(sc, x, val) \ 1904 do { \ 1905 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1906 (0xFFFF0000 & x), 4); \ 1907 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1908 } while(0) 1909 1910/* 1911 * This magic number is written to the firmware mailbox at 0xb50 1912 * before a software reset is issued. After the internal firmware 1913 * has completed its initialization it will write the opposite of 1914 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1915 * driver to synchronize with the firmware. 1916 / 1917#define BGE_MAGIC_NUMBER 0x4B657654 1918* 1919typedef struct { 1920 uint32_t bge_addr_hi; 1921 uint32_t bge_addr_lo; 1922} bge_hostaddr; 1923 1924#define BGE_HOSTADDR(x, y) \ 1925 do { \ 1926 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1927 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1928 } while(0) 1929 1930#define BGE_ADDR_LO(y) \ 1931 ((uint64_t) (y) & 0xFFFFFFFF) 1932#define BGE_ADDR_HI(y) \ 1933 ((uint64_t) (y) >> 32) 1934 1935/* Ring control block structure / 1936struct bge_rcb { 1937* bge_hostaddr bge_hostaddr; 1938 uint32_t bge_maxlen_flags; 1939 uint32_t bge_nicaddr; 1940}; 1941 1942#define RCB_WRITE_4(sc, rcb, offset, val) \ 1943 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 1944#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 1945 1946#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1947#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1948 1949struct bge_tx_bd { 1950 bge_hostaddr bge_addr; 1951#if BYTE_ORDER == LITTLE_ENDIAN 1952 uint16_t bge_flags; 1953 uint16_t bge_len; 1954 uint16_t bge_vlan_tag; 1955 uint16_t bge_mss; 1956#else 1957 uint16_t bge_len; 1958 uint16_t bge_flags; 1959 uint16_t bge_mss; 1960 uint16_t bge_vlan_tag; 1961#endif 1962}; 1963 1964#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1965#define BGE_TXBDFLAG_IP_CSUM 0x0002 1966#define BGE_TXBDFLAG_END 0x0004 1967#define BGE_TXBDFLAG_IP_FRAG 0x0008 1968#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1969#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1970#define BGE_TXBDFLAG_COAL_NOW 0x0080 1971#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1972#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1973#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1974#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1975#define BGE_TXBDFLAG_NO_CRC 0x8000 1976 1977#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1978 BGE_SEND_RING_1_TO_4 + \ 1979 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1980 1981struct bge_rx_bd { 1982 bge_hostaddr bge_addr; 1983#if BYTE_ORDER == LITTLE_ENDIAN 1984 uint16_t bge_len; 1985 uint16_t bge_idx; 1986 uint16_t bge_flags; 1987 uint16_t bge_type; 1988 uint16_t bge_tcp_udp_csum; 1989 uint16_t bge_ip_csum; 1990 uint16_t bge_vlan_tag; 1991 uint16_t bge_error_flag; 1992#else 1993 uint16_t bge_idx; 1994 uint16_t bge_len; 1995 uint16_t bge_type; 1996 uint16_t bge_flags; 1997 uint16_t bge_ip_csum; 1998 uint16_t bge_tcp_udp_csum; 1999 uint16_t bge_error_flag; 2000 uint16_t bge_vlan_tag; 2001#endif 2002 uint32_t bge_rsvd; 2003 uint32_t bge_opaque; 2004}; 2005 2006struct bge_extrx_bd { 2007 bge_hostaddr bge_addr1; 2008 bge_hostaddr bge_addr2; 2009 bge_hostaddr bge_addr3; 2010#if BYTE_ORDER == LITTLE_ENDIAN 2011 uint16_t bge_len2; 2012 uint16_t bge_len1; 2013 uint16_t bge_rsvd1; 2014 uint16_t bge_len3; 2015#else 2016 uint16_t bge_len1; 2017 uint16_t bge_len2; 2018 uint16_t bge_len3; 2019 uint16_t bge_rsvd1; 2020#endif 2021 bge_hostaddr bge_addr0; 2022#if BYTE_ORDER == LITTLE_ENDIAN 2023 uint16_t bge_len0; 2024 uint16_t bge_idx; 2025 uint16_t bge_flags; 2026 uint16_t bge_type; 2027 uint16_t bge_tcp_udp_csum; 2028 uint16_t bge_ip_csum; 2029 uint16_t bge_vlan_tag; 2030 uint16_t bge_error_flag; 2031#else 2032 uint16_t bge_idx; 2033 uint16_t bge_len0; 2034 uint16_t bge_type; 2035 uint16_t bge_flags; 2036 uint16_t bge_ip_csum; 2037 uint16_t bge_tcp_udp_csum; 2038 uint16_t bge_error_flag; 2039 uint16_t bge_vlan_tag; 2040#endif 2041 uint32_t bge_rsvd0; 2042 uint32_t bge_opaque; 2043}; 2044 2045#define BGE_RXBDFLAG_END 0x0004 2046#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2047#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2048#define BGE_RXBDFLAG_ERROR 0x0400 2049#define BGE_RXBDFLAG_MINI_RING 0x0800 2050#define BGE_RXBDFLAG_IP_CSUM 0x1000 2051#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2052#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2053 2054#define BGE_RXERRFLAG_BAD_CRC 0x0001 2055#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2056#define BGE_RXERRFLAG_LINK_LOST 0x0004 2057#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2058#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2059#define BGE_RXERRFLAG_RUNT 0x0020 2060#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2061#define BGE_RXERRFLAG_GIANT 0x0080 2062 2063struct bge_sts_idx { 2064#if BYTE_ORDER == LITTLE_ENDIAN 2065 uint16_t bge_rx_prod_idx; 2066 uint16_t bge_tx_cons_idx; 2067#else 2068 uint16_t bge_tx_cons_idx; 2069 uint16_t bge_rx_prod_idx; 2070#endif 2071}; 2072 2073struct bge_status_block { 2074 uint32_t bge_status; 2075 uint32_t bge_rsvd0; 2076#if BYTE_ORDER == LITTLE_ENDIAN 2077 uint16_t bge_rx_jumbo_cons_idx; 2078 uint16_t bge_rx_std_cons_idx; 2079 uint16_t bge_rx_mini_cons_idx; 2080 uint16_t bge_rsvd1; 2081#else 2082 uint16_t bge_rx_std_cons_idx; 2083 uint16_t bge_rx_jumbo_cons_idx; 2084 uint16_t bge_rsvd1; 2085 uint16_t bge_rx_mini_cons_idx; 2086#endif 2087 struct bge_sts_idx bge_idx[16]; 2088}; 2089 2090#define BGE_STATFLAG_UPDATED 0x00000001 2091#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2092#define BGE_STATFLAG_ERROR 0x00000004 2093 2094 2095/* 2096 * Broadcom Vendor ID 2097 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2098 * even though they're now manufactured by Broadcom) 2099 / 2100#define BCOM_VENDORID 0x14E4 2101#define BCOM_DEVICEID_BCM5700 0x1644 2102#define BCOM_DEVICEID_BCM5701 0x1645 2103#define BCOM_DEVICEID_BCM5702 0x1646 2104#define BCOM_DEVICEID_BCM5702X 0x16A6 2105#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2106#define BCOM_DEVICEID_BCM5703 0x1647 2107#define BCOM_DEVICEID_BCM5703X 0x16A7 2108#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2109#define BCOM_DEVICEID_BCM5704C 0x1648 2110#define BCOM_DEVICEID_BCM5704S 0x16A8 2111#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2112#define BCOM_DEVICEID_BCM5705 0x1653 2113#define BCOM_DEVICEID_BCM5705K 0x1654 2114#define BCOM_DEVICEID_BCM5705F 0x166E 2115#define BCOM_DEVICEID_BCM5705M 0x165D 2116#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2117#define BCOM_DEVICEID_BCM5714C 0x1668 2118#define BCOM_DEVICEID_BCM5714S 0x1669 2119#define BCOM_DEVICEID_BCM5715 0x1678 2120#define BCOM_DEVICEID_BCM5715S 0x1679 2121#define BCOM_DEVICEID_BCM5720 0x1658 2122#define BCOM_DEVICEID_BCM5721 0x1659 2123#define BCOM_DEVICEID_BCM5722 0x165A 2124#define BCOM_DEVICEID_BCM5723 0x165B 2125#define BCOM_DEVICEID_BCM5750 0x1676 2126#define BCOM_DEVICEID_BCM5750M 0x167C 2127#define BCOM_DEVICEID_BCM5751 0x1677 2128#define BCOM_DEVICEID_BCM5751F 0x167E 2129#define BCOM_DEVICEID_BCM5751M 0x167D 2130#define BCOM_DEVICEID_BCM5752 0x1600 2131#define BCOM_DEVICEID_BCM5752M 0x1601 2132#define BCOM_DEVICEID_BCM5753 0x16F7 2133#define BCOM_DEVICEID_BCM5753F 0x16FE 2134#define BCOM_DEVICEID_BCM5753M 0x16FD 2135#define BCOM_DEVICEID_BCM5754 0x167A 2136#define BCOM_DEVICEID_BCM5754M 0x1672 2137#define BCOM_DEVICEID_BCM5755 0x167B 2138#define BCOM_DEVICEID_BCM5755M 0x1673 2139#define BCOM_DEVICEID_BCM5756 0x1674 2140#define BCOM_DEVICEID_BCM5761 0x1681 2141#define BCOM_DEVICEID_BCM5761E 0x1680 2142#define BCOM_DEVICEID_BCM5761S 0x1688 2143#define BCOM_DEVICEID_BCM5761SE 0x1689 2144#define BCOM_DEVICEID_BCM5764 0x1684 2145#define BCOM_DEVICEID_BCM5780 0x166A 2146#define BCOM_DEVICEID_BCM5780S 0x166B 2147#define BCOM_DEVICEID_BCM5781 0x16DD 2148#define BCOM_DEVICEID_BCM5782 0x1696 2149#define BCOM_DEVICEID_BCM5784 0x1698 2150#define BCOM_DEVICEID_BCM5785F 0x16a0 2151#define BCOM_DEVICEID_BCM5785G 0x1699 2152#define BCOM_DEVICEID_BCM5786 0x169A 2153#define BCOM_DEVICEID_BCM5787 0x169B 2154#define BCOM_DEVICEID_BCM5787M 0x1693 2155#define BCOM_DEVICEID_BCM5787F 0x167f 2156#define BCOM_DEVICEID_BCM5788 0x169C 2157#define BCOM_DEVICEID_BCM5789 0x169D 2158#define BCOM_DEVICEID_BCM5901 0x170D 2159#define BCOM_DEVICEID_BCM5901A2 0x170E 2160#define BCOM_DEVICEID_BCM5903M 0x16FF 2161#define BCOM_DEVICEID_BCM5906 0x1712 2162#define BCOM_DEVICEID_BCM5906M 0x1713 2163#define BCOM_DEVICEID_BCM57760 0x1690 2164#define BCOM_DEVICEID_BCM57780 0x1692 2165#define BCOM_DEVICEID_BCM57788 0x1691 2166#define BCOM_DEVICEID_BCM57790 0x1694 2167* 2168/* 2169 * Alteon AceNIC PCI vendor/device ID. 2170 / 2171#define ALTEON_VENDORID 0x12AE 2172#define ALTEON_DEVICEID_ACENIC 0x0001 2173#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2174#define ALTEON_DEVICEID_BCM5700 0x0003 2175#define ALTEON_DEVICEID_BCM5701 0x0004 2176* 2177/* 2178 * 3Com 3c996 PCI vendor/device ID. 2179 / 2180#define TC_VENDORID 0x10B7 2181#define TC_DEVICEID_3C996 0x0003 2182* 2183/* 2184 * SysKonnect PCI vendor ID 2185 / 2186#define SK_VENDORID 0x1148 2187#define SK_DEVICEID_ALTIMA 0x4400 2188#define SK_SUBSYSID_9D21 0x4421 2189#define SK_SUBSYSID_9D41 0x4441 2190* 2191/* 2192 * Altima PCI vendor/device ID. 2193 / 2194#define ALTIMA_VENDORID 0x173b 2195#define ALTIMA_DEVICE_AC1000 0x03e8 2196#define ALTIMA_DEVICE_AC1002 0x03e9 2197#define ALTIMA_DEVICE_AC9100 0x03ea 2198* 2199/* 2200 * Dell PCI vendor ID 2201 / 2202* 2203#define DELL_VENDORID 0x1028 2204 2205/* 2206 * Apple PCI vendor ID. 2207 / 2208#define APPLE_VENDORID 0x106b 2209#define APPLE_DEVICE_BCM5701 0x1645 2210* 2211/* 2212 * Sun PCI vendor ID 2213 / 2214#define SUN_VENDORID 0x108e 2215* 2216/* 2217 * Fujitsu vendor/device IDs 2218 / 2219#define FJTSU_VENDORID 0x10cf 2220#define FJTSU_DEVICEID_PW008GE5 0x11a1 2221#define FJTSU_DEVICEID_PW008GE4 0x11a2 2222#define FJTSU_DEVICEID_PP250450 0x11cc / PRIMEPOWER250/450 LAN / 2223* 2224/* 2225 * Offset of MAC address inside EEPROM. 2226 / 2227#define BGE_EE_MAC_OFFSET 0x7C 2228#define BGE_EE_MAC_OFFSET_5906 0x10 2229#define BGE_EE_HWCFG_OFFSET 0xC8 2230* 2231#define BGE_HWCFG_VOLTAGE 0x00000003 2232#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2233#define BGE_HWCFG_MEDIA 0x00000030 2234#define BGE_HWCFG_ASF 0x00000080 2235 2236#define BGE_VOLTAGE_1POINT3 0x00000000 2237#define BGE_VOLTAGE_1POINT8 0x00000001 2238 2239#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2240#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2241#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2242 2243#define BGE_MEDIA_UNSPEC 0x00000000 2244#define BGE_MEDIA_COPPER 0x00000010 2245#define BGE_MEDIA_FIBER 0x00000020 2246 2247#define BGE_TICKS_PER_SEC 1000000 2248 2249/* 2250 * Ring size constants. 2251 / 2252#define BGE_EVENT_RING_CNT 256 2253#define BGE_CMD_RING_CNT 64 2254#define BGE_STD_RX_RING_CNT 512 2255#define BGE_JUMBO_RX_RING_CNT 256 2256#define BGE_MINI_RX_RING_CNT 1024 2257#define BGE_RETURN_RING_CNT 1024 2258* 2259/* 5705 has smaller return ring size / 2260* 2261#define BGE_RETURN_RING_CNT_5705 512 2262 2263/* 2264 * Possible TX ring sizes. 2265 / 2266#define BGE_TX_RING_CNT_128 128 2267#define BGE_TX_RING_BASE_128 0x3800 2268* 2269#define BGE_TX_RING_CNT_256 256 2270#define BGE_TX_RING_BASE_256 0x3000 2271 2272#define BGE_TX_RING_CNT_512 512 2273#define BGE_TX_RING_BASE_512 0x2000 2274 2275#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2276#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2277 2278/* 2279 * Tigon III statistics counters. 2280 / 2281/ Statistics maintained MAC Receive block. / 2282struct bge_rx_mac_stats { 2283* bge_hostaddr ifHCInOctets; 2284 bge_hostaddr Reserved1; 2285 bge_hostaddr etherStatsFragments; 2286 bge_hostaddr ifHCInUcastPkts; 2287 bge_hostaddr ifHCInMulticastPkts; 2288 bge_hostaddr ifHCInBroadcastPkts; 2289 bge_hostaddr dot3StatsFCSErrors; 2290 bge_hostaddr dot3StatsAlignmentErrors; 2291 bge_hostaddr xonPauseFramesReceived; 2292 bge_hostaddr xoffPauseFramesReceived; 2293 bge_hostaddr macControlFramesReceived; 2294 bge_hostaddr xoffStateEntered; 2295 bge_hostaddr dot3StatsFramesTooLong; 2296 bge_hostaddr etherStatsJabbers; 2297 bge_hostaddr etherStatsUndersizePkts; 2298 bge_hostaddr inRangeLengthError; 2299 bge_hostaddr outRangeLengthError; 2300 bge_hostaddr etherStatsPkts64Octets; 2301 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2302 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2303 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2304 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2305 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2306 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2307 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2308 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2309 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2310}; 2311 2312 2313/* Statistics maintained MAC Transmit block. / 2314struct bge_tx_mac_stats { 2315* bge_hostaddr ifHCOutOctets; 2316 bge_hostaddr Reserved2; 2317 bge_hostaddr etherStatsCollisions; 2318 bge_hostaddr outXonSent; 2319 bge_hostaddr outXoffSent; 2320 bge_hostaddr flowControlDone; 2321 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2322 bge_hostaddr dot3StatsSingleCollisionFrames; 2323 bge_hostaddr dot3StatsMultipleCollisionFrames; 2324 bge_hostaddr dot3StatsDeferredTransmissions; 2325 bge_hostaddr Reserved3; 2326 bge_hostaddr dot3StatsExcessiveCollisions; 2327 bge_hostaddr dot3StatsLateCollisions; 2328 bge_hostaddr dot3Collided2Times; 2329 bge_hostaddr dot3Collided3Times; 2330 bge_hostaddr dot3Collided4Times; 2331 bge_hostaddr dot3Collided5Times; 2332 bge_hostaddr dot3Collided6Times; 2333 bge_hostaddr dot3Collided7Times; 2334 bge_hostaddr dot3Collided8Times; 2335 bge_hostaddr dot3Collided9Times; 2336 bge_hostaddr dot3Collided10Times; 2337 bge_hostaddr dot3Collided11Times; 2338 bge_hostaddr dot3Collided12Times; 2339 bge_hostaddr dot3Collided13Times; 2340 bge_hostaddr dot3Collided14Times; 2341 bge_hostaddr dot3Collided15Times; 2342 bge_hostaddr ifHCOutUcastPkts; 2343 bge_hostaddr ifHCOutMulticastPkts; 2344 bge_hostaddr ifHCOutBroadcastPkts; 2345 bge_hostaddr dot3StatsCarrierSenseErrors; 2346 bge_hostaddr ifOutDiscards; 2347 bge_hostaddr ifOutErrors; 2348}; 2349 2350/* Stats counters access through registers / 2351struct bge_mac_stats_regs { 2352* uint32_t ifHCOutOctets; 2353 uint32_t Reserved0; 2354 uint32_t etherStatsCollisions; 2355 uint32_t outXonSent; 2356 uint32_t outXoffSent; 2357 uint32_t Reserved1; 2358 uint32_t dot3StatsInternalMacTransmitErrors; 2359 uint32_t dot3StatsSingleCollisionFrames; 2360 uint32_t dot3StatsMultipleCollisionFrames; 2361 uint32_t dot3StatsDeferredTransmissions; 2362 uint32_t Reserved2; 2363 uint32_t dot3StatsExcessiveCollisions; 2364 uint32_t dot3StatsLateCollisions; 2365 uint32_t Reserved3[14]; 2366 uint32_t ifHCOutUcastPkts; 2367 uint32_t ifHCOutMulticastPkts; 2368 uint32_t ifHCOutBroadcastPkts; 2369 uint32_t Reserved4[2]; 2370 uint32_t ifHCInOctets; 2371 uint32_t Reserved5; 2372 uint32_t etherStatsFragments; 2373 uint32_t ifHCInUcastPkts; 2374 uint32_t ifHCInMulticastPkts; 2375 uint32_t ifHCInBroadcastPkts; 2376 uint32_t dot3StatsFCSErrors; 2377 uint32_t dot3StatsAlignmentErrors; 2378 uint32_t xonPauseFramesReceived; 2379 uint32_t xoffPauseFramesReceived; 2380 uint32_t macControlFramesReceived; 2381 uint32_t xoffStateEntered; 2382 uint32_t dot3StatsFramesTooLong; 2383 uint32_t etherStatsJabbers; 2384 uint32_t etherStatsUndersizePkts; 2385}; 2386 2387struct bge_stats { 2388 uint8_t Reserved0[256]; 2389 2390 /* Statistics maintained by Receive MAC. / 2391* struct bge_rx_mac_stats rxstats; 2392 2393 bge_hostaddr Unused1[37]; 2394 2395 /* Statistics maintained by Transmit MAC. / 2396* struct bge_tx_mac_stats txstats; 2397 2398 bge_hostaddr Unused2[31]; 2399 2400 /* Statistics maintained by Receive List Placement. / 2401* bge_hostaddr COSIfHCInPkts[16]; 2402 bge_hostaddr COSFramesDroppedDueToFilters; 2403 bge_hostaddr nicDmaWriteQueueFull; 2404 bge_hostaddr nicDmaWriteHighPriQueueFull; 2405 bge_hostaddr nicNoMoreRxBDs; 2406 bge_hostaddr ifInDiscards; 2407 bge_hostaddr ifInErrors; 2408 bge_hostaddr nicRecvThresholdHit; 2409 2410 bge_hostaddr Unused3[9]; 2411 2412 /* Statistics maintained by Send Data Initiator. / 2413* bge_hostaddr COSIfHCOutPkts[16]; 2414 bge_hostaddr nicDmaReadQueueFull; 2415 bge_hostaddr nicDmaReadHighPriQueueFull; 2416 bge_hostaddr nicSendDataCompQueueFull; 2417 2418 /* Statistics maintained by Host Coalescing. / 2419* bge_hostaddr nicRingSetSendProdIndex; 2420 bge_hostaddr nicRingStatusUpdate; 2421 bge_hostaddr nicInterrupts; 2422 bge_hostaddr nicAvoidedInterrupts; 2423 bge_hostaddr nicSendThresholdHit; 2424 2425 uint8_t Reserved4[320]; 2426}; 2427 2428/* 2429 * Tigon general information block. This resides in host memory 2430 * and contains the status counters, ring control blocks and 2431 * producer pointers. 2432 / 2433* 2434struct bge_gib { 2435 struct bge_stats bge_stats; 2436 struct bge_rcb bge_tx_rcb[16]; 2437 struct bge_rcb bge_std_rx_rcb; 2438 struct bge_rcb bge_jumbo_rx_rcb; 2439 struct bge_rcb bge_mini_rx_rcb; 2440 struct bge_rcb bge_return_rcb; 2441}; 2442 2443#define BGE_FRAMELEN 1518 2444#define BGE_MAX_FRAMELEN 1536 2445#define BGE_JUMBO_FRAMELEN 9018 2446#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2447#define BGE_MIN_FRAMELEN 60 2448 2449/* 2450 * Other utility macros. 2451 / 2452#define BGE_INC(x, y) (x) = (x + 1) % y 2453* 2454/* 2455 * Register access macros. The Tigon always uses memory mapped register 2456 * accesses and all registers must be accessed with 32 bit operations. 2457 / 2458* 2459#define CSR_WRITE_4(sc, reg, val) \ 2460 bus_write_4(sc->bge_res, reg, val) 2461 2462#define CSR_READ_4(sc, reg) \ 2463 bus_read_4(sc->bge_res, reg) 2464 2465#define BGE_SETBIT(sc, reg, x) \ 2466 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2467#define BGE_CLRBIT(sc, reg, x) \ 2468 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2469 2470#define PCI_SETBIT(dev, reg, x, s) \ 2471 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2472#define PCI_CLRBIT(dev, reg, x, s) \ 2473 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2474 2475/* 2476 * Memory management stuff. 2477 / 2478* 2479#define BGE_NSEG_JUMBO 4 2480#define BGE_NSEG_NEW 32 2481#define BGE_TSOSEG_SZ 4096 2482 2483/* Maximum DMA address for controllers that have 40bit DMA address bug. / 2484#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2485#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2486#else 2487#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2488#endif 2489* 2490/* 2491 * Ring structures. Most of these reside in host memory and we tell 2492 * the NIC where they are via the ring control blocks. The exceptions 2493 * are the tx and command rings, which live in NIC memory and which 2494 * we access via the shared memory window. 2495 / 2496* 2497struct bge_ring_data { 2498 struct bge_rx_bd bge_rx_std_ring; 2499* bus_addr_t bge_rx_std_ring_paddr; 2500 struct bge_extrx_bd bge_rx_jumbo_ring; 2501* bus_addr_t bge_rx_jumbo_ring_paddr; 2502 struct bge_rx_bd bge_rx_return_ring; 2503* bus_addr_t bge_rx_return_ring_paddr; 2504 struct bge_tx_bd bge_tx_ring; 2505* bus_addr_t bge_tx_ring_paddr; 2506 struct bge_status_block bge_status_block; 2507* bus_addr_t bge_status_block_paddr; 2508 struct bge_stats bge_stats; 2509* bus_addr_t bge_stats_paddr; 2510 struct bge_gib bge_info; 2511}; 2512 2513#define BGE_STD_RX_RING_SZ \ 2514 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2515#define BGE_JUMBO_RX_RING_SZ \ 2516 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2517#define BGE_TX_RING_SZ \ 2518 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2519#define BGE_RX_RTN_RING_SZ(x) \ 2520 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2521 2522#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2523 2524#define BGE_STATS_SZ sizeof (struct bge_stats) 2525 2526/* 2527 * Mbuf pointers. We need these to keep track of the virtual addresses 2528 * of our mbuf chains since we can only convert from physical to virtual, 2529 * not the other way around. 2530 / 2531struct bge_chain_data { 2532* bus_dma_tag_t bge_parent_tag; 2533 bus_dma_tag_t bge_rx_std_ring_tag; 2534 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2535 bus_dma_tag_t bge_rx_return_ring_tag; 2536 bus_dma_tag_t bge_tx_ring_tag; 2537 bus_dma_tag_t bge_status_tag; 2538 bus_dma_tag_t bge_stats_tag; 2539 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag / 2540* bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag / 2541* bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag / 2542* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2543 bus_dmamap_t bge_rx_std_sparemap; 2544 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2545 bus_dmamap_t bge_rx_jumbo_sparemap; 2546 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2547 bus_dmamap_t bge_rx_std_ring_map; 2548 bus_dmamap_t bge_rx_jumbo_ring_map; 2549 bus_dmamap_t bge_tx_ring_map; 2550 bus_dmamap_t bge_rx_return_ring_map; 2551 bus_dmamap_t bge_status_map; 2552 bus_dmamap_t bge_stats_map; 2553 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2554* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2555* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2556* int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2557 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2558}; 2559 2560struct bge_dmamap_arg { 2561 struct bge_softc sc; 2562* bus_addr_t bge_busaddr; 2563 uint16_t bge_flags; 2564 int bge_idx; 2565 int bge_maxsegs; 2566 struct bge_tx_bd bge_ring; 2567}; 2568* 2569#define BGE_HWREV_TIGON 0x01 2570#define BGE_HWREV_TIGON_II 0x02 2571#define BGE_TIMEOUT 100000 2572#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2573* 2574struct bge_bcom_hack { 2575 int reg; 2576 int val; 2577}; 2578 2579#define ASF_ENABLE 1 2580#define ASF_NEW_HANDSHAKE 2 2581#define ASF_STACKUP 4 2582 2583struct bge_softc { 2584 struct ifnet bge_ifp; / interface info / 2585* device_t bge_dev; 2586 struct mtx bge_mtx; 2587 device_t bge_miibus; 2588 void bge_intrhand; 2589* struct resource bge_irq; 2590* struct resource bge_res; 2591* struct ifmedia bge_ifmedia; /* TBI media info / 2592* int bge_expcap; 2593 int bge_msicap; 2594 int bge_pcixcap; 2595 uint32_t bge_flags; 2596#define BGE_FLAG_TBI 0x00000001 2597#define BGE_FLAG_JUMBO 0x00000002 2598#define BGE_FLAG_WIRESPEED 0x00000004 2599#define BGE_FLAG_EADDR 0x00000008 2600#define BGE_FLAG_MII_SERDES 0x00000010 2601#define BGE_FLAG_MSI 0x00000100 2602#define BGE_FLAG_PCIX 0x00000200 2603#define BGE_FLAG_PCIE 0x00000400 2604#define BGE_FLAG_TSO 0x00000800 2605#define BGE_FLAG_5700_FAMILY 0x00001000 2606#define BGE_FLAG_5705_PLUS 0x00002000 2607#define BGE_FLAG_5714_FAMILY 0x00004000 2608#define BGE_FLAG_575X_PLUS 0x00008000 2609#define BGE_FLAG_5755_PLUS 0x00010000 2610#define BGE_FLAG_40BIT_BUG 0x00020000 2611#define BGE_FLAG_4G_BNDRY_BUG 0x00040000 2612#define BGE_FLAG_RX_ALIGNBUG 0x00100000 2613#define BGE_FLAG_NO_3LED 0x00200000 2614#define BGE_FLAG_ADC_BUG 0x00400000 2615#define BGE_FLAG_5704_A0_BUG 0x00800000 2616#define BGE_FLAG_JITTER_BUG 0x01000000 2617#define BGE_FLAG_BER_BUG 0x02000000 2618#define BGE_FLAG_ADJUST_TRIM 0x04000000 2619#define BGE_FLAG_CRC_BUG 0x08000000 2620#define BGE_FLAG_5788 0x20000000 2621 uint32_t bge_chipid; 2622 uint32_t bge_asicrev; 2623 uint32_t bge_chiprev; 2624 uint8_t bge_asf_mode; 2625 uint8_t bge_asf_count; 2626 struct bge_ring_data bge_ldata; /* rings / 2627* struct bge_chain_data bge_cdata; /* mbufs / 2628* uint16_t bge_tx_saved_considx; 2629 uint16_t bge_rx_saved_considx; 2630 uint16_t bge_ev_saved_considx; 2631 uint16_t bge_return_ring_cnt; 2632 uint16_t bge_std; /* current std ring head / 2633* uint16_t bge_jumbo; /* current jumo ring head / 2634* uint32_t bge_stat_ticks; 2635 uint32_t bge_rx_coal_ticks; 2636 uint32_t bge_tx_coal_ticks; 2637 uint32_t bge_tx_prodidx; 2638 uint32_t bge_rx_max_coal_bds; 2639 uint32_t bge_tx_max_coal_bds; 2640 uint32_t bge_tx_buf_ratio; 2641 int bge_if_flags; 2642 int bge_txcnt; 2643 int bge_link; /* link state / 2644* int bge_link_evt; /* pending link event / 2645* int bge_timer; 2646 int bge_forced_collapse;	34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81#define BGE_UNMAPPED 0x00001000 82#define BGE_UNMAPPED_END 0x00001FFF 83#define BGE_DMA_DESCRIPTORS 0x00002000 84#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85#define BGE_SEND_RING_1_TO_4 0x00004000 86#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 87 88/ Firmware interface / 89#define BGE_FW_DRV_ALIVE 0x00000001 90#define BGE_FW_PAUSE 0x00000002 91 92/ Mappings for internal memory configuration / 93#define BGE_STD_RX_RINGS 0x00006000 94#define BGE_STD_RX_RINGS_END 0x00006FFF 95#define BGE_JUMBO_RX_RINGS 0x00007000 96#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97#define BGE_BUFFPOOL_1 0x00008000 98#define BGE_BUFFPOOL_1_END 0x0000FFFF 99#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 100#define BGE_BUFFPOOL_2_END 0x00017FFF 101#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 102#define BGE_BUFFPOOL_3_END 0x0001FFFF 103* 104/* Mappings for external SSRAM configurations / 105#define BGE_SEND_RING_5_TO_6 0x00006000 106#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107#define BGE_SEND_RING_7_TO_8 0x00007000 108#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109#define BGE_SEND_RING_9_TO_16 0x00008000 110#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111#define BGE_EXT_STD_RX_RINGS 0x0000C000 112#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115#define BGE_MINI_RX_RINGS 0x0000E000 116#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 118#define BGE_AVAIL_REGION1_END 0x00017FFF 119#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 120#define BGE_AVAIL_REGION2_END 0x0001FFFF 121#define BGE_EXT_SSRAM 0x00020000 122#define BGE_EXT_SSRAM_END 0x000FFFFF 123* 124 125/* 126 * BCM570x register offsets. These are memory mapped registers 127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 128 * Each register must be accessed using 32 bit operations. 129 * 130 * All registers are accessed through a 32K shared memory block. 131 * The first group of registers are actually copies of the PCI 132 * configuration space registers. 133 / 134* 135/* 136 * PCI registers defined in the PCI 2.2 spec. 137 / 138#define BGE_PCI_VID 0x00 139#define BGE_PCI_DID 0x02 140#define BGE_PCI_CMD 0x04 141#define BGE_PCI_STS 0x06 142#define BGE_PCI_REV 0x08 143#define BGE_PCI_CLASS 0x09 144#define BGE_PCI_CACHESZ 0x0C 145#define BGE_PCI_LATTIMER 0x0D 146#define BGE_PCI_HDRTYPE 0x0E 147#define BGE_PCI_BIST 0x0F 148#define BGE_PCI_BAR0 0x10 149#define BGE_PCI_BAR1 0x14 150#define BGE_PCI_SUBSYS 0x2C 151#define BGE_PCI_SUBVID 0x2E 152#define BGE_PCI_ROMBASE 0x30 153#define BGE_PCI_CAPPTR 0x34 154#define BGE_PCI_INTLINE 0x3C 155#define BGE_PCI_INTPIN 0x3D 156#define BGE_PCI_MINGNT 0x3E 157#define BGE_PCI_MAXLAT 0x3F 158#define BGE_PCI_PCIXCAP 0x40 159#define BGE_PCI_NEXTPTR_PM 0x41 160#define BGE_PCI_PCIX_CMD 0x42 161#define BGE_PCI_PCIX_STS 0x44 162#define BGE_PCI_PWRMGMT_CAPID 0x48 163#define BGE_PCI_NEXTPTR_VPD 0x49 164#define BGE_PCI_PWRMGMT_CAPS 0x4A 165#define BGE_PCI_PWRMGMT_CMD 0x4C 166#define BGE_PCI_PWRMGMT_STS 0x4D 167#define BGE_PCI_PWRMGMT_DATA 0x4F 168#define BGE_PCI_VPD_CAPID 0x50 169#define BGE_PCI_NEXTPTR_MSI 0x51 170#define BGE_PCI_VPD_ADDR 0x52 171#define BGE_PCI_VPD_DATA 0x54 172#define BGE_PCI_MSI_CAPID 0x58 173#define BGE_PCI_NEXTPTR_NONE 0x59 174#define BGE_PCI_MSI_CTL 0x5A 175#define BGE_PCI_MSI_ADDR_HI 0x5C 176#define BGE_PCI_MSI_ADDR_LO 0x60 177#define BGE_PCI_MSI_DATA 0x64 178* 179/* 180 * PCI Express definitions 181 * According to 182 * PCI Express base specification, REV. 1.0a 183 / 184* 185/* PCI Express device control, 16bits / 186#define BGE_PCIE_DEVCTL 0x08 187#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 188#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 189#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 190#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 191#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 192#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 193#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 194* 195/* PCI MSI. ??? / 196#define BGE_PCIE_CAPID_REG 0xD0 197#define BGE_PCIE_CAPID 0x10 198* 199/* 200 * PCI registers specific to the BCM570x family. 201 / 202#define BGE_PCI_MISC_CTL 0x68 203#define BGE_PCI_DMA_RW_CTL 0x6C 204#define BGE_PCI_PCISTATE 0x70 205#define BGE_PCI_CLKCTL 0x74 206#define BGE_PCI_REG_BASEADDR 0x78 207#define BGE_PCI_MEMWIN_BASEADDR 0x7C 208#define BGE_PCI_REG_DATA 0x80 209#define BGE_PCI_MEMWIN_DATA 0x84 210#define BGE_PCI_MODECTL 0x88 211#define BGE_PCI_MISC_CFG 0x8C 212#define BGE_PCI_MISC_LOCALCTL 0x90 213#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 214#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219#define BGE_PCI_ISR_MBX_HI 0xB0 220#define BGE_PCI_ISR_MBX_LO 0xB4 221#define BGE_PCI_PRODID_ASICREV 0xBC 222* 223/* PCI Misc. Host control register / 224#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 225#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 226#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 227#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 228#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 229#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 230#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 231#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 232#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 233#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 234* 235#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 236#if BYTE_ORDER == LITTLE_ENDIAN 237#define BGE_DMA_SWAP_OPTIONS \ 238 BGE_MODECTL_WORDSWAP_NONFRAME\| \ 239 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 240#else 241#define BGE_DMA_SWAP_OPTIONS \ 242 BGE_MODECTL_WORDSWAP_NONFRAME\|BGE_MODECTL_BYTESWAP_NONFRAME\| \ 243 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 244#endif 245 246#define BGE_INIT \ 247 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 248 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 249 250#define BGE_CHIPID_TIGON_I 0x4000 251#define BGE_CHIPID_TIGON_II 0x6000 252#define BGE_CHIPID_BCM5700_A0 0x7000 253#define BGE_CHIPID_BCM5700_A1 0x7001 254#define BGE_CHIPID_BCM5700_B0 0x7100 255#define BGE_CHIPID_BCM5700_B1 0x7101 256#define BGE_CHIPID_BCM5700_B2 0x7102 257#define BGE_CHIPID_BCM5700_B3 0x7103 258#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 259#define BGE_CHIPID_BCM5700_C0 0x7200 260#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr / 261#define BGE_CHIPID_BCM5701_B0 0x0100 262#define BGE_CHIPID_BCM5701_B2 0x0102 263#define BGE_CHIPID_BCM5701_B5 0x0105 264#define BGE_CHIPID_BCM5703_A0 0x1000 265#define BGE_CHIPID_BCM5703_A1 0x1001 266#define BGE_CHIPID_BCM5703_A2 0x1002 267#define BGE_CHIPID_BCM5703_A3 0x1003 268#define BGE_CHIPID_BCM5703_B0 0x1100 269#define BGE_CHIPID_BCM5704_A0 0x2000 270#define BGE_CHIPID_BCM5704_A1 0x2001 271#define BGE_CHIPID_BCM5704_A2 0x2002 272#define BGE_CHIPID_BCM5704_A3 0x2003 273#define BGE_CHIPID_BCM5704_B0 0x2100 274#define BGE_CHIPID_BCM5705_A0 0x3000 275#define BGE_CHIPID_BCM5705_A1 0x3001 276#define BGE_CHIPID_BCM5705_A2 0x3002 277#define BGE_CHIPID_BCM5705_A3 0x3003 278#define BGE_CHIPID_BCM5750_A0 0x4000 279#define BGE_CHIPID_BCM5750_A1 0x4001 280#define BGE_CHIPID_BCM5750_A3 0x4000 281#define BGE_CHIPID_BCM5750_B0 0x4100 282#define BGE_CHIPID_BCM5750_B1 0x4101 283#define BGE_CHIPID_BCM5750_C0 0x4200 284#define BGE_CHIPID_BCM5750_C1 0x4201 285#define BGE_CHIPID_BCM5750_C2 0x4202 286#define BGE_CHIPID_BCM5714_A0 0x5000 287#define BGE_CHIPID_BCM5752_A0 0x6000 288#define BGE_CHIPID_BCM5752_A1 0x6001 289#define BGE_CHIPID_BCM5752_A2 0x6002 290#define BGE_CHIPID_BCM5714_B0 0x8000 291#define BGE_CHIPID_BCM5714_B3 0x8003 292#define BGE_CHIPID_BCM5715_A0 0x9000 293#define BGE_CHIPID_BCM5715_A1 0x9001 294#define BGE_CHIPID_BCM5715_A3 0x9003 295#define BGE_CHIPID_BCM5755_A0 0xa000 296#define BGE_CHIPID_BCM5755_A1 0xa001 297#define BGE_CHIPID_BCM5755_A2 0xa002 298#define BGE_CHIPID_BCM5722_A0 0xa200 299#define BGE_CHIPID_BCM5754_A0 0xb000 300#define BGE_CHIPID_BCM5754_A1 0xb001 301#define BGE_CHIPID_BCM5754_A2 0xb002 302#define BGE_CHIPID_BCM5761_A0 0x5761000 303#define BGE_CHIPID_BCM5761_A1 0x5761100 304#define BGE_CHIPID_BCM5784_A0 0x5784000 305#define BGE_CHIPID_BCM5784_A1 0x5784100 306#define BGE_CHIPID_BCM5787_A0 0xb000 307#define BGE_CHIPID_BCM5787_A1 0xb001 308#define BGE_CHIPID_BCM5787_A2 0xb002 309#define BGE_CHIPID_BCM5906_A1 0xc001 310#define BGE_CHIPID_BCM5906_A2 0xc002 311#define BGE_CHIPID_BCM57780_A0 0x57780000 312#define BGE_CHIPID_BCM57780_A1 0x57780001 313* 314/* shorthand one / 315#define BGE_ASICREV(x) ((x) >> 12) 316#define BGE_ASICREV_BCM5701 0x00 317#define BGE_ASICREV_BCM5703 0x01 318#define BGE_ASICREV_BCM5704 0x02 319#define BGE_ASICREV_BCM5705 0x03 320#define BGE_ASICREV_BCM5750 0x04 321#define BGE_ASICREV_BCM5714_A0 0x05 322#define BGE_ASICREV_BCM5752 0x06 323#define BGE_ASICREV_BCM5700 0x07 324#define BGE_ASICREV_BCM5780 0x08 325#define BGE_ASICREV_BCM5714 0x09 326#define BGE_ASICREV_BCM5755 0x0a 327#define BGE_ASICREV_BCM5754 0x0b 328#define BGE_ASICREV_BCM5787 0x0b 329#define BGE_ASICREV_BCM5906 0x0c 330/ Should consult BGE_PCI_PRODID_ASICREV for ChipID / 331#define BGE_ASICREV_USE_PRODID_REG 0x0f 332/ BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. / 333#define BGE_ASICREV_BCM5761 0x5761 334#define BGE_ASICREV_BCM5784 0x5784 335#define BGE_ASICREV_BCM5785 0x5785 336#define BGE_ASICREV_BCM57780 0x57780 337* 338/* chip revisions / 339#define BGE_CHIPREV(x) ((x) >> 8) 340#define BGE_CHIPREV_5700_AX 0x70 341#define BGE_CHIPREV_5700_BX 0x71 342#define BGE_CHIPREV_5700_CX 0x72 343#define BGE_CHIPREV_5701_AX 0x00 344#define BGE_CHIPREV_5703_AX 0x10 345#define BGE_CHIPREV_5704_AX 0x20 346#define BGE_CHIPREV_5704_BX 0x21 347#define BGE_CHIPREV_5750_AX 0x40 348#define BGE_CHIPREV_5750_BX 0x41 349/ BGE_PCI_PRODID_ASICREV chip rev. identifiers. / 350#define BGE_CHIPREV_5761_AX 0x57611 351#define BGE_CHIPREV_5784_AX 0x57841 352* 353/* PCI DMA Read/Write Control register / 354#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 355#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 356#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 357#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 358#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 359#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 360#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 361#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 362#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 363#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 364#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 365#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 366* 367#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 368#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 369#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 370#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 371 372#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 373#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 374#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 375#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 376#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 377#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 378#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 379#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 380 381#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 382#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 383#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 384#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 385#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 386#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 387#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 388#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 389 390/* 391 * PCI state register -- note, this register is read only 392 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 393 * register is set. 394 / 395#define BGE_PCISTATE_FORCE_RESET 0x00000001 396#define BGE_PCISTATE_INTR_STATE 0x00000002 397#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 398#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 66/133, 0 = 33/66 / 399#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 400#define BGE_PCISTATE_WANT_EXPROM 0x00000020 401#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 402#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 403#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 404* 405/* 406 * PCI Clock Control register -- note, this register is read only 407 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 408 * register is set. 409 / 410#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 411#define BGE_PCICLOCKCTL_M66EN 0x00000080 412#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 413#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 414#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 415#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 416#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 417#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 418#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 419#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 420* 421 422#ifndef PCIM_CMD_MWIEN 423#define PCIM_CMD_MWIEN 0x0010 424#endif 425#ifndef PCIM_CMD_INTxDIS 426#define PCIM_CMD_INTxDIS 0x0400 427#endif 428 429/* 430 * High priority mailbox registers 431 * Each mailbox is 64-bits wide, though we only use the 432 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 433 * first. The NIC will load the mailbox after the lower 32 bit word 434 * has been updated. 435 / 436#define BGE_MBX_IRQ0_HI 0x0200 437#define BGE_MBX_IRQ0_LO 0x0204 438#define BGE_MBX_IRQ1_HI 0x0208 439#define BGE_MBX_IRQ1_LO 0x020C 440#define BGE_MBX_IRQ2_HI 0x0210 441#define BGE_MBX_IRQ2_LO 0x0214 442#define BGE_MBX_IRQ3_HI 0x0218 443#define BGE_MBX_IRQ3_LO 0x021C 444#define BGE_MBX_GEN0_HI 0x0220 445#define BGE_MBX_GEN0_LO 0x0224 446#define BGE_MBX_GEN1_HI 0x0228 447#define BGE_MBX_GEN1_LO 0x022C 448#define BGE_MBX_GEN2_HI 0x0230 449#define BGE_MBX_GEN2_LO 0x0234 450#define BGE_MBX_GEN3_HI 0x0228 451#define BGE_MBX_GEN3_LO 0x022C 452#define BGE_MBX_GEN4_HI 0x0240 453#define BGE_MBX_GEN4_LO 0x0244 454#define BGE_MBX_GEN5_HI 0x0248 455#define BGE_MBX_GEN5_LO 0x024C 456#define BGE_MBX_GEN6_HI 0x0250 457#define BGE_MBX_GEN6_LO 0x0254 458#define BGE_MBX_GEN7_HI 0x0258 459#define BGE_MBX_GEN7_LO 0x025C 460#define BGE_MBX_RELOAD_STATS_HI 0x0260 461#define BGE_MBX_RELOAD_STATS_LO 0x0264 462#define BGE_MBX_RX_STD_PROD_HI 0x0268 463#define BGE_MBX_RX_STD_PROD_LO 0x026C 464#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 465#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 466#define BGE_MBX_RX_MINI_PROD_HI 0x0278 467#define BGE_MBX_RX_MINI_PROD_LO 0x027C 468#define BGE_MBX_RX_CONS0_HI 0x0280 469#define BGE_MBX_RX_CONS0_LO 0x0284 470#define BGE_MBX_RX_CONS1_HI 0x0288 471#define BGE_MBX_RX_CONS1_LO 0x028C 472#define BGE_MBX_RX_CONS2_HI 0x0290 473#define BGE_MBX_RX_CONS2_LO 0x0294 474#define BGE_MBX_RX_CONS3_HI 0x0298 475#define BGE_MBX_RX_CONS3_LO 0x029C 476#define BGE_MBX_RX_CONS4_HI 0x02A0 477#define BGE_MBX_RX_CONS4_LO 0x02A4 478#define BGE_MBX_RX_CONS5_HI 0x02A8 479#define BGE_MBX_RX_CONS5_LO 0x02AC 480#define BGE_MBX_RX_CONS6_HI 0x02B0 481#define BGE_MBX_RX_CONS6_LO 0x02B4 482#define BGE_MBX_RX_CONS7_HI 0x02B8 483#define BGE_MBX_RX_CONS7_LO 0x02BC 484#define BGE_MBX_RX_CONS8_HI 0x02C0 485#define BGE_MBX_RX_CONS8_LO 0x02C4 486#define BGE_MBX_RX_CONS9_HI 0x02C8 487#define BGE_MBX_RX_CONS9_LO 0x02CC 488#define BGE_MBX_RX_CONS10_HI 0x02D0 489#define BGE_MBX_RX_CONS10_LO 0x02D4 490#define BGE_MBX_RX_CONS11_HI 0x02D8 491#define BGE_MBX_RX_CONS11_LO 0x02DC 492#define BGE_MBX_RX_CONS12_HI 0x02E0 493#define BGE_MBX_RX_CONS12_LO 0x02E4 494#define BGE_MBX_RX_CONS13_HI 0x02E8 495#define BGE_MBX_RX_CONS13_LO 0x02EC 496#define BGE_MBX_RX_CONS14_HI 0x02F0 497#define BGE_MBX_RX_CONS14_LO 0x02F4 498#define BGE_MBX_RX_CONS15_HI 0x02F8 499#define BGE_MBX_RX_CONS15_LO 0x02FC 500#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 501#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 502#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 503#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 504#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 505#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 506#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 507#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 508#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 509#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 510#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 511#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 512#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 513#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 514#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 515#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 516#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 517#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 518#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 519#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 520#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 521#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 522#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 523#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 524#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 525#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 526#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 527#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 528#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 529#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 530#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 531#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 532#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 533#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 534#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 535#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 536#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 537#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 538#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 539#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 540#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 541#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 542#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 543#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 544#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 545#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 546#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 547#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 548#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 549#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 550#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 551#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 552#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 553#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 554#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 555#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 556#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 557#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 558#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 559#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 560#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 561#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 562#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 563#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 564* 565#define BGE_TX_RINGS_MAX 4 566#define BGE_TX_RINGS_EXTSSRAM_MAX 16 567#define BGE_RX_RINGS_MAX 16 568 569/* Ethernet MAC control registers / 570#define BGE_MAC_MODE 0x0400 571#define BGE_MAC_STS 0x0404 572#define BGE_MAC_EVT_ENB 0x0408 573#define BGE_MAC_LED_CTL 0x040C 574#define BGE_MAC_ADDR1_LO 0x0410 575#define BGE_MAC_ADDR1_HI 0x0414 576#define BGE_MAC_ADDR2_LO 0x0418 577#define BGE_MAC_ADDR2_HI 0x041C 578#define BGE_MAC_ADDR3_LO 0x0420 579#define BGE_MAC_ADDR3_HI 0x0424 580#define BGE_MAC_ADDR4_LO 0x0428 581#define BGE_MAC_ADDR4_HI 0x042C 582#define BGE_WOL_PATPTR 0x0430 583#define BGE_WOL_PATCFG 0x0434 584#define BGE_TX_RANDOM_BACKOFF 0x0438 585#define BGE_RX_MTU 0x043C 586#define BGE_GBIT_PCS_TEST 0x0440 587#define BGE_TX_TBI_AUTONEG 0x0444 588#define BGE_RX_TBI_AUTONEG 0x0448 589#define BGE_MI_COMM 0x044C 590#define BGE_MI_STS 0x0450 591#define BGE_MI_MODE 0x0454 592#define BGE_AUTOPOLL_STS 0x0458 593#define BGE_TX_MODE 0x045C 594#define BGE_TX_STS 0x0460 595#define BGE_TX_LENGTHS 0x0464 596#define BGE_RX_MODE 0x0468 597#define BGE_RX_STS 0x046C 598#define BGE_MAR0 0x0470 599#define BGE_MAR1 0x0474 600#define BGE_MAR2 0x0478 601#define BGE_MAR3 0x047C 602#define BGE_RX_BD_RULES_CTL0 0x0480 603#define BGE_RX_BD_RULES_MASKVAL0 0x0484 604#define BGE_RX_BD_RULES_CTL1 0x0488 605#define BGE_RX_BD_RULES_MASKVAL1 0x048C 606#define BGE_RX_BD_RULES_CTL2 0x0490 607#define BGE_RX_BD_RULES_MASKVAL2 0x0494 608#define BGE_RX_BD_RULES_CTL3 0x0498 609#define BGE_RX_BD_RULES_MASKVAL3 0x049C 610#define BGE_RX_BD_RULES_CTL4 0x04A0 611#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 612#define BGE_RX_BD_RULES_CTL5 0x04A8 613#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 614#define BGE_RX_BD_RULES_CTL6 0x04B0 615#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 616#define BGE_RX_BD_RULES_CTL7 0x04B8 617#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 618#define BGE_RX_BD_RULES_CTL8 0x04C0 619#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 620#define BGE_RX_BD_RULES_CTL9 0x04C8 621#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 622#define BGE_RX_BD_RULES_CTL10 0x04D0 623#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 624#define BGE_RX_BD_RULES_CTL11 0x04D8 625#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 626#define BGE_RX_BD_RULES_CTL12 0x04E0 627#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 628#define BGE_RX_BD_RULES_CTL13 0x04E8 629#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 630#define BGE_RX_BD_RULES_CTL14 0x04F0 631#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 632#define BGE_RX_BD_RULES_CTL15 0x04F8 633#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 634#define BGE_RX_RULES_CFG 0x0500 635#define BGE_SERDES_CFG 0x0590 636#define BGE_SERDES_STS 0x0594 637#define BGE_SGDIG_CFG 0x05B0 638#define BGE_SGDIG_STS 0x05B4 639#define BGE_MAC_STATS 0x0800 640* 641/* Ethernet MAC Mode register / 642#define BGE_MACMODE_RESET 0x00000001 643#define BGE_MACMODE_HALF_DUPLEX 0x00000002 644#define BGE_MACMODE_PORTMODE 0x0000000C 645#define BGE_MACMODE_LOOPBACK 0x00000010 646#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 647#define BGE_MACMODE_TX_BURST_ENB 0x00000100 648#define BGE_MACMODE_MAX_DEFER 0x00000200 649#define BGE_MACMODE_LINK_POLARITY 0x00000400 650#define BGE_MACMODE_RX_STATS_ENB 0x00000800 651#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 652#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 653#define BGE_MACMODE_TX_STATS_ENB 0x00004000 654#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 655#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 656#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 657#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 658#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 659#define BGE_MACMODE_MIP_ENB 0x00100000 660#define BGE_MACMODE_TXDMA_ENB 0x00200000 661#define BGE_MACMODE_RXDMA_ENB 0x00400000 662#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 663* 664#define BGE_PORTMODE_NONE 0x00000000 665#define BGE_PORTMODE_MII 0x00000004 666#define BGE_PORTMODE_GMII 0x00000008 667#define BGE_PORTMODE_TBI 0x0000000C 668 669/* MAC Status register / 670#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 671#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 672#define BGE_MACSTAT_RX_CFG 0x00000004 673#define BGE_MACSTAT_CFG_CHANGED 0x00000008 674#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 675#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 676#define BGE_MACSTAT_LINK_CHANGED 0x00001000 677#define BGE_MACSTAT_MI_COMPLETE 0x00400000 678#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 679#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 680#define BGE_MACSTAT_ODI_ERROR 0x02000000 681#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 682#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 683* 684/* MAC Event Enable Register / 685#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 686#define BGE_EVTENB_LINK_CHANGED 0x00001000 687#define BGE_EVTENB_MI_COMPLETE 0x00400000 688#define BGE_EVTENB_MI_INTERRUPT 0x00800000 689#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 690#define BGE_EVTENB_ODI_ERROR 0x02000000 691#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 692#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 693* 694/* LED Control Register / 695#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 696#define BGE_LEDCTL_1000MBPS_LED 0x00000002 697#define BGE_LEDCTL_100MBPS_LED 0x00000004 698#define BGE_LEDCTL_10MBPS_LED 0x00000008 699#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 700#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 701#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 702#define BGE_LEDCTL_1000MBPS_STS 0x00000080 703#define BGE_LEDCTL_100MBPS_STS 0x00000100 704#define BGE_LEDCTL_10MBPS_STS 0x00000200 705#define BGE_LEDCTL_TRADLED_STS 0x00000400 706#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 707#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 708* 709/* TX backoff seed register / 710#define BGE_TX_BACKOFF_SEED_MASK 0x3F 711* 712/* Autopoll status register / 713#define BGE_AUTOPOLLSTS_ERROR 0x00000001 714* 715/* Transmit MAC mode register / 716#define BGE_TXMODE_RESET 0x00000001 717#define BGE_TXMODE_ENABLE 0x00000002 718#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 719#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 720#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 721* 722/* Transmit MAC status register / 723#define BGE_TXSTAT_RX_XOFFED 0x00000001 724#define BGE_TXSTAT_SENT_XOFF 0x00000002 725#define BGE_TXSTAT_SENT_XON 0x00000004 726#define BGE_TXSTAT_LINK_UP 0x00000008 727#define BGE_TXSTAT_ODI_UFLOW 0x00000010 728#define BGE_TXSTAT_ODI_OFLOW 0x00000020 729* 730/* Transmit MAC lengths register / 731#define BGE_TXLEN_SLOTTIME 0x000000FF 732#define BGE_TXLEN_IPG 0x00000F00 733#define BGE_TXLEN_CRS 0x00003000 734* 735/* Receive MAC mode register / 736#define BGE_RXMODE_RESET 0x00000001 737#define BGE_RXMODE_ENABLE 0x00000002 738#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 739#define BGE_RXMODE_RX_GIANTS 0x00000020 740#define BGE_RXMODE_RX_RUNTS 0x00000040 741#define BGE_RXMODE_8022_LENCHECK 0x00000080 742#define BGE_RXMODE_RX_PROMISC 0x00000100 743#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 744#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 745* 746/* Receive MAC status register / 747#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 748#define BGE_RXSTAT_RCVD_XOFF 0x00000002 749#define BGE_RXSTAT_RCVD_XON 0x00000004 750* 751/* Receive Rules Control register / 752#define BGE_RXRULECTL_OFFSET 0x000000FF 753#define BGE_RXRULECTL_CLASS 0x00001F00 754#define BGE_RXRULECTL_HDRTYPE 0x0000E000 755#define BGE_RXRULECTL_COMPARE_OP 0x00030000 756#define BGE_RXRULECTL_MAP 0x01000000 757#define BGE_RXRULECTL_DISCARD 0x02000000 758#define BGE_RXRULECTL_MASK 0x04000000 759#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 760#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 761#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 762#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 763* 764/* Receive Rules Mask register / 765#define BGE_RXRULEMASK_VALUE 0x0000FFFF 766#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 767* 768/* SERDES configuration register / 769#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 770#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 771#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 772#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 773#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 774#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 775#define BGE_SERDESCFG_TXMODE 0x00001000 776#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 777#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 778#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 779#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 780#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 781#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 782#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 783#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 784#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 785* 786/* SERDES status register / 787#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 788#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 789* 790/* SGDIG config (not documented) / 791#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 792#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 793#define BGE_SGDIGCFG_SEND 0x40000000 794#define BGE_SGDIGCFG_AUTO 0x80000000 795* 796/* SGDIG status (not documented) / 797#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 798#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 799#define BGE_SGDIGSTS_DONE 0x00000002 800* 801 802/* MI communication register / 803#define BGE_MICOMM_DATA 0x0000FFFF 804#define BGE_MICOMM_REG 0x001F0000 805#define BGE_MICOMM_PHY 0x03E00000 806#define BGE_MICOMM_CMD 0x0C000000 807#define BGE_MICOMM_READFAIL 0x10000000 808#define BGE_MICOMM_BUSY 0x20000000 809* 810#define BGE_MIREG(x) ((x & 0x1F) << 16) 811#define BGE_MIPHY(x) ((x & 0x1F) << 21) 812#define BGE_MICMD_WRITE 0x04000000 813#define BGE_MICMD_READ 0x08000000 814 815/* MI status register / 816#define BGE_MISTS_LINK 0x00000001 817#define BGE_MISTS_10MBPS 0x00000002 818* 819#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 820#define BGE_MIMODE_AUTOPOLL 0x00000010 821#define BGE_MIMODE_CLKCNT 0x001F0000 822 823 824/* 825 * Send data initiator control registers. 826 / 827#define BGE_SDI_MODE 0x0C00 828#define BGE_SDI_STATUS 0x0C04 829#define BGE_SDI_STATS_CTL 0x0C08 830#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 831#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 832#define BGE_LOCSTATS_COS0 0x0C80 833#define BGE_LOCSTATS_COS1 0x0C84 834#define BGE_LOCSTATS_COS2 0x0C88 835#define BGE_LOCSTATS_COS3 0x0C8C 836#define BGE_LOCSTATS_COS4 0x0C90 837#define BGE_LOCSTATS_COS5 0x0C84 838#define BGE_LOCSTATS_COS6 0x0C98 839#define BGE_LOCSTATS_COS7 0x0C9C 840#define BGE_LOCSTATS_COS8 0x0CA0 841#define BGE_LOCSTATS_COS9 0x0CA4 842#define BGE_LOCSTATS_COS10 0x0CA8 843#define BGE_LOCSTATS_COS11 0x0CAC 844#define BGE_LOCSTATS_COS12 0x0CB0 845#define BGE_LOCSTATS_COS13 0x0CB4 846#define BGE_LOCSTATS_COS14 0x0CB8 847#define BGE_LOCSTATS_COS15 0x0CBC 848#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 849#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 850#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 851#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 852#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 853#define BGE_LOCSTATS_IRQS 0x0CD4 854#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 855#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 856* 857/* Send Data Initiator mode register / 858#define BGE_SDIMODE_RESET 0x00000001 859#define BGE_SDIMODE_ENABLE 0x00000002 860#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 861* 862/* Send Data Initiator stats register / 863#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 864* 865/* Send Data Initiator stats control register / 866#define BGE_SDISTATSCTL_ENABLE 0x00000001 867#define BGE_SDISTATSCTL_FASTER 0x00000002 868#define BGE_SDISTATSCTL_CLEAR 0x00000004 869#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 870#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 871* 872/* 873 * Send Data Completion Control registers 874 / 875#define BGE_SDC_MODE 0x1000 876#define BGE_SDC_STATUS 0x1004 877* 878/* Send Data completion mode register / 879#define BGE_SDCMODE_RESET 0x00000001 880#define BGE_SDCMODE_ENABLE 0x00000002 881#define BGE_SDCMODE_ATTN 0x00000004 882#define BGE_SDCMODE_CDELAY 0x00000010 883* 884/* Send Data completion status register / 885#define BGE_SDCSTAT_ATTN 0x00000004 886* 887/* 888 * Send BD Ring Selector Control registers 889 / 890#define BGE_SRS_MODE 0x1400 891#define BGE_SRS_STATUS 0x1404 892#define BGE_SRS_HWDIAG 0x1408 893#define BGE_SRS_LOC_NIC_CONS0 0x1440 894#define BGE_SRS_LOC_NIC_CONS1 0x1444 895#define BGE_SRS_LOC_NIC_CONS2 0x1448 896#define BGE_SRS_LOC_NIC_CONS3 0x144C 897#define BGE_SRS_LOC_NIC_CONS4 0x1450 898#define BGE_SRS_LOC_NIC_CONS5 0x1454 899#define BGE_SRS_LOC_NIC_CONS6 0x1458 900#define BGE_SRS_LOC_NIC_CONS7 0x145C 901#define BGE_SRS_LOC_NIC_CONS8 0x1460 902#define BGE_SRS_LOC_NIC_CONS9 0x1464 903#define BGE_SRS_LOC_NIC_CONS10 0x1468 904#define BGE_SRS_LOC_NIC_CONS11 0x146C 905#define BGE_SRS_LOC_NIC_CONS12 0x1470 906#define BGE_SRS_LOC_NIC_CONS13 0x1474 907#define BGE_SRS_LOC_NIC_CONS14 0x1478 908#define BGE_SRS_LOC_NIC_CONS15 0x147C 909* 910/* Send BD Ring Selector Mode register / 911#define BGE_SRSMODE_RESET 0x00000001 912#define BGE_SRSMODE_ENABLE 0x00000002 913#define BGE_SRSMODE_ATTN 0x00000004 914* 915/* Send BD Ring Selector Status register / 916#define BGE_SRSSTAT_ERROR 0x00000004 917* 918/* Send BD Ring Selector HW Diagnostics register / 919#define BGE_SRSHWDIAG_STATE 0x0000000F 920#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 921#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 922#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 923* 924/* 925 * Send BD Initiator Selector Control registers 926 / 927#define BGE_SBDI_MODE 0x1800 928#define BGE_SBDI_STATUS 0x1804 929#define BGE_SBDI_LOC_NIC_PROD0 0x1808 930#define BGE_SBDI_LOC_NIC_PROD1 0x180C 931#define BGE_SBDI_LOC_NIC_PROD2 0x1810 932#define BGE_SBDI_LOC_NIC_PROD3 0x1814 933#define BGE_SBDI_LOC_NIC_PROD4 0x1818 934#define BGE_SBDI_LOC_NIC_PROD5 0x181C 935#define BGE_SBDI_LOC_NIC_PROD6 0x1820 936#define BGE_SBDI_LOC_NIC_PROD7 0x1824 937#define BGE_SBDI_LOC_NIC_PROD8 0x1828 938#define BGE_SBDI_LOC_NIC_PROD9 0x182C 939#define BGE_SBDI_LOC_NIC_PROD10 0x1830 940#define BGE_SBDI_LOC_NIC_PROD11 0x1834 941#define BGE_SBDI_LOC_NIC_PROD12 0x1838 942#define BGE_SBDI_LOC_NIC_PROD13 0x183C 943#define BGE_SBDI_LOC_NIC_PROD14 0x1840 944#define BGE_SBDI_LOC_NIC_PROD15 0x1844 945* 946/* Send BD Initiator Mode register / 947#define BGE_SBDIMODE_RESET 0x00000001 948#define BGE_SBDIMODE_ENABLE 0x00000002 949#define BGE_SBDIMODE_ATTN 0x00000004 950* 951/* Send BD Initiator Status register / 952#define BGE_SBDISTAT_ERROR 0x00000004 953* 954/* 955 * Send BD Completion Control registers 956 / 957#define BGE_SBDC_MODE 0x1C00 958#define BGE_SBDC_STATUS 0x1C04 959* 960/* Send BD Completion Control Mode register / 961#define BGE_SBDCMODE_RESET 0x00000001 962#define BGE_SBDCMODE_ENABLE 0x00000002 963#define BGE_SBDCMODE_ATTN 0x00000004 964* 965/* Send BD Completion Control Status register / 966#define BGE_SBDCSTAT_ATTN 0x00000004 967* 968/* 969 * Receive List Placement Control registers 970 / 971#define BGE_RXLP_MODE 0x2000 972#define BGE_RXLP_STATUS 0x2004 973#define BGE_RXLP_SEL_LIST_LOCK 0x2008 974#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 975#define BGE_RXLP_CFG 0x2010 976#define BGE_RXLP_STATS_CTL 0x2014 977#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 978#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 979#define BGE_RXLP_HEAD0 0x2100 980#define BGE_RXLP_TAIL0 0x2104 981#define BGE_RXLP_COUNT0 0x2108 982#define BGE_RXLP_HEAD1 0x2110 983#define BGE_RXLP_TAIL1 0x2114 984#define BGE_RXLP_COUNT1 0x2118 985#define BGE_RXLP_HEAD2 0x2120 986#define BGE_RXLP_TAIL2 0x2124 987#define BGE_RXLP_COUNT2 0x2128 988#define BGE_RXLP_HEAD3 0x2130 989#define BGE_RXLP_TAIL3 0x2134 990#define BGE_RXLP_COUNT3 0x2138 991#define BGE_RXLP_HEAD4 0x2140 992#define BGE_RXLP_TAIL4 0x2144 993#define BGE_RXLP_COUNT4 0x2148 994#define BGE_RXLP_HEAD5 0x2150 995#define BGE_RXLP_TAIL5 0x2154 996#define BGE_RXLP_COUNT5 0x2158 997#define BGE_RXLP_HEAD6 0x2160 998#define BGE_RXLP_TAIL6 0x2164 999#define BGE_RXLP_COUNT6 0x2168 1000#define BGE_RXLP_HEAD7 0x2170 1001#define BGE_RXLP_TAIL7 0x2174 1002#define BGE_RXLP_COUNT7 0x2178 1003#define BGE_RXLP_HEAD8 0x2180 1004#define BGE_RXLP_TAIL8 0x2184 1005#define BGE_RXLP_COUNT8 0x2188 1006#define BGE_RXLP_HEAD9 0x2190 1007#define BGE_RXLP_TAIL9 0x2194 1008#define BGE_RXLP_COUNT9 0x2198 1009#define BGE_RXLP_HEAD10 0x21A0 1010#define BGE_RXLP_TAIL10 0x21A4 1011#define BGE_RXLP_COUNT10 0x21A8 1012#define BGE_RXLP_HEAD11 0x21B0 1013#define BGE_RXLP_TAIL11 0x21B4 1014#define BGE_RXLP_COUNT11 0x21B8 1015#define BGE_RXLP_HEAD12 0x21C0 1016#define BGE_RXLP_TAIL12 0x21C4 1017#define BGE_RXLP_COUNT12 0x21C8 1018#define BGE_RXLP_HEAD13 0x21D0 1019#define BGE_RXLP_TAIL13 0x21D4 1020#define BGE_RXLP_COUNT13 0x21D8 1021#define BGE_RXLP_HEAD14 0x21E0 1022#define BGE_RXLP_TAIL14 0x21E4 1023#define BGE_RXLP_COUNT14 0x21E8 1024#define BGE_RXLP_HEAD15 0x21F0 1025#define BGE_RXLP_TAIL15 0x21F4 1026#define BGE_RXLP_COUNT15 0x21F8 1027#define BGE_RXLP_LOCSTAT_COS0 0x2200 1028#define BGE_RXLP_LOCSTAT_COS1 0x2204 1029#define BGE_RXLP_LOCSTAT_COS2 0x2208 1030#define BGE_RXLP_LOCSTAT_COS3 0x220C 1031#define BGE_RXLP_LOCSTAT_COS4 0x2210 1032#define BGE_RXLP_LOCSTAT_COS5 0x2214 1033#define BGE_RXLP_LOCSTAT_COS6 0x2218 1034#define BGE_RXLP_LOCSTAT_COS7 0x221C 1035#define BGE_RXLP_LOCSTAT_COS8 0x2220 1036#define BGE_RXLP_LOCSTAT_COS9 0x2224 1037#define BGE_RXLP_LOCSTAT_COS10 0x2228 1038#define BGE_RXLP_LOCSTAT_COS11 0x222C 1039#define BGE_RXLP_LOCSTAT_COS12 0x2230 1040#define BGE_RXLP_LOCSTAT_COS13 0x2234 1041#define BGE_RXLP_LOCSTAT_COS14 0x2238 1042#define BGE_RXLP_LOCSTAT_COS15 0x223C 1043#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1044#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1045#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1046#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1047#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1048#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1049#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1050* 1051 1052/* Receive List Placement mode register / 1053#define BGE_RXLPMODE_RESET 0x00000001 1054#define BGE_RXLPMODE_ENABLE 0x00000002 1055#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1056#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1057#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1058* 1059/* Receive List Placement Status register / 1060#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1061#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1062#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1063* 1064/* 1065 * Receive Data and Receive BD Initiator Control Registers 1066 / 1067#define BGE_RDBDI_MODE 0x2400 1068#define BGE_RDBDI_STATUS 0x2404 1069#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1070#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1071#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1072#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1073#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1074#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1075#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1076#define BGE_RX_STD_RCB_NICADDR 0x245C 1077#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1078#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1079#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1080#define BGE_RX_MINI_RCB_NICADDR 0x246C 1081#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1082#define BGE_RDBDI_STD_RX_CONS 0x2474 1083#define BGE_RDBDI_MINI_RX_CONS 0x2478 1084#define BGE_RDBDI_RETURN_PROD0 0x2480 1085#define BGE_RDBDI_RETURN_PROD1 0x2484 1086#define BGE_RDBDI_RETURN_PROD2 0x2488 1087#define BGE_RDBDI_RETURN_PROD3 0x248C 1088#define BGE_RDBDI_RETURN_PROD4 0x2490 1089#define BGE_RDBDI_RETURN_PROD5 0x2494 1090#define BGE_RDBDI_RETURN_PROD6 0x2498 1091#define BGE_RDBDI_RETURN_PROD7 0x249C 1092#define BGE_RDBDI_RETURN_PROD8 0x24A0 1093#define BGE_RDBDI_RETURN_PROD9 0x24A4 1094#define BGE_RDBDI_RETURN_PROD10 0x24A8 1095#define BGE_RDBDI_RETURN_PROD11 0x24AC 1096#define BGE_RDBDI_RETURN_PROD12 0x24B0 1097#define BGE_RDBDI_RETURN_PROD13 0x24B4 1098#define BGE_RDBDI_RETURN_PROD14 0x24B8 1099#define BGE_RDBDI_RETURN_PROD15 0x24BC 1100#define BGE_RDBDI_HWDIAG 0x24C0 1101* 1102 1103/* Receive Data and Receive BD Initiator Mode register / 1104#define BGE_RDBDIMODE_RESET 0x00000001 1105#define BGE_RDBDIMODE_ENABLE 0x00000002 1106#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1107#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1108#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1109* 1110/* Receive Data and Receive BD Initiator Status register / 1111#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1112#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1113#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1114* 1115 1116/* 1117 * Receive Data Completion Control registers 1118 / 1119#define BGE_RDC_MODE 0x2800 1120* 1121/* Receive Data Completion Mode register / 1122#define BGE_RDCMODE_RESET 0x00000001 1123#define BGE_RDCMODE_ENABLE 0x00000002 1124#define BGE_RDCMODE_ATTN 0x00000004 1125* 1126/* 1127 * Receive BD Initiator Control registers 1128 / 1129#define BGE_RBDI_MODE 0x2C00 1130#define BGE_RBDI_STATUS 0x2C04 1131#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1132#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1133#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1134#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1135#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1136#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1137* 1138/* Receive BD Initiator Mode register / 1139#define BGE_RBDIMODE_RESET 0x00000001 1140#define BGE_RBDIMODE_ENABLE 0x00000002 1141#define BGE_RBDIMODE_ATTN 0x00000004 1142* 1143/* Receive BD Initiator Status register / 1144#define BGE_RBDISTAT_ATTN 0x00000004 1145* 1146/* 1147 * Receive BD Completion Control registers 1148 / 1149#define BGE_RBDC_MODE 0x3000 1150#define BGE_RBDC_STATUS 0x3004 1151#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1152#define BGE_RBDC_STD_BD_PROD 0x300C 1153#define BGE_RBDC_MINI_BD_PROD 0x3010 1154* 1155/* Receive BD completion mode register / 1156#define BGE_RBDCMODE_RESET 0x00000001 1157#define BGE_RBDCMODE_ENABLE 0x00000002 1158#define BGE_RBDCMODE_ATTN 0x00000004 1159* 1160/* Receive BD completion status register / 1161#define BGE_RBDCSTAT_ERROR 0x00000004 1162* 1163/* 1164 * Receive List Selector Control registers 1165 / 1166#define BGE_RXLS_MODE 0x3400 1167#define BGE_RXLS_STATUS 0x3404 1168* 1169/* Receive List Selector Mode register / 1170#define BGE_RXLSMODE_RESET 0x00000001 1171#define BGE_RXLSMODE_ENABLE 0x00000002 1172#define BGE_RXLSMODE_ATTN 0x00000004 1173* 1174/* Receive List Selector Status register / 1175#define BGE_RXLSSTAT_ERROR 0x00000004 1176* 1177/* 1178 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1179 / 1180#define BGE_MBCF_MODE 0x3800 1181#define BGE_MBCF_STATUS 0x3804 1182* 1183/* Mbuf Cluster Free mode register / 1184#define BGE_MBCFMODE_RESET 0x00000001 1185#define BGE_MBCFMODE_ENABLE 0x00000002 1186#define BGE_MBCFMODE_ATTN 0x00000004 1187* 1188/* Mbuf Cluster Free status register / 1189#define BGE_MBCFSTAT_ERROR 0x00000004 1190* 1191/* 1192 * Host Coalescing Control registers 1193 / 1194#define BGE_HCC_MODE 0x3C00 1195#define BGE_HCC_STATUS 0x3C04 1196#define BGE_HCC_RX_COAL_TICKS 0x3C08 1197#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1198#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1199#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1200#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1201#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1202#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1203#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1204#define BGE_HCC_STATS_TICKS 0x3C28 1205#define BGE_HCC_STATS_ADDR_HI 0x3C30 1206#define BGE_HCC_STATS_ADDR_LO 0x3C34 1207#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1208#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1209#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1210#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1211#define BGE_FLOW_ATTN 0x3C48 1212#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1213#define BGE_HCC_STD_BD_CONS 0x3C54 1214#define BGE_HCC_MINI_BD_CONS 0x3C58 1215#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1216#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1217#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1218#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1219#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1220#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1221#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1222#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1223#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1224#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1225#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1226#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1227#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1228#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1229#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1230#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1231#define BGE_HCC_TX_BD_CONS0 0x3CC0 1232#define BGE_HCC_TX_BD_CONS1 0x3CC4 1233#define BGE_HCC_TX_BD_CONS2 0x3CC8 1234#define BGE_HCC_TX_BD_CONS3 0x3CCC 1235#define BGE_HCC_TX_BD_CONS4 0x3CD0 1236#define BGE_HCC_TX_BD_CONS5 0x3CD4 1237#define BGE_HCC_TX_BD_CONS6 0x3CD8 1238#define BGE_HCC_TX_BD_CONS7 0x3CDC 1239#define BGE_HCC_TX_BD_CONS8 0x3CE0 1240#define BGE_HCC_TX_BD_CONS9 0x3CE4 1241#define BGE_HCC_TX_BD_CONS10 0x3CE8 1242#define BGE_HCC_TX_BD_CONS11 0x3CEC 1243#define BGE_HCC_TX_BD_CONS12 0x3CF0 1244#define BGE_HCC_TX_BD_CONS13 0x3CF4 1245#define BGE_HCC_TX_BD_CONS14 0x3CF8 1246#define BGE_HCC_TX_BD_CONS15 0x3CFC 1247* 1248 1249/* Host coalescing mode register / 1250#define BGE_HCCMODE_RESET 0x00000001 1251#define BGE_HCCMODE_ENABLE 0x00000002 1252#define BGE_HCCMODE_ATTN 0x00000004 1253#define BGE_HCCMODE_COAL_NOW 0x00000008 1254#define BGE_HCCMODE_MSI_BITS 0x00000070 1255#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1256* 1257#define BGE_STATBLKSZ_FULL 0x00000000 1258#define BGE_STATBLKSZ_64BYTE 0x00000080 1259#define BGE_STATBLKSZ_32BYTE 0x00000100 1260 1261/* Host coalescing status register / 1262#define BGE_HCCSTAT_ERROR 0x00000004 1263* 1264/* Flow attention register / 1265#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1266#define BGE_FLOWATTN_MEMARB 0x00000080 1267#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1268#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1269#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1270#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1271#define BGE_FLOWATTN_RDBDI 0x00080000 1272#define BGE_FLOWATTN_RXLS 0x00100000 1273#define BGE_FLOWATTN_RXLP 0x00200000 1274#define BGE_FLOWATTN_RBDC 0x00400000 1275#define BGE_FLOWATTN_RBDI 0x00800000 1276#define BGE_FLOWATTN_SDC 0x08000000 1277#define BGE_FLOWATTN_SDI 0x10000000 1278#define BGE_FLOWATTN_SRS 0x20000000 1279#define BGE_FLOWATTN_SBDC 0x40000000 1280#define BGE_FLOWATTN_SBDI 0x80000000 1281* 1282/* 1283 * Memory arbiter registers 1284 / 1285#define BGE_MARB_MODE 0x4000 1286#define BGE_MARB_STATUS 0x4004 1287#define BGE_MARB_TRAPADDR_HI 0x4008 1288#define BGE_MARB_TRAPADDR_LO 0x400C 1289* 1290/* Memory arbiter mode register / 1291#define BGE_MARBMODE_RESET 0x00000001 1292#define BGE_MARBMODE_ENABLE 0x00000002 1293#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1294#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1295#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1296#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1297#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1298#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1299#define BGE_MARBMODE_PCI_TRAP 0x00000100 1300#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1301#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1302#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1303#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1304#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1305#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1306#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1307#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1308#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1309#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1310#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1311#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1312#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1313#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1314#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1315#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1316#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1317* 1318/* Memory arbiter status register / 1319#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1320#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1321#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1322#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1323#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1324#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1325#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1326#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1327#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1328#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1329#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1330#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1331#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1332#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1333#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1334#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1335#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1336#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1337#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1338#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1339#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1340#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1341#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1342#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1343* 1344/* 1345 * Buffer manager control registers 1346 / 1347#define BGE_BMAN_MODE 0x4400 1348#define BGE_BMAN_STATUS 0x4404 1349#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1350#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1351#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1352#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1353#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1354#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1355#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1356#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1357#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1358#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1359#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1360#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1361#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1362#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1363#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1364#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1365#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1366#define BGE_BMAN_HWDIAG_1 0x444C 1367#define BGE_BMAN_HWDIAG_2 0x4450 1368#define BGE_BMAN_HWDIAG_3 0x4454 1369* 1370/* Buffer manager mode register / 1371#define BGE_BMANMODE_RESET 0x00000001 1372#define BGE_BMANMODE_ENABLE 0x00000002 1373#define BGE_BMANMODE_ATTN 0x00000004 1374#define BGE_BMANMODE_TESTMODE 0x00000008 1375#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1376* 1377/* Buffer manager status register / 1378#define BGE_BMANSTAT_ERRO 0x00000004 1379#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1380* 1381 1382/* 1383 * Read DMA Control registers 1384 / 1385#define BGE_RDMA_MODE 0x4800 1386#define BGE_RDMA_STATUS 0x4804 1387* 1388/* Read DMA mode register / 1389#define BGE_RDMAMODE_RESET 0x00000001 1390#define BGE_RDMAMODE_ENABLE 0x00000002 1391#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1392#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1393#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1394#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1395#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1396#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1397#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1398#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1399#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1400#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1401#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1402#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1403#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1404#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1405#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1406#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1407* 1408/* Read DMA status register / 1409#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1410#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1411#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1412#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1413#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1414#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1415#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1416#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1417* 1418/* 1419 * Write DMA control registers 1420 / 1421#define BGE_WDMA_MODE 0x4C00 1422#define BGE_WDMA_STATUS 0x4C04 1423* 1424/* Write DMA mode register / 1425#define BGE_WDMAMODE_RESET 0x00000001 1426#define BGE_WDMAMODE_ENABLE 0x00000002 1427#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1428#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1429#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1430#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1431#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1432#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1433#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1434#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1435#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1436#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1437* 1438/* Write DMA status register / 1439#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1440#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1441#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1442#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1443#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1444#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1445#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1446#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1447* 1448 1449/* 1450 * RX CPU registers 1451 / 1452#define BGE_RXCPU_MODE 0x5000 1453#define BGE_RXCPU_STATUS 0x5004 1454#define BGE_RXCPU_PC 0x501C 1455* 1456/* RX CPU mode register / 1457#define BGE_RXCPUMODE_RESET 0x00000001 1458#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1459#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1460#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1461#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1462#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1463#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1464#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1465#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1466#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1467#define BGE_RXCPUMODE_HALTCPU 0x00000400 1468#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1469#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1470#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1471* 1472/* RX CPU status register / 1473#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1474#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1475#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1476#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1477#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1478#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1479#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1480#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1481#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1482#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1483#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1484#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1485#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1486#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1487#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1488#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1489#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1490* 1491/* 1492 * V? CPU registers 1493 / 1494#define BGE_VCPU_STATUS 0x5100 1495#define BGE_VCPU_EXT_CTRL 0x6890 1496* 1497#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1498#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1499 1500#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1501#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1502 1503/* 1504 * TX CPU registers 1505 / 1506#define BGE_TXCPU_MODE 0x5400 1507#define BGE_TXCPU_STATUS 0x5404 1508#define BGE_TXCPU_PC 0x541C 1509* 1510/* TX CPU mode register / 1511#define BGE_TXCPUMODE_RESET 0x00000001 1512#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1513#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1514#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1515#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1516#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1517#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1518#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1519#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1520#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1521#define BGE_TXCPUMODE_HALTCPU 0x00000400 1522#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1523#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1524* 1525/* TX CPU status register / 1526#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1527#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1528#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1529#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1530#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1531#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1532#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1533#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1534#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1535#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1536#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1537#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1538#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1539#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1540#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1541#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1542#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1543* 1544 1545/* 1546 * Low priority mailbox registers 1547 / 1548#define BGE_LPMBX_IRQ0_HI 0x5800 1549#define BGE_LPMBX_IRQ0_LO 0x5804 1550#define BGE_LPMBX_IRQ1_HI 0x5808 1551#define BGE_LPMBX_IRQ1_LO 0x580C 1552#define BGE_LPMBX_IRQ2_HI 0x5810 1553#define BGE_LPMBX_IRQ2_LO 0x5814 1554#define BGE_LPMBX_IRQ3_HI 0x5818 1555#define BGE_LPMBX_IRQ3_LO 0x581C 1556#define BGE_LPMBX_GEN0_HI 0x5820 1557#define BGE_LPMBX_GEN0_LO 0x5824 1558#define BGE_LPMBX_GEN1_HI 0x5828 1559#define BGE_LPMBX_GEN1_LO 0x582C 1560#define BGE_LPMBX_GEN2_HI 0x5830 1561#define BGE_LPMBX_GEN2_LO 0x5834 1562#define BGE_LPMBX_GEN3_HI 0x5828 1563#define BGE_LPMBX_GEN3_LO 0x582C 1564#define BGE_LPMBX_GEN4_HI 0x5840 1565#define BGE_LPMBX_GEN4_LO 0x5844 1566#define BGE_LPMBX_GEN5_HI 0x5848 1567#define BGE_LPMBX_GEN5_LO 0x584C 1568#define BGE_LPMBX_GEN6_HI 0x5850 1569#define BGE_LPMBX_GEN6_LO 0x5854 1570#define BGE_LPMBX_GEN7_HI 0x5858 1571#define BGE_LPMBX_GEN7_LO 0x585C 1572#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1573#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1574#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1575#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1576#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1577#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1578#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1579#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1580#define BGE_LPMBX_RX_CONS0_HI 0x5880 1581#define BGE_LPMBX_RX_CONS0_LO 0x5884 1582#define BGE_LPMBX_RX_CONS1_HI 0x5888 1583#define BGE_LPMBX_RX_CONS1_LO 0x588C 1584#define BGE_LPMBX_RX_CONS2_HI 0x5890 1585#define BGE_LPMBX_RX_CONS2_LO 0x5894 1586#define BGE_LPMBX_RX_CONS3_HI 0x5898 1587#define BGE_LPMBX_RX_CONS3_LO 0x589C 1588#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1589#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1590#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1591#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1592#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1593#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1594#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1595#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1596#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1597#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1598#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1599#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1600#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1601#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1602#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1603#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1604#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1605#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1606#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1607#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1608#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1609#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1610#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1611#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1612#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1613#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1614#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1615#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1616#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1617#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1618#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1619#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1620#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1621#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1622#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1623#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1624#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1625#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1626#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1627#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1628#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1629#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1630#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1631#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1632#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1633#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1634#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1635#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1636#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1637#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1638#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1639#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1640#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1641#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1642#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1643#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1644#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1645#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1646#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1647#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1648#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1649#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1650#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1651#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1652#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1653#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1654#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1655#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1656#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1657#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1658#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1659#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1660#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1661#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1662#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1663#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1664#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1665#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1666#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1667#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1668#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1669#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1670#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1671#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1672#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1673#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1674#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1675#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1676* 1677/* 1678 * Flow throw Queue reset register 1679 / 1680#define BGE_FTQ_RESET 0x5C00 1681* 1682#define BGE_FTQRESET_DMAREAD 0x00000002 1683#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1684#define BGE_FTQRESET_DMADONE 0x00000010 1685#define BGE_FTQRESET_SBDC 0x00000020 1686#define BGE_FTQRESET_SDI 0x00000040 1687#define BGE_FTQRESET_WDMA 0x00000080 1688#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1689#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1690#define BGE_FTQRESET_SDC 0x00000400 1691#define BGE_FTQRESET_HCC 0x00000800 1692#define BGE_FTQRESET_TXFIFO 0x00001000 1693#define BGE_FTQRESET_MBC 0x00002000 1694#define BGE_FTQRESET_RBDC 0x00004000 1695#define BGE_FTQRESET_RXLP 0x00008000 1696#define BGE_FTQRESET_RDBDI 0x00010000 1697#define BGE_FTQRESET_RDC 0x00020000 1698#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1699 1700/* 1701 * Message Signaled Interrupt registers 1702 / 1703#define BGE_MSI_MODE 0x6000 1704#define BGE_MSI_STATUS 0x6004 1705#define BGE_MSI_FIFOACCESS 0x6008 1706* 1707/* MSI mode register / 1708#define BGE_MSIMODE_RESET 0x00000001 1709#define BGE_MSIMODE_ENABLE 0x00000002 1710#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1711#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1712* 1713/* MSI status register / 1714#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1715#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1716#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1717#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1718#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1719* 1720 1721/* 1722 * DMA Completion registers 1723 / 1724#define BGE_DMAC_MODE 0x6400 1725* 1726/* DMA Completion mode register / 1727#define BGE_DMACMODE_RESET 0x00000001 1728#define BGE_DMACMODE_ENABLE 0x00000002 1729* 1730 1731/* 1732 * General control registers. 1733 / 1734#define BGE_MODE_CTL 0x6800 1735#define BGE_MISC_CFG 0x6804 1736#define BGE_MISC_LOCAL_CTL 0x6808 1737#define BGE_CPU_EVENT 0x6810 1738#define BGE_EE_ADDR 0x6838 1739#define BGE_EE_DATA 0x683C 1740#define BGE_EE_CTL 0x6840 1741#define BGE_MDI_CTL 0x6844 1742#define BGE_EE_DELAY 0x6848 1743#define BGE_FASTBOOT_PC 0x6894 1744* 1745/* 1746 * NVRAM Control registers 1747 / 1748#define BGE_NVRAM_CMD 0x7000 1749#define BGE_NVRAM_STAT 0x7004 1750#define BGE_NVRAM_WRDATA 0x7008 1751#define BGE_NVRAM_ADDR 0x700c 1752#define BGE_NVRAM_RDDATA 0x7010 1753#define BGE_NVRAM_CFG1 0x7014 1754#define BGE_NVRAM_CFG2 0x7018 1755#define BGE_NVRAM_CFG3 0x701c 1756#define BGE_NVRAM_SWARB 0x7020 1757#define BGE_NVRAM_ACCESS 0x7024 1758#define BGE_NVRAM_WRITE1 0x7028 1759* 1760#define BGE_NVRAMCMD_RESET 0x00000001 1761#define BGE_NVRAMCMD_DONE 0x00000008 1762#define BGE_NVRAMCMD_START 0x00000010 1763#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd / 1764#define BGE_NVRAMCMD_ERASE 0x00000040 1765#define BGE_NVRAMCMD_FIRST 0x00000080 1766#define BGE_NVRAMCMD_LAST 0x00000100 1767* 1768#define BGE_NVRAM_READCMD \ 1769 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1770 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE) 1771#define BGE_NVRAM_WRITECMD \ 1772 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1773 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE\|BGE_NVRAMCMD_WR) 1774 1775#define BGE_NVRAMSWARB_SET0 0x00000001 1776#define BGE_NVRAMSWARB_SET1 0x00000002 1777#define BGE_NVRAMSWARB_SET2 0x00000003 1778#define BGE_NVRAMSWARB_SET3 0x00000004 1779#define BGE_NVRAMSWARB_CLR0 0x00000010 1780#define BGE_NVRAMSWARB_CLR1 0x00000020 1781#define BGE_NVRAMSWARB_CLR2 0x00000040 1782#define BGE_NVRAMSWARB_CLR3 0x00000080 1783#define BGE_NVRAMSWARB_GNT0 0x00000100 1784#define BGE_NVRAMSWARB_GNT1 0x00000200 1785#define BGE_NVRAMSWARB_GNT2 0x00000400 1786#define BGE_NVRAMSWARB_GNT3 0x00000800 1787#define BGE_NVRAMSWARB_REQ0 0x00001000 1788#define BGE_NVRAMSWARB_REQ1 0x00002000 1789#define BGE_NVRAMSWARB_REQ2 0x00004000 1790#define BGE_NVRAMSWARB_REQ3 0x00008000 1791 1792#define BGE_NVRAMACC_ENABLE 0x00000001 1793#define BGE_NVRAMACC_WRENABLE 0x00000002 1794 1795/* Mode control register / 1796#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1797#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1798#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1799#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1800#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1801#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1802#define BGE_MODECTL_NO_RX_CRC 0x00000400 1803#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1804#define BGE_MODECTL_NO_TX_INTR 0x00002000 1805#define BGE_MODECTL_NO_RX_INTR 0x00004000 1806#define BGE_MODECTL_FORCE_PCI32 0x00008000 1807#define BGE_MODECTL_STACKUP 0x00010000 1808#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1809#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1810#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1811#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1812#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1813#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1814#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1815#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1816#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1817#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1818* 1819/* Misc. config register / 1820#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1821#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1822#define BGE_MISCCFG_BOARD_ID 0x0001E000 1823#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1824#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1825#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1826#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1827* 1828#define BGE_32BITTIME_66MHZ (0x41 << 1) 1829 1830/* Misc. Local Control / 1831#define BGE_MLC_INTR_STATE 0x00000001 1832#define BGE_MLC_INTR_CLR 0x00000002 1833#define BGE_MLC_INTR_SET 0x00000004 1834#define BGE_MLC_INTR_ONATTN 0x00000008 1835#define BGE_MLC_MISCIO_IN0 0x00000100 1836#define BGE_MLC_MISCIO_IN1 0x00000200 1837#define BGE_MLC_MISCIO_IN2 0x00000400 1838#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1839#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1840#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1841#define BGE_MLC_MISCIO_OUT0 0x00004000 1842#define BGE_MLC_MISCIO_OUT1 0x00008000 1843#define BGE_MLC_MISCIO_OUT2 0x00010000 1844#define BGE_MLC_EXTRAM_ENB 0x00020000 1845#define BGE_MLC_SRAM_SIZE 0x001C0000 1846#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 1847#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 1848#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1849#define BGE_MLC_AUTO_EEPROM 0x01000000 1850* 1851#define BGE_SSRAMSIZE_256KB 0x00000000 1852#define BGE_SSRAMSIZE_512KB 0x00040000 1853#define BGE_SSRAMSIZE_1MB 0x00080000 1854#define BGE_SSRAMSIZE_2MB 0x000C0000 1855#define BGE_SSRAMSIZE_4MB 0x00100000 1856#define BGE_SSRAMSIZE_8MB 0x00140000 1857#define BGE_SSRAMSIZE_16M 0x00180000 1858 1859/* EEPROM address register / 1860#define BGE_EEADDR_ADDRESS 0x0000FFFC 1861#define BGE_EEADDR_HALFCLK 0x01FF0000 1862#define BGE_EEADDR_START 0x02000000 1863#define BGE_EEADDR_DEVID 0x1C000000 1864#define BGE_EEADDR_RESET 0x20000000 1865#define BGE_EEADDR_DONE 0x40000000 1866#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 1867* 1868#define BGE_EEDEVID(x) ((x & 7) << 26) 1869#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1870#define BGE_HALFCLK_384SCL 0x60 1871#define BGE_EE_READCMD \ 1872 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1873 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 1874#define BGE_EE_WRCMD \ 1875 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1876 BGE_EEADDR_START\|BGE_EEADDR_DONE) 1877 1878/* EEPROM Control register / 1879#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1880#define BGE_EECTL_CLKOUT 0x00000002 1881#define BGE_EECTL_CLKIN 0x00000004 1882#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1883#define BGE_EECTL_DATAOUT 0x00000010 1884#define BGE_EECTL_DATAIN 0x00000020 1885* 1886/* MDI (MII/GMII) access register / 1887#define BGE_MDI_DATA 0x00000001 1888#define BGE_MDI_DIR 0x00000002 1889#define BGE_MDI_SEL 0x00000004 1890#define BGE_MDI_CLK 0x00000008 1891* 1892#define BGE_MEMWIN_START 0x00008000 1893#define BGE_MEMWIN_END 0x0000FFFF 1894 1895 1896#define BGE_MEMWIN_READ(sc, x, val) \ 1897 do { \ 1898 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1899 (0xFFFF0000 & x), 4); \ 1900 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1901 } while(0) 1902 1903#define BGE_MEMWIN_WRITE(sc, x, val) \ 1904 do { \ 1905 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1906 (0xFFFF0000 & x), 4); \ 1907 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1908 } while(0) 1909 1910/* 1911 * This magic number is written to the firmware mailbox at 0xb50 1912 * before a software reset is issued. After the internal firmware 1913 * has completed its initialization it will write the opposite of 1914 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1915 * driver to synchronize with the firmware. 1916 / 1917#define BGE_MAGIC_NUMBER 0x4B657654 1918* 1919typedef struct { 1920 uint32_t bge_addr_hi; 1921 uint32_t bge_addr_lo; 1922} bge_hostaddr; 1923 1924#define BGE_HOSTADDR(x, y) \ 1925 do { \ 1926 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1927 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1928 } while(0) 1929 1930#define BGE_ADDR_LO(y) \ 1931 ((uint64_t) (y) & 0xFFFFFFFF) 1932#define BGE_ADDR_HI(y) \ 1933 ((uint64_t) (y) >> 32) 1934 1935/* Ring control block structure / 1936struct bge_rcb { 1937* bge_hostaddr bge_hostaddr; 1938 uint32_t bge_maxlen_flags; 1939 uint32_t bge_nicaddr; 1940}; 1941 1942#define RCB_WRITE_4(sc, rcb, offset, val) \ 1943 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 1944#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 1945 1946#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1947#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1948 1949struct bge_tx_bd { 1950 bge_hostaddr bge_addr; 1951#if BYTE_ORDER == LITTLE_ENDIAN 1952 uint16_t bge_flags; 1953 uint16_t bge_len; 1954 uint16_t bge_vlan_tag; 1955 uint16_t bge_mss; 1956#else 1957 uint16_t bge_len; 1958 uint16_t bge_flags; 1959 uint16_t bge_mss; 1960 uint16_t bge_vlan_tag; 1961#endif 1962}; 1963 1964#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1965#define BGE_TXBDFLAG_IP_CSUM 0x0002 1966#define BGE_TXBDFLAG_END 0x0004 1967#define BGE_TXBDFLAG_IP_FRAG 0x0008 1968#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1969#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1970#define BGE_TXBDFLAG_COAL_NOW 0x0080 1971#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1972#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1973#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1974#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1975#define BGE_TXBDFLAG_NO_CRC 0x8000 1976 1977#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1978 BGE_SEND_RING_1_TO_4 + \ 1979 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1980 1981struct bge_rx_bd { 1982 bge_hostaddr bge_addr; 1983#if BYTE_ORDER == LITTLE_ENDIAN 1984 uint16_t bge_len; 1985 uint16_t bge_idx; 1986 uint16_t bge_flags; 1987 uint16_t bge_type; 1988 uint16_t bge_tcp_udp_csum; 1989 uint16_t bge_ip_csum; 1990 uint16_t bge_vlan_tag; 1991 uint16_t bge_error_flag; 1992#else 1993 uint16_t bge_idx; 1994 uint16_t bge_len; 1995 uint16_t bge_type; 1996 uint16_t bge_flags; 1997 uint16_t bge_ip_csum; 1998 uint16_t bge_tcp_udp_csum; 1999 uint16_t bge_error_flag; 2000 uint16_t bge_vlan_tag; 2001#endif 2002 uint32_t bge_rsvd; 2003 uint32_t bge_opaque; 2004}; 2005 2006struct bge_extrx_bd { 2007 bge_hostaddr bge_addr1; 2008 bge_hostaddr bge_addr2; 2009 bge_hostaddr bge_addr3; 2010#if BYTE_ORDER == LITTLE_ENDIAN 2011 uint16_t bge_len2; 2012 uint16_t bge_len1; 2013 uint16_t bge_rsvd1; 2014 uint16_t bge_len3; 2015#else 2016 uint16_t bge_len1; 2017 uint16_t bge_len2; 2018 uint16_t bge_len3; 2019 uint16_t bge_rsvd1; 2020#endif 2021 bge_hostaddr bge_addr0; 2022#if BYTE_ORDER == LITTLE_ENDIAN 2023 uint16_t bge_len0; 2024 uint16_t bge_idx; 2025 uint16_t bge_flags; 2026 uint16_t bge_type; 2027 uint16_t bge_tcp_udp_csum; 2028 uint16_t bge_ip_csum; 2029 uint16_t bge_vlan_tag; 2030 uint16_t bge_error_flag; 2031#else 2032 uint16_t bge_idx; 2033 uint16_t bge_len0; 2034 uint16_t bge_type; 2035 uint16_t bge_flags; 2036 uint16_t bge_ip_csum; 2037 uint16_t bge_tcp_udp_csum; 2038 uint16_t bge_error_flag; 2039 uint16_t bge_vlan_tag; 2040#endif 2041 uint32_t bge_rsvd0; 2042 uint32_t bge_opaque; 2043}; 2044 2045#define BGE_RXBDFLAG_END 0x0004 2046#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2047#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2048#define BGE_RXBDFLAG_ERROR 0x0400 2049#define BGE_RXBDFLAG_MINI_RING 0x0800 2050#define BGE_RXBDFLAG_IP_CSUM 0x1000 2051#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2052#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2053 2054#define BGE_RXERRFLAG_BAD_CRC 0x0001 2055#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2056#define BGE_RXERRFLAG_LINK_LOST 0x0004 2057#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2058#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2059#define BGE_RXERRFLAG_RUNT 0x0020 2060#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2061#define BGE_RXERRFLAG_GIANT 0x0080 2062 2063struct bge_sts_idx { 2064#if BYTE_ORDER == LITTLE_ENDIAN 2065 uint16_t bge_rx_prod_idx; 2066 uint16_t bge_tx_cons_idx; 2067#else 2068 uint16_t bge_tx_cons_idx; 2069 uint16_t bge_rx_prod_idx; 2070#endif 2071}; 2072 2073struct bge_status_block { 2074 uint32_t bge_status; 2075 uint32_t bge_rsvd0; 2076#if BYTE_ORDER == LITTLE_ENDIAN 2077 uint16_t bge_rx_jumbo_cons_idx; 2078 uint16_t bge_rx_std_cons_idx; 2079 uint16_t bge_rx_mini_cons_idx; 2080 uint16_t bge_rsvd1; 2081#else 2082 uint16_t bge_rx_std_cons_idx; 2083 uint16_t bge_rx_jumbo_cons_idx; 2084 uint16_t bge_rsvd1; 2085 uint16_t bge_rx_mini_cons_idx; 2086#endif 2087 struct bge_sts_idx bge_idx[16]; 2088}; 2089 2090#define BGE_STATFLAG_UPDATED 0x00000001 2091#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2092#define BGE_STATFLAG_ERROR 0x00000004 2093 2094 2095/* 2096 * Broadcom Vendor ID 2097 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2098 * even though they're now manufactured by Broadcom) 2099 / 2100#define BCOM_VENDORID 0x14E4 2101#define BCOM_DEVICEID_BCM5700 0x1644 2102#define BCOM_DEVICEID_BCM5701 0x1645 2103#define BCOM_DEVICEID_BCM5702 0x1646 2104#define BCOM_DEVICEID_BCM5702X 0x16A6 2105#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2106#define BCOM_DEVICEID_BCM5703 0x1647 2107#define BCOM_DEVICEID_BCM5703X 0x16A7 2108#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2109#define BCOM_DEVICEID_BCM5704C 0x1648 2110#define BCOM_DEVICEID_BCM5704S 0x16A8 2111#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2112#define BCOM_DEVICEID_BCM5705 0x1653 2113#define BCOM_DEVICEID_BCM5705K 0x1654 2114#define BCOM_DEVICEID_BCM5705F 0x166E 2115#define BCOM_DEVICEID_BCM5705M 0x165D 2116#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2117#define BCOM_DEVICEID_BCM5714C 0x1668 2118#define BCOM_DEVICEID_BCM5714S 0x1669 2119#define BCOM_DEVICEID_BCM5715 0x1678 2120#define BCOM_DEVICEID_BCM5715S 0x1679 2121#define BCOM_DEVICEID_BCM5720 0x1658 2122#define BCOM_DEVICEID_BCM5721 0x1659 2123#define BCOM_DEVICEID_BCM5722 0x165A 2124#define BCOM_DEVICEID_BCM5723 0x165B 2125#define BCOM_DEVICEID_BCM5750 0x1676 2126#define BCOM_DEVICEID_BCM5750M 0x167C 2127#define BCOM_DEVICEID_BCM5751 0x1677 2128#define BCOM_DEVICEID_BCM5751F 0x167E 2129#define BCOM_DEVICEID_BCM5751M 0x167D 2130#define BCOM_DEVICEID_BCM5752 0x1600 2131#define BCOM_DEVICEID_BCM5752M 0x1601 2132#define BCOM_DEVICEID_BCM5753 0x16F7 2133#define BCOM_DEVICEID_BCM5753F 0x16FE 2134#define BCOM_DEVICEID_BCM5753M 0x16FD 2135#define BCOM_DEVICEID_BCM5754 0x167A 2136#define BCOM_DEVICEID_BCM5754M 0x1672 2137#define BCOM_DEVICEID_BCM5755 0x167B 2138#define BCOM_DEVICEID_BCM5755M 0x1673 2139#define BCOM_DEVICEID_BCM5756 0x1674 2140#define BCOM_DEVICEID_BCM5761 0x1681 2141#define BCOM_DEVICEID_BCM5761E 0x1680 2142#define BCOM_DEVICEID_BCM5761S 0x1688 2143#define BCOM_DEVICEID_BCM5761SE 0x1689 2144#define BCOM_DEVICEID_BCM5764 0x1684 2145#define BCOM_DEVICEID_BCM5780 0x166A 2146#define BCOM_DEVICEID_BCM5780S 0x166B 2147#define BCOM_DEVICEID_BCM5781 0x16DD 2148#define BCOM_DEVICEID_BCM5782 0x1696 2149#define BCOM_DEVICEID_BCM5784 0x1698 2150#define BCOM_DEVICEID_BCM5785F 0x16a0 2151#define BCOM_DEVICEID_BCM5785G 0x1699 2152#define BCOM_DEVICEID_BCM5786 0x169A 2153#define BCOM_DEVICEID_BCM5787 0x169B 2154#define BCOM_DEVICEID_BCM5787M 0x1693 2155#define BCOM_DEVICEID_BCM5787F 0x167f 2156#define BCOM_DEVICEID_BCM5788 0x169C 2157#define BCOM_DEVICEID_BCM5789 0x169D 2158#define BCOM_DEVICEID_BCM5901 0x170D 2159#define BCOM_DEVICEID_BCM5901A2 0x170E 2160#define BCOM_DEVICEID_BCM5903M 0x16FF 2161#define BCOM_DEVICEID_BCM5906 0x1712 2162#define BCOM_DEVICEID_BCM5906M 0x1713 2163#define BCOM_DEVICEID_BCM57760 0x1690 2164#define BCOM_DEVICEID_BCM57780 0x1692 2165#define BCOM_DEVICEID_BCM57788 0x1691 2166#define BCOM_DEVICEID_BCM57790 0x1694 2167* 2168/* 2169 * Alteon AceNIC PCI vendor/device ID. 2170 / 2171#define ALTEON_VENDORID 0x12AE 2172#define ALTEON_DEVICEID_ACENIC 0x0001 2173#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2174#define ALTEON_DEVICEID_BCM5700 0x0003 2175#define ALTEON_DEVICEID_BCM5701 0x0004 2176* 2177/* 2178 * 3Com 3c996 PCI vendor/device ID. 2179 / 2180#define TC_VENDORID 0x10B7 2181#define TC_DEVICEID_3C996 0x0003 2182* 2183/* 2184 * SysKonnect PCI vendor ID 2185 / 2186#define SK_VENDORID 0x1148 2187#define SK_DEVICEID_ALTIMA 0x4400 2188#define SK_SUBSYSID_9D21 0x4421 2189#define SK_SUBSYSID_9D41 0x4441 2190* 2191/* 2192 * Altima PCI vendor/device ID. 2193 / 2194#define ALTIMA_VENDORID 0x173b 2195#define ALTIMA_DEVICE_AC1000 0x03e8 2196#define ALTIMA_DEVICE_AC1002 0x03e9 2197#define ALTIMA_DEVICE_AC9100 0x03ea 2198* 2199/* 2200 * Dell PCI vendor ID 2201 / 2202* 2203#define DELL_VENDORID 0x1028 2204 2205/* 2206 * Apple PCI vendor ID. 2207 / 2208#define APPLE_VENDORID 0x106b 2209#define APPLE_DEVICE_BCM5701 0x1645 2210* 2211/* 2212 * Sun PCI vendor ID 2213 / 2214#define SUN_VENDORID 0x108e 2215* 2216/* 2217 * Fujitsu vendor/device IDs 2218 / 2219#define FJTSU_VENDORID 0x10cf 2220#define FJTSU_DEVICEID_PW008GE5 0x11a1 2221#define FJTSU_DEVICEID_PW008GE4 0x11a2 2222#define FJTSU_DEVICEID_PP250450 0x11cc / PRIMEPOWER250/450 LAN / 2223* 2224/* 2225 * Offset of MAC address inside EEPROM. 2226 / 2227#define BGE_EE_MAC_OFFSET 0x7C 2228#define BGE_EE_MAC_OFFSET_5906 0x10 2229#define BGE_EE_HWCFG_OFFSET 0xC8 2230* 2231#define BGE_HWCFG_VOLTAGE 0x00000003 2232#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2233#define BGE_HWCFG_MEDIA 0x00000030 2234#define BGE_HWCFG_ASF 0x00000080 2235 2236#define BGE_VOLTAGE_1POINT3 0x00000000 2237#define BGE_VOLTAGE_1POINT8 0x00000001 2238 2239#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2240#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2241#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2242 2243#define BGE_MEDIA_UNSPEC 0x00000000 2244#define BGE_MEDIA_COPPER 0x00000010 2245#define BGE_MEDIA_FIBER 0x00000020 2246 2247#define BGE_TICKS_PER_SEC 1000000 2248 2249/* 2250 * Ring size constants. 2251 / 2252#define BGE_EVENT_RING_CNT 256 2253#define BGE_CMD_RING_CNT 64 2254#define BGE_STD_RX_RING_CNT 512 2255#define BGE_JUMBO_RX_RING_CNT 256 2256#define BGE_MINI_RX_RING_CNT 1024 2257#define BGE_RETURN_RING_CNT 1024 2258* 2259/* 5705 has smaller return ring size / 2260* 2261#define BGE_RETURN_RING_CNT_5705 512 2262 2263/* 2264 * Possible TX ring sizes. 2265 / 2266#define BGE_TX_RING_CNT_128 128 2267#define BGE_TX_RING_BASE_128 0x3800 2268* 2269#define BGE_TX_RING_CNT_256 256 2270#define BGE_TX_RING_BASE_256 0x3000 2271 2272#define BGE_TX_RING_CNT_512 512 2273#define BGE_TX_RING_BASE_512 0x2000 2274 2275#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2276#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2277 2278/* 2279 * Tigon III statistics counters. 2280 / 2281/ Statistics maintained MAC Receive block. / 2282struct bge_rx_mac_stats { 2283* bge_hostaddr ifHCInOctets; 2284 bge_hostaddr Reserved1; 2285 bge_hostaddr etherStatsFragments; 2286 bge_hostaddr ifHCInUcastPkts; 2287 bge_hostaddr ifHCInMulticastPkts; 2288 bge_hostaddr ifHCInBroadcastPkts; 2289 bge_hostaddr dot3StatsFCSErrors; 2290 bge_hostaddr dot3StatsAlignmentErrors; 2291 bge_hostaddr xonPauseFramesReceived; 2292 bge_hostaddr xoffPauseFramesReceived; 2293 bge_hostaddr macControlFramesReceived; 2294 bge_hostaddr xoffStateEntered; 2295 bge_hostaddr dot3StatsFramesTooLong; 2296 bge_hostaddr etherStatsJabbers; 2297 bge_hostaddr etherStatsUndersizePkts; 2298 bge_hostaddr inRangeLengthError; 2299 bge_hostaddr outRangeLengthError; 2300 bge_hostaddr etherStatsPkts64Octets; 2301 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2302 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2303 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2304 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2305 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2306 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2307 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2308 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2309 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2310}; 2311 2312 2313/* Statistics maintained MAC Transmit block. / 2314struct bge_tx_mac_stats { 2315* bge_hostaddr ifHCOutOctets; 2316 bge_hostaddr Reserved2; 2317 bge_hostaddr etherStatsCollisions; 2318 bge_hostaddr outXonSent; 2319 bge_hostaddr outXoffSent; 2320 bge_hostaddr flowControlDone; 2321 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2322 bge_hostaddr dot3StatsSingleCollisionFrames; 2323 bge_hostaddr dot3StatsMultipleCollisionFrames; 2324 bge_hostaddr dot3StatsDeferredTransmissions; 2325 bge_hostaddr Reserved3; 2326 bge_hostaddr dot3StatsExcessiveCollisions; 2327 bge_hostaddr dot3StatsLateCollisions; 2328 bge_hostaddr dot3Collided2Times; 2329 bge_hostaddr dot3Collided3Times; 2330 bge_hostaddr dot3Collided4Times; 2331 bge_hostaddr dot3Collided5Times; 2332 bge_hostaddr dot3Collided6Times; 2333 bge_hostaddr dot3Collided7Times; 2334 bge_hostaddr dot3Collided8Times; 2335 bge_hostaddr dot3Collided9Times; 2336 bge_hostaddr dot3Collided10Times; 2337 bge_hostaddr dot3Collided11Times; 2338 bge_hostaddr dot3Collided12Times; 2339 bge_hostaddr dot3Collided13Times; 2340 bge_hostaddr dot3Collided14Times; 2341 bge_hostaddr dot3Collided15Times; 2342 bge_hostaddr ifHCOutUcastPkts; 2343 bge_hostaddr ifHCOutMulticastPkts; 2344 bge_hostaddr ifHCOutBroadcastPkts; 2345 bge_hostaddr dot3StatsCarrierSenseErrors; 2346 bge_hostaddr ifOutDiscards; 2347 bge_hostaddr ifOutErrors; 2348}; 2349 2350/* Stats counters access through registers / 2351struct bge_mac_stats_regs { 2352* uint32_t ifHCOutOctets; 2353 uint32_t Reserved0; 2354 uint32_t etherStatsCollisions; 2355 uint32_t outXonSent; 2356 uint32_t outXoffSent; 2357 uint32_t Reserved1; 2358 uint32_t dot3StatsInternalMacTransmitErrors; 2359 uint32_t dot3StatsSingleCollisionFrames; 2360 uint32_t dot3StatsMultipleCollisionFrames; 2361 uint32_t dot3StatsDeferredTransmissions; 2362 uint32_t Reserved2; 2363 uint32_t dot3StatsExcessiveCollisions; 2364 uint32_t dot3StatsLateCollisions; 2365 uint32_t Reserved3[14]; 2366 uint32_t ifHCOutUcastPkts; 2367 uint32_t ifHCOutMulticastPkts; 2368 uint32_t ifHCOutBroadcastPkts; 2369 uint32_t Reserved4[2]; 2370 uint32_t ifHCInOctets; 2371 uint32_t Reserved5; 2372 uint32_t etherStatsFragments; 2373 uint32_t ifHCInUcastPkts; 2374 uint32_t ifHCInMulticastPkts; 2375 uint32_t ifHCInBroadcastPkts; 2376 uint32_t dot3StatsFCSErrors; 2377 uint32_t dot3StatsAlignmentErrors; 2378 uint32_t xonPauseFramesReceived; 2379 uint32_t xoffPauseFramesReceived; 2380 uint32_t macControlFramesReceived; 2381 uint32_t xoffStateEntered; 2382 uint32_t dot3StatsFramesTooLong; 2383 uint32_t etherStatsJabbers; 2384 uint32_t etherStatsUndersizePkts; 2385}; 2386 2387struct bge_stats { 2388 uint8_t Reserved0[256]; 2389 2390 /* Statistics maintained by Receive MAC. / 2391* struct bge_rx_mac_stats rxstats; 2392 2393 bge_hostaddr Unused1[37]; 2394 2395 /* Statistics maintained by Transmit MAC. / 2396* struct bge_tx_mac_stats txstats; 2397 2398 bge_hostaddr Unused2[31]; 2399 2400 /* Statistics maintained by Receive List Placement. / 2401* bge_hostaddr COSIfHCInPkts[16]; 2402 bge_hostaddr COSFramesDroppedDueToFilters; 2403 bge_hostaddr nicDmaWriteQueueFull; 2404 bge_hostaddr nicDmaWriteHighPriQueueFull; 2405 bge_hostaddr nicNoMoreRxBDs; 2406 bge_hostaddr ifInDiscards; 2407 bge_hostaddr ifInErrors; 2408 bge_hostaddr nicRecvThresholdHit; 2409 2410 bge_hostaddr Unused3[9]; 2411 2412 /* Statistics maintained by Send Data Initiator. / 2413* bge_hostaddr COSIfHCOutPkts[16]; 2414 bge_hostaddr nicDmaReadQueueFull; 2415 bge_hostaddr nicDmaReadHighPriQueueFull; 2416 bge_hostaddr nicSendDataCompQueueFull; 2417 2418 /* Statistics maintained by Host Coalescing. / 2419* bge_hostaddr nicRingSetSendProdIndex; 2420 bge_hostaddr nicRingStatusUpdate; 2421 bge_hostaddr nicInterrupts; 2422 bge_hostaddr nicAvoidedInterrupts; 2423 bge_hostaddr nicSendThresholdHit; 2424 2425 uint8_t Reserved4[320]; 2426}; 2427 2428/* 2429 * Tigon general information block. This resides in host memory 2430 * and contains the status counters, ring control blocks and 2431 * producer pointers. 2432 / 2433* 2434struct bge_gib { 2435 struct bge_stats bge_stats; 2436 struct bge_rcb bge_tx_rcb[16]; 2437 struct bge_rcb bge_std_rx_rcb; 2438 struct bge_rcb bge_jumbo_rx_rcb; 2439 struct bge_rcb bge_mini_rx_rcb; 2440 struct bge_rcb bge_return_rcb; 2441}; 2442 2443#define BGE_FRAMELEN 1518 2444#define BGE_MAX_FRAMELEN 1536 2445#define BGE_JUMBO_FRAMELEN 9018 2446#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2447#define BGE_MIN_FRAMELEN 60 2448 2449/* 2450 * Other utility macros. 2451 / 2452#define BGE_INC(x, y) (x) = (x + 1) % y 2453* 2454/* 2455 * Register access macros. The Tigon always uses memory mapped register 2456 * accesses and all registers must be accessed with 32 bit operations. 2457 / 2458* 2459#define CSR_WRITE_4(sc, reg, val) \ 2460 bus_write_4(sc->bge_res, reg, val) 2461 2462#define CSR_READ_4(sc, reg) \ 2463 bus_read_4(sc->bge_res, reg) 2464 2465#define BGE_SETBIT(sc, reg, x) \ 2466 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2467#define BGE_CLRBIT(sc, reg, x) \ 2468 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2469 2470#define PCI_SETBIT(dev, reg, x, s) \ 2471 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2472#define PCI_CLRBIT(dev, reg, x, s) \ 2473 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2474 2475/* 2476 * Memory management stuff. 2477 / 2478* 2479#define BGE_NSEG_JUMBO 4 2480#define BGE_NSEG_NEW 32 2481#define BGE_TSOSEG_SZ 4096 2482 2483/* Maximum DMA address for controllers that have 40bit DMA address bug. / 2484#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2485#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2486#else 2487#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2488#endif 2489* 2490/* 2491 * Ring structures. Most of these reside in host memory and we tell 2492 * the NIC where they are via the ring control blocks. The exceptions 2493 * are the tx and command rings, which live in NIC memory and which 2494 * we access via the shared memory window. 2495 / 2496* 2497struct bge_ring_data { 2498 struct bge_rx_bd bge_rx_std_ring; 2499* bus_addr_t bge_rx_std_ring_paddr; 2500 struct bge_extrx_bd bge_rx_jumbo_ring; 2501* bus_addr_t bge_rx_jumbo_ring_paddr; 2502 struct bge_rx_bd bge_rx_return_ring; 2503* bus_addr_t bge_rx_return_ring_paddr; 2504 struct bge_tx_bd bge_tx_ring; 2505* bus_addr_t bge_tx_ring_paddr; 2506 struct bge_status_block bge_status_block; 2507* bus_addr_t bge_status_block_paddr; 2508 struct bge_stats bge_stats; 2509* bus_addr_t bge_stats_paddr; 2510 struct bge_gib bge_info; 2511}; 2512 2513#define BGE_STD_RX_RING_SZ \ 2514 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2515#define BGE_JUMBO_RX_RING_SZ \ 2516 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2517#define BGE_TX_RING_SZ \ 2518 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2519#define BGE_RX_RTN_RING_SZ(x) \ 2520 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2521 2522#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2523 2524#define BGE_STATS_SZ sizeof (struct bge_stats) 2525 2526/* 2527 * Mbuf pointers. We need these to keep track of the virtual addresses 2528 * of our mbuf chains since we can only convert from physical to virtual, 2529 * not the other way around. 2530 / 2531struct bge_chain_data { 2532* bus_dma_tag_t bge_parent_tag; 2533 bus_dma_tag_t bge_rx_std_ring_tag; 2534 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2535 bus_dma_tag_t bge_rx_return_ring_tag; 2536 bus_dma_tag_t bge_tx_ring_tag; 2537 bus_dma_tag_t bge_status_tag; 2538 bus_dma_tag_t bge_stats_tag; 2539 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag / 2540* bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag / 2541* bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag / 2542* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2543 bus_dmamap_t bge_rx_std_sparemap; 2544 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2545 bus_dmamap_t bge_rx_jumbo_sparemap; 2546 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2547 bus_dmamap_t bge_rx_std_ring_map; 2548 bus_dmamap_t bge_rx_jumbo_ring_map; 2549 bus_dmamap_t bge_tx_ring_map; 2550 bus_dmamap_t bge_rx_return_ring_map; 2551 bus_dmamap_t bge_status_map; 2552 bus_dmamap_t bge_stats_map; 2553 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2554* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2555* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2556* int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2557 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2558}; 2559 2560struct bge_dmamap_arg { 2561 struct bge_softc sc; 2562* bus_addr_t bge_busaddr; 2563 uint16_t bge_flags; 2564 int bge_idx; 2565 int bge_maxsegs; 2566 struct bge_tx_bd bge_ring; 2567}; 2568* 2569#define BGE_HWREV_TIGON 0x01 2570#define BGE_HWREV_TIGON_II 0x02 2571#define BGE_TIMEOUT 100000 2572#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2573* 2574struct bge_bcom_hack { 2575 int reg; 2576 int val; 2577}; 2578 2579#define ASF_ENABLE 1 2580#define ASF_NEW_HANDSHAKE 2 2581#define ASF_STACKUP 4 2582 2583struct bge_softc { 2584 struct ifnet bge_ifp; / interface info / 2585* device_t bge_dev; 2586 struct mtx bge_mtx; 2587 device_t bge_miibus; 2588 void bge_intrhand; 2589* struct resource bge_irq; 2590* struct resource bge_res; 2591* struct ifmedia bge_ifmedia; /* TBI media info / 2592* int bge_expcap; 2593 int bge_msicap; 2594 int bge_pcixcap; 2595 uint32_t bge_flags; 2596#define BGE_FLAG_TBI 0x00000001 2597#define BGE_FLAG_JUMBO 0x00000002 2598#define BGE_FLAG_WIRESPEED 0x00000004 2599#define BGE_FLAG_EADDR 0x00000008 2600#define BGE_FLAG_MII_SERDES 0x00000010 2601#define BGE_FLAG_MSI 0x00000100 2602#define BGE_FLAG_PCIX 0x00000200 2603#define BGE_FLAG_PCIE 0x00000400 2604#define BGE_FLAG_TSO 0x00000800 2605#define BGE_FLAG_5700_FAMILY 0x00001000 2606#define BGE_FLAG_5705_PLUS 0x00002000 2607#define BGE_FLAG_5714_FAMILY 0x00004000 2608#define BGE_FLAG_575X_PLUS 0x00008000 2609#define BGE_FLAG_5755_PLUS 0x00010000 2610#define BGE_FLAG_40BIT_BUG 0x00020000 2611#define BGE_FLAG_4G_BNDRY_BUG 0x00040000 2612#define BGE_FLAG_RX_ALIGNBUG 0x00100000 2613#define BGE_FLAG_NO_3LED 0x00200000 2614#define BGE_FLAG_ADC_BUG 0x00400000 2615#define BGE_FLAG_5704_A0_BUG 0x00800000 2616#define BGE_FLAG_JITTER_BUG 0x01000000 2617#define BGE_FLAG_BER_BUG 0x02000000 2618#define BGE_FLAG_ADJUST_TRIM 0x04000000 2619#define BGE_FLAG_CRC_BUG 0x08000000 2620#define BGE_FLAG_5788 0x20000000 2621 uint32_t bge_chipid; 2622 uint32_t bge_asicrev; 2623 uint32_t bge_chiprev; 2624 uint8_t bge_asf_mode; 2625 uint8_t bge_asf_count; 2626 struct bge_ring_data bge_ldata; /* rings / 2627* struct bge_chain_data bge_cdata; /* mbufs / 2628* uint16_t bge_tx_saved_considx; 2629 uint16_t bge_rx_saved_considx; 2630 uint16_t bge_ev_saved_considx; 2631 uint16_t bge_return_ring_cnt; 2632 uint16_t bge_std; /* current std ring head / 2633* uint16_t bge_jumbo; /* current jumo ring head / 2634* uint32_t bge_stat_ticks; 2635 uint32_t bge_rx_coal_ticks; 2636 uint32_t bge_tx_coal_ticks; 2637 uint32_t bge_tx_prodidx; 2638 uint32_t bge_rx_max_coal_bds; 2639 uint32_t bge_tx_max_coal_bds; 2640 uint32_t bge_tx_buf_ratio; 2641 int bge_if_flags; 2642 int bge_txcnt; 2643 int bge_link; /* link state / 2644* int bge_link_evt; /* pending link event / 2645* int bge_timer; 2646 int bge_forced_collapse;
	2647 int bge_forced_udpcsum; 2648 int bge_csum_features;
2647 struct callout bge_stat_ch; 2648 uint32_t bge_rx_discards; 2649 uint32_t bge_tx_discards; 2650 uint32_t bge_tx_collisions; 2651#ifdef DEVICE_POLLING 2652 int rxcycles; 2653#endif /* DEVICE_POLLING / 2654* struct task bge_intr_task; 2655 struct taskqueue bge_tq; 2656}; 2657* 2658#define BGE_LOCK_INIT(_sc, _name) \ 2659 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2660#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2661#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2662#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2663#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)	2649 struct callout bge_stat_ch; 2650 uint32_t bge_rx_discards; 2651 uint32_t bge_tx_discards; 2652 uint32_t bge_tx_collisions; 2653#ifdef DEVICE_POLLING 2654 int rxcycles; 2655#endif /* DEVICE_POLLING / 2656* struct task bge_intr_task; 2657 struct taskqueue bge_tq; 2658}; 2659* 2660#define BGE_LOCK_INIT(_sc, _name) \ 2661 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2662#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2663#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2664#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2665#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)