| if_bge.c (169878) | if_bge.c (169880) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 18 unchanged lines hidden (view full) --- 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 18 unchanged lines hidden (view full) --- 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> |
| 35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 169878 2007-05-22 19:11:39Z jkim $"); | 35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 169880 2007-05-22 19:22:58Z jkim $"); |
| 36 37/* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external --- 1131 unchanged lines hidden (view full) --- 1175 for (i = BGE_STATS_BLOCK; 1176 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1177 BGE_MEMWIN_WRITE(sc, i, 0); 1178 1179 for (i = BGE_STATUS_BLOCK; 1180 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1181 BGE_MEMWIN_WRITE(sc, i, 0); 1182 | 36 37/* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external --- 1131 unchanged lines hidden (view full) --- 1175 for (i = BGE_STATS_BLOCK; 1176 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1177 BGE_MEMWIN_WRITE(sc, i, 0); 1178 1179 for (i = BGE_STATUS_BLOCK; 1180 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1181 BGE_MEMWIN_WRITE(sc, i, 0); 1182 |
| 1183 /* Set up the PCI DMA control register. */ | 1183 /* 1184 * Set up the PCI DMA control register. 1185 */ 1186 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1187 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); |
| 1184 if (sc->bge_flags & BGE_FLAG_PCIE) { | 1188 if (sc->bge_flags & BGE_FLAG_PCIE) { |
| 1185 /* PCI Express bus */ 1186 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1187 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) | 1188 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2); | 1189 /* Read watermark not used, 128 bytes for write. */ 1190 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); |
| 1189 } else if (sc->bge_flags & BGE_FLAG_PCIX) { | 1191 } else if (sc->bge_flags & BGE_FLAG_PCIX) { |
| 1190 /* PCI-X bus */ | |
| 1191 if (BGE_IS_5714_FAMILY(sc)) { | 1192 if (BGE_IS_5714_FAMILY(sc)) { |
| 1192 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1193 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1194 /* XXX magic values, Broadcom-supplied Linux driver */ 1195 dma_rw_ctl |= (1 << 20) | (1 << 18); 1196 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) 1197 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1198 else 1199 dma_rw_ctl |= 1 << 15; 1200 1201 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1202 /* 1203 * The 5704 uses a different encoding of read/write 1204 * watermarks. 1205 */ 1206 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1207 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | 1208 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3); 1209 else 1210 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1211 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) | 1212 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) | | 1193 /* 256 bytes for read and write. */ 1194 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1195 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1196 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1197 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1198 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1199 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1200 /* 1536 bytes for read, 384 bytes for write. */ 1201 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1202 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1203 } else { 1204 /* 384 bytes for read and write. */ 1205 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1206 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | |
| 1213 0x0F; | 1207 0x0F; |
| 1214 1215 /* 1216 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1217 * for hardware bugs. 1218 */ | 1208 } |
| 1219 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1220 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1221 uint32_t tmp; 1222 | 1209 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1210 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1211 uint32_t tmp; 1212 |
| 1213 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ |
|
| 1223 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; | 1214 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; |
| 1224 if (tmp == 0x6 || tmp == 0x7) 1225 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; | 1215 if (tmp == 6 || tmp == 7) 1216 dma_rw_ctl |= 1217 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1218 1219 /* Set PCI-X DMA write workaround. */ 1220 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; |
| 1226 } | 1221 } |
| 1227 } else 1228 /* Conventional PCI bus */ 1229 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1230 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | 1231 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) | 1232 0x0F; | 1222 } else { 1223 /* Conventional PCI bus: 256 bytes for read and write. */ 1224 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1225 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); |
| 1233 | 1226 |
| 1227 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1228 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1229 dma_rw_ctl |= 0x0F; 1230 } 1231 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1232 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1233 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1234 BGE_PCIDMARWCTL_ASRT_ALL_BE; |
|
| 1234 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || | 1235 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || |
| 1235 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1236 sc->bge_asicrev == BGE_ASICREV_BCM5705) | 1236 sc->bge_asicrev == BGE_ASICREV_BCM5704) |
| 1237 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1238 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1239 1240 /* 1241 * Set up general mode register. 1242 */ 1243 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1244 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | --- 3258 unchanged lines hidden --- | 1237 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1238 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1239 1240 /* 1241 * Set up general mode register. 1242 */ 1243 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1244 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | --- 3258 unchanged lines hidden --- |