35c35
< __FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 169878 2007-05-22 19:11:39Z jkim $");
---
> __FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 169880 2007-05-22 19:22:58Z jkim $");
1183c1183,1187
< /* Set up the PCI DMA control register. */
---
> /*
> * Set up the PCI DMA control register.
> */
> dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
> BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1185,1188c1189,1190
< /* PCI Express bus */
< dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
< BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) |
< BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2);
---
> /* Read watermark not used, 128 bytes for write. */
> dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1190d1191
< /* PCI-X bus */
1192,1212c1193,1206
< dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
< dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
< /* XXX magic values, Broadcom-supplied Linux driver */
< dma_rw_ctl |= (1 << 20) | (1 << 18);
< if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
< dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
< else
< dma_rw_ctl |= 1 << 15;
<
< } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
< /*
< * The 5704 uses a different encoding of read/write
< * watermarks.
< */
< dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
< BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
< BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3);
< else
< dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
< BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) |
< BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) |
---
> /* 256 bytes for read and write. */
> dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
> BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
> dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
> BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
> BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
> } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
> /* 1536 bytes for read, 384 bytes for write. */
> dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
> BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
> } else {
> /* 384 bytes for read and write. */
> dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
> BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1214,1218c1208
<
< /*
< * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
< * for hardware bugs.
< */
---
> }
1222a1213
> /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1224,1225c1215,1220
< if (tmp == 0x6 || tmp == 0x7)
< dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
---
> if (tmp == 6 || tmp == 7)
> dma_rw_ctl |=
> BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
>
> /* Set PCI-X DMA write workaround. */
> dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1227,1232c1222,1225
< } else
< /* Conventional PCI bus */
< dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
< BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
< BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) |
< 0x0F;
---
> } else {
> /* Conventional PCI bus: 256 bytes for read and write. */
> dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
> BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1233a1227,1234
> if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
> sc->bge_asicrev != BGE_ASICREV_BCM5750)
> dma_rw_ctl |= 0x0F;
> }
> if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
> sc->bge_asicrev == BGE_ASICREV_BCM5701)
> dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
> BGE_PCIDMARWCTL_ASRT_ALL_BE;
1235,1236c1236
< sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
< sc->bge_asicrev == BGE_ASICREV_BCM5705)
---
> sc->bge_asicrev == BGE_ASICREV_BCM5704)