1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
--- 18 unchanged lines hidden (view full) ---
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 226867 2011-10-27 22:10:52Z yongari $");
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
--- 252 unchanged lines hidden (view full) ---
296 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
297 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
298 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
299 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
300 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
301 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
302 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
303 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
304 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
305 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
306 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
307 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
308 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
309 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
310 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
311 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
--- 32 unchanged lines hidden (view full) ---
344 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
345 /* 5754 and 5787 share the same ASIC ID */
346 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
347 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
348 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
349 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
350 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
351 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
352
353 { 0, NULL }
354};
355
356#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
357#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
358#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
359#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
--- 72 unchanged lines hidden (view full) ---
432static void bge_free_rx_ring_std(struct bge_softc *);
433static int bge_init_rx_ring_jumbo(struct bge_softc *);
434static void bge_free_rx_ring_jumbo(struct bge_softc *);
435static void bge_free_tx_ring(struct bge_softc *);
436static int bge_init_tx_ring(struct bge_softc *);
437
438static int bge_chipinit(struct bge_softc *);
439static int bge_blockinit(struct bge_softc *);
440
441static int bge_has_eaddr(struct bge_softc *);
442static uint32_t bge_readmem_ind(struct bge_softc *, int);
443static void bge_writemem_ind(struct bge_softc *, int, int);
444static void bge_writembx(struct bge_softc *, int, int);
445#ifdef notdef
446static uint32_t bge_readreg_ind(struct bge_softc *, int);
447#endif
--- 928 unchanged lines hidden (view full) ---
1376 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1377 BGE_RX_CPU_DRV_EVENT))
1378 break;
1379 DELAY(10);
1380 }
1381 }
1382}
1383
1384/*
1385 * Do endian, PCI and DMA initialization.
1386 */
1387static int
1388bge_chipinit(struct bge_softc *sc)
1389{
1390 uint32_t dma_rw_ctl, misc_ctl;
1391 uint16_t val;
1392 int i;
1393
1394 /* Set endianness before we access any non-PCI registers. */
1395 misc_ctl = BGE_INIT;
1396 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1397 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1398 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
--- 101 unchanged lines hidden (view full) ---
1500 sc->bge_asicrev != BGE_ASICREV_BCM57765)
1501 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1502 }
1503 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1504
1505 /*
1506 * Set up general mode register.
1507 */
1508 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1509 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1510 BGE_MODECTL_TX_NO_PHDR_CSUM);
1511
1512 /*
1513 * BCM5701 B5 have a bug causing data corruption when using
1514 * 64-bit DMA reads, which can be terminated early and then
1515 * completed later as 32-bit accesses, in combination with
1516 * certain bridges.
1517 */
1518 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1519 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1520 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1521
1522 /*
1523 * Tell the firmware the driver is running
1524 */
1525 if (sc->bge_asf_mode & ASF_STACKUP)
1526 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1527
1528 /*
1529 * Disable memory write invalidate. Apparently it is not supported
1530 * properly by these devices. Also ensure that INTx isn't disabled,
1531 * as these chips need it even when using MSI.
1532 */
1533 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1534 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1535
--- 42 unchanged lines hidden (view full) ---
1578
1579 /* Configure DMA resource pool */
1580 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1581 BGE_DMA_DESCRIPTORS);
1582 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1583 }
1584
1585 /* Configure mbuf pool watermarks */
1586 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1587 sc->bge_asicrev == BGE_ASICREV_BCM57765) {
1588 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1589 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1590 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1591 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1592 } else {
1593 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1594 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1595 }
--- 118 unchanged lines hidden (view full) ---
1714 * Bits 15-2 : Reserved (should be 0)
1715 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1716 * Bit 0 : Reserved
1717 */
1718 rcb->bge_maxlen_flags =
1719 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1720 }
1721 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1722 sc->bge_asicrev == BGE_ASICREV_BCM5719)
1723 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1724 else
1725 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1726 /* Write the standard receive producer ring control block. */
1727 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1728 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1729 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1730 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
--- 16 unchanged lines hidden (view full) ---
1747 rcb->bge_hostaddr.bge_addr_hi =
1748 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1749 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1750 sc->bge_cdata.bge_rx_jumbo_ring_map,
1751 BUS_DMASYNC_PREREAD);
1752 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1753 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1754 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1755 sc->bge_asicrev == BGE_ASICREV_BCM5719)
1756 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1757 else
1758 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1759 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1760 rcb->bge_hostaddr.bge_addr_hi);
1761 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1762 rcb->bge_hostaddr.bge_addr_lo);
1763 /* Program the jumbo receive producer ring RCB parameters. */
--- 72 unchanged lines hidden (view full) ---
1836 }
1837
1838 /* Configure send ring RCB 0 (we use only the first ring) */
1839 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1840 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1841 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1842 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1843 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1844 sc->bge_asicrev == BGE_ASICREV_BCM5719)
1845 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1846 else
1847 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1848 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1849 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1850 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1851
1852 /*
1853 * Disable all receive return rings by setting the
1854 * 'ring diabled' bit in the flags field of all the receive
1855 * return ring control blocks, located in NIC memory.
1856 */
1857 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1858 sc->bge_asicrev == BGE_ASICREV_BCM5719) {
1859 /* Should be 17, use 16 until we get an SRAM map. */
1860 limit = 16;
1861 } else if (!BGE_IS_5705_PLUS(sc))
1862 limit = BGE_RX_RINGS_MAX;
1863 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1864 sc->bge_asicrev == BGE_ASICREV_BCM57765)
1865 limit = 4;
1866 else
--- 27 unchanged lines hidden (view full) ---
1894 /* Set random backoff seed for TX */
1895 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1896 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1897 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1898 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1899 BGE_TX_BACKOFF_SEED_MASK);
1900
1901 /* Set inter-packet gap */
1902 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1903
1904 /*
1905 * Specify which ring to use for packets that don't match
1906 * any RX rules.
1907 */
1908 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1909
1910 /*
--- 138 unchanged lines hidden (view full) ---
2049 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2050 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2051 val |= BGE_RDMAMODE_TSO4_ENABLE;
2052 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2053 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2054 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2055 val |= BGE_RDMAMODE_TSO6_ENABLE;
2056 }
2057 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2058 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2059 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2060 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2061 BGE_IS_5717_PLUS(sc)) {
2062 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
2063 /*
2064 * Adjust tx margin to prevent TX data corruption and
2065 * fix internal FIFO overflow.
2066 */
2067 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2068 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2069 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2070 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2071 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2072 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2073 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2074 }
2075 /*
2076 * Enable fix for read DMA FIFO overruns.
2077 * The fix is to limit the number of RX BDs
2078 * the hardware would fetch at a fime.
2079 */
2080 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
2081 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2082 }
2083
2084 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2085 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2086 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2087 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2088 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2089 }
2090
2091 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2092 DELAY(40);
--- 142 unchanged lines hidden (view full) ---
2235 /*
2236 * Find the ASCI revision. Different chips
2237 * use different registers.
2238 */
2239 switch (pci_get_device(dev)) {
2240 case BCOM_DEVICEID_BCM5717:
2241 case BCOM_DEVICEID_BCM5718:
2242 case BCOM_DEVICEID_BCM5719:
2243 id = pci_read_config(dev,
2244 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2245 break;
2246 case BCOM_DEVICEID_BCM57761:
2247 case BCOM_DEVICEID_BCM57765:
2248 case BCOM_DEVICEID_BCM57781:
2249 case BCOM_DEVICEID_BCM57785:
2250 case BCOM_DEVICEID_BCM57791:
--- 508 unchanged lines hidden (view full) ---
2759 /*
2760 * Find the ASCI revision. Different chips use different
2761 * registers.
2762 */
2763 switch (pci_get_device(dev)) {
2764 case BCOM_DEVICEID_BCM5717:
2765 case BCOM_DEVICEID_BCM5718:
2766 case BCOM_DEVICEID_BCM5719:
2767 sc->bge_chipid = pci_read_config(dev,
2768 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2769 break;
2770 case BCOM_DEVICEID_BCM57761:
2771 case BCOM_DEVICEID_BCM57765:
2772 case BCOM_DEVICEID_BCM57781:
2773 case BCOM_DEVICEID_BCM57785:
2774 case BCOM_DEVICEID_BCM57791:
--- 15 unchanged lines hidden (view full) ---
2790 * PHY address mapping for various devices.
2791 *
2792 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2793 * ---------+-------+-------+-------+-------+
2794 * BCM57XX | 1 | X | X | X |
2795 * BCM5704 | 1 | X | 1 | X |
2796 * BCM5717 | 1 | 8 | 2 | 9 |
2797 * BCM5719 | 1 | 8 | 2 | 9 |
2798 *
2799 * Other addresses may respond but they are not
2800 * IEEE compliant PHYs and should be ignored.
2801 */
2802 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2803 sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2804 f = pci_get_function(dev);
2805 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2806 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2807 BGE_SGDIGSTS_IS_SERDES)
2808 phy_addr = f + 8;
2809 else
2810 phy_addr = f + 1;
2811 } else {
--- 18 unchanged lines hidden (view full) ---
2830
2831 if (bge_has_eaddr(sc))
2832 sc->bge_flags |= BGE_FLAG_EADDR;
2833
2834 /* Save chipset family. */
2835 switch (sc->bge_asicrev) {
2836 case BGE_ASICREV_BCM5717:
2837 case BGE_ASICREV_BCM5719:
2838 case BGE_ASICREV_BCM57765:
2839 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
2840 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
2841 BGE_FLAG_JUMBO_FRAME;
2842 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2843 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2844 /* Jumbo frame on BCM5719 A0 does not work. */
2845 sc->bge_flags &= ~BGE_FLAG_JUMBO;
--- 39 unchanged lines hidden (view full) ---
2885 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2886 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2887 if (pci_get_subvendor(dev) == DELL_VENDORID)
2888 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2889 if ((BGE_IS_5705_PLUS(sc)) &&
2890 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2891 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
2892 sc->bge_asicrev != BGE_ASICREV_BCM5719 &&
2893 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2894 sc->bge_asicrev != BGE_ASICREV_BCM57765 &&
2895 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2896 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2897 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2898 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2899 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2900 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
--- 104 unchanged lines hidden (view full) ---
3005 */
3006 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3007 /*
3008 * Found a PCI Express capabilities register, this
3009 * must be a PCI Express device.
3010 */
3011 sc->bge_flags |= BGE_FLAG_PCIE;
3012 sc->bge_expcap = reg;
3013 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3014 pci_set_max_read_req(dev, 2048);
3015 else if (pci_get_max_read_req(dev) != 4096)
3016 pci_set_max_read_req(dev, 4096);
3017 } else {
3018 /*
3019 * Check if the device is in PCI-X Mode.
3020 * (This bit is not valid on PCI Express controllers.)
3021 */
--- 569 unchanged lines hidden (view full) ---
3591 */
3592 for (i = 0; i < BGE_TIMEOUT; i++) {
3593 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3594 break;
3595 DELAY(10);
3596 }
3597
3598 /* Fix up byte swapping. */
3599 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3600 BGE_MODECTL_BYTESWAP_DATA);
3601
3602 /* Tell the ASF firmware we are up */
3603 if (sc->bge_asf_mode & ASF_STACKUP)
3604 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3605
3606 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3607
3608 /*
--- 14 unchanged lines hidden (view full) ---
3623 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3624 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3625 /* Enable Data FIFO protection. */
3626 val = CSR_READ_4(sc, 0x7C00);
3627 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3628 }
3629 DELAY(10000);
3630
3631 return (0);
3632}
3633
3634static __inline void
3635bge_rxreuse_std(struct bge_softc *sc, int i)
3636{
3637 struct bge_rx_bd *r;
3638
--- 1198 unchanged lines hidden (view full) ---
4837
4838 /* Init TX ring. */
4839 bge_init_tx_ring(sc);
4840
4841 /* Enable TX MAC state machine lockup fix. */
4842 mode = CSR_READ_4(sc, BGE_TX_MODE);
4843 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
4844 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
4845 /* Turn on transmitter. */
4846 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
4847
4848 /* Turn on receiver. */
4849 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4850
4851 /*
4852 * Set the number of good frames to receive after RX MBUF
--- 1153 unchanged lines hidden ---
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
--- 18 unchanged lines hidden (view full) ---
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 226867 2011-10-27 22:10:52Z yongari $");
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
--- 252 unchanged lines hidden (view full) ---
296 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
297 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
298 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
299 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
300 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
301 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
302 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
303 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
304 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
305 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
306 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
307 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
308 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
309 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
310 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
311 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
--- 32 unchanged lines hidden (view full) ---
344 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
345 /* 5754 and 5787 share the same ASIC ID */
346 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
347 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
348 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
349 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
350 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
351 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
352
353 { 0, NULL }
354};
355
356#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
357#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
358#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
359#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
--- 72 unchanged lines hidden (view full) ---
432static void bge_free_rx_ring_std(struct bge_softc *);
433static int bge_init_rx_ring_jumbo(struct bge_softc *);
434static void bge_free_rx_ring_jumbo(struct bge_softc *);
435static void bge_free_tx_ring(struct bge_softc *);
436static int bge_init_tx_ring(struct bge_softc *);
437
438static int bge_chipinit(struct bge_softc *);
439static int bge_blockinit(struct bge_softc *);
440
441static int bge_has_eaddr(struct bge_softc *);
442static uint32_t bge_readmem_ind(struct bge_softc *, int);
443static void bge_writemem_ind(struct bge_softc *, int, int);
444static void bge_writembx(struct bge_softc *, int, int);
445#ifdef notdef
446static uint32_t bge_readreg_ind(struct bge_softc *, int);
447#endif
--- 928 unchanged lines hidden (view full) ---
1376 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1377 BGE_RX_CPU_DRV_EVENT))
1378 break;
1379 DELAY(10);
1380 }
1381 }
1382}
1383
1384/*
1385 * Do endian, PCI and DMA initialization.
1386 */
1387static int
1388bge_chipinit(struct bge_softc *sc)
1389{
1390 uint32_t dma_rw_ctl, misc_ctl;
1391 uint16_t val;
1392 int i;
1393
1394 /* Set endianness before we access any non-PCI registers. */
1395 misc_ctl = BGE_INIT;
1396 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1397 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1398 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
--- 101 unchanged lines hidden (view full) ---
1500 sc->bge_asicrev != BGE_ASICREV_BCM57765)
1501 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1502 }
1503 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1504
1505 /*
1506 * Set up general mode register.
1507 */
1508 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1509 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1510 BGE_MODECTL_TX_NO_PHDR_CSUM);
1511
1512 /*
1513 * BCM5701 B5 have a bug causing data corruption when using
1514 * 64-bit DMA reads, which can be terminated early and then
1515 * completed later as 32-bit accesses, in combination with
1516 * certain bridges.
1517 */
1518 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1519 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1520 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1521
1522 /*
1523 * Tell the firmware the driver is running
1524 */
1525 if (sc->bge_asf_mode & ASF_STACKUP)
1526 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1527
1528 /*
1529 * Disable memory write invalidate. Apparently it is not supported
1530 * properly by these devices. Also ensure that INTx isn't disabled,
1531 * as these chips need it even when using MSI.
1532 */
1533 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1534 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1535
--- 42 unchanged lines hidden (view full) ---
1578
1579 /* Configure DMA resource pool */
1580 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1581 BGE_DMA_DESCRIPTORS);
1582 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1583 }
1584
1585 /* Configure mbuf pool watermarks */
1586 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1587 sc->bge_asicrev == BGE_ASICREV_BCM57765) {
1588 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1589 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1590 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1591 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1592 } else {
1593 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1594 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1595 }
--- 118 unchanged lines hidden (view full) ---
1714 * Bits 15-2 : Reserved (should be 0)
1715 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1716 * Bit 0 : Reserved
1717 */
1718 rcb->bge_maxlen_flags =
1719 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1720 }
1721 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1722 sc->bge_asicrev == BGE_ASICREV_BCM5719)
1723 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1724 else
1725 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1726 /* Write the standard receive producer ring control block. */
1727 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1728 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1729 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1730 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
--- 16 unchanged lines hidden (view full) ---
1747 rcb->bge_hostaddr.bge_addr_hi =
1748 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1749 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1750 sc->bge_cdata.bge_rx_jumbo_ring_map,
1751 BUS_DMASYNC_PREREAD);
1752 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1753 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1754 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1755 sc->bge_asicrev == BGE_ASICREV_BCM5719)
1756 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1757 else
1758 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1759 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1760 rcb->bge_hostaddr.bge_addr_hi);
1761 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1762 rcb->bge_hostaddr.bge_addr_lo);
1763 /* Program the jumbo receive producer ring RCB parameters. */
--- 72 unchanged lines hidden (view full) ---
1836 }
1837
1838 /* Configure send ring RCB 0 (we use only the first ring) */
1839 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1840 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1841 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1842 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1843 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1844 sc->bge_asicrev == BGE_ASICREV_BCM5719)
1845 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1846 else
1847 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1848 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1849 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1850 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1851
1852 /*
1853 * Disable all receive return rings by setting the
1854 * 'ring diabled' bit in the flags field of all the receive
1855 * return ring control blocks, located in NIC memory.
1856 */
1857 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1858 sc->bge_asicrev == BGE_ASICREV_BCM5719) {
1859 /* Should be 17, use 16 until we get an SRAM map. */
1860 limit = 16;
1861 } else if (!BGE_IS_5705_PLUS(sc))
1862 limit = BGE_RX_RINGS_MAX;
1863 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1864 sc->bge_asicrev == BGE_ASICREV_BCM57765)
1865 limit = 4;
1866 else
--- 27 unchanged lines hidden (view full) ---
1894 /* Set random backoff seed for TX */
1895 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1896 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1897 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1898 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1899 BGE_TX_BACKOFF_SEED_MASK);
1900
1901 /* Set inter-packet gap */
1902 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1903
1904 /*
1905 * Specify which ring to use for packets that don't match
1906 * any RX rules.
1907 */
1908 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1909
1910 /*
--- 138 unchanged lines hidden (view full) ---
2049 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2050 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2051 val |= BGE_RDMAMODE_TSO4_ENABLE;
2052 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2053 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2054 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2055 val |= BGE_RDMAMODE_TSO6_ENABLE;
2056 }
2057 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2058 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2059 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2060 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2061 BGE_IS_5717_PLUS(sc)) {
2062 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
2063 /*
2064 * Adjust tx margin to prevent TX data corruption and
2065 * fix internal FIFO overflow.
2066 */
2067 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2068 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2069 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2070 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2071 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2072 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2073 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2074 }
2075 /*
2076 * Enable fix for read DMA FIFO overruns.
2077 * The fix is to limit the number of RX BDs
2078 * the hardware would fetch at a fime.
2079 */
2080 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
2081 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2082 }
2083
2084 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2085 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2086 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2087 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2088 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2089 }
2090
2091 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2092 DELAY(40);
--- 142 unchanged lines hidden (view full) ---
2235 /*
2236 * Find the ASCI revision. Different chips
2237 * use different registers.
2238 */
2239 switch (pci_get_device(dev)) {
2240 case BCOM_DEVICEID_BCM5717:
2241 case BCOM_DEVICEID_BCM5718:
2242 case BCOM_DEVICEID_BCM5719:
2243 id = pci_read_config(dev,
2244 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2245 break;
2246 case BCOM_DEVICEID_BCM57761:
2247 case BCOM_DEVICEID_BCM57765:
2248 case BCOM_DEVICEID_BCM57781:
2249 case BCOM_DEVICEID_BCM57785:
2250 case BCOM_DEVICEID_BCM57791:
--- 508 unchanged lines hidden (view full) ---
2759 /*
2760 * Find the ASCI revision. Different chips use different
2761 * registers.
2762 */
2763 switch (pci_get_device(dev)) {
2764 case BCOM_DEVICEID_BCM5717:
2765 case BCOM_DEVICEID_BCM5718:
2766 case BCOM_DEVICEID_BCM5719:
2767 sc->bge_chipid = pci_read_config(dev,
2768 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2769 break;
2770 case BCOM_DEVICEID_BCM57761:
2771 case BCOM_DEVICEID_BCM57765:
2772 case BCOM_DEVICEID_BCM57781:
2773 case BCOM_DEVICEID_BCM57785:
2774 case BCOM_DEVICEID_BCM57791:
--- 15 unchanged lines hidden (view full) ---
2790 * PHY address mapping for various devices.
2791 *
2792 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2793 * ---------+-------+-------+-------+-------+
2794 * BCM57XX | 1 | X | X | X |
2795 * BCM5704 | 1 | X | 1 | X |
2796 * BCM5717 | 1 | 8 | 2 | 9 |
2797 * BCM5719 | 1 | 8 | 2 | 9 |
2798 *
2799 * Other addresses may respond but they are not
2800 * IEEE compliant PHYs and should be ignored.
2801 */
2802 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2803 sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2804 f = pci_get_function(dev);
2805 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2806 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2807 BGE_SGDIGSTS_IS_SERDES)
2808 phy_addr = f + 8;
2809 else
2810 phy_addr = f + 1;
2811 } else {
--- 18 unchanged lines hidden (view full) ---
2830
2831 if (bge_has_eaddr(sc))
2832 sc->bge_flags |= BGE_FLAG_EADDR;
2833
2834 /* Save chipset family. */
2835 switch (sc->bge_asicrev) {
2836 case BGE_ASICREV_BCM5717:
2837 case BGE_ASICREV_BCM5719:
2838 case BGE_ASICREV_BCM57765:
2839 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
2840 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
2841 BGE_FLAG_JUMBO_FRAME;
2842 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2843 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2844 /* Jumbo frame on BCM5719 A0 does not work. */
2845 sc->bge_flags &= ~BGE_FLAG_JUMBO;
--- 39 unchanged lines hidden (view full) ---
2885 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2886 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2887 if (pci_get_subvendor(dev) == DELL_VENDORID)
2888 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2889 if ((BGE_IS_5705_PLUS(sc)) &&
2890 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2891 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
2892 sc->bge_asicrev != BGE_ASICREV_BCM5719 &&
2893 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2894 sc->bge_asicrev != BGE_ASICREV_BCM57765 &&
2895 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2896 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2897 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2898 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2899 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2900 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
--- 104 unchanged lines hidden (view full) ---
3005 */
3006 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3007 /*
3008 * Found a PCI Express capabilities register, this
3009 * must be a PCI Express device.
3010 */
3011 sc->bge_flags |= BGE_FLAG_PCIE;
3012 sc->bge_expcap = reg;
3013 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3014 pci_set_max_read_req(dev, 2048);
3015 else if (pci_get_max_read_req(dev) != 4096)
3016 pci_set_max_read_req(dev, 4096);
3017 } else {
3018 /*
3019 * Check if the device is in PCI-X Mode.
3020 * (This bit is not valid on PCI Express controllers.)
3021 */
--- 569 unchanged lines hidden (view full) ---
3591 */
3592 for (i = 0; i < BGE_TIMEOUT; i++) {
3593 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3594 break;
3595 DELAY(10);
3596 }
3597
3598 /* Fix up byte swapping. */
3599 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3600 BGE_MODECTL_BYTESWAP_DATA);
3601
3602 /* Tell the ASF firmware we are up */
3603 if (sc->bge_asf_mode & ASF_STACKUP)
3604 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3605
3606 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3607
3608 /*
--- 14 unchanged lines hidden (view full) ---
3623 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3624 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3625 /* Enable Data FIFO protection. */
3626 val = CSR_READ_4(sc, 0x7C00);
3627 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3628 }
3629 DELAY(10000);
3630
3631 return (0);
3632}
3633
3634static __inline void
3635bge_rxreuse_std(struct bge_softc *sc, int i)
3636{
3637 struct bge_rx_bd *r;
3638
--- 1198 unchanged lines hidden (view full) ---
4837
4838 /* Init TX ring. */
4839 bge_init_tx_ring(sc);
4840
4841 /* Enable TX MAC state machine lockup fix. */
4842 mode = CSR_READ_4(sc, BGE_TX_MODE);
4843 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
4844 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
4845 /* Turn on transmitter. */
4846 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
4847
4848 /* Turn on receiver. */
4849 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4850
4851 /*
4852 * Set the number of good frames to receive after RX MBUF
--- 1153 unchanged lines hidden ---