1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 169878 2007-05-22 19:11:39Z jkim $");
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

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1175 for (i = BGE_STATS_BLOCK;
1176 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1177 BGE_MEMWIN_WRITE(sc, i, 0);
1178
1179 for (i = BGE_STATUS_BLOCK;
1180 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1181 BGE_MEMWIN_WRITE(sc, i, 0);
1182
1183 /* Set up the PCI DMA control register. */
1184 if (sc->bge_flags & BGE_FLAG_PCIE) {
1185 /* PCI Express bus */
1186 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1187 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) |
1188 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2);
1189 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1190 /* PCI-X bus */
1191 if (BGE_IS_5714_FAMILY(sc)) {
1192 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
1193 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1194 /* XXX magic values, Broadcom-supplied Linux driver */
1195 dma_rw_ctl |= (1 << 20) | (1 << 18);
1196 if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
1197 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1198 else
1199 dma_rw_ctl |= 1 << 15;
1200
1201 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1202 /*
1203 * The 5704 uses a different encoding of read/write
1204 * watermarks.
1205 */
1206 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1207 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
1208 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3);
1209 else
1210 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1211 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) |
1212 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) |
1213 0x0F;
1214
1215 /*
1216 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1217 * for hardware bugs.
1218 */
1219 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1220 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1221 uint32_t tmp;
1222
1223 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1224 if (tmp == 0x6 || tmp == 0x7)
1225 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1226 }
1227 } else
1228 /* Conventional PCI bus */
1229 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1230 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
1231 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) |
1232 0x0F;
1233
1234 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1235 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1236 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1237 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1238 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1239
1240 /*
1241 * Set up general mode register.
1242 */
1243 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1244 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |

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