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if_athvar.h (140432) if_athvar.h (140438)
1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 *
1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 *
36 * $FreeBSD: head/sys/dev/ath/if_athvar.h 140432 2005-01-18 19:03:04Z sam $
36 * $FreeBSD: head/sys/dev/ath/if_athvar.h 140438 2005-01-18 19:42:17Z sam $
37 */
38
39/*
40 * Defintions for the Atheros Wireless LAN controller driver.
41 */
42#ifndef _DEV_ATH_ATHVAR_H
43#define _DEV_ATH_ATHVAR_H
44
45#include <sys/taskqueue.h>
46
47#include <contrib/dev/ath/ah.h>
48#include <net80211/ieee80211_radiotap.h>
49#include <dev/ath/if_athioctl.h>
50#include <dev/ath/if_athrate.h>
51
52#define ATH_TIMEOUT 1000
53
54#define ATH_RXBUF 40 /* number of RX buffers */
37 */
38
39/*
40 * Defintions for the Atheros Wireless LAN controller driver.
41 */
42#ifndef _DEV_ATH_ATHVAR_H
43#define _DEV_ATH_ATHVAR_H
44
45#include <sys/taskqueue.h>
46
47#include <contrib/dev/ath/ah.h>
48#include <net80211/ieee80211_radiotap.h>
49#include <dev/ath/if_athioctl.h>
50#include <dev/ath/if_athrate.h>
51
52#define ATH_TIMEOUT 1000
53
54#define ATH_RXBUF 40 /* number of RX buffers */
55#define ATH_TXBUF 60 /* number of TX buffers */
56#define ATH_TXDESC 8 /* number of descriptors per buffer */
55#define ATH_TXBUF 100 /* number of TX buffers */
56#define ATH_TXDESC 10 /* number of descriptors per buffer */
57#define ATH_TXMAXTRY 11 /* max number of transmit attempts */
58#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
59
60/* driver-specific node state */
61struct ath_node {
62 struct ieee80211_node an_node; /* base class */
63 u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */
64 u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */
65 u_int32_t an_avgrssi; /* average rssi over all rx frames */
66 HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */
67 /* variable-length rate control state follows */
68};
69#define ATH_NODE(ni) ((struct ath_node *)(ni))
70#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
71
72#define ATH_RSSI_LPF_LEN 10
73#define ATH_RSSI_DUMMY_MARKER 0x127
74#define ATH_EP_MUL(x, mul) ((x) * (mul))
75#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
76#define ATH_LPF_RSSI(x, y, len) \
77 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
78#define ATH_RSSI_LPF(x, y) do { \
79 if ((y) >= -20) \
80 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
81} while (0)
82
83struct ath_buf {
84 STAILQ_ENTRY(ath_buf) bf_list;
85 int bf_nseg;
86 struct ath_desc *bf_desc; /* virtual addr of desc */
87 bus_addr_t bf_daddr; /* physical addr of desc */
88 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
89 struct mbuf *bf_m; /* mbuf for buf */
90 struct ieee80211_node *bf_node; /* pointer to the node */
91 bus_size_t bf_mapsize;
57#define ATH_TXMAXTRY 11 /* max number of transmit attempts */
58#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
59
60/* driver-specific node state */
61struct ath_node {
62 struct ieee80211_node an_node; /* base class */
63 u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */
64 u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */
65 u_int32_t an_avgrssi; /* average rssi over all rx frames */
66 HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */
67 /* variable-length rate control state follows */
68};
69#define ATH_NODE(ni) ((struct ath_node *)(ni))
70#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
71
72#define ATH_RSSI_LPF_LEN 10
73#define ATH_RSSI_DUMMY_MARKER 0x127
74#define ATH_EP_MUL(x, mul) ((x) * (mul))
75#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
76#define ATH_LPF_RSSI(x, y, len) \
77 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
78#define ATH_RSSI_LPF(x, y) do { \
79 if ((y) >= -20) \
80 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
81} while (0)
82
83struct ath_buf {
84 STAILQ_ENTRY(ath_buf) bf_list;
85 int bf_nseg;
86 struct ath_desc *bf_desc; /* virtual addr of desc */
87 bus_addr_t bf_daddr; /* physical addr of desc */
88 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
89 struct mbuf *bf_m; /* mbuf for buf */
90 struct ieee80211_node *bf_node; /* pointer to the node */
91 bus_size_t bf_mapsize;
92#define ATH_MAX_SCATTER 64
92#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
93 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
94};
95typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
96
97/*
98 * DMA state for tx/rx descriptors.
99 */
100struct ath_descdma {
101 const char* dd_name;
102 struct ath_desc *dd_desc; /* descriptors */
103 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
104 bus_addr_t dd_desc_len; /* size of dd_desc */
105 bus_dma_segment_t dd_dseg;
106 bus_dma_tag_t dd_dmat; /* bus DMA tag */
107 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
108 struct ath_buf *dd_bufptr; /* associated buffers */
109};
110
111/*
112 * Data transmit queue state. One of these exists for each
113 * hardware transmit queue. Packets sent to us from above
114 * are assigned to queues based on their priority. Not all
115 * devices support a complete set of hardware transmit queues.
116 * For those devices the array sc_ac2q will map multiple
117 * priorities to fewer hardware queues (typically all to one
118 * hardware queue).
119 */
120struct ath_txq {
121 u_int axq_qnum; /* hardware q number */
122 u_int axq_depth; /* queue depth (stat only) */
123 u_int axq_intrcnt; /* interrupt count */
124 u_int32_t *axq_link; /* link ptr in last TX desc */
125 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
126 struct mtx axq_lock; /* lock on q and link */
127};
128
129#define ATH_TXQ_LOCK_INIT(_sc, _tq) \
130 mtx_init(&(_tq)->axq_lock, \
131 device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF)
132#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
133#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
134#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
135#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
136
137#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
138 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
139 (_tq)->axq_depth++; \
140} while (0)
141#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
142 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
143 (_tq)->axq_depth--; \
144} while (0)
145
146struct ath_softc {
147 struct arpcom sc_arp; /* interface common */
148 struct ath_stats sc_stats; /* interface statistics */
149 struct ieee80211com sc_ic; /* IEEE 802.11 common */
150 int sc_regdomain;
151 int sc_countrycode;
152 int sc_debug;
153 void (*sc_recv_mgmt)(struct ieee80211com *,
154 struct mbuf *,
155 struct ieee80211_node *,
156 int, int, u_int32_t);
157 int (*sc_newstate)(struct ieee80211com *,
158 enum ieee80211_state, int);
159 void (*sc_node_free)(struct ieee80211_node *);
160 device_t sc_dev;
161 bus_space_tag_t sc_st; /* bus space tag */
162 bus_space_handle_t sc_sh; /* bus space handle */
163 bus_dma_tag_t sc_dmat; /* bus DMA tag */
164 struct mtx sc_mtx; /* master lock (recursive) */
165 struct ath_hal *sc_ah; /* Atheros HAL */
166 struct ath_ratectrl *sc_rc; /* tx rate control support */
167 void (*sc_setdefantenna)(struct ath_softc *, u_int);
168 unsigned int sc_invalid : 1,/* disable hardware accesses */
169 sc_mrretry : 1, /* multi-rate retry support */
170 sc_softled : 1, /* enable LED gpio status */
171 sc_splitmic: 1, /* split TKIP MIC keys */
172 sc_needmib : 1, /* enable MIB stats intr */
173 sc_hasdiversity : 1,/* rx diversity available */
174 sc_diversity : 1,/* enable rx diversity */
175 sc_hasveol : 1, /* tx VEOL support */
176 sc_hastpc : 1, /* per-packet TPC support */
177 sc_ledstate: 1, /* LED on/off state */
178 sc_blinking: 1; /* LED blink operation active */
179 /* rate tables */
180 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
181 const HAL_RATE_TABLE *sc_currates; /* current rate table */
182 enum ieee80211_phymode sc_curmode; /* current phy mode */
183 u_int16_t sc_curtxpow; /* current tx power limit */
184 HAL_CHANNEL sc_curchan; /* current h/w channel */
185 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
186 struct {
187 u_int8_t ieeerate; /* IEEE rate */
188 u_int8_t flags; /* radiotap flags */
189 u_int16_t ledon; /* softled on time */
190 u_int16_t ledoff; /* softled off time */
191 } sc_hwmap[32]; /* h/w rate ix mappings */
192 u_int8_t sc_protrix; /* protection rate index */
193 u_int sc_txantenna; /* tx antenna (fixed or auto) */
194 HAL_INT sc_imask; /* interrupt mask copy */
195 u_int sc_keymax; /* size of key cache */
196 u_int8_t sc_keymap[16]; /* bit map of key cache use */
197
198 u_int sc_ledpin; /* GPIO pin for driving LED */
199 u_int sc_ledon; /* pin setting for LED on */
200 u_int sc_ledidle; /* idle polling interval */
201 u_int32_t sc_ipackets; /* last data packet count */
202 int sc_ledevent; /* time of last LED event */
203 u_int8_t sc_rxrate; /* current rx rate for LED */
204 u_int8_t sc_txrate; /* current tx rate for LED */
205 u_int16_t sc_ledoff; /* off time for current blink */
206 struct callout sc_ledtimer; /* led off timer */
207
208 struct bpf_if *sc_drvbpf;
209 union {
210 struct ath_tx_radiotap_header th;
211 u_int8_t pad[64];
212 } u_tx_rt;
213 int sc_tx_th_len;
214 union {
215 struct {
216 struct ath_rx_radiotap_header th;
217 struct ieee80211_qosframe wh;
218 } u;
219 u_int8_t pad[64];
220 } u_rx_rt;
221 int sc_rx_rt_len;
222
223 struct task sc_fataltask; /* fatal int processing */
224
225 struct ath_descdma sc_rxdma; /* RX descriptos */
226 ath_bufhead sc_rxbuf; /* receive buffer */
227 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
228 struct task sc_rxtask; /* rx int processing */
229 struct task sc_rxorntask; /* rxorn int processing */
230 u_int8_t sc_defant; /* current default antenna */
231 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
232
233 struct ath_descdma sc_txdma; /* TX descriptors */
234 ath_bufhead sc_txbuf; /* transmit buffer */
235 struct mtx sc_txbuflock; /* txbuf lock */
236 int sc_tx_timer; /* transmit timeout */
237 u_int sc_txqsetup; /* h/w queues setup */
238 u_int sc_txintrperiod;/* tx interrupt batching */
239 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
240 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
241 struct task sc_txtask; /* tx int processing */
242
243 struct ath_descdma sc_bdma; /* beacon descriptors */
244 ath_bufhead sc_bbuf; /* beacon buffers */
245 u_int sc_bhalq; /* HAL q for outgoing beacons */
246 u_int sc_bmisscount; /* missed beacon transmits */
247 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
248 struct ath_txq *sc_cabq; /* tx q for cab frames */
249 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
250 struct task sc_bmisstask; /* bmiss int processing */
251 struct task sc_bstucktask; /* stuck beacon processing */
252 enum {
253 OK, /* no change needed */
254 UPDATE, /* update pending */
255 COMMIT /* beacon sent, commit change */
256 } sc_updateslot; /* slot time update fsm */
257
258 struct callout sc_cal_ch; /* callout handle for cals */
259 struct callout sc_scan_ch; /* callout handle for scan */
260};
261#define sc_if sc_arp.ac_if
262#define sc_tx_th u_tx_rt.th
263#define sc_rx u_rx_rt.u
264#define sc_rx_th sc_rx.th
265#define sc_rx_wh sc_rx.wh
266
267#define ATH_LOCK_INIT(_sc) \
268 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
269 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
270#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
271#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
272#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
273#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
274
275#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
276
277#define ATH_TXBUF_LOCK_INIT(_sc) \
278 mtx_init(&(_sc)->sc_txbuflock, \
279 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF)
280#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
281#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
282#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
283#define ATH_TXBUF_LOCK_ASSERT(_sc) \
284 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
285
286int ath_attach(u_int16_t, struct ath_softc *);
287int ath_detach(struct ath_softc *);
288void ath_resume(struct ath_softc *);
289void ath_suspend(struct ath_softc *);
290void ath_shutdown(struct ath_softc *);
291void ath_intr(void *);
292
293/*
294 * HAL definitions to comply with local coding convention.
295 */
296#define ath_hal_detach(_ah) \
297 ((*(_ah)->ah_detach)((_ah)))
298#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
299 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
300#define ath_hal_getratetable(_ah, _mode) \
301 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
302#define ath_hal_getmac(_ah, _mac) \
303 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
304#define ath_hal_setmac(_ah, _mac) \
305 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
306#define ath_hal_intrset(_ah, _mask) \
307 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
308#define ath_hal_intrget(_ah) \
309 ((*(_ah)->ah_getInterrupts)((_ah)))
310#define ath_hal_intrpend(_ah) \
311 ((*(_ah)->ah_isInterruptPending)((_ah)))
312#define ath_hal_getisr(_ah, _pmask) \
313 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
314#define ath_hal_updatetxtriglevel(_ah, _inc) \
315 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
316#define ath_hal_setpower(_ah, _mode, _sleepduration) \
317 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration)))
318#define ath_hal_keycachesize(_ah) \
319 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
320#define ath_hal_keyreset(_ah, _ix) \
321 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
322#define ath_hal_keyset(_ah, _ix, _pk, _mac) \
323 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
324#define ath_hal_keyisvalid(_ah, _ix) \
325 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
326#define ath_hal_keysetmac(_ah, _ix, _mac) \
327 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
328#define ath_hal_getrxfilter(_ah) \
329 ((*(_ah)->ah_getRxFilter)((_ah)))
330#define ath_hal_setrxfilter(_ah, _filter) \
331 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
332#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
333 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
334#define ath_hal_waitforbeacon(_ah, _bf) \
335 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
336#define ath_hal_putrxbuf(_ah, _bufaddr) \
337 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
338#define ath_hal_gettsf32(_ah) \
339 ((*(_ah)->ah_getTsf32)((_ah)))
340#define ath_hal_gettsf64(_ah) \
341 ((*(_ah)->ah_getTsf64)((_ah)))
342#define ath_hal_resettsf(_ah) \
343 ((*(_ah)->ah_resetTsf)((_ah)))
344#define ath_hal_rxena(_ah) \
345 ((*(_ah)->ah_enableReceive)((_ah)))
346#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
347 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
348#define ath_hal_gettxbuf(_ah, _q) \
349 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
350#define ath_hal_numtxpending(_ah, _q) \
351 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
352#define ath_hal_getrxbuf(_ah) \
353 ((*(_ah)->ah_getRxDP)((_ah)))
354#define ath_hal_txstart(_ah, _q) \
355 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
356#define ath_hal_setchannel(_ah, _chan) \
357 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
358#define ath_hal_calibrate(_ah, _chan) \
359 ((*(_ah)->ah_perCalibration)((_ah), (_chan)))
360#define ath_hal_setledstate(_ah, _state) \
361 ((*(_ah)->ah_setLedState)((_ah), (_state)))
362#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
363 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
364#define ath_hal_beaconreset(_ah) \
365 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
366#define ath_hal_beacontimers(_ah, _bs) \
367 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
368#define ath_hal_setassocid(_ah, _bss, _associd) \
369 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
370#define ath_hal_phydisable(_ah) \
371 ((*(_ah)->ah_phyDisable)((_ah)))
372#define ath_hal_setopmode(_ah) \
373 ((*(_ah)->ah_setPCUConfig)((_ah)))
374#define ath_hal_stoptxdma(_ah, _qnum) \
375 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
376#define ath_hal_stoppcurecv(_ah) \
377 ((*(_ah)->ah_stopPcuReceive)((_ah)))
378#define ath_hal_startpcurecv(_ah) \
379 ((*(_ah)->ah_startPcuReceive)((_ah)))
380#define ath_hal_stopdmarecv(_ah) \
381 ((*(_ah)->ah_stopDmaReceive)((_ah)))
382#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
383 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
384 (_indata), (_insize), (_outdata), (_outsize)))
385#define ath_hal_setuptxqueue(_ah, _type, _irq) \
386 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
387#define ath_hal_resettxqueue(_ah, _q) \
388 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
389#define ath_hal_releasetxqueue(_ah, _q) \
390 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
391#define ath_hal_gettxqueueprops(_ah, _q, _qi) \
392 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
393#define ath_hal_settxqueueprops(_ah, _q, _qi) \
394 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
395#define ath_hal_getrfgain(_ah) \
396 ((*(_ah)->ah_getRfGain)((_ah)))
397#define ath_hal_getdefantenna(_ah) \
398 ((*(_ah)->ah_getDefAntenna)((_ah)))
399#define ath_hal_setdefantenna(_ah, _ant) \
400 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
401#define ath_hal_rxmonitor(_ah, _arg) \
402 ((*(_ah)->ah_rxMonitor)((_ah), (_arg)))
403#define ath_hal_mibevent(_ah, _stats) \
404 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
405#define ath_hal_setslottime(_ah, _us) \
406 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
407#define ath_hal_getslottime(_ah) \
408 ((*(_ah)->ah_getSlotTime)((_ah)))
409#define ath_hal_setacktimeout(_ah, _us) \
410 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
411#define ath_hal_getacktimeout(_ah) \
412 ((*(_ah)->ah_getAckTimeout)((_ah)))
413#define ath_hal_setctstimeout(_ah, _us) \
414 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
415#define ath_hal_getctstimeout(_ah) \
416 ((*(_ah)->ah_getCTSTimeout)((_ah)))
417#define ath_hal_getcapability(_ah, _cap, _param, _result) \
418 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
419#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
420 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
421#define ath_hal_ciphersupported(_ah, _cipher) \
422 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
423#define ath_hal_getregdomain(_ah, _prd) \
424 ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd))
425#define ath_hal_getcountrycode(_ah, _pcc) \
426 (*(_pcc) = (_ah)->ah_countryCode)
427#define ath_hal_tkipsplit(_ah) \
428 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
429#define ath_hal_hwphycounters(_ah) \
430 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
431#define ath_hal_hasdiversity(_ah) \
432 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
433#define ath_hal_getdiversity(_ah) \
434 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
435#define ath_hal_setdiversity(_ah, _v) \
436 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
437#define ath_hal_getdiag(_ah, _pv) \
438 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
439#define ath_hal_setdiag(_ah, _v) \
440 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
441#define ath_hal_getnumtxqueues(_ah, _pv) \
442 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
443#define ath_hal_hasveol(_ah) \
444 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
445#define ath_hal_hastxpowlimit(_ah) \
446 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
447#define ath_hal_settxpowlimit(_ah, _pow) \
448 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
449#define ath_hal_gettxpowlimit(_ah, _ppow) \
450 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
451#define ath_hal_getmaxtxpow(_ah, _ppow) \
452 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
453#define ath_hal_gettpscale(_ah, _scale) \
454 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
455#define ath_hal_settpscale(_ah, _v) \
456 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
457#define ath_hal_hastpc(_ah) \
458 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
459#define ath_hal_gettpc(_ah) \
460 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
461#define ath_hal_settpc(_ah, _v) \
462 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
463#define ath_hal_hasbursting(_ah) \
464 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
465
466#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
467 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
468#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \
469 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext)))
470#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
471 _txr0, _txtr0, _keyix, _ant, _flags, \
472 _rtsrate, _rtsdura) \
473 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
474 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
475 (_flags), (_rtsrate), (_rtsdura)))
476#define ath_hal_setupxtxdesc(_ah, _ds, \
477 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
478 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
479 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
480#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
481 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
482#define ath_hal_txprocdesc(_ah, _ds) \
483 ((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
484#define ath_hal_updateCTSForBursting(_ah, _ds, _prevds, _prevdsWithCTS, \
485 _gatingds, _txOpLimit, _ctsDuration) \
486 ((*(_ah)->ah_updateCTSForBursting)((_ah), (_ds), (_prevds), \
487 (_prevdsWithCTS), (_gatingds), (_txOpLimit), (_ctsDuration)))
488
489#define ath_hal_gpioCfgOutput(_ah, _gpio) \
490 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
491#define ath_hal_gpioset(_ah, _gpio, _b) \
492 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
493
494#endif /* _DEV_ATH_ATHVAR_H */
93 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
94};
95typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
96
97/*
98 * DMA state for tx/rx descriptors.
99 */
100struct ath_descdma {
101 const char* dd_name;
102 struct ath_desc *dd_desc; /* descriptors */
103 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
104 bus_addr_t dd_desc_len; /* size of dd_desc */
105 bus_dma_segment_t dd_dseg;
106 bus_dma_tag_t dd_dmat; /* bus DMA tag */
107 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
108 struct ath_buf *dd_bufptr; /* associated buffers */
109};
110
111/*
112 * Data transmit queue state. One of these exists for each
113 * hardware transmit queue. Packets sent to us from above
114 * are assigned to queues based on their priority. Not all
115 * devices support a complete set of hardware transmit queues.
116 * For those devices the array sc_ac2q will map multiple
117 * priorities to fewer hardware queues (typically all to one
118 * hardware queue).
119 */
120struct ath_txq {
121 u_int axq_qnum; /* hardware q number */
122 u_int axq_depth; /* queue depth (stat only) */
123 u_int axq_intrcnt; /* interrupt count */
124 u_int32_t *axq_link; /* link ptr in last TX desc */
125 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
126 struct mtx axq_lock; /* lock on q and link */
127};
128
129#define ATH_TXQ_LOCK_INIT(_sc, _tq) \
130 mtx_init(&(_tq)->axq_lock, \
131 device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF)
132#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
133#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
134#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
135#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
136
137#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
138 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
139 (_tq)->axq_depth++; \
140} while (0)
141#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
142 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
143 (_tq)->axq_depth--; \
144} while (0)
145
146struct ath_softc {
147 struct arpcom sc_arp; /* interface common */
148 struct ath_stats sc_stats; /* interface statistics */
149 struct ieee80211com sc_ic; /* IEEE 802.11 common */
150 int sc_regdomain;
151 int sc_countrycode;
152 int sc_debug;
153 void (*sc_recv_mgmt)(struct ieee80211com *,
154 struct mbuf *,
155 struct ieee80211_node *,
156 int, int, u_int32_t);
157 int (*sc_newstate)(struct ieee80211com *,
158 enum ieee80211_state, int);
159 void (*sc_node_free)(struct ieee80211_node *);
160 device_t sc_dev;
161 bus_space_tag_t sc_st; /* bus space tag */
162 bus_space_handle_t sc_sh; /* bus space handle */
163 bus_dma_tag_t sc_dmat; /* bus DMA tag */
164 struct mtx sc_mtx; /* master lock (recursive) */
165 struct ath_hal *sc_ah; /* Atheros HAL */
166 struct ath_ratectrl *sc_rc; /* tx rate control support */
167 void (*sc_setdefantenna)(struct ath_softc *, u_int);
168 unsigned int sc_invalid : 1,/* disable hardware accesses */
169 sc_mrretry : 1, /* multi-rate retry support */
170 sc_softled : 1, /* enable LED gpio status */
171 sc_splitmic: 1, /* split TKIP MIC keys */
172 sc_needmib : 1, /* enable MIB stats intr */
173 sc_hasdiversity : 1,/* rx diversity available */
174 sc_diversity : 1,/* enable rx diversity */
175 sc_hasveol : 1, /* tx VEOL support */
176 sc_hastpc : 1, /* per-packet TPC support */
177 sc_ledstate: 1, /* LED on/off state */
178 sc_blinking: 1; /* LED blink operation active */
179 /* rate tables */
180 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
181 const HAL_RATE_TABLE *sc_currates; /* current rate table */
182 enum ieee80211_phymode sc_curmode; /* current phy mode */
183 u_int16_t sc_curtxpow; /* current tx power limit */
184 HAL_CHANNEL sc_curchan; /* current h/w channel */
185 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
186 struct {
187 u_int8_t ieeerate; /* IEEE rate */
188 u_int8_t flags; /* radiotap flags */
189 u_int16_t ledon; /* softled on time */
190 u_int16_t ledoff; /* softled off time */
191 } sc_hwmap[32]; /* h/w rate ix mappings */
192 u_int8_t sc_protrix; /* protection rate index */
193 u_int sc_txantenna; /* tx antenna (fixed or auto) */
194 HAL_INT sc_imask; /* interrupt mask copy */
195 u_int sc_keymax; /* size of key cache */
196 u_int8_t sc_keymap[16]; /* bit map of key cache use */
197
198 u_int sc_ledpin; /* GPIO pin for driving LED */
199 u_int sc_ledon; /* pin setting for LED on */
200 u_int sc_ledidle; /* idle polling interval */
201 u_int32_t sc_ipackets; /* last data packet count */
202 int sc_ledevent; /* time of last LED event */
203 u_int8_t sc_rxrate; /* current rx rate for LED */
204 u_int8_t sc_txrate; /* current tx rate for LED */
205 u_int16_t sc_ledoff; /* off time for current blink */
206 struct callout sc_ledtimer; /* led off timer */
207
208 struct bpf_if *sc_drvbpf;
209 union {
210 struct ath_tx_radiotap_header th;
211 u_int8_t pad[64];
212 } u_tx_rt;
213 int sc_tx_th_len;
214 union {
215 struct {
216 struct ath_rx_radiotap_header th;
217 struct ieee80211_qosframe wh;
218 } u;
219 u_int8_t pad[64];
220 } u_rx_rt;
221 int sc_rx_rt_len;
222
223 struct task sc_fataltask; /* fatal int processing */
224
225 struct ath_descdma sc_rxdma; /* RX descriptos */
226 ath_bufhead sc_rxbuf; /* receive buffer */
227 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
228 struct task sc_rxtask; /* rx int processing */
229 struct task sc_rxorntask; /* rxorn int processing */
230 u_int8_t sc_defant; /* current default antenna */
231 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
232
233 struct ath_descdma sc_txdma; /* TX descriptors */
234 ath_bufhead sc_txbuf; /* transmit buffer */
235 struct mtx sc_txbuflock; /* txbuf lock */
236 int sc_tx_timer; /* transmit timeout */
237 u_int sc_txqsetup; /* h/w queues setup */
238 u_int sc_txintrperiod;/* tx interrupt batching */
239 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
240 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
241 struct task sc_txtask; /* tx int processing */
242
243 struct ath_descdma sc_bdma; /* beacon descriptors */
244 ath_bufhead sc_bbuf; /* beacon buffers */
245 u_int sc_bhalq; /* HAL q for outgoing beacons */
246 u_int sc_bmisscount; /* missed beacon transmits */
247 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
248 struct ath_txq *sc_cabq; /* tx q for cab frames */
249 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
250 struct task sc_bmisstask; /* bmiss int processing */
251 struct task sc_bstucktask; /* stuck beacon processing */
252 enum {
253 OK, /* no change needed */
254 UPDATE, /* update pending */
255 COMMIT /* beacon sent, commit change */
256 } sc_updateslot; /* slot time update fsm */
257
258 struct callout sc_cal_ch; /* callout handle for cals */
259 struct callout sc_scan_ch; /* callout handle for scan */
260};
261#define sc_if sc_arp.ac_if
262#define sc_tx_th u_tx_rt.th
263#define sc_rx u_rx_rt.u
264#define sc_rx_th sc_rx.th
265#define sc_rx_wh sc_rx.wh
266
267#define ATH_LOCK_INIT(_sc) \
268 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
269 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
270#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
271#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
272#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
273#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
274
275#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
276
277#define ATH_TXBUF_LOCK_INIT(_sc) \
278 mtx_init(&(_sc)->sc_txbuflock, \
279 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF)
280#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
281#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
282#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
283#define ATH_TXBUF_LOCK_ASSERT(_sc) \
284 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
285
286int ath_attach(u_int16_t, struct ath_softc *);
287int ath_detach(struct ath_softc *);
288void ath_resume(struct ath_softc *);
289void ath_suspend(struct ath_softc *);
290void ath_shutdown(struct ath_softc *);
291void ath_intr(void *);
292
293/*
294 * HAL definitions to comply with local coding convention.
295 */
296#define ath_hal_detach(_ah) \
297 ((*(_ah)->ah_detach)((_ah)))
298#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
299 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
300#define ath_hal_getratetable(_ah, _mode) \
301 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
302#define ath_hal_getmac(_ah, _mac) \
303 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
304#define ath_hal_setmac(_ah, _mac) \
305 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
306#define ath_hal_intrset(_ah, _mask) \
307 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
308#define ath_hal_intrget(_ah) \
309 ((*(_ah)->ah_getInterrupts)((_ah)))
310#define ath_hal_intrpend(_ah) \
311 ((*(_ah)->ah_isInterruptPending)((_ah)))
312#define ath_hal_getisr(_ah, _pmask) \
313 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
314#define ath_hal_updatetxtriglevel(_ah, _inc) \
315 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
316#define ath_hal_setpower(_ah, _mode, _sleepduration) \
317 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration)))
318#define ath_hal_keycachesize(_ah) \
319 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
320#define ath_hal_keyreset(_ah, _ix) \
321 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
322#define ath_hal_keyset(_ah, _ix, _pk, _mac) \
323 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
324#define ath_hal_keyisvalid(_ah, _ix) \
325 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
326#define ath_hal_keysetmac(_ah, _ix, _mac) \
327 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
328#define ath_hal_getrxfilter(_ah) \
329 ((*(_ah)->ah_getRxFilter)((_ah)))
330#define ath_hal_setrxfilter(_ah, _filter) \
331 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
332#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
333 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
334#define ath_hal_waitforbeacon(_ah, _bf) \
335 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
336#define ath_hal_putrxbuf(_ah, _bufaddr) \
337 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
338#define ath_hal_gettsf32(_ah) \
339 ((*(_ah)->ah_getTsf32)((_ah)))
340#define ath_hal_gettsf64(_ah) \
341 ((*(_ah)->ah_getTsf64)((_ah)))
342#define ath_hal_resettsf(_ah) \
343 ((*(_ah)->ah_resetTsf)((_ah)))
344#define ath_hal_rxena(_ah) \
345 ((*(_ah)->ah_enableReceive)((_ah)))
346#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
347 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
348#define ath_hal_gettxbuf(_ah, _q) \
349 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
350#define ath_hal_numtxpending(_ah, _q) \
351 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
352#define ath_hal_getrxbuf(_ah) \
353 ((*(_ah)->ah_getRxDP)((_ah)))
354#define ath_hal_txstart(_ah, _q) \
355 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
356#define ath_hal_setchannel(_ah, _chan) \
357 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
358#define ath_hal_calibrate(_ah, _chan) \
359 ((*(_ah)->ah_perCalibration)((_ah), (_chan)))
360#define ath_hal_setledstate(_ah, _state) \
361 ((*(_ah)->ah_setLedState)((_ah), (_state)))
362#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
363 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
364#define ath_hal_beaconreset(_ah) \
365 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
366#define ath_hal_beacontimers(_ah, _bs) \
367 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
368#define ath_hal_setassocid(_ah, _bss, _associd) \
369 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
370#define ath_hal_phydisable(_ah) \
371 ((*(_ah)->ah_phyDisable)((_ah)))
372#define ath_hal_setopmode(_ah) \
373 ((*(_ah)->ah_setPCUConfig)((_ah)))
374#define ath_hal_stoptxdma(_ah, _qnum) \
375 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
376#define ath_hal_stoppcurecv(_ah) \
377 ((*(_ah)->ah_stopPcuReceive)((_ah)))
378#define ath_hal_startpcurecv(_ah) \
379 ((*(_ah)->ah_startPcuReceive)((_ah)))
380#define ath_hal_stopdmarecv(_ah) \
381 ((*(_ah)->ah_stopDmaReceive)((_ah)))
382#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
383 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
384 (_indata), (_insize), (_outdata), (_outsize)))
385#define ath_hal_setuptxqueue(_ah, _type, _irq) \
386 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
387#define ath_hal_resettxqueue(_ah, _q) \
388 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
389#define ath_hal_releasetxqueue(_ah, _q) \
390 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
391#define ath_hal_gettxqueueprops(_ah, _q, _qi) \
392 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
393#define ath_hal_settxqueueprops(_ah, _q, _qi) \
394 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
395#define ath_hal_getrfgain(_ah) \
396 ((*(_ah)->ah_getRfGain)((_ah)))
397#define ath_hal_getdefantenna(_ah) \
398 ((*(_ah)->ah_getDefAntenna)((_ah)))
399#define ath_hal_setdefantenna(_ah, _ant) \
400 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
401#define ath_hal_rxmonitor(_ah, _arg) \
402 ((*(_ah)->ah_rxMonitor)((_ah), (_arg)))
403#define ath_hal_mibevent(_ah, _stats) \
404 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
405#define ath_hal_setslottime(_ah, _us) \
406 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
407#define ath_hal_getslottime(_ah) \
408 ((*(_ah)->ah_getSlotTime)((_ah)))
409#define ath_hal_setacktimeout(_ah, _us) \
410 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
411#define ath_hal_getacktimeout(_ah) \
412 ((*(_ah)->ah_getAckTimeout)((_ah)))
413#define ath_hal_setctstimeout(_ah, _us) \
414 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
415#define ath_hal_getctstimeout(_ah) \
416 ((*(_ah)->ah_getCTSTimeout)((_ah)))
417#define ath_hal_getcapability(_ah, _cap, _param, _result) \
418 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
419#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
420 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
421#define ath_hal_ciphersupported(_ah, _cipher) \
422 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
423#define ath_hal_getregdomain(_ah, _prd) \
424 ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd))
425#define ath_hal_getcountrycode(_ah, _pcc) \
426 (*(_pcc) = (_ah)->ah_countryCode)
427#define ath_hal_tkipsplit(_ah) \
428 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
429#define ath_hal_hwphycounters(_ah) \
430 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
431#define ath_hal_hasdiversity(_ah) \
432 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
433#define ath_hal_getdiversity(_ah) \
434 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
435#define ath_hal_setdiversity(_ah, _v) \
436 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
437#define ath_hal_getdiag(_ah, _pv) \
438 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
439#define ath_hal_setdiag(_ah, _v) \
440 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
441#define ath_hal_getnumtxqueues(_ah, _pv) \
442 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
443#define ath_hal_hasveol(_ah) \
444 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
445#define ath_hal_hastxpowlimit(_ah) \
446 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
447#define ath_hal_settxpowlimit(_ah, _pow) \
448 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
449#define ath_hal_gettxpowlimit(_ah, _ppow) \
450 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
451#define ath_hal_getmaxtxpow(_ah, _ppow) \
452 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
453#define ath_hal_gettpscale(_ah, _scale) \
454 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
455#define ath_hal_settpscale(_ah, _v) \
456 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
457#define ath_hal_hastpc(_ah) \
458 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
459#define ath_hal_gettpc(_ah) \
460 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
461#define ath_hal_settpc(_ah, _v) \
462 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
463#define ath_hal_hasbursting(_ah) \
464 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
465
466#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
467 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
468#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \
469 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext)))
470#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
471 _txr0, _txtr0, _keyix, _ant, _flags, \
472 _rtsrate, _rtsdura) \
473 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
474 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
475 (_flags), (_rtsrate), (_rtsdura)))
476#define ath_hal_setupxtxdesc(_ah, _ds, \
477 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
478 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
479 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
480#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
481 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
482#define ath_hal_txprocdesc(_ah, _ds) \
483 ((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
484#define ath_hal_updateCTSForBursting(_ah, _ds, _prevds, _prevdsWithCTS, \
485 _gatingds, _txOpLimit, _ctsDuration) \
486 ((*(_ah)->ah_updateCTSForBursting)((_ah), (_ds), (_prevds), \
487 (_prevdsWithCTS), (_gatingds), (_txOpLimit), (_ctsDuration)))
488
489#define ath_hal_gpioCfgOutput(_ah, _gpio) \
490 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
491#define ath_hal_gpioset(_ah, _gpio, _b) \
492 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
493
494#endif /* _DEV_ATH_ATHVAR_H */