| ar5416reg.h (221666) | ar5416reg.h (221806) |
|---|---|
| 1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * | 1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * |
| 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 221666 2011-05-08 15:25:22Z adrian $ | 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 221806 2011-05-12 10:11:24Z adrian $ |
| 18 */ 19#ifndef _DEV_ATH_AR5416REG_H 20#define _DEV_ATH_AR5416REG_H 21 22#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23 24/* 25 * Register added starting with the AR5416 --- 47 unchanged lines hidden (view full) --- 73 74#ifdef AH_SUPPORT_AR9130 75/* RTC_DERIVED_* - only for AR9130 */ 76#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 77#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 78#define AR_RTC_DERIVED_CLK_PERIOD_S 1 79#endif /* AH_SUPPORT_AR9130 */ 80 | 18 */ 19#ifndef _DEV_ATH_AR5416REG_H 20#define _DEV_ATH_AR5416REG_H 21 22#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23 24/* 25 * Register added starting with the AR5416 --- 47 unchanged lines hidden (view full) --- 73 74#ifdef AH_SUPPORT_AR9130 75/* RTC_DERIVED_* - only for AR9130 */ 76#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 77#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 78#define AR_RTC_DERIVED_CLK_PERIOD_S 1 79#endif /* AH_SUPPORT_AR9130 */ 80 |
| 81/* AR9280: rf long shift registers */ 82#define AR_AN_RF2G1_CH0 0x7810 83#define AR_AN_RF5G1_CH0 0x7818 84#define AR_AN_RF2G1_CH1 0x7834 85#define AR_AN_RF5G1_CH1 0x783C 86#define AR_AN_TOP2 0x7894 87#define AR_AN_SYNTH9 0x7868 88#define AR9285_AN_RF2G1 0x7820 89#define AR9285_AN_RF2G2 0x7824 90#define AR9285_AN_RF2G3 0x7828 91#define AR9285_AN_RF2G4 0x782C 92#define AR9285_AN_RF2G6 0x7834 93#define AR9285_AN_RF2G7 0x7838 94#define AR9285_AN_RF2G8 0x783C 95#define AR9285_AN_RF2G9 0x7840 96#define AR9285_AN_RXTXBB1 0x7854 97#define AR9285_AN_TOP2 0x7868 98#define AR9285_AN_TOP3 0x786c 99#define AR9285_AN_TOP4 0x7870 100#define AR9285_AN_TOP4_DEFAULT 0x10142c00 101 | |
| 102#define AR_RESET_TSF 0x8020 103#define AR_RXFIFO_CFG 0x8114 104#define AR_PHY_ERR_1 0x812c 105#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 106#define AR_PHY_ERR_2 0x8134 107#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 108#define AR_TSFOOR_THRESHOLD 0x813c 109#define AR_PHY_ERR_3 0x8168 --- 259 unchanged lines hidden (view full) --- 369 370#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 371#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 372 373#define AR_RTC_PLL_CLKSEL 0x00000300 374#define AR_RTC_PLL_CLKSEL_S 8 375 376/* AR9280: rf long shift registers */ | 81#define AR_RESET_TSF 0x8020 82#define AR_RXFIFO_CFG 0x8114 83#define AR_PHY_ERR_1 0x812c 84#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 85#define AR_PHY_ERR_2 0x8134 86#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 87#define AR_TSFOOR_THRESHOLD 0x813c 88#define AR_PHY_ERR_3 0x8168 --- 259 unchanged lines hidden (view full) --- 348 349#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 350#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 351 352#define AR_RTC_PLL_CLKSEL 0x00000300 353#define AR_RTC_PLL_CLKSEL_S 8 354 355/* AR9280: rf long shift registers */ |
| 356#define AR_AN_RF2G1_CH0 0x7810 357#define AR_AN_RF5G1_CH0 0x7818 358#define AR_AN_RF2G1_CH1 0x7834 359#define AR_AN_RF5G1_CH1 0x783C 360#define AR_AN_TOP2 0x7894 361#define AR_AN_SYNTH9 0x7868 362 |
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| 377#define AR_AN_RF2G1_CH0_OB 0x03800000 378#define AR_AN_RF2G1_CH0_OB_S 23 379#define AR_AN_RF2G1_CH0_DB 0x1C000000 380#define AR_AN_RF2G1_CH0_DB_S 26 381 382#define AR_AN_RF5G1_CH0_OB5 0x00070000 383#define AR_AN_RF5G1_CH0_OB5_S 16 384#define AR_AN_RF5G1_CH0_DB5 0x00380000 --- 18 unchanged lines hidden (view full) --- 403#define AR_AN_TOP2_LOCALBIAS 0x00200000 404#define AR_AN_TOP2_LOCALBIAS_S 21 405#define AR_AN_TOP2_PWDCLKIND 0x00400000 406#define AR_AN_TOP2_PWDCLKIND_S 22 407 408#define AR_AN_SYNTH9_REFDIVA 0xf8000000 409#define AR_AN_SYNTH9_REFDIVA_S 27 410 | 363#define AR_AN_RF2G1_CH0_OB 0x03800000 364#define AR_AN_RF2G1_CH0_OB_S 23 365#define AR_AN_RF2G1_CH0_DB 0x1C000000 366#define AR_AN_RF2G1_CH0_DB_S 26 367 368#define AR_AN_RF5G1_CH0_OB5 0x00070000 369#define AR_AN_RF5G1_CH0_OB5_S 16 370#define AR_AN_RF5G1_CH0_DB5 0x00380000 --- 18 unchanged lines hidden (view full) --- 389#define AR_AN_TOP2_LOCALBIAS 0x00200000 390#define AR_AN_TOP2_LOCALBIAS_S 21 391#define AR_AN_TOP2_PWDCLKIND 0x00400000 392#define AR_AN_TOP2_PWDCLKIND_S 22 393 394#define AR_AN_SYNTH9_REFDIVA 0xf8000000 395#define AR_AN_SYNTH9_REFDIVA_S 27 396 |
| 411/* AR9285 Analog registers */ 412#define AR9285_AN_RF2G1_ENPACAL 0x00000800 413#define AR9285_AN_RF2G1_ENPACAL_S 11 414#define AR9285_AN_RF2G1_PDPADRV1 0x02000000 415#define AR9285_AN_RF2G1_PDPADRV1_S 25 416#define AR9285_AN_RF2G1_PDPADRV2 0x01000000 417#define AR9285_AN_RF2G1_PDPADRV2_S 24 418#define AR9285_AN_RF2G1_PDPAOUT 0x00800000 419#define AR9285_AN_RF2G1_PDPAOUT_S 23 420 421#define AR9285_AN_RF2G2_OFFCAL 0x00001000 422#define AR9285_AN_RF2G2_OFFCAL_S 12 423 424#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 425#define AR9285_AN_RF2G3_PDVCCOMP_S 25 426#define AR9285_AN_RF2G3_OB_0 0x00E00000 427#define AR9285_AN_RF2G3_OB_0_S 21 428#define AR9285_AN_RF2G3_OB_1 0x001C0000 429#define AR9285_AN_RF2G3_OB_1_S 18 430#define AR9285_AN_RF2G3_OB_2 0x00038000 431#define AR9285_AN_RF2G3_OB_2_S 15 432#define AR9285_AN_RF2G3_OB_3 0x00007000 433#define AR9285_AN_RF2G3_OB_3_S 12 434#define AR9285_AN_RF2G3_OB_4 0x00000E00 435#define AR9285_AN_RF2G3_OB_4_S 9 436 437#define AR9285_AN_RF2G3_DB1_0 0x000001C0 438#define AR9285_AN_RF2G3_DB1_0_S 6 439#define AR9285_AN_RF2G3_DB1_1 0x00000038 440#define AR9285_AN_RF2G3_DB1_1_S 3 441#define AR9285_AN_RF2G3_DB1_2 0x00000007 442#define AR9285_AN_RF2G3_DB1_2_S 0 443 444#define AR9285_AN_RF2G4_DB1_3 0xE0000000 445#define AR9285_AN_RF2G4_DB1_3_S 29 446#define AR9285_AN_RF2G4_DB1_4 0x1C000000 447#define AR9285_AN_RF2G4_DB1_4_S 26 448 449#define AR9285_AN_RF2G4_DB2_0 0x03800000 450#define AR9285_AN_RF2G4_DB2_0_S 23 451#define AR9285_AN_RF2G4_DB2_1 0x00700000 452#define AR9285_AN_RF2G4_DB2_1_S 20 453#define AR9285_AN_RF2G4_DB2_2 0x000E0000 454#define AR9285_AN_RF2G4_DB2_2_S 17 455#define AR9285_AN_RF2G4_DB2_3 0x0001C000 456#define AR9285_AN_RF2G4_DB2_3_S 14 457#define AR9285_AN_RF2G4_DB2_4 0x00003800 458#define AR9285_AN_RF2G4_DB2_4_S 11 459 460#define AR9285_AN_RF2G6_CCOMP 0x00007800 461#define AR9285_AN_RF2G6_CCOMP_S 11 462#define AR9285_AN_RF2G6_OFFS 0x03f00000 463#define AR9285_AN_RF2G6_OFFS_S 20 464 | |
| 465#define AR9271_AN_RF2G6_OFFS 0x07f00000 466#define AR9271_AN_RF2G6_OFFS_S 20 467 | 397#define AR9271_AN_RF2G6_OFFS 0x07f00000 398#define AR9271_AN_RF2G6_OFFS_S 20 399 |
| 468#define AR9285_AN_RF2G7_PWDDB 0x00000002 469#define AR9285_AN_RF2G7_PWDDB_S 1 470#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 471#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 472 473#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 474#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 475 476#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 477#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 478#define AR9285_AN_RXTXBB1_PDV2I 0x00000080 479#define AR9285_AN_RXTXBB1_PDV2I_S 7 480#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 481#define AR9285_AN_RXTXBB1_PDDACIF_S 8 482#define AR9285_AN_RXTXBB1_SPARE9 0x00000001 483#define AR9285_AN_RXTXBB1_SPARE9_S 0 484 485#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 486#define AR9285_AN_TOP3_XPABIAS_LVL_S 2 487#define AR9285_AN_TOP3_PWDDAC 0x00800000 488#define AR9285_AN_TOP3_PWDDAC_S 23 489 | |
| 490/* Sleep control */ 491#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 492#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 493 494#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 495#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 496 497/* Sleep Registers */ --- 249 unchanged lines hidden --- | 400/* Sleep control */ 401#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 402#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 403 404#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 405#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 406 407/* Sleep Registers */ --- 249 unchanged lines hidden --- |