1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2005-2006 Atheros Communications, Inc.
4 * All rights reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
| 1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2005-2006 Atheros Communications, Inc.
4 * All rights reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
|
18 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_regdomain.h 219394 2011-03-08 07:42:09Z adrian $
| 18 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_regdomain.h 219442 2011-03-10 03:13:56Z adrian $
|
19 */
20#ifndef __AH_REGDOMAIN_H__
21#define __AH_REGDOMAIN_H__
22
23/*
24 * BMLEN defines the size of the bitmask used to hold frequency
25 * band specifications. Note this must agree with the BM macro
26 * definition that's used to setup initializers. See also further
27 * comments below.
28 */
29#define BMLEN 2 /* 2 x 64 bits in each channel bitmask */
30typedef uint64_t chanbmask_t[BMLEN];
31
32/*
| 19 */
20#ifndef __AH_REGDOMAIN_H__
21#define __AH_REGDOMAIN_H__
22
23/*
24 * BMLEN defines the size of the bitmask used to hold frequency
25 * band specifications. Note this must agree with the BM macro
26 * definition that's used to setup initializers. See also further
27 * comments below.
28 */
29#define BMLEN 2 /* 2 x 64 bits in each channel bitmask */
30typedef uint64_t chanbmask_t[BMLEN];
31
32/*
|
| 33 * The following describe the bit masks for different passive scan
34 * capability/requirements per regdomain.
35 */
36#define NO_PSCAN 0x0ULL /* NB: must be zero */
37#define PSCAN_FCC 0x0000000000000001ULL
38#define PSCAN_FCC_T 0x0000000000000002ULL
39#define PSCAN_ETSI 0x0000000000000004ULL
40#define PSCAN_MKK1 0x0000000000000008ULL
41#define PSCAN_MKK2 0x0000000000000010ULL
42#define PSCAN_MKKA 0x0000000000000020ULL
43#define PSCAN_MKKA_G 0x0000000000000040ULL
44#define PSCAN_ETSIA 0x0000000000000080ULL
45#define PSCAN_ETSIB 0x0000000000000100ULL
46#define PSCAN_ETSIC 0x0000000000000200ULL
47#define PSCAN_WWR 0x0000000000000400ULL
48#define PSCAN_MKKA1 0x0000000000000800ULL
49#define PSCAN_MKKA1_G 0x0000000000001000ULL
50#define PSCAN_MKKA2 0x0000000000002000ULL
51#define PSCAN_MKKA2_G 0x0000000000004000ULL
52#define PSCAN_MKK3 0x0000000000008000ULL
53#define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL
54#define IS_ECM_CHAN 0x8000000000000000ULL
55
56/*
57 * The following are flags for different requirements per reg domain.
58 * These requirements are either inhereted from the reg domain pair or
59 * from the unitary reg domain if the reg domain pair flags value is 0
60 */
61enum {
62 NO_REQ = 0x00000000, /* NB: must be zero */
63 DISALLOW_ADHOC_11A = 0x00000001, /* adhoc not allowed in 5GHz */
64 DISALLOW_ADHOC_11A_TURB = 0x00000002, /* not allowed w/ 5GHz turbo */
65 NEED_NFC = 0x00000004, /* need noise floor check */
66 ADHOC_PER_11D = 0x00000008, /* must receive 11d beacon */
67 LIMIT_FRAME_4MS = 0x00000020, /* 4msec tx burst limit */
68 NO_HOSTAP = 0x00000040, /* No HOSTAP mode opereation */
69};
70
71/* Bit masks for DFS per regdomain */
72enum {
73 NO_DFS = 0x0000000000000000ULL, /* NB: must be zero */
74 DFS_FCC3 = 0x0000000000000001ULL,
75 DFS_ETSI = 0x0000000000000002ULL,
76 DFS_MKK4 = 0x0000000000000004ULL,
77};
78
79enum { /* conformance test limits */
80 FCC = 0x10,
81 MKK = 0x40,
82 ETSI = 0x30,
83};
84
85/*
|
33 * THE following table is the mapping of regdomain pairs specified by
34 * an 8 bit regdomain value to the individual unitary reg domains
35 */
36typedef struct regDomainPair {
37 HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */
38 HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */
39 HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */
40 uint32_t flags5GHz; /* Requirements flags (AdHoc
--- 70 unchanged lines hidden --- | 86 * THE following table is the mapping of regdomain pairs specified by
87 * an 8 bit regdomain value to the individual unitary reg domains
88 */
89typedef struct regDomainPair {
90 HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */
91 HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */
92 HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */
93 uint32_t flags5GHz; /* Requirements flags (AdHoc
--- 70 unchanged lines hidden --- |