1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-highpoint.c 188765 2009-02-18 22:17:48Z mav $");
| 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-highpoint.c 188769 2009-02-19 00:32:55Z mav $");
|
29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/malloc.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_highpoint_chipinit(device_t dev);
56static int ata_highpoint_ch_attach(device_t dev);
57static void ata_highpoint_setmode(device_t dev, int mode);
58static int ata_highpoint_check_80pin(device_t dev, int mode);
59
60/* misc defines */
61#define HPT_366 0
62#define HPT_370 1
63#define HPT_372 2
64#define HPT_374 3
65#define HPT_OLD 1
66
67
68/*
69 * HighPoint chipset support functions
70 */
71static int
72ata_highpoint_probe(device_t dev)
73{
74 struct ata_pci_controller *ctlr = device_get_softc(dev);
75 struct ata_chip_id *idx;
76 static struct ata_chip_id ids[] =
77 {{ ATA_HPT374, 0x07, HPT_374, 0, ATA_UDMA6, "HPT374" },
78 { ATA_HPT372, 0x02, HPT_372, 0, ATA_UDMA6, "HPT372N" },
79 { ATA_HPT372, 0x01, HPT_372, 0, ATA_UDMA6, "HPT372" },
80 { ATA_HPT371, 0x01, HPT_372, 0, ATA_UDMA6, "HPT371" },
81 { ATA_HPT366, 0x05, HPT_372, 0, ATA_UDMA6, "HPT372" },
82 { ATA_HPT366, 0x03, HPT_370, 0, ATA_UDMA5, "HPT370" },
83 { ATA_HPT366, 0x02, HPT_366, 0, ATA_UDMA4, "HPT368" },
84 { ATA_HPT366, 0x00, HPT_366, HPT_OLD, ATA_UDMA4, "HPT366" },
85 { ATA_HPT302, 0x01, HPT_372, 0, ATA_UDMA6, "HPT302" },
86 { 0, 0, 0, 0, 0, 0}};
87 char buffer[64];
88
89 if (pci_get_vendor(dev) != ATA_HIGHPOINT_ID)
90 return ENXIO;
91
92 if (!(idx = ata_match_chip(dev, ids)))
93 return ENXIO;
94
95 strcpy(buffer, "HighPoint ");
96 strcat(buffer, idx->text);
97 if (idx->cfg1 == HPT_374) {
98 if (pci_get_function(dev) == 0)
99 strcat(buffer, " (channel 0+1)");
100 if (pci_get_function(dev) == 1)
101 strcat(buffer, " (channel 2+3)");
102 }
103 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
104 device_set_desc_copy(dev, buffer);
105 ctlr->chip = idx;
106 ctlr->chipinit = ata_highpoint_chipinit;
107 return 0;
108}
109
110static int
111ata_highpoint_chipinit(device_t dev)
112{
113 struct ata_pci_controller *ctlr = device_get_softc(dev);
114
115 if (ata_setup_interrupt(dev, ata_generic_intr))
116 return ENXIO;
117
118 if (ctlr->chip->cfg2 == HPT_OLD) {
119 /* disable interrupt prediction */
120 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
121 }
122 else {
123 /* disable interrupt prediction */
124 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
125 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
126
127 /* enable interrupts */
128 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
129
130 /* set clocks etc */
131 if (ctlr->chip->cfg1 < HPT_372)
132 pci_write_config(dev, 0x5b, 0x22, 1);
133 else
134 pci_write_config(dev, 0x5b,
135 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
136 }
137 ctlr->ch_attach = ata_highpoint_ch_attach;
| 29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/malloc.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_highpoint_chipinit(device_t dev);
56static int ata_highpoint_ch_attach(device_t dev);
57static void ata_highpoint_setmode(device_t dev, int mode);
58static int ata_highpoint_check_80pin(device_t dev, int mode);
59
60/* misc defines */
61#define HPT_366 0
62#define HPT_370 1
63#define HPT_372 2
64#define HPT_374 3
65#define HPT_OLD 1
66
67
68/*
69 * HighPoint chipset support functions
70 */
71static int
72ata_highpoint_probe(device_t dev)
73{
74 struct ata_pci_controller *ctlr = device_get_softc(dev);
75 struct ata_chip_id *idx;
76 static struct ata_chip_id ids[] =
77 {{ ATA_HPT374, 0x07, HPT_374, 0, ATA_UDMA6, "HPT374" },
78 { ATA_HPT372, 0x02, HPT_372, 0, ATA_UDMA6, "HPT372N" },
79 { ATA_HPT372, 0x01, HPT_372, 0, ATA_UDMA6, "HPT372" },
80 { ATA_HPT371, 0x01, HPT_372, 0, ATA_UDMA6, "HPT371" },
81 { ATA_HPT366, 0x05, HPT_372, 0, ATA_UDMA6, "HPT372" },
82 { ATA_HPT366, 0x03, HPT_370, 0, ATA_UDMA5, "HPT370" },
83 { ATA_HPT366, 0x02, HPT_366, 0, ATA_UDMA4, "HPT368" },
84 { ATA_HPT366, 0x00, HPT_366, HPT_OLD, ATA_UDMA4, "HPT366" },
85 { ATA_HPT302, 0x01, HPT_372, 0, ATA_UDMA6, "HPT302" },
86 { 0, 0, 0, 0, 0, 0}};
87 char buffer[64];
88
89 if (pci_get_vendor(dev) != ATA_HIGHPOINT_ID)
90 return ENXIO;
91
92 if (!(idx = ata_match_chip(dev, ids)))
93 return ENXIO;
94
95 strcpy(buffer, "HighPoint ");
96 strcat(buffer, idx->text);
97 if (idx->cfg1 == HPT_374) {
98 if (pci_get_function(dev) == 0)
99 strcat(buffer, " (channel 0+1)");
100 if (pci_get_function(dev) == 1)
101 strcat(buffer, " (channel 2+3)");
102 }
103 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
104 device_set_desc_copy(dev, buffer);
105 ctlr->chip = idx;
106 ctlr->chipinit = ata_highpoint_chipinit;
107 return 0;
108}
109
110static int
111ata_highpoint_chipinit(device_t dev)
112{
113 struct ata_pci_controller *ctlr = device_get_softc(dev);
114
115 if (ata_setup_interrupt(dev, ata_generic_intr))
116 return ENXIO;
117
118 if (ctlr->chip->cfg2 == HPT_OLD) {
119 /* disable interrupt prediction */
120 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
121 }
122 else {
123 /* disable interrupt prediction */
124 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
125 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
126
127 /* enable interrupts */
128 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
129
130 /* set clocks etc */
131 if (ctlr->chip->cfg1 < HPT_372)
132 pci_write_config(dev, 0x5b, 0x22, 1);
133 else
134 pci_write_config(dev, 0x5b,
135 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
136 }
137 ctlr->ch_attach = ata_highpoint_ch_attach;
|
| 138 ctlr->ch_detach = ata_pci_ch_detach;
|
138 ctlr->setmode = ata_highpoint_setmode;
139 return 0;
140}
141
142static int
143ata_highpoint_ch_attach(device_t dev)
144{
145 struct ata_channel *ch = device_get_softc(dev);
146
147 /* setup the usual register normal pci style */
148 if (ata_pci_ch_attach(dev))
149 return ENXIO;
150
151 ch->flags |= ATA_ALWAYS_DMASTAT;
152 return 0;
153}
154
155static void
156ata_highpoint_setmode(device_t dev, int mode)
157{
158 device_t gparent = GRANDPARENT(dev);
159 struct ata_pci_controller *ctlr = device_get_softc(gparent);
160 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
161 struct ata_device *atadev = device_get_softc(dev);
162 int devno = (ch->unit << 1) + atadev->unit;
163 int error;
164 u_int32_t timings33[][4] = {
165 /* HPT366 HPT370 HPT372 HPT374 mode */
166 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
167 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
168 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
169 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
170 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
171 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
172 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
173 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
174 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
175 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
176 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
177 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
178 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
179 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
180 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
181 };
182
183 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
184
185 if (ctlr->chip->cfg1 == HPT_366 && ata_atapi(dev))
186 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
187
188 mode = ata_highpoint_check_80pin(dev, mode);
189
190 /*
191 * most if not all HPT chips cant really handle that the device is
192 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
193 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
194 */
195 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
196 ata_limit_mode(dev, mode, ATA_UDMA5));
197 if (bootverbose)
198 device_printf(dev, "%ssetting %s on HighPoint chip\n",
199 (error) ? "FAILURE " : "", ata_mode2str(mode));
200 if (!error)
201 pci_write_config(gparent, 0x40 + (devno << 2),
202 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
203 atadev->mode = mode;
204}
205
206static int
207ata_highpoint_check_80pin(device_t dev, int mode)
208{
209 device_t gparent = GRANDPARENT(dev);
210 struct ata_pci_controller *ctlr = device_get_softc(gparent);
211 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
212 u_int8_t reg, val, res;
213
214 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(gparent) == 1) {
215 reg = ch->unit ? 0x57 : 0x53;
216 val = pci_read_config(gparent, reg, 1);
217 pci_write_config(gparent, reg, val | 0x80, 1);
218 }
219 else {
220 reg = 0x5b;
221 val = pci_read_config(gparent, reg, 1);
222 pci_write_config(gparent, reg, val & 0xfe, 1);
223 }
224 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
225 pci_write_config(gparent, reg, val, 1);
226
227 if (mode > ATA_UDMA2 && res) {
228 ata_print_cable(dev, "controller");
229 mode = ATA_UDMA2;
230 }
231 return mode;
232}
233
234ATA_DECLARE_DRIVER(ata_highpoint);
| 139 ctlr->setmode = ata_highpoint_setmode;
140 return 0;
141}
142
143static int
144ata_highpoint_ch_attach(device_t dev)
145{
146 struct ata_channel *ch = device_get_softc(dev);
147
148 /* setup the usual register normal pci style */
149 if (ata_pci_ch_attach(dev))
150 return ENXIO;
151
152 ch->flags |= ATA_ALWAYS_DMASTAT;
153 return 0;
154}
155
156static void
157ata_highpoint_setmode(device_t dev, int mode)
158{
159 device_t gparent = GRANDPARENT(dev);
160 struct ata_pci_controller *ctlr = device_get_softc(gparent);
161 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
162 struct ata_device *atadev = device_get_softc(dev);
163 int devno = (ch->unit << 1) + atadev->unit;
164 int error;
165 u_int32_t timings33[][4] = {
166 /* HPT366 HPT370 HPT372 HPT374 mode */
167 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
168 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
169 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
170 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
171 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
172 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
173 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
174 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
175 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
176 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
177 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
178 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
179 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
180 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
181 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
182 };
183
184 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
185
186 if (ctlr->chip->cfg1 == HPT_366 && ata_atapi(dev))
187 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
188
189 mode = ata_highpoint_check_80pin(dev, mode);
190
191 /*
192 * most if not all HPT chips cant really handle that the device is
193 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
194 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
195 */
196 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
197 ata_limit_mode(dev, mode, ATA_UDMA5));
198 if (bootverbose)
199 device_printf(dev, "%ssetting %s on HighPoint chip\n",
200 (error) ? "FAILURE " : "", ata_mode2str(mode));
201 if (!error)
202 pci_write_config(gparent, 0x40 + (devno << 2),
203 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
204 atadev->mode = mode;
205}
206
207static int
208ata_highpoint_check_80pin(device_t dev, int mode)
209{
210 device_t gparent = GRANDPARENT(dev);
211 struct ata_pci_controller *ctlr = device_get_softc(gparent);
212 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
213 u_int8_t reg, val, res;
214
215 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(gparent) == 1) {
216 reg = ch->unit ? 0x57 : 0x53;
217 val = pci_read_config(gparent, reg, 1);
218 pci_write_config(gparent, reg, val | 0x80, 1);
219 }
220 else {
221 reg = 0x5b;
222 val = pci_read_config(gparent, reg, 1);
223 pci_write_config(gparent, reg, val & 0xfe, 1);
224 }
225 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
226 pci_write_config(gparent, reg, val, 1);
227
228 if (mode > ATA_UDMA2 && res) {
229 ata_print_cable(dev, "controller");
230 mode = ATA_UDMA2;
231 }
232 return mode;
233}
234
235ATA_DECLARE_DRIVER(ata_highpoint);
|