Deleted Added
full compact
aic7xxx.h (41646) aic7xxx.h (41816)
1/*
2 * Interface to the generic driver for the aic7xxx based adaptec
3 * SCSI controllers. This is used to implement product specific
4 * probe and attach routines.
5 *
6 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs.
7 * All rights reserved.
8 *

--- 20 unchanged lines hidden (view full) ---

29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
1/*
2 * Interface to the generic driver for the aic7xxx based adaptec
3 * SCSI controllers. This is used to implement product specific
4 * probe and attach routines.
5 *
6 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs.
7 * All rights reserved.
8 *

--- 20 unchanged lines hidden (view full) ---

29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * $Id: aic7xxx.h,v 1.2 1998/11/23 01:33:47 gibbs Exp $
37 * $Id: aic7xxx.h,v 1.3 1998/12/10 04:14:50 gibbs Exp $
38 */
39
40#ifndef _AIC7XXX_H_
41#define _AIC7XXX_H_
42
43#include "ahc.h" /* for NAHC from config */
44#include "opt_aic7xxx.h" /* for config options */
45

--- 66 unchanged lines hidden (view full) ---

112 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */
113 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */
114 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */
115 AHC_AIC7770_FE = AHC_FENONE,
116 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP,
117 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP,
118 AHC_AIC7870_FE = AHC_FENONE,
119 AHC_AIC7880_FE = AHC_ULTRA,
38 */
39
40#ifndef _AIC7XXX_H_
41#define _AIC7XXX_H_
42
43#include "ahc.h" /* for NAHC from config */
44#include "opt_aic7xxx.h" /* for config options */
45

--- 66 unchanged lines hidden (view full) ---

112 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */
113 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */
114 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */
115 AHC_AIC7770_FE = AHC_FENONE,
116 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP,
117 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP,
118 AHC_AIC7870_FE = AHC_FENONE,
119 AHC_AIC7880_FE = AHC_ULTRA,
120 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID,
120 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS
121 |AHC_SG_PRELOAD|AHC_MULTI_TID,
121 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA,
122 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA,
122 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID,
123 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS
124 |AHC_SG_PRELOAD|AHC_MULTI_TID,
123} ahc_feature;
124
125typedef enum {
126 AHC_FNONE = 0x000,
127 AHC_PAGESCBS = 0x001,/* Enable SCB paging */
128 AHC_CHANNEL_B_PRIMARY = 0x002,/*
129 * On twin channel adapters, probe
130 * channel B first since it is the
131 * primary bus.
132 */
133 AHC_USEDEFAULTS = 0x004,/*
134 * For cards without an seeprom
135 * or a BIOS to initialize the chip's
136 * SRAM, we use the default target
137 * settings.
138 */
139 AHC_INDIRECT_PAGING = 0x008,
140 AHC_SHARED_SRAM = 0x010,
141 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */
125} ahc_feature;
126
127typedef enum {
128 AHC_FNONE = 0x000,
129 AHC_PAGESCBS = 0x001,/* Enable SCB paging */
130 AHC_CHANNEL_B_PRIMARY = 0x002,/*
131 * On twin channel adapters, probe
132 * channel B first since it is the
133 * primary bus.
134 */
135 AHC_USEDEFAULTS = 0x004,/*
136 * For cards without an seeprom
137 * or a BIOS to initialize the chip's
138 * SRAM, we use the default target
139 * settings.
140 */
141 AHC_INDIRECT_PAGING = 0x008,
142 AHC_SHARED_SRAM = 0x010,
143 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */
144 AHC_RESET_BUS_A = 0x040,
145 AHC_RESET_BUS_B = 0x080,
142 AHC_EXTENDED_TRANS_A = 0x100,
143 AHC_EXTENDED_TRANS_B = 0x200,
144 AHC_TERM_ENB_A = 0x400,
145 AHC_TERM_ENB_B = 0x800,
146 AHC_INITIATORMODE = 0x1000,/*
147 * Allow initiator operations on
148 * this controller.
149 */

--- 114 unchanged lines hidden (view full) ---

264 u_int8_t pad[7];
265};
266
267/*
268 * Per lun target mode state including accept TIO CCB
269 * and immediate notify CCB pools.
270 */
271struct tmode_lstate {
146 AHC_EXTENDED_TRANS_A = 0x100,
147 AHC_EXTENDED_TRANS_B = 0x200,
148 AHC_TERM_ENB_A = 0x400,
149 AHC_TERM_ENB_B = 0x800,
150 AHC_INITIATORMODE = 0x1000,/*
151 * Allow initiator operations on
152 * this controller.
153 */

--- 114 unchanged lines hidden (view full) ---

268 u_int8_t pad[7];
269};
270
271/*
272 * Per lun target mode state including accept TIO CCB
273 * and immediate notify CCB pools.
274 */
275struct tmode_lstate {
272 SLIST_HEAD(, ccb_hdr) accept_tios;
273 SLIST_HEAD(, ccb_hdr) immed_notifies;
276 struct ccb_hdr_slist accept_tios;
277 struct ccb_hdr_slist immed_notifies;
274};
275
276/*
277 * Per target mode enabled target state. Esentially just an array of
278 * pointers to lun target state.
279 */
280struct tmode_tstate {
281 struct tmode_lstate* enabled_luns[8];

--- 256 unchanged lines hidden ---
278};
279
280/*
281 * Per target mode enabled target state. Esentially just an array of
282 * pointers to lun target state.
283 */
284struct tmode_tstate {
285 struct tmode_lstate* enabled_luns[8];

--- 256 unchanged lines hidden ---